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ARM: shmobile: r8a7794: Add SDHI clocks to device tree

PATCH New Simon Horman 2 participants 2 messages Dec 12, 2014 – Dec 17, 2014

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Simon Horman

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#0 lore raw

PATCH v2 1/1 ARM: shmobile: r8a7794: Add SDHI clocks to device tree

From: Shinobu Uehara <[email protected]>

Signed-off-by Shinobu Uehara <[email protected]>
[horms: omitted device nodes; only add clock]
Signed-off-by Simon Horman <[email protected]>

---
Based on the renesas-devel-20141212-v3.18 tag of my renesas tree

v2 [Simon Horman]
* As suggested by Magnus Damm
- Added missing sdhi0 portions
(this was an error on my part when rebasing Uehara-san's patch)

v1 [Simon Horman]
* Removed portions of patch which add device nodes
* Renamed patch from
"ARM: shmobile: r8a7794: Add SDHI clocks and devices to device tree" to "ARM: shmobile: r8a7794: Add SDHI clocks to device tree"

---
 arch/arm/boot/dts/r8a7794.dtsi            | 20 +++++++++++++++++++-
 include/dt-bindings/clock/r8a7794-clock.h |  3 +++
 2 files changed, 22 insertions(+), 1 deletion(-)
arch/arm/boot/dts/r8a7794.dtsi +19 -1
index 068ca09..8794df8 100644
@@ -293,6 +293,21 @@
 			clock-output-names = "main", "pll0", "pll1", "pll3",
 					     "lb", "qspi", "sdh", "sd0", "z";
 		};
+		/* Variable factor clocks */
+		sd1_clk: sd2_clk at e6150078 {
+			compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
+			reg = <0 0xe6150078 0 4>;
+			clocks = <&pll1_div2_clk>;
+			#clock-cells = <0>;
+			clock-output-names = "sd1";
+		};
+		sd2_clk: sd3_clk at e615007c {
+			compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
+			reg = <0 0xe615007c 0 4>;
+			clocks = <&pll1_div2_clk>;
+			#clock-cells = <0>;
+			clock-output-names = "sd2";
+		};
 
 		/* Fixed factor clocks */
 		pll1_div2_clk: pll1_div2_clk {

@@ -496,13 +511,16 @@
 		mstp3_clks: mstp3_clks at e615013c {
 			compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
 			reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
-			clocks = <&rclk_clk>, <&hp_clk>, <&hp_clk>;
+			clocks = <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7794_CLK_SD0>,
+			         <&rclk_clk>, <&hp_clk>, <&hp_clk>;
 			#clock-cells = <1>;
 			clock-indices = <
+			        R8A7794_CLK_SDHI2 R8A7794_CLK_SDHI1 R8A7794_CLK_SDHI0
 				R8A7794_CLK_CMT1 R8A7794_CLK_USBDMAC0
 				R8A7794_CLK_USBDMAC1
 			>;
 			clock-output-names =
+			        "sdhi2", "sdhi1", "sdhi0",
 				"cmt1", "usbdmac0", "usbdmac1";
 		};
 		mstp7_clks: mstp7_clks at e615014c {
include/dt-bindings/clock/r8a7794-clock.h +3 -0
index fba89a4..f013cdc 100644
@@ -52,6 +52,9 @@
 #define R8A7794_CLK_SYS_DMAC0		19
 
 /* MSTP3 */
+#define R8A7794_CLK_SDHI2		11
+#define R8A7794_CLK_SDHI1		12
+#define R8A7794_CLK_SDHI0		14
 #define R8A7794_CLK_CMT1		29
 #define R8A7794_CLK_USBDMAC0		30
 #define R8A7794_CLK_USBDMAC1		31
Signature · 1 line
2.1.3
#1 lore raw

PATCH v2 1/1 ARM: shmobile: r8a7794: Add SDHI clocks to device tree

Quoted 5 lines · Simon Horman

From: Shinobu Uehara <[email protected]>

Signed-off-by Shinobu Uehara <[email protected]>
[horms: omitted device nodes; only add clock]
Signed-off-by Simon Horman <[email protected]>

I have queued up this patch.

Quoted 85 lines

---
Based on the renesas-devel-20141212-v3.18 tag of my renesas tree

v2 [Simon Horman]
* As suggested by Magnus Damm
- Added missing sdhi0 portions
(this was an error on my part when rebasing Uehara-san's patch)

v1 [Simon Horman]
* Removed portions of patch which add device nodes
* Renamed patch from
"ARM: shmobile: r8a7794: Add SDHI clocks and devices to device tree" to "ARM: shmobile: r8a7794: Add SDHI clocks to device tree"

---
 arch/arm/boot/dts/r8a7794.dtsi            | 20 +++++++++++++++++++-
 include/dt-bindings/clock/r8a7794-clock.h |  3 +++
 2 files changed, 22 insertions(+), 1 deletion(-)
arch/arm/boot/dts/r8a7794.dtsi +19 -1
index 068ca09..8794df8 100644
@@ -293,6 +293,21 @@
 			clock-output-names = "main", "pll0", "pll1", "pll3",
 					     "lb", "qspi", "sdh", "sd0", "z";
 		};
+		/* Variable factor clocks */
+		sd1_clk: sd2_clk at e6150078 {
+			compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
+			reg = <0 0xe6150078 0 4>;
+			clocks = <&pll1_div2_clk>;
+			#clock-cells = <0>;
+			clock-output-names = "sd1";
+		};
+		sd2_clk: sd3_clk at e615007c {
+			compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
+			reg = <0 0xe615007c 0 4>;
+			clocks = <&pll1_div2_clk>;
+			#clock-cells = <0>;
+			clock-output-names = "sd2";
+		};
 
 		/* Fixed factor clocks */
 		pll1_div2_clk: pll1_div2_clk {

@@ -496,13 +511,16 @@
 		mstp3_clks: mstp3_clks at e615013c {
 			compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
 			reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
-			clocks = <&rclk_clk>, <&hp_clk>, <&hp_clk>;
+			clocks = <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7794_CLK_SD0>,
+			         <&rclk_clk>, <&hp_clk>, <&hp_clk>;
 			#clock-cells = <1>;
 			clock-indices = <
+			        R8A7794_CLK_SDHI2 R8A7794_CLK_SDHI1 R8A7794_CLK_SDHI0
 				R8A7794_CLK_CMT1 R8A7794_CLK_USBDMAC0
 				R8A7794_CLK_USBDMAC1
 			>;
 			clock-output-names =
+			        "sdhi2", "sdhi1", "sdhi0",
 				"cmt1", "usbdmac0", "usbdmac1";
 		};
 		mstp7_clks: mstp7_clks at e615014c {
include/dt-bindings/clock/r8a7794-clock.h +3 -0
index fba89a4..f013cdc 100644
@@ -52,6 +52,9 @@
 #define R8A7794_CLK_SYS_DMAC0		19
 
 /* MSTP3 */
+#define R8A7794_CLK_SDHI2		11
+#define R8A7794_CLK_SDHI1		12
+#define R8A7794_CLK_SDHI0		14
 #define R8A7794_CLK_CMT1		29
 #define R8A7794_CLK_USBDMAC0		30
 #define R8A7794_CLK_USBDMAC1		31
Signature · 6 lines
2.1.3

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