ARM: tegra: Add PCIe support
Subsystems (8)
v4 cover ARM: tegra: Add PCIe support
From: Thierry Reding <[email protected]>
(Commit message updated by Simon Glass <[email protected]> who is sending this series originally created by Thierry)
This series adds PCIe support for Tegra20, Tegra30 and Tegra124. The size is mostly due to the large number of infrastructure that's added (Tegra- specific drivers required by the PCIe driver). In this version I've included all patches that were previously split into three separate series. Spreading them over multiple series is probably not worth it since there might be some dependencies between them and only the end result gives a completely working setup.
Some patches have already been applied to this series.
Patch 1 implements a driver for the AS3722 PMIC used on the Venice2 and Jetson TK1 boards.
Patches 2-7 are preparatory work for the Tegra PCIe controller. They add missing clock driver functionality as well as drivers for the Tegra powergat and XUSB pad controller blocks.
Patch 8 adds the PCIe controller driver for Tegra20, Tegra30 and Tegra124.
Device tree nodes and configurations options to enable PCIe on the TrimSlice (Tegra20), Beaver, Cardhu (Tegra30) and Jetson TK1 (Tegra124) boards are added in patches 9-17.
Patch 18 implements non-cached memory support that will be used in the last batch of patches to implement more reliable packet transfers in the r8169 driver. Patch 19 enables non-cached memory support on Tegra.
(Note from Simon: These patches may have already been applied in the ARM tree, but I can't see them there).
Finally, patches 20-23 implement non-cached memory support and various fixes in the r8169 driver and add support for the revision of the NIC found on the Jetson TK1.
The above boards all have an ethernet NIC connected to PCIe, which is what I tested with.
Note from Simon: I have:
- rebased this on top of the I2C driver model series
- dropped the I2C framework patches
- adjust the PMIC driver and code that calls it to use driver mode
- tested the I2C changes on Jetson-TK1
Changes in v4:
- Use const unsigned for bus and address
- Insert missing word 'to' in a comment
- Fix typo in commit message
Changes in v3:
- Use driver model for the PMIC
- Use driver model to access the PMIC
- Use driver model to access the PMIC
- Avoid build error with noncached_init() when the dcache is disabled
- Remove cache-line size warning if dcache is disabled
Thierry Reding (23):
power: Add AMS AS3722 PMIC support
ARM: tegra: Implement tegra_plle_enable()
ARM: tegra: Provide PCIEXCLK reset ID
ARM: tegra: Implement powergate support
ARM: tegra: Implement XUSB pad controller
ARM: tegra: Add XUSB pad controller on Tegra124
ARM: tegra: Enable XUSB pad controller on Jetson TK1
pci: tegra: Add Tegra PCIe driver
ARM: tegra: Add Tegra20 PCIe device tree node
ARM: tegra: Enable PCIe on TrimSlice
ARM: tegra: Add GIC for Tegra30
ARM: tegra: Add Tegra30 PCIe device tree node
ARM: tegra: Enable PCIe on Cardhu
ARM: tegra: Enable PCIe on Beaver
ARM: tegra: Add GIC for Tegra124
ARM: tegra: Add Tegra124 PCIe device tree node
ARM: tegra: Enable PCIe on Jetson TK1
ARM: Implement non-cached memory support
ARM: tegra: Enable non-cached memory
net: rtl8169: Honor CONFIG_SYS_RX_ETH_BUFFER
net: rtl8169: Properly align buffers
net: rtl8169: Use non-cached memory if available
net: rtl8169: Add support for RTL-8168/8111g
README | 19 + arch/arm/cpu/tegra-common/Makefile | 2 + arch/arm/cpu/tegra-common/powergate.c | 102 ++ arch/arm/cpu/tegra-common/xusb-padctl.c | 39 + arch/arm/cpu/tegra124-common/Makefile | 1 + arch/arm/cpu/tegra124-common/clock.c | 109 +++ arch/arm/cpu/tegra124-common/xusb-padctl.c | 716 ++++++++++++++ arch/arm/cpu/tegra20-common/clock.c | 141 ++- arch/arm/cpu/tegra30-common/clock.c | 155 +++ arch/arm/dts/tegra124-jetson-tk1.dts | 373 +++++++ arch/arm/dts/tegra124.dtsi | 89 ++ arch/arm/dts/tegra20-trimslice.dts | 69 ++ arch/arm/dts/tegra20.dtsi | 59 ++ arch/arm/dts/tegra30-beaver.dts | 245 +++++ arch/arm/dts/tegra30-cardhu.dts | 362 +++++++ arch/arm/dts/tegra30.dtsi | 83 ++ arch/arm/include/asm/arch-tegra/powergate.h | 38 + arch/arm/include/asm/arch-tegra/xusb-padctl.h | 24 + arch/arm/include/asm/arch-tegra114/powergate.h | 6 + arch/arm/include/asm/arch-tegra124/clock.h | 2 + arch/arm/include/asm/arch-tegra124/powergate.h | 6 + arch/arm/include/asm/arch-tegra20/clock-tables.h | 2 +- arch/arm/include/asm/arch-tegra20/clock.h | 2 + arch/arm/include/asm/arch-tegra20/powergate.h | 6 + arch/arm/include/asm/arch-tegra30/clock.h | 2 + arch/arm/include/asm/arch-tegra30/powergate.h | 6 + arch/arm/include/asm/system.h | 5 + arch/arm/lib/cache.c | 44 + board/compulab/trimslice/trimslice.c | 8 + board/nvidia/cardhu/cardhu.c | 52 + board/nvidia/common/board.c | 3 + board/nvidia/jetson-tk1/jetson-tk1.c | 52 + common/board_r.c | 11 + drivers/net/rtl8169.c | 127 ++- drivers/pci/Makefile | 1 + drivers/pci/pci_tegra.c | 1143 ++++++++++++++++++++++ drivers/power/Makefile | 1 + drivers/power/as3722.c | 264 +++++ include/configs/beaver.h | 10 + include/configs/cardhu.h | 10 + include/configs/jetson-tk1.h | 13 + include/configs/tegra-common.h | 2 + include/configs/trimslice.h | 10 + include/dt-bindings/clock/tegra20-car.h | 2 +- include/dt-bindings/clock/tegra30-car.h | 2 +- include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h | 7 + include/fdtdec.h | 6 + include/power/as3722.h | 27 + lib/fdtdec.c | 5 + 49 files changed, 4424 insertions(+), 39 deletions(-) create mode 100644 arch/arm/cpu/tegra-common/powergate.c create mode 100644 arch/arm/cpu/tegra-common/xusb-padctl.c create mode 100644 arch/arm/cpu/tegra124-common/xusb-padctl.c create mode 100644 arch/arm/include/asm/arch-tegra/powergate.h create mode 100644 arch/arm/include/asm/arch-tegra/xusb-padctl.h create mode 100644 arch/arm/include/asm/arch-tegra114/powergate.h create mode 100644 arch/arm/include/asm/arch-tegra124/powergate.h create mode 100644 arch/arm/include/asm/arch-tegra20/powergate.h create mode 100644 arch/arm/include/asm/arch-tegra30/powergate.h create mode 100644 drivers/pci/pci_tegra.c create mode 100644 drivers/power/as3722.c create mode 100644 include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h create mode 100644 include/power/as3722.h
Signature · 1 line
2.2.0.rc0.207.ga3a616c
PATCH v4 1/23 power: Add AMS AS3722 PMIC support
From: Thierry Reding <[email protected]>
The AS3722 provides a number of DC/DC converters and LDOs as well as 8 GPIOs.
---
Changes in v4:
- Use const unsigned for bus and address
Changes in v3:
- Use driver model for the PMIC
drivers/power/Makefile | 1 + drivers/power/as3722.c | 264 +++++++++++++++++++++++++++++++++++++++++++++++++ include/fdtdec.h | 1 + include/power/as3722.h | 27 +++++ lib/fdtdec.c | 1 + 5 files changed, 294 insertions(+) create mode 100644 drivers/power/as3722.c create mode 100644 include/power/as3722.h
drivers/power/Makefile +1 -0
@@ -5,6 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # +obj-$(CONFIG_AS3722_POWER) += as3722.o obj-$(CONFIG_AXP152_POWER) += axp152.o obj-$(CONFIG_AXP209_POWER) += axp209.o obj-$(CONFIG_AXP221_POWER) += axp221.o
drivers/power/as3722.c new file +264 -0
264 lines not on this page · raw message
include/fdtdec.h +1 -0
@@ -123,6 +123,7 @@ enum fdt_compat_id {COMPAT_INTEL_PANTHERPOINT_AHCI ,/* Intel Pantherpoint AHCI */ COMPAT_INTEL_MODEL_206AX ,/* Intel Model 206AX CPU */ COMPAT_INTEL_GMA ,/* Intel Graphics Media Accelerator */ +COMPAT_AMS_AS3722 ,/* AMS AS3722 PMIC */ COMPAT_COUNT, };
include/power/as3722.h new file +27 -0
@@ -0,0 +1,27 @@ +/* +* Copyright (C) 2014 NVIDIA Corporation +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef __POWER_AS3722_H__ +#define __POWER_AS3722_H__ + +#include <asm/types.h> + +#define AS3722_GPIO_OUTPUT_VDDH (1 << 0) +#define AS3722_GPIO_INVERT (1 << 1) + +struct udevice ; + +int as3722_init (struct udevice **devp); +int as3722_sd_enable (struct udevice *pmic,unsigned int sd); +int as3722_sd_set_voltage (struct udevice *pmic,unsigned int sd,u8 value); +int as3722_ldo_enable (struct udevice *pmic,unsigned int ldo); +int as3722_ldo_set_voltage (struct udevice *pmic,unsigned int ldo,u8 value); +int as3722_gpio_configure (struct udevice *pmic,unsigned int gpio, +unsigned long flags); +int as3722_gpio_direction_output (struct udevice *pmic,unsigned int gpio, +unsigned int level); + +#endif /* __POWER_AS3722_H__ */
lib/fdtdec.c +1 -0
@@ -78,6 +78,7 @@ static const char * const compat_names[COMPAT_COUNT] = {COMPAT (INTEL_PANTHERPOINT_AHCI ,"intel,pantherpoint-ahci" ),COMPAT (INTEL_MODEL_206AX ,"intel,model-206ax" ),COMPAT (INTEL_GMA ,"intel,gma" ), + COMPAT(AMS_AS3722, "ams,as3722"), };const char *fdtdec_get_compatible (enum fdt_compat_id id)
Signature · 1 line
2.2.0.rc0.207.ga3a616c
PATCH v4 2/23 ARM: tegra: Implement tegra_plle_enable()
In reply to Simon GlassFrom: Thierry Reding <[email protected]>
This function is required by PCIe and SATA. This patch implements it on Tegra20, Tegra30 and Tegra124. It isn't implemented for Tegra114 because it doesn't support PCIe or SATA.
---
Changes in v4: None
Changes in v3: None
arch/arm/cpu/tegra124-common/clock.c | 109 ++++++++++++++++++++ arch/arm/cpu/tegra20-common/clock.c | 137 +++++++++++++++++++++++++ arch/arm/cpu/tegra30-common/clock.c | 154 +++++++++++++++++++++++++++++ arch/arm/include/asm/arch-tegra124/clock.h | 2 + arch/arm/include/asm/arch-tegra20/clock.h | 2 + arch/arm/include/asm/arch-tegra30/clock.h | 2 + 6 files changed, 406 insertions(+)
arch/arm/cpu/tegra124-common/clock.c +109 -0
@@ -824,3 +824,112 @@ void arch_timer_init(void)writel (val, &sysctr->cntcr);debug ("%s: TSC CNTCR = 0x%08X\n" , __func__, val); } + +#define PLLE_SS_CNTL 0x68 +#define PLLE_SS_CNTL_SSCINCINTR (x) (((x) & 0x3f) << 24) +#define PLLE_SS_CNTL_SSCINC (x) (((x) & 0xff) << 16) +#define PLLE_SS_CNTL_SSCINVERT (1 << 15) +#define PLLE_SS_CNTL_SSCCENTER (1 << 14) +#define PLLE_SS_CNTL_SSCBYP (1 << 12) +#define PLLE_SS_CNTL_INTERP_RESET (1 << 11) +#define PLLE_SS_CNTL_BYPASS_SS (1 << 10) +#define PLLE_SS_CNTL_SSCMAX (x) (((x) & 0x1ff) << 0) + +#define PLLE_BASE 0x0e8 +#define PLLE_BASE_ENABLE (1 << 30) +#define PLLE_BASE_LOCK_OVERRIDE (1 << 29) +#define PLLE_BASE_PLDIV_CML (x) (((x) & 0xf) << 24) +#define PLLE_BASE_NDIV (x) (((x) & 0xff) << 8) +#define PLLE_BASE_MDIV (x) (((x) & 0xff) << 0) + +#define PLLE_MISC 0x0ec +#define PLLE_MISC_IDDQ_SWCTL (1 << 14) +#define PLLE_MISC_IDDQ_OVERRIDE (1 << 13) +#define PLLE_MISC_LOCK_ENABLE (1 << 9) +#define PLLE_MISC_PTS (1 << 8) +#define PLLE_MISC_VREG_BG_CTRL (x) (((x) & 0x3) << 4) +#define PLLE_MISC_VREG_CTRL (x) (((x) & 0x3) << 2) + +#define PLLE_AUX 0x48c +#define PLLE_AUX_SEQ_ENABLE (1 << 24) +#define PLLE_AUX_ENABLE_SWCTL (1 << 4) + +int tegra_plle_enable (void ) +{ +unsigned int m =1 , n =200 , cpcon =13 ; +u32 value; + + value =readl (NV_PA_CLK_RST_BASE +PLLE_BASE ); + value &= ~PLLE_BASE_LOCK_OVERRIDE ; +writel (value,NV_PA_CLK_RST_BASE +PLLE_BASE ); + + value =readl (NV_PA_CLK_RST_BASE +PLLE_AUX ); + value |=PLLE_AUX_ENABLE_SWCTL ; + value &= ~PLLE_AUX_SEQ_ENABLE ; +writel (value,NV_PA_CLK_RST_BASE +PLLE_AUX ); + +udelay (1 ); + + value =readl (NV_PA_CLK_RST_BASE +PLLE_MISC ); + value |=PLLE_MISC_IDDQ_SWCTL ; + value &= ~PLLE_MISC_IDDQ_OVERRIDE ; + value |=PLLE_MISC_LOCK_ENABLE ; + value |=PLLE_MISC_PTS ; + value |=PLLE_MISC_VREG_BG_CTRL (3 ); + value |=PLLE_MISC_VREG_CTRL (2 ); +writel (value,NV_PA_CLK_RST_BASE +PLLE_MISC ); + +udelay (5 ); + + value =readl (NV_PA_CLK_RST_BASE +PLLE_SS_CNTL ); + value |=PLLE_SS_CNTL_SSCBYP |PLLE_SS_CNTL_INTERP_RESET | +PLLE_SS_CNTL_BYPASS_SS ; +writel (value,NV_PA_CLK_RST_BASE +PLLE_SS_CNTL ); + + value =readl (NV_PA_CLK_RST_BASE +PLLE_BASE ); + value &= ~PLLE_BASE_PLDIV_CML (0xf ); + value &= ~PLLE_BASE_NDIV (0xff ); + value &= ~PLLE_BASE_MDIV (0xff ); + value |=PLLE_BASE_PLDIV_CML (cpcon); + value |=PLLE_BASE_NDIV (n); + value |=PLLE_BASE_MDIV (m); +writel (value,NV_PA_CLK_RST_BASE +PLLE_BASE ); + +udelay (1 ); + + value =readl (NV_PA_CLK_RST_BASE +PLLE_BASE ); + value |=PLLE_BASE_ENABLE ; +writel (value,NV_PA_CLK_RST_BASE +PLLE_BASE ); + +/* wait for lock */ +udelay (300 ); + + value =readl (NV_PA_CLK_RST_BASE +PLLE_SS_CNTL ); + value &= ~PLLE_SS_CNTL_SSCINVERT ; + value &= ~PLLE_SS_CNTL_SSCCENTER ; + + value &= ~PLLE_SS_CNTL_SSCINCINTR (0x3f ); + value &= ~PLLE_SS_CNTL_SSCINC (0xff ); + value &= ~PLLE_SS_CNTL_SSCMAX (0x1ff ); + + value |=PLLE_SS_CNTL_SSCINCINTR (0x20 ); + value |=PLLE_SS_CNTL_SSCINC (0x01 ); + value |=PLLE_SS_CNTL_SSCMAX (0x25 ); + +writel (value,NV_PA_CLK_RST_BASE +PLLE_SS_CNTL ); + + value =readl (NV_PA_CLK_RST_BASE +PLLE_SS_CNTL ); + value &= ~PLLE_SS_CNTL_SSCBYP ; + value &= ~PLLE_SS_CNTL_BYPASS_SS ; +writel (value,NV_PA_CLK_RST_BASE +PLLE_SS_CNTL ); + +udelay (1 ); + + value =readl (NV_PA_CLK_RST_BASE +PLLE_SS_CNTL ); + value &= ~PLLE_SS_CNTL_INTERP_RESET ; +writel (value,NV_PA_CLK_RST_BASE +PLLE_SS_CNTL ); + +udelay (1 ); + +return 0 ; +}
arch/arm/cpu/tegra20-common/clock.c +137 -0
146 lines not on this page · raw message
arch/arm/cpu/tegra30-common/clock.c +154 -0
163 lines not on this page · raw message
arch/arm/include/asm/arch-tegra124/clock.h +2 -0
@@ -16,4 +16,6 @@#define OSC_FREQ_SHIFT 28#define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT) +int tegra_plle_enable (void ); +#endif /* _TEGRA124_CLOCK_H_ */
arch/arm/include/asm/arch-tegra20/clock.h +2 -0
@@ -15,4 +15,6 @@#define OSC_FREQ_SHIFT 30#define OSC_FREQ_MASK (3U << OSC_FREQ_SHIFT) +int tegra_plle_enable (void ); +#endif /* _TEGRA20_CLOCK_H */
arch/arm/include/asm/arch-tegra30/clock.h +2 -0
@@ -25,4 +25,6 @@#define OSC_FREQ_SHIFT 28#define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT) +int tegra_plle_enable (void ); +#endif /* _TEGRA30_CLOCK_H_ */
Signature · 1 line
2.2.0.rc0.207.ga3a616c
PATCH v4 3/23 ARM: tegra: Provide PCIEXCLK reset ID
In reply to Simon GlassFrom: Thierry Reding <[email protected]>
This reset is required for PCIe and the corresponding ID therefore needs to be defined. The enumeration value for this was properly defined on some SoCs but not on others. Similarly, some contained it in the mapping of peripheral IDs to clock IDs, other didn't. This patch defines it consistently for all supported SoC generations.
---
Changes in v4: None
Changes in v3: None
arch/arm/cpu/tegra20-common/clock.c | 4 ++-- arch/arm/cpu/tegra30-common/clock.c | 1 + arch/arm/include/asm/arch-tegra20/clock-tables.h | 2 +- 3 files changed, 4 insertions(+), 3 deletions(-)
arch/arm/cpu/tegra20-common/clock.c +2 -2
@@ -333,7 +333,7 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {/* 0x48 */ NONE (AFI ),NONE (CORESIGHT ), -NONE (RESERVED74 ), +NONE (PCIEXCLK ),NONE (AVPUCQ ),NONE (RESERVED76 ), NONE(RESERVED77),
@@ -495,7 +495,7 @@ enum periph_id clk_id_to_periph_id(int clk_id)case PERIPH_ID_RESERVED30 :case PERIPH_ID_RESERVED35 :case PERIPH_ID_RESERVED56 : -case PERIPH_ID_RESERVED74 : +case PERIPH_ID_PCIEXCLK :case PERIPH_ID_RESERVED76 :case PERIPH_ID_RESERVED77 :case PERIPH_ID_RESERVED78 :
arch/arm/cpu/tegra30-common/clock.c +1 -0
@@ -564,6 +564,7 @@ enum periph_id clk_id_to_periph_id(int clk_id)case PERIPH_ID_RESERVED43 :case PERIPH_ID_RESERVED45 :case PERIPH_ID_RESERVED56 : +case PERIPH_ID_PCIEXCLK :case PERIPH_ID_RESERVED76 :case PERIPH_ID_RESERVED77 :case PERIPH_ID_RESERVED78 :
arch/arm/include/asm/arch-tegra20/clock-tables.h +1 -1
@@ -131,7 +131,7 @@ enum periph_id {/* 72 */ PERIPH_ID_AFI ,PERIPH_ID_CORESIGHT , -PERIPH_ID_RESERVED74 , +PERIPH_ID_PCIEXCLK ,PERIPH_ID_AVPUCQ ,PERIPH_ID_RESERVED76 , PERIPH_ID_RESERVED77,
Signature · 1 line
2.2.0.rc0.207.ga3a616c
PATCH v4 4/23 ARM: tegra: Implement powergate support
In reply to Simon GlassFrom: Thierry Reding <[email protected]>
Implement the powergate API that allows various power partitions to be power up and down.
---
Changes in v4: None
Changes in v3: None
arch/arm/cpu/tegra-common/Makefile | 1 + arch/arm/cpu/tegra-common/powergate.c | 102 +++++++++++++++++++++++++ arch/arm/include/asm/arch-tegra/powergate.h | 38 +++++++++ arch/arm/include/asm/arch-tegra114/powergate.h | 6 ++ arch/arm/include/asm/arch-tegra124/powergate.h | 6 ++ arch/arm/include/asm/arch-tegra20/powergate.h | 6 ++ arch/arm/include/asm/arch-tegra30/powergate.h | 6 ++ 7 files changed, 165 insertions(+) create mode 100644 arch/arm/cpu/tegra-common/powergate.c create mode 100644 arch/arm/include/asm/arch-tegra/powergate.h create mode 100644 arch/arm/include/asm/arch-tegra114/powergate.h create mode 100644 arch/arm/include/asm/arch-tegra124/powergate.h create mode 100644 arch/arm/include/asm/arch-tegra20/powergate.h create mode 100644 arch/arm/include/asm/arch-tegra30/powergate.h
arch/arm/cpu/tegra-common/Makefile +1 -0
@@ -13,5 +13,6 @@ obj-y += cache.o obj-y += clock.o obj-y += lowlevel_init.o obj-y += pinmux-common.o +obj-y += powergate.o obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o obj-$(CONFIG_TEGRA124) += vpr.o
arch/arm/cpu/tegra-common/powergate.c new file +102 -0
102 lines not on this page · raw message
arch/arm/include/asm/arch-tegra/powergate.h new file +38 -0
@@ -0,0 +1,38 @@ +#ifndef _TEGRA_POWERGATE_H_ +#define _TEGRA_POWERGATE_H_ + +#include <asm/arch/clock.h> + +enum tegra_powergate { +TEGRA_POWERGATE_CPU , +TEGRA_POWERGATE_3D , +TEGRA_POWERGATE_VENC , +TEGRA_POWERGATE_PCIE , +TEGRA_POWERGATE_VDEC , +TEGRA_POWERGATE_L2 , +TEGRA_POWERGATE_MPE , +TEGRA_POWERGATE_HEG , +TEGRA_POWERGATE_SATA , +TEGRA_POWERGATE_CPU1 , +TEGRA_POWERGATE_CPU2 , +TEGRA_POWERGATE_CPU3 , +TEGRA_POWERGATE_CELP , +TEGRA_POWERGATE_3D1 , +TEGRA_POWERGATE_CPU0 , +TEGRA_POWERGATE_C0NC , +TEGRA_POWERGATE_C1NC , +TEGRA_POWERGATE_SOR , +TEGRA_POWERGATE_DIS , +TEGRA_POWERGATE_DISB , +TEGRA_POWERGATE_XUSBA , +TEGRA_POWERGATE_XUSBB , +TEGRA_POWERGATE_XUSBC , +TEGRA_POWERGATE_VIC , +TEGRA_POWERGATE_IRAM , +}; + +int tegra_powergate_sequence_power_up (enum tegra_powergate id, +enum periph_id periph); +int tegra_powergate_power_off (enum tegra_powergate id); + +#endif
arch/arm/include/asm/arch-tegra114/powergate.h new file +6 -0
@@ -0,0 +1,6 @@ +#ifndef _TEGRA114_POWERGATE_H_ +#define _TEGRA114_POWERGATE_H_ + +#include <asm/arch-tegra/powergate.h> + +#endif /* _TEGRA114_POWERGATE_H_ */
arch/arm/include/asm/arch-tegra124/powergate.h new file +6 -0
@@ -0,0 +1,6 @@ +#ifndef _TEGRA124_POWERGATE_H_ +#define _TEGRA124_POWERGATE_H_ + +#include <asm/arch-tegra/powergate.h> + +#endif /* _TEGRA124_POWERGATE_H_ */
arch/arm/include/asm/arch-tegra20/powergate.h new file +6 -0
@@ -0,0 +1,6 @@ +#ifndef _TEGRA20_POWERGATE_H_ +#define _TEGRA20_POWERGATE_H_ + +#include <asm/arch-tegra/powergate.h> + +#endif /* _TEGRA20_POWERGATE_H_ */
arch/arm/include/asm/arch-tegra30/powergate.h new file +6 -0
@@ -0,0 +1,6 @@ +#ifndef _TEGRA30_POWERGATE_H_ +#define _TEGRA30_POWERGATE_H_ + +#include <asm/arch-tegra/powergate.h> + +#endif /* _TEGRA30_POWERGATE_H_ */
Signature · 1 line
2.2.0.rc0.207.ga3a616c
PATCH v4 5/23 ARM: tegra: Implement XUSB pad controller
In reply to Simon GlassFrom: Thierry Reding <[email protected]>
This controller was introduced on Tegra114 to handle XUSB pads. On Tegra124 it is also used for PCIe and SATA pin muxing and PHY control. Only the Tegra124 PCIe and SATA functionality is currently implemented, with weak symbols on Tegra114.
Tegra20 and Tegra30 also provide weak symbols for these functions so that drivers can use the same API irrespective of which SoC they're being built for.
---
Changes in v4: None
Changes in v3: None
arch/arm/cpu/tegra-common/Makefile | 1 + arch/arm/cpu/tegra-common/xusb-padctl.c | 39 ++ arch/arm/cpu/tegra124-common/Makefile | 1 + arch/arm/cpu/tegra124-common/xusb-padctl.c | 716 +++++++++++++++++++++++ arch/arm/include/asm/arch-tegra/xusb-padctl.h | 24 + board/nvidia/common/board.c | 3 + include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h | 7 + include/fdtdec.h | 2 + lib/fdtdec.c | 1 + 9 files changed, 794 insertions(+) create mode 100644 arch/arm/cpu/tegra-common/xusb-padctl.c create mode 100644 arch/arm/cpu/tegra124-common/xusb-padctl.c create mode 100644 arch/arm/include/asm/arch-tegra/xusb-padctl.h create mode 100644 include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h
arch/arm/cpu/tegra-common/Makefile +1 -0
@@ -14,5 +14,6 @@ obj-y += clock.o obj-y += lowlevel_init.o obj-y += pinmux-common.o obj-y += powergate.o +obj-y += xusb-padctl.o obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o obj-$(CONFIG_TEGRA124) += vpr.o
arch/arm/cpu/tegra-common/xusb-padctl.c new file +39 -0
@@ -0,0 +1,39 @@ +/* +* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. +* +* SPDX-License-Identifier: GPL-2.0 +*/ + +#include <common.h> +#include <errno.h> + +#include <asm/arch-tegra/xusb-padctl.h> + +struct tegra_xusb_phy *__weak tegra_xusb_phy_get (unsigned int type) +{ +return NULL ; +} + +int __weak tegra_xusb_phy_prepare (struct tegra_xusb_phy *phy) +{ +return -ENOSYS ; +} + +int __weak tegra_xusb_phy_enable (struct tegra_xusb_phy *phy) +{ +return -ENOSYS ; +} + +int __weak tegra_xusb_phy_disable (struct tegra_xusb_phy *phy) +{ +return -ENOSYS ; +} + +int __weak tegra_xusb_phy_unprepare (struct tegra_xusb_phy *phy) +{ +return -ENOSYS ; +} + +void __weak tegra_xusb_padctl_init (const void *fdt) +{ +}
arch/arm/cpu/tegra124-common/Makefile +1 -0
@@ -8,3 +8,4 @@ obj-y += clock.o obj-y += funcmux.o obj-y += pinmux.o +obj-y += xusb-padctl.o
arch/arm/cpu/tegra124-common/xusb-padctl.c new file +716 -0
716 lines not on this page · raw message
arch/arm/include/asm/arch-tegra/xusb-padctl.h new file +24 -0
@@ -0,0 +1,24 @@ +#ifndef _TEGRA_XUSB_PADCTL_H_ +#define _TEGRA_XUSB_PADCTL_H_ + +struct tegra_xusb_phy ; + +/** +* tegra_xusb_phy_get() - obtain a reference to a specified padctl PHY +* @type: the type of PHY to obtain +* +* The type of PHY varies between SoC generations. Typically there are XUSB, +* PCIe and SATA PHYs, though not all generations support all of them. The +* value of type can usually be directly parsed from a device tree. +* +* Return: a pointer to the PHY or NULL if no such PHY exists +*/ +struct tegra_xusb_phy *tegra_xusb_phy_get (unsigned int type); + +void tegra_xusb_padctl_init (const void *fdt); +int tegra_xusb_phy_prepare (struct tegra_xusb_phy *phy); +int tegra_xusb_phy_enable (struct tegra_xusb_phy *phy); +int tegra_xusb_phy_disable (struct tegra_xusb_phy *phy); +int tegra_xusb_phy_unprepare (struct tegra_xusb_phy *phy); + +#endif
board/nvidia/common/board.c +3 -0
@@ -38,6 +38,7 @@#include <asm/arch-tegra/tegra_mmc.h> #include <asm/arch-tegra/mmc.h> #endif +#include <asm/arch-tegra/xusb-padctl.h> #include <i2c.h> #include <spi.h> #include "emc.h"
@@ -137,6 +138,8 @@ int board_init(void)pin_mux_nand ();#endif +tegra_xusb_padctl_init (gd->fdt_blob); +#ifdef CONFIG_TEGRA_LP0 /* save Sdram params to PMC 2, 4, and 24 for WB0 */ warmboot_save_sdram_params ();
include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h new file +7 -0
@@ -0,0 +1,7 @@ +#ifndef _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H +#define _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H 1 + +#define TEGRA_XUSB_PADCTL_PCIE 0 +#define TEGRA_XUSB_PADCTL_SATA 1 + +#endif /* _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H */
include/fdtdec.h +2 -0
@@ -86,6 +86,8 @@ enum fdt_compat_id {COMPAT_NVIDIA_TEGRA20_SFLASH ,/* Tegra 2 SPI flash controller */ COMPAT_NVIDIA_TEGRA20_SLINK ,/* Tegra 2 SPI SLINK controller */ COMPAT_NVIDIA_TEGRA114_SPI ,/* Tegra 114 SPI controller */ +COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL , +/* Tegra124 XUSB pad controller */ COMPAT_SMSC_LAN9215 ,/* SMSC 10/100 Ethernet LAN9215 */ COMPAT_SAMSUNG_EXYNOS5_SROMC ,/* Exynos5 SROMC */ COMPAT_SAMSUNG_S3C2440_I2C, /* Exynos I2C Controller */
lib/fdtdec.c +1 -0
@@ -41,6 +41,7 @@ static const char * const compat_names[COMPAT_COUNT] = {COMPAT (NVIDIA_TEGRA20_SFLASH ,"nvidia,tegra20-sflash" ),COMPAT (NVIDIA_TEGRA20_SLINK ,"nvidia,tegra20-slink" ),COMPAT (NVIDIA_TEGRA114_SPI ,"nvidia,tegra114-spi" ), +COMPAT (NVIDIA_TEGRA124_XUSB_PADCTL ,"nvidia,tegra124-xusb-padctl" ),COMPAT (SMSC_LAN9215 ,"smsc,lan9215" ),COMPAT (SAMSUNG_EXYNOS5_SROMC ,"samsung,exynos-sromc" ), COMPAT(SAMSUNG_S3C2440_I2C, "samsung,s3c2440-i2c"),
Signature · 1 line
2.2.0.rc0.207.ga3a616c
PATCH v4 6/23 ARM: tegra: Add XUSB pad controller on Tegra124
In reply to Simon GlassFrom: Thierry Reding <[email protected]>
The XUSB pad controller is used for pinmuxing of the XUSB, PCIe and SATA lanes.
---
Changes in v4: None
Changes in v3: None
arch/arm/dts/tegra124.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+)
arch/arm/dts/tegra124.dtsi +10 -0
@@ -2,6 +2,7 @@ #include <dt-bindings/gpio/tegra-gpio.h> #include <dt-bindings/pinctrl/pinctrl-tegra.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> #include "skeleton.dtsi"
@@ -269,6 +270,15 @@ clocks = <&tegra_car 105>; }; + padctl: padctl at 7009f000 { + compatible = "nvidia,tegra124-xusb-padctl"; + reg = <0x7009f000 0x1000>; + resets = <&tegra_car 142>; + reset-names = "padctl"; + + #phy-cells = <1>; + }; + sdhci at 700b0000 { compatible = "nvidia,tegra124-sdhci"; reg = <0x700b0000 0x200>;
Signature · 1 line
2.2.0.rc0.207.ga3a616c
PATCH v4 7/23 ARM: tegra: Enable XUSB pad controller on Jetson TK1
In reply to Simon GlassFrom: Thierry Reding <[email protected]>
Add the PCIe and SATA lane configuration to the Jetson TK1 device tree, so that the XUSB pad controller can be appropriately configured.
---
Changes in v4: None
Changes in v3: None
arch/arm/dts/tegra124-jetson-tk1.dts | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+)
arch/arm/dts/tegra124-jetson-tk1.dts +26 -0
@@ -69,6 +69,32 @@ spi-max-frequency = <25000000>; }; + padctl at 7009f000 { + pinctrl-0 = <&padctl_default>; + pinctrl-names = "default"; + + padctl_default: pinmux { + usb3 { + nvidia,lanes = "pcie-0", "pcie-1"; + nvidia,function = "usb3"; + nvidia,iddq = <0>; + }; + + pcie { + nvidia,lanes = "pcie-2", "pcie-3", + "pcie-4"; + nvidia,function = "pcie"; + nvidia,iddq = <0>; + }; + + sata { + nvidia,lanes = "sata-0"; + nvidia,function = "sata"; + nvidia,iddq = <0>; + }; + }; + }; + sdhci at 700b0400 { status = "okay"; cd-gpios = <&gpio 170 1>; /* gpio PV2 */
Signature · 1 line
2.2.0.rc0.207.ga3a616c
PATCH v4 8/23 pci: tegra: Add Tegra PCIe driver
In reply to Simon GlassFrom: Thierry Reding <[email protected]>
Add support for the PCIe controller found on some generations of Tegra. Tegra20 has 2 root ports with a total of 4 lanes, Tegra30 has 3 root ports with a total of 6 lanes and Tegra124 has 2 root ports with a total of 5 lanes.
This is based on the Linux kernel driver, originally submitted upstream by Mike Rapoport.
---
Changes in v4: None
Changes in v3: None
drivers/pci/Makefile | 1 + drivers/pci/pci_tegra.c | 1143 +++++++++++++++++++++++++++++++++++++++++++++++ include/fdtdec.h | 3 + lib/fdtdec.c | 3 + 4 files changed, 1150 insertions(+) create mode 100644 drivers/pci/pci_tegra.c
drivers/pci/Makefile +1 -0
@@ -15,5 +15,6 @@ obj-$(CONFIG_FTPCI100) += pci_ftpci100.o obj-$(CONFIG_SH4_PCI) += pci_sh4.o obj-$(CONFIG_SH7751_PCI) +=pci_sh7751.o obj-$(CONFIG_SH7780_PCI) +=pci_sh7780.o +obj-$(CONFIG_PCI_TEGRA) += pci_tegra.o obj-$(CONFIG_TSI108_PCI) += tsi108_pci.o obj-$(CONFIG_WINBOND_83C553) += w83c553f.o
drivers/pci/pci_tegra.c new file +1143 -0
1,143 lines not on this page · raw message
include/fdtdec.h +3 -0
@@ -86,6 +86,9 @@ enum fdt_compat_id {COMPAT_NVIDIA_TEGRA20_SFLASH ,/* Tegra 2 SPI flash controller */ COMPAT_NVIDIA_TEGRA20_SLINK ,/* Tegra 2 SPI SLINK controller */ COMPAT_NVIDIA_TEGRA114_SPI ,/* Tegra 114 SPI controller */ +COMPAT_NVIDIA_TEGRA124_PCIE ,/* Tegra 124 PCIe controller */ +COMPAT_NVIDIA_TEGRA30_PCIE ,/* Tegra 30 PCIe controller */ +COMPAT_NVIDIA_TEGRA20_PCIE ,/* Tegra 20 PCIe controller */ COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL ,/* Tegra124 XUSB pad controller */ COMPAT_SMSC_LAN9215, /* SMSC 10/100 Ethernet LAN9215 */
lib/fdtdec.c +3 -0
@@ -41,6 +41,9 @@ static const char * const compat_names[COMPAT_COUNT] = {COMPAT (NVIDIA_TEGRA20_SFLASH ,"nvidia,tegra20-sflash" ),COMPAT (NVIDIA_TEGRA20_SLINK ,"nvidia,tegra20-slink" ),COMPAT (NVIDIA_TEGRA114_SPI ,"nvidia,tegra114-spi" ), +COMPAT (NVIDIA_TEGRA124_PCIE ,"nvidia,tegra124-pcie" ), +COMPAT (NVIDIA_TEGRA30_PCIE ,"nvidia,tegra30-pcie" ), +COMPAT (NVIDIA_TEGRA20_PCIE ,"nvidia,tegra20-pcie" ),COMPAT (NVIDIA_TEGRA124_XUSB_PADCTL ,"nvidia,tegra124-xusb-padctl" ),COMPAT (SMSC_LAN9215 ,"smsc,lan9215" ), COMPAT(SAMSUNG_EXYNOS5_SROMC, "samsung,exynos-sromc"),
Signature · 1 line
2.2.0.rc0.207.ga3a616c
PATCH v4 9/23 ARM: tegra: Add Tegra20 PCIe device tree node
In reply to Simon GlassFrom: Thierry Reding <[email protected]>
Add the device tree node for the PCIe controller found on Tegra20 SoCs.
---
Changes in v4: None
Changes in v3: None
arch/arm/dts/tegra20.dtsi | 59 +++++++++++++++++++++++++++++++++ include/dt-bindings/clock/tegra20-car.h | 2 +- 2 files changed, 60 insertions(+), 1 deletion(-)
arch/arm/dts/tegra20.dtsi +59 -0
@@ -332,6 +332,65 @@ reg = <0x7000f400 0x200>; }; + pcie-controller at 80003000 { + compatible = "nvidia,tegra20-pcie"; + device_type = "pci"; + reg = <0x80003000 0x00000800 /* PADS registers */ + 0x80003800 0x00000200 /* AFI registers */ + 0x90000000 0x10000000>; /* configuration space */ + reg-names = "pads", "afi", "cs"; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */ + GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + + bus-range = <0x00 0xff>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */ + 0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */ + 0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0xa0000000 0xa0000000 0 0x08000000 /* non-prefetchable memory */ + 0xc2000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */ + + clocks = <&tegra_car TEGRA20_CLK_PEX>, + <&tegra_car TEGRA20_CLK_AFI>, + <&tegra_car TEGRA20_CLK_PCIE_XCLK>, + <&tegra_car TEGRA20_CLK_PLL_E>; + clock-names = "pex", "afi", "pcie_xclk", "pll_e"; + status = "disabled"; + + pci at 1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>; + reg = <0x000800 0 0 0 0>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <2>; + }; + + pci at 2,0 { + device_type = "pci"; + assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>; + reg = <0x001000 0 0 0 0>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <2>; + }; + }; + usb at c5000000 { compatible = "nvidia,tegra20-ehci", "usb-ehci"; reg = <0xc5000000 0x4000>;
include/dt-bindings/clock/tegra20-car.h +1 -1
@@ -92,7 +92,7 @@#define TEGRA20_CLK_OWR 71#define TEGRA20_CLK_AFI 72#define TEGRA20_CLK_CSITE 73 -/* 74 */ +#define TEGRA20_CLK_PCIE_XCLK 74#define TEGRA20_CLK_AVPUCQ 75#define TEGRA20_CLK_LA 76/* 77 */
Signature · 1 line
2.2.0.rc0.207.ga3a616c
PATCH v4 10/23 ARM: tegra: Enable PCIe on TrimSlice
In reply to Simon GlassFrom: Thierry Reding <[email protected]>
The TrimSlice has an ethernet NIC connected to the PCIe bus. Enable the PCIe controller and the network driver so that the device can boot over the network.
---
Changes in v4: None
Changes in v3: None
arch/arm/dts/tegra20-trimslice.dts | 69 ++++++++++++++++++++++++++++++++++++ board/compulab/trimslice/trimslice.c | 8 +++++ include/configs/trimslice.h | 10 ++++++ 3 files changed, 87 insertions(+)
arch/arm/dts/tegra20-trimslice.dts +69 -0
@@ -47,6 +47,20 @@ status = "disabled"; }; + pcie-controller at 80003000 { + status = "okay"; + + avdd-pex-supply = <&pci_vdd_reg>; + vdd-pex-supply = <&pci_vdd_reg>; + avdd-pex-pll-supply = <&pci_vdd_reg>; + avdd-plle-supply = <&pci_vdd_reg>; + vddio-pex-clk-supply = <&pci_clk_reg>; + + pci at 1,0 { + status = "okay"; + }; + }; + usb at c5000000 { nvidia,vbus-gpio = <&gpio 170 0>; /* PV2 */ };
@@ -66,4 +80,59 @@ wp-gpios = <&gpio 122 0>; /* gpio PP2 */ bus-width = <4>; }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + hdmi_vdd_reg: regulator at 0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "avdd_hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + hdmi_pll_reg: regulator at 1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "avdd_hdmi_pll"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vbus_reg: regulator at 2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(V, 2) 0>; + regulator-always-on; + regulator-boot-on; + }; + + pci_clk_reg: regulator at 3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "pci_clk"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + pci_vdd_reg: regulator at 4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "pci_vdd"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + }; + }; + };
board/compulab/trimslice/trimslice.c +8 -0
@@ -13,6 +13,7 @@#include <asm/arch/pinmux.h> #include <asm/gpio.h> #include <i2c.h> +#include <netdev.h> void pin_mux_usb (void ) {
@@ -40,3 +41,10 @@ void pin_mux_mmc(void)/* For CD GPIO PP1 */ pinmux_tristate_disable (PMUX_PINGRP_DAP3 ); } + +#ifdef CONFIG_PCI +int board_eth_init (bd_t *bis) +{ +return pci_eth_init (bis); +} +#endif
include/configs/trimslice.h +10 -0
@@ -60,6 +60,16 @@#define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_ASIX +/* PCI host support */ +#define CONFIG_PCI +#define CONFIG_PCI_TEGRA +#define CONFIG_PCI_PNP +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PCI_ENUM + +/* PCI networking support */ +#define CONFIG_RTL8169 +/* General networking support */ #define CONFIG_CMD_NET #define CONFIG_CMD_DHCP
Signature · 1 line
2.2.0.rc0.207.ga3a616c
PATCH v4 11/23 ARM: tegra: Add GIC for Tegra30
In reply to Simon GlassFrom: Thierry Reding <[email protected]>
Add a device tree node for the GIC found on Tegra30. U-Boot doesn't use it directly but subsequent patches will add device tree nodes that reference it by phandle.
---
Changes in v4: None
Changes in v3: None
arch/arm/dts/tegra30.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+)
arch/arm/dts/tegra30.dtsi +9 -0
@@ -6,6 +6,15 @@ / { compatible = "nvidia,tegra30"; + interrupt-parent = <&intc>; + + intc: interrupt-controller at 50041000 { + compatible = "arm,cortex-a9-gic"; + reg = <0x50041000 0x1000 + 0x50040100 0x0100>; + interrupt-controller; + #interrupt-cells = <3>; + }; tegra_car: clock { compatible = "nvidia,tegra30-car";
Signature · 1 line
2.2.0.rc0.207.ga3a616c
PATCH v4 12/23 ARM: tegra: Add Tegra30 PCIe device tree node
In reply to Simon GlassFrom: Thierry Reding <[email protected]>
Add the device tree node for the PCIe controller found on Tegra30 SoCs.
---
Changes in v4: None
Changes in v3: None
arch/arm/dts/tegra30.dtsi | 74 +++++++++++++++++++++++++++++++++ include/dt-bindings/clock/tegra30-car.h | 2 +- 2 files changed, 75 insertions(+), 1 deletion(-)
arch/arm/dts/tegra30.dtsi +74 -0
@@ -16,6 +16,80 @@ #interrupt-cells = <3>; }; + pcie-controller at 00003000 { + compatible = "nvidia,tegra30-pcie"; + device_type = "pci"; + reg = <0x00003000 0x00000800 /* PADS registers */ + 0x00003800 0x00000200 /* AFI registers */ + 0x10000000 0x10000000>; /* configuration space */ + reg-names = "pads", "afi", "cs"; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */ + GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + + bus-range = <0x00 0xff>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */ + 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */ + 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */ + 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x20000000 0x20000000 0 0x10000000 /* non-prefetchable memory */ + 0xc2000000 0 0x30000000 0x30000000 0 0x10000000>; /* prefetchable memory */ + + clocks = <&tegra_car TEGRA30_CLK_PCIE>, + <&tegra_car TEGRA30_CLK_AFI>, + <&tegra_car TEGRA30_CLK_PCIEX>, + <&tegra_car TEGRA30_CLK_PLL_E>, + <&tegra_car TEGRA30_CLK_CML0>; + clock-names = "pex", "afi", "pcie_xclk", "pll_e", "cml"; + status = "disabled"; + + pci at 1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>; + reg = <0x000800 0 0 0 0>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <2>; + }; + + pci at 2,0 { + device_type = "pci"; + assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>; + reg = <0x001000 0 0 0 0>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <2>; + }; + + pci at 3,0 { + device_type = "pci"; + assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>; + reg = <0x001800 0 0 0 0>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <2>; + }; + }; + tegra_car: clock { compatible = "nvidia,tegra30-car"; reg = <0x60006000 0x1000>;
include/dt-bindings/clock/tegra30-car.h +1 -1
@@ -92,7 +92,7 @@#define TEGRA30_CLK_OWR 71#define TEGRA30_CLK_AFI 72#define TEGRA30_CLK_CSITE 73 -/* 74 */ +#define TEGRA30_CLK_PCIEX 74#define TEGRA30_CLK_AVPUCQ 75#define TEGRA30_CLK_LA 76/* 77 */
Signature · 1 line
2.2.0.rc0.207.ga3a616c
PATCH v4 13/23 ARM: tegra: Enable PCIe on Cardhu
In reply to Simon GlassFrom: Thierry Reding <[email protected]>
The PCIe bus on Cardhu is routed to the dock connector. An ethernet NIC is available on the dock over the PCIe bus. Enable the PCIe controller and the network device driver so that the device can boot over the network.
---
Changes in v4: None
Changes in v3:
- Use driver model to access the PMIC
arch/arm/dts/tegra30-cardhu.dts | 362 ++++++++++++++++++++++++++++++++++++++++ board/nvidia/cardhu/cardhu.c | 52 ++++++ include/configs/cardhu.h | 10 ++ 3 files changed, 424 insertions(+)
arch/arm/dts/tegra30-cardhu.dts +362 -0
@@ -27,6 +27,31 @@ reg = <0x80000000 0x40000000>; }; + pcie-controller at 00003000 { + status = "okay"; + + /* AVDD_PEXA and VDD_PEXA inputs are grounded on Cardhu. */ + avdd-pexb-supply = <&ldo1_reg>; + vdd-pexb-supply = <&ldo1_reg>; + avdd-pex-pll-supply = <&ldo1_reg>; + hvdd-pex-supply = <&pex_hvdd_3v3_reg>; + vddio-pex-ctl-supply = <&sys_3v3_reg>; + avdd-plle-supply = <&ldo2_reg>; + + pci at 1,0 { + nvidia,num-lanes = <4>; + }; + + pci at 2,0 { + nvidia,num-lanes = <1>; + }; + + pci at 3,0 { + status = "okay"; + nvidia,num-lanes = <1>; + }; + }; + i2c at 7000c000 { status = "okay"; clock-frequency = <100000>;
@@ -50,6 +75,107 @@ i2c at 7000d000 { status = "okay"; clock-frequency = <100000>; + + pmic: tps65911 at 2d { + compatible = "ti,tps65911"; + reg = <0x2d>; + + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <2>; + interrupt-controller; + + ti,system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + + vcc1-supply = <&vdd_ac_bat_reg>; + vcc2-supply = <&vdd_ac_bat_reg>; + vcc3-supply = <&vio_reg>; + vcc4-supply = <&vdd_5v0_reg>; + vcc5-supply = <&vdd_ac_bat_reg>; + vcc6-supply = <&vdd2_reg>; + vcc7-supply = <&vdd_ac_bat_reg>; + vccio-supply = <&vdd_ac_bat_reg>; + + regulators { + vdd1_reg: vdd1 { + regulator-name = "vddio_ddr_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vdd2_reg: vdd2 { + regulator-name = "vdd_1v5_gen"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + vddctrl_reg: vddctrl { + regulator-name = "vdd_cpu,vdd_sys"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vio_reg: vio { + regulator-name = "vdd_1v8_gen"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo1_reg: ldo1 { + regulator-name = "vdd_pexa,vdd_pexb"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + ldo2_reg: ldo2 { + regulator-name = "vdd_sata,avdd_plle"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + /* LDO3 is not connected to anything */ + + ldo4_reg: ldo4 { + regulator-name = "vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo5_reg: ldo5 { + regulator-name = "vddio_sdmmc,avdd_vdac"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo6_reg: ldo6 { + regulator-name = "avdd_dsi_csi,pwrdet_mipi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo7_reg: ldo7 { + regulator-name = "vdd_pllm,x,u,a_p_c_s"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo8_reg: ldo8 { + regulator-name = "vdd_ddr_hs"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + }; + }; }; spi at 7000da00 {
@@ -74,4 +200,240 @@ nvidia,vbus-gpio = <&gpio 236 0>; /* PDD4 */ status = "okay"; }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + vdd_ac_bat_reg: regulator at 0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "vdd_ac_bat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + cam_1v8_reg: regulator at 1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "cam_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>; + vin-supply = <&vio_reg>; + }; + + cp_5v_reg: regulator at 2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "cp_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + enable-active-high; + gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; + }; + + emmc_3v3_reg: regulator at 3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "emmc_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>; + vin-supply = <&sys_3v3_reg>; + }; + + modem_3v3_reg: regulator at 4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "modem_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>; + }; + + pex_hvdd_3v3_reg: regulator at 5 { + compatible = "regulator-fixed"; + reg = <5>; + regulator-name = "pex_hvdd_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>; + vin-supply = <&sys_3v3_reg>; + }; + + vdd_cam1_ldo_reg: regulator at 6 { + compatible = "regulator-fixed"; + reg = <6>; + regulator-name = "vdd_cam1_ldo"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>; + vin-supply = <&sys_3v3_reg>; + }; + + vdd_cam2_ldo_reg: regulator at 7 { + compatible = "regulator-fixed"; + reg = <7>; + regulator-name = "vdd_cam2_ldo"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>; + vin-supply = <&sys_3v3_reg>; + }; + + vdd_cam3_ldo_reg: regulator at 8 { + compatible = "regulator-fixed"; + reg = <8>; + regulator-name = "vdd_cam3_ldo"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>; + vin-supply = <&sys_3v3_reg>; + }; + + vdd_com_reg: regulator at 9 { + compatible = "regulator-fixed"; + reg = <9>; + regulator-name = "vdd_com"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>; + vin-supply = <&sys_3v3_reg>; + }; + + vdd_fuse_3v3_reg: regulator at 10 { + compatible = "regulator-fixed"; + reg = <10>; + regulator-name = "vdd_fuse_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>; + vin-supply = <&sys_3v3_reg>; + }; + + vdd_pnl1_reg: regulator at 11 { + compatible = "regulator-fixed"; + reg = <11>; + regulator-name = "vdd_pnl1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>; + vin-supply = <&sys_3v3_reg>; + }; + + vdd_vid_reg: regulator at 12 { + compatible = "regulator-fixed"; + reg = <12>; + regulator-name = "vddio_vid"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>; + gpio-open-drain; + vin-supply = <&vdd_5v0_reg>; + }; + + ddr_reg: regulator at 100 { + compatible = "regulator-fixed"; + regulator-name = "ddr"; + reg = <100>; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; + }; + + sys_3v3_reg: regulator at 101 { + compatible = "regulator-fixed"; + reg = <101>; + regulator-name = "sys_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; + }; + + usb1_vbus_reg: regulator at 102 { + compatible = "regulator-fixed"; + reg = <102>; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>; + gpio-open-drain; + vin-supply = <&vdd_5v0_reg>; + }; + + usb3_vbus_reg: regulator at 103 { + compatible = "regulator-fixed"; + reg = <103>; + regulator-name = "usb3_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>; + gpio-open-drain; + vin-supply = <&vdd_5v0_reg>; + }; + + vdd_5v0_reg: regulator at 104 { + compatible = "regulator-fixed"; + reg = <104>; + regulator-name = "5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&pmic 8 GPIO_ACTIVE_HIGH>; + }; + + vdd_bl_reg: regulator at 105 { + compatible = "regulator-fixed"; + reg = <105>; + regulator-name = "vdd_bl"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>; + }; + + vdd_bl2_reg: regulator at 106 { + compatible = "regulator-fixed"; + reg = <106>; + regulator-name = "vdd_bl2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>; + }; + }; };
board/nvidia/cardhu/cardhu.c +52 -0
63 lines not on this page · raw message
include/configs/cardhu.h +10 -0
@@ -78,6 +78,16 @@#define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_ASIX +/* PCI host support */ +#define CONFIG_PCI +#define CONFIG_PCI_TEGRA +#define CONFIG_PCI_PNP +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PCI_ENUM + +/* PCI networking support */ +#define CONFIG_RTL8169 +/* General networking support */ #define CONFIG_CMD_NET #define CONFIG_CMD_DHCP
Signature · 1 line
2.2.0.rc0.207.ga3a616c
PATCH v4 14/23 ARM: tegra: Enable PCIe on Beaver
In reply to Simon GlassFrom: Thierry Reding <[email protected]>
The Beaver has an ethernet NIC connected to the PCIe bus. Enable the PCIe controller and the network device driver so that the device can boot over the network.
In addition the board has a mini-PCIe expansion slot.
---
Changes in v4: None
Changes in v3: None
arch/arm/dts/tegra30-beaver.dts | 245 ++++++++++++++++++++++++++++++++++++++++ include/configs/beaver.h | 10 ++ 2 files changed, 255 insertions(+)
arch/arm/dts/tegra30-beaver.dts +245 -0
@@ -28,6 +28,33 @@ reg = <0x80000000 0x7ff00000>; }; + pcie-controller at 00003000 { + status = "okay"; + + avdd-pexa-supply = <&ldo1_reg>; + vdd-pexa-supply = <&ldo1_reg>; + avdd-pexb-supply = <&ldo1_reg>; + vdd-pexb-supply = <&ldo1_reg>; + avdd-pex-pll-supply = <&ldo1_reg>; + avdd-plle-supply = <&ldo1_reg>; + vddio-pex-ctl-supply = <&sys_3v3_reg>; + hvdd-pex-supply = <&sys_3v3_pexs_reg>; + + pci at 1,0 { + status = "okay"; + nvidia,num-lanes = <2>; + }; + + pci at 2,0 { + nvidia,num-lanes = <2>; + }; + + pci at 3,0 { + status = "okay"; + nvidia,num-lanes = <2>; + }; + }; + i2c at 7000c000 { status = "okay"; clock-frequency = <100000>;
@@ -51,6 +78,110 @@ i2c at 7000d000 { status = "okay"; clock-frequency = <100000>; + + pmic: tps65911 at 2d { + compatible = "ti,tps65911"; + reg = <0x2d>; + + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <2>; + interrupt-controller; + + ti,system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + + vcc1-supply = <&vdd_5v_in_reg>; + vcc2-supply = <&vdd_5v_in_reg>; + vcc3-supply = <&vio_reg>; + vcc4-supply = <&vdd_5v_in_reg>; + vcc5-supply = <&vdd_5v_in_reg>; + vcc6-supply = <&vdd2_reg>; + vcc7-supply = <&vdd_5v_in_reg>; + vccio-supply = <&vdd_5v_in_reg>; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + vdd1_reg: vdd1 { + regulator-name = "vddio_ddr_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vdd2_reg: vdd2 { + regulator-name = "vdd_1v5_gen"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + vddctrl_reg: vddctrl { + regulator-name = "vdd_cpu,vdd_sys"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vio_reg: vio { + regulator-name = "vdd_1v8_gen"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo1_reg: ldo1 { + regulator-name = "vdd_pexa,vdd_pexb"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + ldo2_reg: ldo2 { + regulator-name = "vdd_sata,avdd_plle"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + /* LDO3 is not connected to anything */ + + ldo4_reg: ldo4 { + regulator-name = "vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo5_reg: ldo5 { + regulator-name = "vddio_sdmmc,avdd_vdac"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo6_reg: ldo6 { + regulator-name = "avdd_dsi_csi,pwrdet_mipi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo7_reg: ldo7 { + regulator-name = "vdd_pllm,x,u,a_p_c_s"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo8_reg: ldo8 { + regulator-name = "vdd_ddr_hs"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + }; + }; }; spi at 7000da00 {
@@ -86,4 +217,118 @@ nvidia,vbus-gpio = <&gpio 236 0>; /* PDD4 */ status = "okay"; }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + vdd_5v_in_reg: regulator at 0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "vdd_5v_in"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + chargepump_5v_reg: regulator at 1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "chargepump_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + enable-active-high; + gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; + }; + + ddr_reg: regulator at 2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; + vin-supply = <&vdd_5v_in_reg>; + }; + + vdd_5v_sata_reg: regulator at 3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "vdd_5v_sata"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>; + vin-supply = <&vdd_5v_in_reg>; + }; + + usb1_vbus_reg: regulator at 4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>; + gpio-open-drain; + vin-supply = <&vdd_5v_in_reg>; + }; + + usb3_vbus_reg: regulator at 5 { + compatible = "regulator-fixed"; + reg = <5>; + regulator-name = "usb3_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>; + gpio-open-drain; + vin-supply = <&vdd_5v_in_reg>; + }; + + sys_3v3_reg: regulator at 6 { + compatible = "regulator-fixed"; + reg = <6>; + regulator-name = "sys_3v3,vdd_3v3_alw"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; + vin-supply = <&vdd_5v_in_reg>; + }; + + sys_3v3_pexs_reg: regulator at 7 { + compatible = "regulator-fixed"; + reg = <7>; + regulator-name = "sys_3v3_pexs"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>; + vin-supply = <&sys_3v3_reg>; + }; + + vdd_5v0_hdmi: regulator at 8 { + compatible = "regulator-fixed"; + reg = <8>; + regulator-name = "+VDD_5V_HDMI"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&sys_3v3_reg>; + }; + }; };
include/configs/beaver.h +10 -0
@@ -76,6 +76,16 @@#define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_ASIX +/* PCI host support */ +#define CONFIG_PCI +#define CONFIG_PCI_TEGRA +#define CONFIG_PCI_PNP +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PCI_ENUM + +/* PCI networking support */ +#define CONFIG_RTL8169 +/* General networking support */ #define CONFIG_CMD_NET #define CONFIG_CMD_DHCP
Signature · 1 line
2.2.0.rc0.207.ga3a616c
PATCH v4 15/23 ARM: tegra: Add GIC for Tegra124
In reply to Simon GlassFrom: Thierry Reding <[email protected]>
Add a device tree node for the GIC v2 found on the Cortex-A15 CPU complex of Tegra124. U-Boot doesn't use this but subsequent patches will add device tree nodes that reference it by phandle.
---
Changes in v4: None
Changes in v3: None
arch/arm/dts/tegra124.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+)
arch/arm/dts/tegra124.dtsi +13 -0
@@ -8,6 +8,19 @@ / { compatible = "nvidia,tegra124"; + interrupt-parent = <&gic>; + + gic: interrupt-controller at 50041000 { + compatible = "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x50041000 0x1000>, + <0x50042000 0x2000>, + <0x50044000 0x2000>, + <0x50046000 0x2000>; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; tegra_car: clock at 60006000 { compatible = "nvidia,tegra124-car";
Signature · 1 line
2.2.0.rc0.207.ga3a616c
PATCH v4 16/23 ARM: tegra: Add Tegra124 PCIe device tree node
In reply to Simon GlassFrom: Thierry Reding <[email protected]>
Add the device tree node for the PCIe controller found on Tegra124 SoCs.
---
Changes in v4: None
Changes in v3: None
arch/arm/dts/tegra124.dtsi | 66 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+)
arch/arm/dts/tegra124.dtsi +66 -0
@@ -10,6 +10,72 @@ compatible = "nvidia,tegra124"; interrupt-parent = <&gic>; + pcie-controller at 01003000 { + compatible = "nvidia,tegra124-pcie"; + device_type = "pci"; + reg = <0x01003000 0x00000800 /* PADS registers */ + 0x01003800 0x00000800 /* AFI registers */ + 0x02000000 0x10000000>; /* configuration space */ + reg-names = "pads", "afi", "cs"; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + + bus-range = <0x00 0xff>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x82000000 0 0x01000000 0x01000000 0 0x00001000 /* port 0 configuration space */ + 0x82000000 0 0x01001000 0x01001000 0 0x00001000 /* port 1 configuration space */ + 0x81000000 0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */ + 0x82000000 0 0x13000000 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */ + 0xc2000000 0 0x20000000 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ + + clocks = <&tegra_car TEGRA124_CLK_PCIE>, + <&tegra_car TEGRA124_CLK_AFI>, + <&tegra_car TEGRA124_CLK_PLL_E>, + <&tegra_car TEGRA124_CLK_CML0>; + clock-names = "pex", "afi", "pll_e", "cml"; + resets = <&tegra_car 70>, + <&tegra_car 72>, + <&tegra_car 74>; + reset-names = "pex", "afi", "pcie_x"; + status = "disabled"; + + phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>; + phy-names = "pcie"; + + pci at 1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; + reg = <0x000800 0 0 0 0>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <2>; + }; + + pci at 2,0 { + device_type = "pci"; + assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; + reg = <0x001000 0 0 0 0>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <1>; + }; + }; + gic: interrupt-controller at 50041000 { compatible = "arm,cortex-a15-gic"; #interrupt-cells = <3>;
Signature · 1 line
2.2.0.rc0.207.ga3a616c
PATCH v4 17/23 ARM: tegra: Enable PCIe on Jetson TK1
In reply to Simon GlassFrom: Thierry Reding <[email protected]>
The Jetson TK1 has an ethernet NIC connected to the PCIe bus and routes the second root port to a miniPCIe slot. Enable the PCIe controller and the network driver to allow the device to boot over the network.
---
Changes in v4: None
Changes in v3:
- Use driver model to access the PMIC
arch/arm/dts/tegra124-jetson-tk1.dts | 347 +++++++++++++++++++++++++++++++++++ board/nvidia/jetson-tk1/jetson-tk1.c | 52 ++++++ include/configs/jetson-tk1.h | 13 ++ 3 files changed, 412 insertions(+)
arch/arm/dts/tegra124-jetson-tk1.dts +347 -0
@@ -29,6 +29,26 @@ reg = <0x80000000 0x80000000>; }; + pcie-controller at 01003000 { + status = "okay"; + + avddio-pex-supply = <&vdd_1v05_run>; + dvddio-pex-supply = <&vdd_1v05_run>; + avdd-pex-pll-supply = <&vdd_1v05_run>; + hvdd-pex-supply = <&vdd_3v3_lp0>; + hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>; + vddio-pex-ctl-supply = <&vdd_3v3_lp0>; + avdd-pll-erefe-supply = <&avdd_1v05_run>; + + pci at 1,0 { + status = "okay"; + }; + + pci at 2,0 { + status = "okay"; + }; + }; + i2c at 7000c000 { status = "okay"; clock-frequency = <100000>;
@@ -49,9 +69,195 @@ clock-frequency = <100000>; }; + /* Expansion PWR_I2C_*, on-board components */ i2c at 7000d000 { status = "okay"; clock-frequency = <400000>; + + pmic: pmic at 40 { + compatible = "ams,as3722"; + reg = <0x40>; + interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; + + ams,system-power-controller; + + #interrupt-cells = <2>; + interrupt-controller; + + gpio-controller; + #gpio-cells = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&as3722_default>; + + as3722_default: pinmux { + gpio0 { + pins = "gpio0"; + function = "gpio"; + bias-pull-down; + }; + + gpio1_2_4_7 { + pins = "gpio1", "gpio2", "gpio4", "gpio7"; + function = "gpio"; + bias-pull-up; + }; + + gpio3_5_6 { + pins = "gpio3", "gpio5", "gpio6"; + bias-high-impedance; + }; + }; + + regulators { + vsup-sd2-supply = <&vdd_5v0_sys>; + vsup-sd3-supply = <&vdd_5v0_sys>; + vsup-sd4-supply = <&vdd_5v0_sys>; + vsup-sd5-supply = <&vdd_5v0_sys>; + vin-ldo0-supply = <&vdd_1v35_lp0>; + vin-ldo1-6-supply = <&vdd_3v3_run>; + vin-ldo2-5-7-supply = <&vddio_1v8>; + vin-ldo3-4-supply = <&vdd_3v3_sys>; + vin-ldo9-10-supply = <&vdd_5v0_sys>; + vin-ldo11-supply = <&vdd_3v3_run>; + + sd0 { + regulator-name = "+VDD_CPU_AP"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1400000>; + regulator-min-microamp = <3500000>; + regulator-max-microamp = <3500000>; + regulator-always-on; + regulator-boot-on; + ams,ext-control = <2>; + }; + + sd1 { + regulator-name = "+VDD_CORE"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-min-microamp = <2500000>; + regulator-max-microamp = <2500000>; + regulator-always-on; + regulator-boot-on; + ams,ext-control = <1>; + }; + + vdd_1v35_lp0: sd2 { + regulator-name = "+1.35V_LP0(sd2)"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + sd3 { + regulator-name = "+1.35V_LP0(sd3)"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_1v05_run: sd4 { + regulator-name = "+1.05V_RUN"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + vddio_1v8: sd5 { + regulator-name = "+1.8V_VDDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd_gpu: sd6 { + regulator-name = "+VDD_GPU_AP"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <1200000>; + regulator-min-microamp = <3500000>; + regulator-max-microamp = <3500000>; + regulator-boot-on; + regulator-always-on; + }; + + avdd_1v05_run: ldo0 { + regulator-name = "+1.05V_RUN_AVDD"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-boot-on; + regulator-always-on; + ams,ext-control = <1>; + }; + + ldo1 { + regulator-name = "+1.8V_RUN_CAM"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo2 { + regulator-name = "+1.2V_GEN_AVDD"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3 { + regulator-name = "+1.05V_LP0_VDD_RTC"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + ams,enable-tracking; + }; + + ldo4 { + regulator-name = "+2.8V_RUN_CAM"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo5 { + regulator-name = "+1.2V_RUN_CAM_FRONT"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vddio_sdmmc3: ldo6 { + regulator-name = "+VDDIO_SDMMC3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + ldo7 { + regulator-name = "+1.05V_RUN_CAM_REAR"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + ldo9 { + regulator-name = "+3.3V_RUN_TOUCH"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo10 { + regulator-name = "+2.8V_RUN_CAM_AF"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo11 { + regulator-name = "+1.8V_RUN_VPP_FUSE"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + }; }; i2c at 7000d100 {
@@ -117,4 +323,145 @@ status = "okay"; nvidia,vbus-gpio = <&gpio 109 0>; /* gpio PN5, USB_VBUS_EN1 */ }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + vdd_mux: regulator at 0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "+VDD_MUX"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_5v0_sys: regulator at 1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "+5V_SYS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_mux>; + }; + + vdd_3v3_sys: regulator at 2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "+3.3V_SYS"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_mux>; + }; + + vdd_3v3_run: regulator at 3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "+3.3V_RUN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + vdd_3v3_hdmi: regulator at 4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdd_3v3_run>; + }; + + vdd_usb1_vbus: regulator at 7 { + compatible = "regulator-fixed"; + reg = <7>; + regulator-name = "+USB0_VBUS_SW"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; + enable-active-high; + gpio-open-drain; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_usb3_vbus: regulator at 8 { + compatible = "regulator-fixed"; + reg = <8>; + regulator-name = "+5V_USB_HS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + gpio-open-drain; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_3v3_lp0: regulator at 10 { + compatible = "regulator-fixed"; + reg = <10>; + regulator-name = "+3.3V_LP0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + vdd_hdmi_pll: regulator at 11 { + compatible = "regulator-fixed"; + reg = <11>; + regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; + vin-supply = <&vdd_1v05_run>; + }; + + vdd_5v0_hdmi: regulator at 12 { + compatible = "regulator-fixed"; + reg = <12>; + regulator-name = "+5V_HDMI_CON"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + + /* Molex power connector */ + vdd_5v0_sata: regulator at 13 { + compatible = "regulator-fixed"; + reg = <13>; + regulator-name = "+5V_SATA"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_12v0_sata: regulator at 14 { + compatible = "regulator-fixed"; + reg = <14>; + regulator-name = "+12V_SATA"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_mux>; + }; + }; };
board/nvidia/jetson-tk1/jetson-tk1.c +52 -0
65 lines not on this page · raw message
include/configs/jetson-tk1.h +13 -0
@@ -10,6 +10,9 @@#include <linux/sizes.h> +/* enable PMIC */ +#define CONFIG_AS3722_POWER +#include "tegra124-common.h" /* High-level configuration options */
@@ -61,6 +64,16 @@#define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_ASIX +/* PCI host support */ +#define CONFIG_PCI +#define CONFIG_PCI_TEGRA +#define CONFIG_PCI_PNP +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PCI_ENUM + +/* PCI networking support */ +#define CONFIG_RTL8169 +/* General networking support */ #define CONFIG_CMD_NET #define CONFIG_CMD_DHCP
Signature · 1 line
2.2.0.rc0.207.ga3a616c
PATCH v4 18/23 ARM: Implement non-cached memory support
In reply to Simon GlassFrom: Thierry Reding <[email protected]>
Implement an API that can be used by drivers to allocate memory from a pool that is mapped uncached. This is useful if drivers would otherwise need to do extensive cache maintenance (or explicitly maintaining the cache isn't safe).
The API is protected using the new CONFIG_SYS_NONCACHED_MEMORY setting. Boards can set this to the size to be used for the non-cached area. The area will typically be right below the malloc() area, but architectures should take care of aligning the beginning and end of the area to honor any mapping restrictions. Architectures must also ensure that mappings established for this area do not overlap with the malloc() area (which should remain cached for improved performance).
While the API is currently only implemented for ARM v7, it should be generic enough to allow other architectures to implement it as well.
---
Changes in v4: None
Changes in v3:
- Avoid build error with noncached_init() when the dcache is disabled
README | 19 +++++++++++++++++++ arch/arm/include/asm/system.h | 5 +++++ arch/arm/lib/cache.c | 44 +++++++++++++++++++++++++++++++++++++++++++ common/board_r.c | 11 +++++++++++ 4 files changed, 79 insertions(+)
README +19 -0
@@ -4007,6 +4007,25 @@ Configuration Settings: boards which do not use the full malloc in SPL (which is enabled with CONFIG_SYS_SPL_MALLOC_START). +- CONFIG_SYS_NONCACHED_MEMORY: + Size of non-cached memory area. This area of memory will be + typically located right below the malloc() area and mapped + uncached in the MMU. This is useful for drivers that would + otherwise require a lot of explicit cache maintenance. For + some drivers it's also impossible to properly maintain the + cache. For example if the regions that need to be flushed + are not a multiple of the cache-line size, *and* padding + cannot be allocated between the regions to align them (i.e. + if the HW requires a contiguous array of regions, and the + size of each region is not cache-aligned), then a flush of + one region may result in overwriting data that hardware has + written to another region in the same cache-line. This can + happen for example in network drivers where descriptors for + buffers are typically smaller than the CPU cache-line (e.g. + 16 bytes vs. 32 or 64 bytes). + + Non-cached memory is only supported on 32-bit ARM at present. + - CONFIG_SYS_BOOTM_LEN: Normally compressed uImages are limited to an uncompressed size of 8 MBytes. If this is not enough,
arch/arm/include/asm/system.h +5 -0
@@ -212,6 +212,11 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,*/ void mmu_page_table_flush (unsigned long start,unsigned long stop); +#ifdef CONFIG_SYS_NONCACHED_MEMORY +void noncached_init (void ); +phys_addr_t noncached_alloc (size_t size,size_t align); +#endif /* CONFIG_SYS_NONCACHED_MEMORY */ +#endif /* __ASSEMBLY__ */ #define arch_align_stack (x) (x)
arch/arm/lib/cache.c +44 -0
53 lines not on this page · raw message
common/board_r.c +11 -0
@@ -265,6 +265,14 @@ static int initr_malloc(void)return 0 ; } +#ifdef CONFIG_SYS_NONCACHED_MEMORY +static int initr_noncached (void ) +{ +noncached_init (); +return 0 ; +} +#endif +#ifdef CONFIG_DM static int initr_dm (void ) {
@@ -687,6 +695,9 @@ init_fnc_t init_sequence_r[] = {#endif initr_barrier, initr_malloc, +#ifdef CONFIG_SYS_NONCACHED_MEMORY + initr_noncached, +#endif bootstage_relocate,#ifdef CONFIG_DM initr_dm,
Signature · 1 line
2.2.0.rc0.207.ga3a616c
PATCH v4 18/23 ARM: Implement non-cached memory support
Hi Albert,
Quoted 26 lines · Simon Glass
From: Thierry Reding <[email protected]>
Implement an API that can be used by drivers to allocate memory from a pool that is mapped uncached. This is useful if drivers would otherwise need to do extensive cache maintenance (or explicitly maintaining the cache isn't safe).
The API is protected using the new
CONFIG_SYS_NONCACHED_MEMORYsetting. Boards can set this to the size to be used for the non-cached area. The area will typically be right below themalloc()area, but architectures should take care of aligning the beginning and end of the area to honor any mapping restrictions. Architectures must also ensure that mappings established for this area do not overlap with themalloc()area (which should remain cached for improved performance).While the API is currently only implemented for ARM v7, it should be generic enough to allow other architectures to implement it as well.
Signed-off-by Thierry Reding <[email protected]>Signed-off-by Simon Glass <[email protected]>---
Changes in v4: None
Changes in v3:
- Avoid build error withnoncached_init()when the dcache is disabled
Quoted 5 lines
README | 19 +++++++++++++++++++ arch/arm/include/asm/system.h | 5 +++++ arch/arm/lib/cache.c | 44 +++++++++++++++++++++++++++++++++++++++++++ common/board_r.c | 11 +++++++++++ 4 files changed, 79 insertions(+)
I think you have applied the other cache patches. Are you OK with this one? I would like to get this series applied very soon (after DM I2C) as it's been around since August.
Quoted 136 lines
README +19
-0@@ -4007,6 +4007,25 @@ Configuration Settings: boards which do not use the full malloc in SPL (which is enabled with CONFIG_SYS_SPL_MALLOC_START). +- CONFIG_SYS_NONCACHED_MEMORY: + Size of non-cached memory area. This area of memory will be + typically located right below the malloc() area and mapped + uncached in the MMU. This is useful for drivers that would + otherwise require a lot of explicit cache maintenance. For + some drivers it's also impossible to properly maintain the + cache. For example if the regions that need to be flushed + are not a multiple of the cache-line size, *and* padding + cannot be allocated between the regions to align them (i.e. + if the HW requires a contiguous array of regions, and the + size of each region is not cache-aligned), then a flush of + one region may result in overwriting data that hardware has + written to another region in the same cache-line. This can + happen for example in network drivers where descriptors for + buffers are typically smaller than the CPU cache-line (e.g. + 16 bytes vs. 32 or 64 bytes). + + Non-cached memory is only supported on 32-bit ARM at present. + - CONFIG_SYS_BOOTM_LEN: Normally compressed uImages are limited to an uncompressed size of 8 MBytes. If this is not enough,arch/arm/include/asm/system.h +5
-0@@ -212,6 +212,11 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,*/ void mmu_page_table_flush (unsigned long start,unsigned long stop); +#ifdef CONFIG_SYS_NONCACHED_MEMORY +void noncached_init (void ); +phys_addr_t noncached_alloc (size_t size,size_t align); +#endif /* CONFIG_SYS_NONCACHED_MEMORY */ +#endif /* __ASSEMBLY__ */ #define arch_align_stack (x) (x)arch/arm/lib/cache.c +44
-0@@ -8,6 +8,7 @@/* for now: just dummy functions to satisfy the linker */ #include <common.h> +#include <malloc.h> __weak void flush_cache (unsigned long start,unsigned long size) {@@ -49,3 +50,46 @@ __weak void enable_caches(void) {puts ("WARNING: Caches not enabled\n" ); } + +#ifdef CONFIG_SYS_NONCACHED_MEMORY +/* +* Reserve one MMU section worth of address space below the malloc() area that +* will be mapped uncached. +*/ +static unsigned long noncached_start; +static unsigned long noncached_end; +static unsigned long noncached_next; + +void noncached_init (void ) +{ +phys_addr_t start, end; +size_t size; + + end =ALIGN (mem_malloc_start,MMU_SECTION_SIZE ) -MMU_SECTION_SIZE ; + size =ALIGN (CONFIG_SYS_NONCACHED_MEMORY ,MMU_SECTION_SIZE ); + start = end - size; + +debug ("mapping memory %pa-%pa non-cached\n" , &start, &end); + + noncached_start = start; + noncached_end = end; + noncached_next = start; + +#ifndef CONFIG_SYS_DCACHE_OFF +mmu_set_region_dcache_behaviour (noncached_start, size,DCACHE_OFF ); +#endif +} + +phys_addr_t noncached_alloc (size_t size,size_t align) +{ +phys_addr_t next =ALIGN (noncached_next, align); + +if (next >= noncached_end || (noncached_end - next) < size) +return 0 ; + +debug ("allocated %zu bytes of uncached memory @%pa\n" , size, &next); + noncached_next = next + size; + +return next; +} +#endif /* CONFIG_SYS_NONCACHED_MEMORY */ common/board_r.c +11
-1@@ -265,6 +265,14 @@ static int initr_malloc(void)return 0 ; } +#ifdef CONFIG_SYS_NONCACHED_MEMORY +static int initr_noncached (void ) +{ +noncached_init (); +return 0 ; +} +#endif +#ifdef CONFIG_DM static int initr_dm (void ) {@@ -687,6 +695,9 @@ init_fnc_t init_sequence_r[] = {#endif initr_barrier, initr_malloc, +#ifdef CONFIG_SYS_NONCACHED_MEMORY + initr_noncached, +#endif bootstage_relocate,#ifdef CONFIG_DM initr_dm, --
Quoted 2 lines
2.2.0.rc0.207.ga3a616c
Regards,
Simon
PATCH v4 18/23 ARM: Implement non-cached memory support
Hello Simon,
Quoted 35 lines · Simon Glass
Hi Albert,
Quoted 26 lines · Simon Glass
From: Thierry Reding <[email protected]>
Implement an API that can be used by drivers to allocate memory from a pool that is mapped uncached. This is useful if drivers would otherwise need to do extensive cache maintenance (or explicitly maintaining the cache isn't safe).
The API is protected using the new
CONFIG_SYS_NONCACHED_MEMORYsetting. Boards can set this to the size to be used for the non-cached area. The area will typically be right below themalloc()area, but architectures should take care of aligning the beginning and end of the area to honor any mapping restrictions. Architectures must also ensure that mappings established for this area do not overlap with themalloc()area (which should remain cached for improved performance).While the API is currently only implemented for ARM v7, it should be generic enough to allow other architectures to implement it as well.
Signed-off-by Thierry Reding <[email protected]>Signed-off-by Simon Glass <[email protected]>---
Changes in v4: None
Changes in v3:
- Avoid build error withnoncached_init()when the dcache is disabledQuoted 5 lines
README | 19 +++++++++++++++++++ arch/arm/include/asm/system.h | 5 +++++ arch/arm/lib/cache.c | 44 +++++++++++++++++++++++++++++++++++++++++++ common/board_r.c | 11 +++++++++++ 4 files changed, 79 insertions(+)
Quoted 3 lines
I think you have applied the other cache patches. Are you OK with this one? I would like to get this series applied very soon (after DM I2C) as it's been around since August.
This is delegated to Tom Warren in Patchwork. I'm delegating it to myself and applying it; if Tom has applied it too, this should not cause a major merge issue.
Amicalement,
Signature · 1 line
Albert.
PATCH v4 18/23 ARM: Implement non-cached memory support
Hi Albert,
Quoted 39 lines · Albert ARIBAUD
Hello Simon,
Quoted 35 lines · Simon Glass
Hi Albert,
Quoted 31 lines · Simon Glass
From: Thierry Reding <[email protected]>
Implement an API that can be used by drivers to allocate memory from a pool that is mapped uncached. This is useful if drivers would otherwise need to do extensive cache maintenance (or explicitly maintaining the cache isn't safe).
The API is protected using the new
CONFIG_SYS_NONCACHED_MEMORYsetting. Boards can set this to the size to be used for the non-cached area. The area will typically be right below themalloc()area, but architectures should take care of aligning the beginning and end of the area to honor any mapping restrictions. Architectures must also ensure that mappings established for this area do not overlap with themalloc()area (which should remain cached for improved performance).While the API is currently only implemented for ARM v7, it should be generic enough to allow other architectures to implement it as well.
Signed-off-by Thierry Reding <[email protected]>Signed-off-by Simon Glass <[email protected]>---
Changes in v4: None
Changes in v3:
- Avoid build error withnoncached_init()when the dcache is disabledREADME | 19 +++++++++++++++++++ arch/arm/include/asm/system.h | 5 +++++ arch/arm/lib/cache.c | 44 +++++++++++++++++++++++++++++++++++++++++++ common/board_r.c | 11 +++++++++++ 4 files changed, 79 insertions(+)
Quoted 7 lines
Quoted 3 lines
I think you have applied the other cache patches. Are you OK with this one? I would like to get this series applied very soon (after DM I2C) as it's been around since August.
This is delegated to Tom Warren in Patchwork. I'm delegating it to myself and applying it; if Tom has applied it too, this should not cause a major merge issue.
Agreed, sounds good, thanks.
Regards,
Simon
A message that is not in the archive (sent off-list or not yet received): [email protected]
PATCH v4 18/23 ARM: Implement non-cached memory support
Hello Tom,
Quoted 3 lines · Tom Warren
Albert,
Please pull u-boot-tegra.git/master into ARM master. ./MAKEALL -s tegra is clean.
I assume this is actually for Tom Rini, as non-core ARM trees now merge directly into mainline.1
Amicalement,
Signature · 1 line
Albert.
PATCH v4 18/23 ARM: Implement non-cached memory support
Hi Albert,
Quoted 10 lines · Albert ARIBAUD
Hello Tom,
Quoted 3 lines · Tom Warren
Albert,
Please pull u-boot-tegra.git/master into ARM master. ./MAKEALL -s tegra is clean.
I assume this is actually for Tom Rini, as non-core ARM trees now merge directly into mainline.1
Yes I think Tom Rini will apply this when he gets back.
Regards,
Simon
PATCH v4 19/23 ARM: tegra: Enable non-cached memory
In reply to Simon GlassFrom: Thierry Reding <[email protected]>
Some boards, most notably those with a PCIe ethernet NIC, require this to avoid cache coherency problems. Since the option adds very little code and overhead enable it across all Tegra generations. Other drivers may also start supporting this functionality at some point, so enabling it now will automatically reap the benefits later on.
---
Changes in v4: None
Changes in v3: None
include/configs/tegra-common.h | 2 ++ 1 file changed, 2 insertions(+)
include/configs/tegra-common.h +2 -0
@@ -50,6 +50,8 @@#ifdef CONFIG_SPL_BUILD #define CONFIG_SYS_MALLOC_SIMPLE #endif +#define CONFIG_SYS_NONCACHED_MEMORY (1 << 20)/* 1 MiB */ +/* * NS16550 Configuration */
Signature · 1 line
2.2.0.rc0.207.ga3a616c
PATCH v4 20/23 net: rtl8169: Honor CONFIG_SYS_RX_ETH_BUFFER
In reply to Simon GlassFrom: Thierry Reding <[email protected]>
According to the top-level README file, this configuration setting can be used to override the number of receive buffers that an ethernet NIC uses.
---
Changes in v4: None
Changes in v3: None
drivers/net/rtl8169.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)
drivers/net/rtl8169.c +5 -1
@@ -79,7 +79,11 @@ static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };#define InterFrameGap 0x03/* 3 means InterFrameGap = the shortest one */ #define NUM_TX_DESC 1/* Number of Tx descriptor registers */ -#define NUM_RX_DESC 4/* Number of Rx descriptor registers */ +#ifdef CONFIG_SYS_RX_ETH_BUFFER +#define NUM_RX_DESC CONFIG_SYS_RX_ETH_BUFFER +#else +#define NUM_RX_DESC 4/* Number of Rx descriptor registers */ +#endif #define RX_BUF_SIZE 1536/* Rx Buffer size */ #define RX_BUF_LEN 8192
Signature · 1 line
2.2.0.rc0.207.ga3a616c
PATCH v4 21/23 net: rtl8169: Properly align buffers
In reply to Simon GlassFrom: Thierry Reding <[email protected]>
RX and TX descriptor rings should be aligned to 256 byte boundaries. Use the DEFINE_ALIGN_BUFFER() macro to define the buffers so that they don't have to be manually aligned later on. Also make sure that the buffers do align to cache-line boundaries in case the cache-line is higher than the 256 byte alignment requirements of the NIC.
Also add a warning if the cache-line size is larger than the descriptor size, because the driver may discard changes to descriptors made by the hardware when requeuing RX buffers.
---
Changes in v4: None
Changes in v3: None
drivers/net/rtl8169.c | 63 +++++++++++++++++++++++++++------------------------ 1 file changed, 34 insertions(+), 29 deletions(-)
drivers/net/rtl8169.c +34 -29
@@ -277,23 +277,41 @@ struct RxDesc {u32 buf_Haddr; }; -/* Define the TX Descriptor */ -static u8 tx_ring[NUM_TX_DESC *sizeof (struct TxDesc ) +256 ]; -/* __attribute__ ((aligned(256))); */ +#define RTL8169_DESC_SIZE 16 -/* Create a static buffer of size RX_BUF_SZ for each -TX Descriptor. All descriptors point to a -part of this buffer */ -static unsigned char txb[NUM_TX_DESC *RX_BUF_SIZE ]; +#if ARCH_DMA_MINALIGN >256 +# define RTL8169_ALIGN ARCH_DMA_MINALIGN +#else +# define RTL8169_ALIGN 256 +#endif + +/* +* Warn if the cache-line size is larger than the descriptor size. In such +* cases the driver will likely fail because the CPU needs to flush the cache +* when requeuing RX buffers, therefore descriptors written by the hardware +* may be discarded. +*/ +#if RTL8169_DESC_SIZE <ARCH_DMA_MINALIGN +#warning cache-line size is larger than descriptor size +#endif + +/* Define the TX Descriptor */ +DEFINE_ALIGN_BUFFER(struct TxDesc, tx_ring, NUM_TX_DESC, RTL8169_ALIGN);/* Define the RX Descriptor */ -static u8 rx_ring[NUM_RX_DESC *sizeof (struct TxDesc ) +256 ]; -/* __attribute__ ((aligned(256))); */ +DEFINE_ALIGN_BUFFER(struct RxDesc, rx_ring, NUM_RX_DESC, RTL8169_ALIGN); -/* Create a static buffer of size RX_BUF_SZ for each -RX Descriptor All descriptors point to a -part of this buffer */ -static unsigned char rxb[NUM_RX_DESC *RX_BUF_SIZE ]; +/* +* Create a static buffer of size RX_BUF_SZ for each TX Descriptor. All +* descriptors point to a part of this buffer. +*/ +DEFINE_ALIGN_BUFFER (u8, txb,NUM_TX_DESC *RX_BUF_SIZE ,RTL8169_ALIGN ); + +/* +* Create a static buffer of size RX_BUF_SZ for each RX Descriptor. All +* descriptors point to a part of this buffer. +*/ +DEFINE_ALIGN_BUFFER (u8, rxb,NUM_RX_DESC *RX_BUF_SIZE ,RTL8169_ALIGN );struct rtl8169_private {void *mmio_addr;/* memory map physical address */
@@ -301,8 +319,6 @@ struct rtl8169_private {unsigned long cur_rx;/* Index into the Rx descriptor buffer of next Rx pkt. */ unsigned long cur_tx;/* Index into the Tx descriptor buffer of next Rx pkt. */ unsigned long dirty_tx; -unsigned char *TxDescArrays;/* Index of Tx Descriptor buffer */ -unsigned char *RxDescArrays;/* Index of Rx Descriptor buffer */ struct TxDesc *TxDescArray;/* Index of 256-alignment Tx Descriptor buffer */ struct RxDesc *RxDescArray;/* Index of 256-alignment Rx Descriptor buffer */ unsigned char *RxBufferRings;/* Index of Rx Buffer */
@@ -711,16 +727,6 @@ static int rtl_reset(struct eth_device *dev, bd_t *bis)printf ("%s\n" , __FUNCTION__);#endif - tpc->TxDescArrays = tx_ring; -/* Tx Desscriptor needs 256 bytes alignment; */ - tpc->TxDescArray = (struct TxDesc *) ((unsigned long )(tpc->TxDescArrays + -255 ) & ~255 ); - - tpc->RxDescArrays = rx_ring; -/* Rx Desscriptor needs 256 bytes alignment; */ - tpc->RxDescArray = (struct RxDesc *) ((unsigned long )(tpc->RxDescArrays + -255 ) & ~255 ); -rtl8169_init_ring (dev);rtl8169_hw_start (dev);/* Construct a perfect filter frame with the mac address as first match
@@ -762,10 +768,6 @@ static void rtl_halt(struct eth_device *dev)RTL_W32 (RxMissed,0 ); - tpc->TxDescArrays =NULL ; - tpc->RxDescArrays =NULL ; - tpc->TxDescArray =NULL ; - tpc->RxDescArray =NULL ;for (i =0 ; i <NUM_RX_DESC ; i++) { tpc->RxBufferRing[i] =NULL ; }
@@ -910,6 +912,9 @@ static int rtl_init(struct eth_device *dev, bd_t *bis)#endif } + tpc->TxDescArray = tx_ring; + tpc->RxDescArray = rx_ring; +return 1 ; }
Signature · 1 line
2.2.0.rc0.207.ga3a616c
PATCH v4 22/23 net: rtl8169: Use non-cached memory if available
In reply to Simon GlassFrom: Thierry Reding <[email protected]>
To work around potential issues with explicit cache maintenance of the RX and TX descriptor rings, allocate them from a pool of uncached memory if the architecture supports it.
---
Changes in v4:
- Insert missing word 'to' in a comment
Changes in v3:
- Remove cache-line size warning if dcache is disabled
drivers/net/rtl8169.c | 71 +++++++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 60 insertions(+), 11 deletions(-)
drivers/net/rtl8169.c +60 -11
@@ -41,6 +41,7 @@* Modified to use le32_to_cpu and cpu_to_le32 properly */ #include <common.h> +#include <errno.h> #include <malloc.h> #include <net.h> #include <netdev.h>
@@ -290,16 +291,15 @@ struct RxDesc {* cases the driver will likely fail because the CPU needs to flush the cache * when requeuing RX buffers, therefore descriptors written by the hardware * may be discarded. +* +* This can be fixed by defining CONFIG_SYS_NONCACHED_MEMORY which will cause +* the driver to allocate descriptors from a pool of non-cached memory. */ #if RTL8169_DESC_SIZE <ARCH_DMA_MINALIGN +#if !defined(CONFIG_SYS_NONCACHED_MEMORY ) && !defined(CONFIG_SYS_DCACHE_OFF )#warning cache-line size is larger than descriptor size#endif - -/* Define the TX Descriptor */ -DEFINE_ALIGN_BUFFER(struct TxDesc, tx_ring, NUM_TX_DESC, RTL8169_ALIGN); - -/* Define the RX Descriptor */ -DEFINE_ALIGN_BUFFER(struct RxDesc, rx_ring, NUM_RX_DESC, RTL8169_ALIGN); +#endif /* * Create a static buffer of size RX_BUF_SZ for each TX Descriptor. All
@@ -418,34 +418,71 @@ match: }/* +* TX and RX descriptors are 16 bytes. This causes problems with the cache +* maintenance on CPUs where the cache-line size exceeds the size of these +* descriptors. What will happen is that when the driver receives a packet +* it will be immediately requeued for the hardware to reuse. The CPU will +* therefore need to flush the cache-line containing the descriptor, which +* will cause all other descriptors in the same cache-line to be flushed +* along with it. If one of those descriptors had been written to by the +* device those changes (and the associated packet) will be lost. +* +* To work around this, we make use of non-cached memory if available. If +* descriptors are mapped uncached there's no need to manually flush them +* or invalidate them. +* +* Note that this only applies to descriptors. The packet data buffers do +* not have the same constraints since they are 1536 bytes large, so they +* are unlikely to share cache-lines. +*/ +static void *rtl_alloc_descs (unsigned int num) +{ +size_t size = num *RTL8169_DESC_SIZE ; + +#ifdef CONFIG_SYS_NONCACHED_MEMORY +return (void *)noncached_alloc (size,RTL8169_ALIGN ); +#else +return memalign (RTL8169_ALIGN , size); +#endif +} + +/* * Cache maintenance functions. These are simple wrappers around the more * general purpose flush_cache() and invalidate_dcache_range() functions. */ static void rtl_inval_rx_desc (struct RxDesc *desc) { +#ifndef CONFIG_SYS_NONCACHED_MEMORY unsigned long start = (unsigned long )desc & ~(ARCH_DMA_MINALIGN -1 );unsigned long end =ALIGN (start +sizeof (*desc),ARCH_DMA_MINALIGN );invalidate_dcache_range (start, end); +#endif }static void rtl_flush_rx_desc (struct RxDesc *desc) { +#ifndef CONFIG_SYS_NONCACHED_MEMORY flush_cache ((unsigned long )desc,sizeof (*desc)); +#endif }static void rtl_inval_tx_desc (struct TxDesc *desc) { +#ifndef CONFIG_SYS_NONCACHED_MEMORY unsigned long start = (unsigned long )desc & ~(ARCH_DMA_MINALIGN -1 );unsigned long end =ALIGN (start +sizeof (*desc),ARCH_DMA_MINALIGN );invalidate_dcache_range (start, end); +#endif }static void rtl_flush_tx_desc (struct TxDesc *desc) { +#ifndef CONFIG_SYS_NONCACHED_MEMORY flush_cache ((unsigned long )desc,sizeof (*desc)); +#endif }static void rtl_inval_buffer (void *buf,size_t size)
@@ -912,10 +949,16 @@ static int rtl_init(struct eth_device *dev, bd_t *bis)#endif } - tpc->TxDescArray = tx_ring; - tpc->RxDescArray = rx_ring; -return 1 ; + tpc->RxDescArray =rtl_alloc_descs (NUM_RX_DESC ); +if (!tpc->RxDescArray) +return -ENOMEM ; + + tpc->TxDescArray =rtl_alloc_descs (NUM_TX_DESC ); +if (!tpc->TxDescArray) +return -ENOMEM ; + +return 0 ; }int rtl8169_initialize (bd_t *bis)
@@ -929,6 +972,7 @@ int rtl8169_initialize(bd_t *bis)while (1 ){unsigned int region;u16 device; +int err;/* Find RTL8169 */ if ((devno =pci_find_devices (supported, idx++)) <0 )
@@ -967,9 +1011,14 @@ int rtl8169_initialize(bd_t *bis) dev->send = rtl_send; dev->recv = rtl_recv; -eth_register (dev); + err =rtl_init (dev, bis); +if (err <0 ) { +printf (pr_fmt ("failed to initialize card: %d\n" ), err); +free (dev); +continue ; + } -rtl_init (dev, bis); +eth_register (dev); card_number++; }
Signature · 1 line
2.2.0.rc0.207.ga3a616c
PATCH v4 23/23 net: rtl8169: Add support for RTL-8168/8111g
In reply to Simon GlassFrom: Thierry Reding <[email protected]>
This network interface card is found on the NVIDIA Jetson TK1.
---
Changes in v4:
- Fix typo in commit message
Changes in v3: None
drivers/net/rtl8169.c | 1 + 1 file changed, 1 insertion(+)
drivers/net/rtl8169.c +1 -0
@@ -253,6 +253,7 @@ static struct { {"RTL-8168b/8111sb", 0x38, 0xff7e1880,}, {"RTL-8168d/8111d", 0x28, 0xff7e1880,}, {"RTL-8168evl/8111evl", 0x2e, 0xff7e1880,}, + {"RTL-8168/8111g", 0x4c, 0xff7e1880,}, {"RTL-8101e", 0x34, 0xff7e1880,}, {"RTL-8100e", 0x32, 0xff7e1880,}, };
Signature · 1 line
2.2.0.rc0.207.ga3a616c
v4 cover ARM: tegra: Add PCIe support
In reply to Simon GlassHi Tom,
Quoted 77 lines · Simon Glass
From: Thierry Reding <[email protected]>
(Commit message updated by Simon Glass <[email protected]> who is sending this series originally created by Thierry)
This series adds PCIe support for Tegra20, Tegra30 and Tegra124. The size is mostly due to the large number of infrastructure that's added (Tegra- specific drivers required by the PCIe driver). In this version I've included all patches that were previously split into three separate series. Spreading them over multiple series is probably not worth it since there might be some dependencies between them and only the end result gives a completely working setup.
Some patches have already been applied to this series.
Patch 1 implements a driver for the AS3722 PMIC used on the Venice2 and Jetson TK1 boards.
Patches 2-7 are preparatory work for the Tegra PCIe controller. They add missing clock driver functionality as well as drivers for the Tegra powergat and XUSB pad controller blocks.
Patch 8 adds the PCIe controller driver for Tegra20, Tegra30 and Tegra124.
Device tree nodes and configurations options to enable PCIe on the TrimSlice (Tegra20), Beaver, Cardhu (Tegra30) and Jetson TK1 (Tegra124) boards are added in patches 9-17.
Patch 18 implements non-cached memory support that will be used in the last batch of patches to implement more reliable packet transfers in the r8169 driver. Patch 19 enables non-cached memory support on Tegra.
(Note from Simon: These patches may have already been applied in the ARM tree, but I can't see them there).
Finally, patches 20-23 implement non-cached memory support and various fixes in the r8169 driver and add support for the revision of the NIC found on the Jetson TK1.
The above boards all have an ethernet NIC connected to PCIe, which is what I tested with.
Note from Simon: I have:
- rebased this on top of the I2C driver model series
- dropped the I2C framework patches
- adjust the PMIC driver and code that calls it to use driver mode
- tested the I2C changes on Jetson-TK1Changes in v4:
- Use const unsigned for bus and address
- Insert missing word 'to' in a comment
- Fix typo in commit messageChanges in v3:
- Use driver model for the PMIC
- Use driver model to access the PMIC
- Use driver model to access the PMIC
- Avoid build error withnoncached_init()when the dcache is disabled
- Remove cache-line size warning if dcache is disabledThierry Reding (23):
power: Add AMS AS3722 PMIC support
ARM: tegra: Implementtegra_plle_enable()
ARM: tegra: Provide PCIEXCLK reset ID
ARM: tegra: Implement powergate support
ARM: tegra: Implement XUSB pad controller
ARM: tegra: Add XUSB pad controller on Tegra124
ARM: tegra: Enable XUSB pad controller on Jetson TK1
pci: tegra: Add Tegra PCIe driver
ARM: tegra: Add Tegra20 PCIe device tree node
ARM: tegra: Enable PCIe on TrimSlice
ARM: tegra: Add GIC for Tegra30
ARM: tegra: Add Tegra30 PCIe device tree node
ARM: tegra: Enable PCIe on Cardhu
ARM: tegra: Enable PCIe on Beaver
ARM: tegra: Add GIC for Tegra124
Quoted 8 lines
ARM: tegra: Add Tegra124 PCIe device tree node
ARM: tegra: Enable PCIe on Jetson TK1
ARM: Implement non-cached memory support
ARM: tegra: Enable non-cached memory
net: rtl8169: HonorCONFIG_SYS_RX_ETH_BUFFER
net: rtl8169: Properly align buffers
net: rtl8169: Use non-cached memory if available
net: rtl8169: Add support for RTL-8168/8111g
The I2C things have hit mainline now so this series is ready now.
There is a trivial fix on the 'Enable non-cached memory' patch - you can add the CONFIG immediately below CONFIG_SYS_NONCACHED_MEMORY perhaps.
I pushed my take on it to u-boot-dm/pcie-working in case it helps.
Quoted 65 lines
README | 19 + arch/arm/cpu/tegra-common/Makefile | 2 + arch/arm/cpu/tegra-common/powergate.c | 102 ++ arch/arm/cpu/tegra-common/xusb-padctl.c | 39 + arch/arm/cpu/tegra124-common/Makefile | 1 + arch/arm/cpu/tegra124-common/clock.c | 109 +++ arch/arm/cpu/tegra124-common/xusb-padctl.c | 716 ++++++++++++++ arch/arm/cpu/tegra20-common/clock.c | 141 ++- arch/arm/cpu/tegra30-common/clock.c | 155 +++ arch/arm/dts/tegra124-jetson-tk1.dts | 373 +++++++ arch/arm/dts/tegra124.dtsi | 89 ++ arch/arm/dts/tegra20-trimslice.dts | 69 ++ arch/arm/dts/tegra20.dtsi | 59 ++ arch/arm/dts/tegra30-beaver.dts | 245 +++++ arch/arm/dts/tegra30-cardhu.dts | 362 +++++++ arch/arm/dts/tegra30.dtsi | 83 ++ arch/arm/include/asm/arch-tegra/powergate.h | 38 + arch/arm/include/asm/arch-tegra/xusb-padctl.h | 24 + arch/arm/include/asm/arch-tegra114/powergate.h | 6 + arch/arm/include/asm/arch-tegra124/clock.h | 2 + arch/arm/include/asm/arch-tegra124/powergate.h | 6 + arch/arm/include/asm/arch-tegra20/clock-tables.h | 2 +- arch/arm/include/asm/arch-tegra20/clock.h | 2 + arch/arm/include/asm/arch-tegra20/powergate.h | 6 + arch/arm/include/asm/arch-tegra30/clock.h | 2 + arch/arm/include/asm/arch-tegra30/powergate.h | 6 + arch/arm/include/asm/system.h | 5 + arch/arm/lib/cache.c | 44 + board/compulab/trimslice/trimslice.c | 8 + board/nvidia/cardhu/cardhu.c | 52 + board/nvidia/common/board.c | 3 + board/nvidia/jetson-tk1/jetson-tk1.c | 52 + common/board_r.c | 11 + drivers/net/rtl8169.c | 127 ++- drivers/pci/Makefile | 1 + drivers/pci/pci_tegra.c | 1143 ++++++++++++++++++++++ drivers/power/Makefile | 1 + drivers/power/as3722.c | 264 +++++ include/configs/beaver.h | 10 + include/configs/cardhu.h | 10 + include/configs/jetson-tk1.h | 13 + include/configs/tegra-common.h | 2 + include/configs/trimslice.h | 10 + include/dt-bindings/clock/tegra20-car.h | 2 +- include/dt-bindings/clock/tegra30-car.h | 2 +- include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h | 7 + include/fdtdec.h | 6 + include/power/as3722.h | 27 + lib/fdtdec.c | 5 + 49 files changed, 4424 insertions(+), 39 deletions(-) create mode 100644 arch/arm/cpu/tegra-common/powergate.c create mode 100644 arch/arm/cpu/tegra-common/xusb-padctl.c create mode 100644 arch/arm/cpu/tegra124-common/xusb-padctl.c create mode 100644 arch/arm/include/asm/arch-tegra/powergate.h create mode 100644 arch/arm/include/asm/arch-tegra/xusb-padctl.h create mode 100644 arch/arm/include/asm/arch-tegra114/powergate.h create mode 100644 arch/arm/include/asm/arch-tegra124/powergate.h create mode 100644 arch/arm/include/asm/arch-tegra20/powergate.h create mode 100644 arch/arm/include/asm/arch-tegra30/powergate.h create mode 100644 drivers/pci/pci_tegra.c create mode 100644 drivers/power/as3722.c create mode 100644 include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h create mode 100644 include/power/as3722.h
Quoted 3 lines
--
2.2.0.rc0.207.ga3a616c
Regards,
Simon