ARM: mvebu: Add Armada 385 AP support

The mvebu SoCs actually have more UARTs than just the one exposed in DEBUG_LL yet.

In order to differentiate them, Add the index in the configuration options and their help.

Signed-off-by Maxime Ripard <[email protected]>

Acked-by Jason Cooper <[email protected]>

---
 arch/arm/Kconfig.debug | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

arch/arm/Kconfig.debug +9 -9

index 5ddd4906f7a7..eb3991cf63ab 100644
@@ -455,13 +455,13 @@ choice
 		  Please adjust DEBUG_UART_PHYS and DEBUG_UART_BASE configuration
 		  options based on your needs.
 
-	config DEBUG_MVEBU_UART
-		bool "Kernel low-level debugging messages via MVEBU UART (old bootloaders)"
+	config DEBUG_MVEBU_UART0
+		bool "Kernel low-level debugging messages via MVEBU UART0 (old bootloaders)"
 		depends on ARCH_MVEBU
 		select DEBUG_UART_8250
 		help
 		  Say Y here if you want kernel low-level debugging support
-		  on MVEBU based platforms.
+		  on MVEBU based platforms on UART0.
 
 		  This option should be used with the old bootloaders
 		  that left the internal registers mapped at

@@ -474,13 +474,13 @@ choice
 		  when u-boot hands over to the kernel, the system
 		  silently crashes, with no serial output at all.
 
-	config DEBUG_MVEBU_UART_ALTERNATE
-		bool "Kernel low-level debugging messages via MVEBU UART (new bootloaders)"
+	config DEBUG_MVEBU_UART0_ALTERNATE
+		bool "Kernel low-level debugging messages via MVEBU UART0 (new bootloaders)"
 		depends on ARCH_MVEBU
 		select DEBUG_UART_8250
 		help
 		  Say Y here if you want kernel low-level debugging support
-		  on MVEBU based platforms.
+		  on MVEBU based platforms on UART0.
 
 		  This option should be used with the new bootloaders
 		  that remap the internal registers at 0xf1000000.

@@ -1282,7 +1282,7 @@ config DEBUG_UART_PHYS
 	default 0xc8000000 if ARCH_IXP4XX && !CPU_BIG_ENDIAN
 	default 0xc8000003 if ARCH_IXP4XX && CPU_BIG_ENDIAN
 	default 0xd0000000 if ARCH_SPEAR3XX || ARCH_SPEAR6XX
-	default 0xd0012000 if DEBUG_MVEBU_UART
+	default 0xd0012000 if DEBUG_MVEBU_UART0
 	default 0xc81004c0 if DEBUG_MESON_UARTAO
 	default 0xd4017000 if DEBUG_MMP_UART2
 	default 0xd4018000 if DEBUG_MMP_UART3

@@ -1296,7 +1296,7 @@ config DEBUG_UART_PHYS
 	default 0xe8008000 if DEBUG_R7S72100_SCIF2
 	default 0xf0000be0 if ARCH_EBSA110
 	default 0xf040ab00 if DEBUG_BRCMSTB_UART
-	default 0xf1012000 if DEBUG_MVEBU_UART_ALTERNATE
+	default 0xf1012000 if DEBUG_MVEBU_UART0_ALTERNATE
 	default 0xf1012000 if ARCH_DOVE || ARCH_MV78XX0 || \
 				ARCH_ORION5X
 	default 0xf7fc9000 if DEBUG_BERLIN_UART

@@ -1377,7 +1377,7 @@ config DEBUG_UART_VIRT
 	default 0xfeb30c00 if DEBUG_KEYSTONE_UART0
 	default 0xfeb31000 if DEBUG_KEYSTONE_UART1
 	default 0xfec02000 if DEBUG_SOCFPGA_UART
-	default 0xfec12000 if DEBUG_MVEBU_UART || DEBUG_MVEBU_UART_ALTERNATE
+	default 0xfec12000 if DEBUG_MVEBU_UART0 || DEBUG_MVEBU_UART0_ALTERNATE
 	default 0xfec20000 if DEBUG_DAVINCI_DMx_UART0
 	default 0xfec90000 if DEBUG_RK32_UART2
 	default 0xfed0c000 if DEBUG_DAVINCI_DA8XX_UART1

Some mvebu boards have the UART1 more easily accessible than the other UARTs found on the system.

Add a debug_ll option for this case.

Signed-off-by Maxime Ripard <[email protected]>

Acked-by Jason Cooper <[email protected]>

---
 arch/arm/Kconfig.debug | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

arch/arm/Kconfig.debug +17 -0

index eb3991cf63ab..7bd1bbccc43c 100644
@@ -489,6 +489,21 @@ choice
 		  when u-boot hands over to the kernel, the system
 		  silently crashes, with no serial output at all.
 
+	config DEBUG_MVEBU_UART1_ALTERNATE
+		bool "Kernel low-level debugging messages via MVEBU UART1 (new bootloaders)"
+		depends on ARCH_MVEBU
+		select DEBUG_UART_8250
+		help
+		  Say Y here if you want kernel low-level debugging support
+		  on MVEBU based platforms on UART1.
+
+		  This option should be used with the new bootloaders
+		  that remap the internal registers at 0xf1000000.
+
+		  If the wrong DEBUG_MVEBU_UART* option is selected,
+		  when u-boot hands over to the kernel, the system
+		  silently crashes, with no serial output at all.
+
 	config DEBUG_VF_UART
 		bool "Vybrid UART"
 		depends on SOC_VF610

@@ -1297,6 +1312,7 @@ config DEBUG_UART_PHYS
 	default 0xf0000be0 if ARCH_EBSA110
 	default 0xf040ab00 if DEBUG_BRCMSTB_UART
 	default 0xf1012000 if DEBUG_MVEBU_UART0_ALTERNATE
+	default 0xf1012100 if DEBUG_MVEBU_UART1_ALTERNATE
 	default 0xf1012000 if ARCH_DOVE || ARCH_MV78XX0 || \
 				ARCH_ORION5X
 	default 0xf7fc9000 if DEBUG_BERLIN_UART

@@ -1378,6 +1394,7 @@ config DEBUG_UART_VIRT
 	default 0xfeb31000 if DEBUG_KEYSTONE_UART1
 	default 0xfec02000 if DEBUG_SOCFPGA_UART
 	default 0xfec12000 if DEBUG_MVEBU_UART0 || DEBUG_MVEBU_UART0_ALTERNATE
+	default 0xfec12100 if DEBUG_MVEBU_UART1_ALTERNATE
 	default 0xfec20000 if DEBUG_DAVINCI_DMx_UART0
 	default 0xfec90000 if DEBUG_RK32_UART2
 	default 0xfed0c000 if DEBUG_DAVINCI_DA8XX_UART1

Some nodes in the DTs have a reg property but no unit name in their node name.

This contradicts the way the ePAPR defines the node names. Fix this.

Signed-off-by Maxime Ripard <[email protected]>

---
 arch/arm/boot/dts/armada-380.dtsi   | 2 +-
 arch/arm/boot/dts/armada-385-db.dts | 2 +-
 arch/arm/boot/dts/armada-385-rd.dts | 2 +-
 arch/arm/boot/dts/armada-385.dtsi   | 2 +-
 arch/arm/boot/dts/armada-38x.dtsi   | 4 ++--
 5 files changed, 6 insertions(+), 6 deletions(-)

arch/arm/boot/dts/armada-380.dtsi +1 -1

index 4173a8ab34e7..13400ce88c54 100644
@@ -32,7 +32,7 @@
 
 	soc {
 		internal-regs {
-			pinctrl {
+			pinctrl at 18000 {
 				compatible = "marvell,mv88f6810-pinctrl";
 				reg = <0x18000 0x20>;
 			};

arch/arm/boot/dts/armada-385-db.dts +1 -1

index 2aaa9d2ac284..212605ccc7b6 100644
@@ -74,7 +74,7 @@
 				phy-mode = "rgmii-id";
 			};
 
-			mdio {
+			mdio at 72004 {
 				phy0: ethernet-phy at 0 {
 					reg = <0>;
 				};

arch/arm/boot/dts/armada-385-rd.dts +1 -1

index aaca2861dc87..74a3bfe6efd7 100644
@@ -67,7 +67,7 @@
 			};
 
 
-			mdio {
+			mdio at 72004 {
 				phy0: ethernet-phy at 0 {
 					reg = <0>;
 				};

arch/arm/boot/dts/armada-385.dtsi +1 -1

index 6283d7912f71..5249a4d3c207 100644
@@ -37,7 +37,7 @@
 
 	soc {
 		internal-regs {
-			pinctrl {
+			pinctrl at 18000 {
 				compatible = "marvell,mv88f6820-pinctrl";
 				reg = <0x18000 0x20>;
 			};

arch/arm/boot/dts/armada-38x.dtsi +2 -2

index 74391dace9e7..ada1f206028b 100644
@@ -193,7 +193,7 @@
 				status = "disabled";
 			};
 
-			pinctrl {
+			pinctrl at 18000 {
 				compatible = "marvell,mv88f6820-pinctrl";
 				reg = <0x18000 0x20>;
 			};

@@ -373,7 +373,7 @@
 				status = "disabled";
 			};
 
-			mdio {
+			mdio at 72004 {
 				#address-cells = <1>;
 				#size-cells = <0>;
 				compatible = "marvell,orion-mdio";

The compatible set in the armada-38x DTSI is always overridden, and the reg defined in there is duplicated in the armada-380 and armada-385 DTSIs.

Remove these useless items.

Signed-off-by Maxime Ripard <[email protected]>

---
 arch/arm/boot/dts/armada-380.dtsi | 1 -
 arch/arm/boot/dts/armada-385.dtsi | 1 -
 arch/arm/boot/dts/armada-38x.dtsi | 1 -
 3 files changed, 3 deletions(-)

arch/arm/boot/dts/armada-380.dtsi +0 -1

index 13400ce88c54..7e509d2d74d0 100644
@@ -34,7 +34,6 @@
 		internal-regs {
 			pinctrl at 18000 {
 				compatible = "marvell,mv88f6810-pinctrl";
-				reg = <0x18000 0x20>;
 			};
 		};
 

arch/arm/boot/dts/armada-385.dtsi +0 -1

index 5249a4d3c207..a54a252ddb4c 100644
@@ -39,7 +39,6 @@
 		internal-regs {
 			pinctrl at 18000 {
 				compatible = "marvell,mv88f6820-pinctrl";
-				reg = <0x18000 0x20>;
 			};
 		};
 

arch/arm/boot/dts/armada-38x.dtsi +0 -1

index ada1f206028b..40200084c6c8 100644
@@ -194,7 +194,6 @@
 			};
 
 			pinctrl at 18000 {
-				compatible = "marvell,mv88f6820-pinctrl";
 				reg = <0x18000 0x20>;
 			};
 

Some pinctrl functions can be shared with all DTS out there, since they are generic, SoC-wide muxing options. Add a number of these to the DTSI to avoid duplication.

Signed-off-by Maxime Ripard <[email protected]>

---
 arch/arm/boot/dts/armada-38x.dtsi | 39 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 39 insertions(+)

arch/arm/boot/dts/armada-38x.dtsi +39 -0

index 40200084c6c8..98885c58be29 100644
@@ -195,6 +195,45 @@
 
 			pinctrl at 18000 {
 				reg = <0x18000 0x20>;
+
+				ge0_rgmii_pins: ge-rgmii-pins-0 {
+					marvell,pins = "mpp6", "mpp7", "mpp8",
+						       "mpp9", "mpp10", "mpp11",
+						       "mpp12", "mpp13", "mpp14",
+						       "mpp15", "mpp16", "mpp17";
+					marvell,function = "ge0";
+				};
+
+				i2c0_pins: i2c-pins-0 {
+					marvell,pins = "mpp2", "mpp3";
+					marvell,function = "i2c0";
+				};
+
+				mdio_pins: mdio-pins {
+					marvell,pins = "mpp4", "mpp5";
+					marvell,function = "ge";
+				};
+
+				ref_clk0_pins: ref-clk-pins-0 {
+					marvell,pins = "mpp45";
+					marvell,function = "ref";
+				};
+
+				spi1_pins: spi-pins-1 {
+					marvell,pins = "mpp56", "mpp57", "mpp58",
+						       "mpp59";
+					marvell,function = "spi1";
+				};
+
+				uart0_pins: uart-pins-0 {
+					marvell,pins = "mpp0", "mpp1";
+					marvell,function = "ua0";
+				};
+
+				uart1_pins: uart-pins-1 {
+					marvell,pins = "mpp19", "mpp20";
+					marvell,function = "ua1";
+				};
 			};
 
 			gpio0: gpio at 18100 {

arch/arm/boot/dts/armada-385-ap.dts new file +2 -0

@@ -0,0 +1,140 @@
+/*
+ * Device Tree file for Marvell Armada 385 Access Point Development board

arch/arm/boot/dts/armada-385-ap.dts new file +27 -0

+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x80000000>; /* 2GB */
+	};
+
+	soc {
+		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
+			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
+
+		internal-regs {
+			spi1: spi at 10680 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&spi1_pins>;
+				status = "okay";
+
+				spi-flash at 0 {
+					#address-cells = <1>;
+					#size-cells = <1>;
+					compatible = "st,m25p128";
+					reg = <0>; /* Chip select 0 */
+					spi-max-frequency = <108000000>;
+				};
+			};
+
+			i2c0: i2c at 11000 {

arch/arm/boot/dts/armada-385-ap.dts new file +17 -0

+			mdio at 72004 {
+				pinctrl-names = <&mdio_pins>;
+
+				phy0: ethernet-phy at 0 {
+					reg = <1>;
+				};
+
+				phy1: ethernet-phy at 1 {
+					reg = <6>;
+				};
+
+				phy2: ethernet-phy at 2 {
+					reg = <4>;
+				};
+			};
+
+			uart0: serial at 12000 {

arch/arm/boot/dts/armada-385-ap.dts new file +10 -0

+
+			ethernet at 30000 {
+				status = "okay";
+				phy = <&phy1>;
+				phy-mode = "sgmii";
+			};
+
+			ethernet at 34000 {
+				status = "okay";
+				phy = <&phy2>;

arch/arm/boot/dts/armada-385-ap.dts new file +31 -0

+				pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
+				status = "okay";
+				phy = <&phy0>;
+				phy-mode = "rgmii-id";
+			};
+		};
+
+		pcie-controller {
+			status = "okay";
+
+			/*
+			 * The three PCIe units are accessible through
+			 * standard mini-PCIe slots on the board.
+			 */
+			pcie at 1,0 {
+				/* Port 0, Lane 0 */
+				status = "okay";
+			};
+
+			pcie at 2,0 {
+				/* Port 1, Lane 0 */
+				status = "okay";
+			};
+
+			pcie at 3,0 {
+				/* Port 2, Lane 0 */
+				status = "okay";
+			};
+		};
+	};
+};

Signature · 1 line

2.2.1

On Tue, Jan 06, 2015 at 04:28:20PM +0100, Maxime Ripard wrote:

Hi Maxime

Quoted 10 lines

arch/arm/boot/dts/armada-385-ap.dts new file +7 -0

@@ -0,0 +1,140 @@
+/*
+ * Device Tree file for Marvell Armada 385 Access Point Development board
+ * (DB-88F6820-AP)
+ *
+ *  Copyright (C) 2014 Marvell
+ *
+ * Nadav Haklai <[email protected]>

arch/arm/boot/dts/armada-385-ap.dts line 12

Quoted 5 lines

arch/arm/boot/dts/armada-385-ap.dts new file +5 -0

+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */

Gregory is in the process of dual licensing some of the other mvebu DT files. This one is single license. Should it be dual?

Quoted 6 lines

arch/arm/boot/dts/armada-385-ap.dts new file +6 -0

+
+/dts-v1/;
+#include "armada-385.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+

arch/arm/boot/dts/armada-385-ap.dts line 24

Quoted 6 lines

arch/arm/boot/dts/armada-385-ap.dts new file +6 -0

+/ {
+	model = "Marvell Armada 385 Access Point Development Board";
+	compatible = "marvell,a385-db-ap", "marvell,armada385", "marvell,armada38x";
+
+	chosen {
+		bootargs = "console=ttyS0,115200";

Humm, ttyS0? Then why add the LL_DEBUG via UART1?

Maybe add

stdout-path = &uart1;

Quoted 31 lines

arch/arm/boot/dts/armada-385-ap.dts new file +31 -0

+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x80000000>; /* 2GB */
+	};
+
+	soc {
+		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
+			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
+
+		internal-regs {
+			spi1: spi at 10680 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&spi1_pins>;
+				status = "okay";
+
+				spi-flash at 0 {
+					#address-cells = <1>;
+					#size-cells = <1>;
+					compatible = "st,m25p128";
+					reg = <0>; /* Chip select 0 */
+					spi-max-frequency = <108000000>;
+				};
+			};
+
+			i2c0: i2c at 11000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&i2c0_pins>;
+				status = "okay";
+				clock-frequency = <100000>;

arch/arm/boot/dts/armada-385-ap.dts line 61

Quoted 6 lines

arch/arm/boot/dts/armada-385-ap.dts new file +6 -0

+			};
+
+			i2c1: i2c at 11100 {
+				status = "okay";
+				clock-frequency = <100000>;
+			};

Is there anything on these two i2c busses?

If not, why enable them and increase the clock speed?

Quoted 23 lines

arch/arm/boot/dts/armada-385-ap.dts new file +22 -0

+			mdio at 72004 {
+				pinctrl-names = <&mdio_pins>;
+
+				phy0: ethernet-phy at 0 {
+					reg = <1>;
+				};
+
+				phy1: ethernet-phy at 1 {
+					reg = <6>;
+				};
+
+				phy2: ethernet-phy at 2 {
+					reg = <4>;
+				};
+			};
+
+			uart0: serial at 12000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&uart0_pins>;
+				status = "okay";
+			};
+

arch/arm/boot/dts/armada-385-ap.dts line 89

Quoted 5 lines

arch/arm/boot/dts/armada-385-ap.dts new file +5 -0

+			uart1: serial at 12100 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&uart1_pins>;
+				status = "okay";
+			};

If it is not obvious from the silk screen, could you describe which connector this uart is on, what pins are what?

Quoted 10 lines

arch/arm/boot/dts/armada-385-ap.dts new file +10 -0

+
+			ethernet at 30000 {
+				status = "okay";
+				phy = <&phy1>;
+				phy-mode = "sgmii";
+			};
+
+			ethernet at 34000 {
+				status = "okay";
+				phy = <&phy2>;

arch/arm/boot/dts/armada-385-ap.dts line 109

Quoted 10 lines

arch/arm/boot/dts/armada-385-ap.dts new file +10 -0

+				phy-mode = "sgmii";
+			};
+
+			ethernet at 70000 {
+				pinctrl-names = "default";
+
+				/*
+				 * The Reference Clock 0 is used to
+				 * provide a clock to the PHY
+				 */

Does this clock need enabling? Should it be listed in the clocks property?

From what I understood, this clock is always running, it's just

Quoted 3 lines

Maybe add

stdout-path = &uart1;

Does that even work with the 8250? Last time I tried with a 3.18, it didn't, and you still needed the console= bootargs.

Quoted 5 lines

Quoted 5 lines

arch/arm/boot/dts/armada-385-ap.dts new file +5 -0

+			i2c0: i2c at 11000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&i2c0_pins>;
+				status = "okay";
+				clock-frequency = <100000>;

Quoted 8 lines

arch/arm/boot/dts/armada-385-ap.dts line 61

Quoted 6 lines

arch/arm/boot/dts/armada-385-ap.dts new file +6 -0

+			};
+
+			i2c1: i2c at 11100 {
+				status = "okay";
+				clock-frequency = <100000>;
+			};

Is there anything on these two i2c busses?

One goes to some pin of the mPCIe slot, the other is connected to the EEPROM.

Quoted 1 line

If not, why enable them and increase the clock speed?

The clock speed is not increased, it's actually the driver's default.

Quoted 6 lines

Quoted 6 lines

arch/arm/boot/dts/armada-385-ap.dts new file +6 -0

+			uart0: serial at 12000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&uart0_pins>;
+				status = "okay";
+			};
+

Quoted 8 lines

arch/arm/boot/dts/armada-385-ap.dts line 89

Quoted 5 lines

arch/arm/boot/dts/armada-385-ap.dts new file +5 -0

+			uart1: serial at 12100 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&uart1_pins>;
+				status = "okay";
+			};

If it is not obvious from the silk screen, could you describe which connector this uart is on, what pins are what?

There's two UART connectors documented in the user guide (JP8 and JP9). UART1 is also connected to a FTDI chip, that is exposed through a mini-USB connector.

Quoted 15 lines

Quoted 15 lines

arch/arm/boot/dts/armada-385-ap.dts new file +15 -0

+
+			ethernet at 30000 {
+				status = "okay";
+				phy = <&phy1>;
+				phy-mode = "sgmii";
+			};
+
+			ethernet at 34000 {
+				status = "okay";
+				phy = <&phy2>;
+				phy-mode = "sgmii";
+			};
+
+			ethernet at 70000 {
+				pinctrl-names = "default";

Quoted 8 lines

arch/arm/boot/dts/armada-385-ap.dts line 109

Quoted 5 lines

arch/arm/boot/dts/armada-385-ap.dts new file +5 -0

+
+				/*
+				 * The Reference Clock 0 is used to
+				 * provide a clock to the PHY
+				 */

Does this clock need enabling? Should it be listed in the clocks property?

From what I understood, this clock is always running, it's just exposed to some external pin, and hence needs some muxing.

Quoted 6 lines

Quoted 3 lines

Maybe add

stdout-path = &uart1;

Does that even work with the 8250? Last time I tried with a 3.18, it didn't, and you still needed the console= bootargs.

It is for the bootloader, not Linux. barebox will use this, etc. I think there are also plans for linux to use this. Not sure how far it has got.

Quoted 14 lines

Quoted 13 lines

arch/arm/boot/dts/armada-385-ap.dts line 61

Quoted 11 lines

arch/arm/boot/dts/armada-385-ap.dts new file +11 -0

+			i2c0: i2c at 11000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&i2c0_pins>;
+				status = "okay";
+				clock-frequency = <100000>;
+			};
+
+			i2c1: i2c at 11100 {
+				status = "okay";
+				clock-frequency = <100000>;
+			};

Is there anything on these two i2c busses?

Quoted 2 lines

One goes to some pin of the mPCIe slot, the other is connected to the EEPROM.

So could you add the EEPROM, and a comment about the mPCIe slot?

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If not, why enable them and increase the clock speed?

The clock speed is not increased, it's actually the driver's default.

Dio you need this then? Is it in the dtsi file?

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arch/arm/boot/dts/armada-385-ap.dts line 89

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arch/arm/boot/dts/armada-385-ap.dts new file +11 -0

+			uart0: serial at 12000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&uart0_pins>;
+				status = "okay";
+			};
+
+			uart1: serial at 12100 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&uart1_pins>;
+				status = "okay";
+			};

If it is not obvious from the silk screen, could you describe which connector this uart is on, what pins are what?

Quoted 3 lines

There's two UART connectors documented in the user guide (JP8 and JP9). UART1 is also connected to a FTDI chip, that is exposed through a mini-USB connector.

I'm guessing the user guide is only available under NDA?

Where as you can get the hardware without an NDA. At least i have a 370-rd, but no NDA. So some minimal documentation would be nice. Especially since it is backwards around to what most people would expect.

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arch/arm/boot/dts/armada-385-ap.dts new file +5 -0

+			i2c0: i2c at 11000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&i2c0_pins>;
+				status = "okay";
+				clock-frequency = <100000>;

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arch/arm/boot/dts/armada-385-ap.dts line 61

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arch/arm/boot/dts/armada-385-ap.dts new file +6 -0

+			};
+
+			i2c1: i2c at 11100 {
+				status = "okay";
+				clock-frequency = <100000>;
+			};

Is there anything on these two i2c busses?

One goes to some pin of the mPCIe slot, the other is connected to the EEPROM.

Quoted 1 line

So could you add the EEPROM, and a comment about the mPCIe slot?

I can't really add the EEPROM: it actually goes to two DIP sockets, one of them holding that EEPROM, the other one being empty.

The default EEPROM also contains the board ID, that will be used by the bootloader. Erasing this will result in a board that can't be booted, so I'm not really sure exposing it to the user is a good idea.

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arch/arm/boot/dts/armada-385-ap.dts line 61

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arch/arm/boot/dts/armada-385-ap.dts new file +11 -0

+			i2c0: i2c at 11000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&i2c0_pins>;
+				status = "okay";
+				clock-frequency = <100000>;
+			};
+
+			i2c1: i2c at 11100 {
+				status = "okay";
+				clock-frequency = <100000>;
+			};

Is there anything on these two i2c busses?

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One goes to some pin of the mPCIe slot, the other is connected to the EEPROM.

So could you add the EEPROM, and a comment about the mPCIe slot?

Quoted 7 lines

I can't really add the EEPROM: it actually goes to two DIP sockets, one of them holding that EEPROM, the other one being empty.

The default EEPROM also contains the board ID, that will be used by the bootloader. Erasing this will result in a board that can't be booted, so I'm not really sure exposing it to the user is a good idea.

O.K, please add a comment. People like me tend to run i2c-detect to see if there is anything interesting on the bus. A warning you can brick the board could save somebody an interesting time.

Andrew

On Tue, Jan 06, 2015 at 04:28:20PM +0100, Maxime Ripard wrote:

Hi Maxime

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arch/arm/boot/dts/armada-385-ap.dts new file +8 -0

@@ -0,0 +1,140 @@
+/*
+ * Device Tree file for Marvell Armada 385 Access Point Development 
+board
+ * (DB-88F6820-AP)
+ *
+ *  Copyright (C) 2014 Marvell
+ *
+ * Nadav Haklai <[email protected]>

arch/arm/boot/dts/armada-385-ap.dts line 12

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arch/arm/boot/dts/armada-385-ap.dts new file +5 -0

+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */

Gregory is in the process of dual licensing some of the other mvebu DT files. This one is single license. Should it be dual?

Quoted 7 lines

arch/arm/boot/dts/armada-385-ap.dts new file +7 -0

+
+/dts-v1/;
+#include "armada-385.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {

arch/arm/boot/dts/armada-385-ap.dts line 24

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arch/arm/boot/dts/armada-385-ap.dts new file +6 -0

+	model = "Marvell Armada 385 Access Point Development Board";
+	compatible = "marvell,a385-db-ap", "marvell,armada385", 
+"marvell,armada38x";
+
+	chosen {
+		bootargs = "console=ttyS0,115200";

Humm, ttyS0? Then why add the LL_DEBUG via UART1?

Maybe add

stdout-path = &uart1;

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arch/arm/boot/dts/armada-385-ap.dts new file +31 -0

+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x80000000>; /* 2GB */
+	};
+
+	soc {
+		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
+			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
+
+		internal-regs {
+			spi1: spi at 10680 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&spi1_pins>;
+				status = "okay";
+
+				spi-flash at 0 {
+					#address-cells = <1>;
+					#size-cells = <1>;
+					compatible = "st,m25p128";
+					reg = <0>; /* Chip select 0 */
+					spi-max-frequency = <108000000>;
+				};
+			};
+
+			i2c0: i2c at 11000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&i2c0_pins>;
+				status = "okay";
+				clock-frequency = <100000>;

arch/arm/boot/dts/armada-385-ap.dts line 61

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arch/arm/boot/dts/armada-385-ap.dts new file +6 -0

+			};
+
+			i2c1: i2c at 11100 {
+				status = "okay";
+				clock-frequency = <100000>;
+			};

Is there anything on these two i2c busses?

If not, why enable them and increase the clock speed?

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arch/arm/boot/dts/armada-385-ap.dts new file +22 -0

+			mdio at 72004 {
+				pinctrl-names = <&mdio_pins>;
+
+				phy0: ethernet-phy at 0 {
+					reg = <1>;
+				};
+
+				phy1: ethernet-phy at 1 {
+					reg = <6>;
+				};
+
+				phy2: ethernet-phy at 2 {
+					reg = <4>;
+				};
+			};
+
+			uart0: serial at 12000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&uart0_pins>;
+				status = "okay";
+			};
+

arch/arm/boot/dts/armada-385-ap.dts line 89

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arch/arm/boot/dts/armada-385-ap.dts new file +5 -0

+			uart1: serial at 12100 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&uart1_pins>;
+				status = "okay";
+			};

If it is not obvious from the silk screen, could you describe which connector this uart is on, what pins are what?

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arch/arm/boot/dts/armada-385-ap.dts new file +10 -0

+
+			ethernet at 30000 {
+				status = "okay";
+				phy = <&phy1>;
+				phy-mode = "sgmii";
+			};
+
+			ethernet at 34000 {
+				status = "okay";
+				phy = <&phy2>;

arch/arm/boot/dts/armada-385-ap.dts line 109

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arch/arm/boot/dts/armada-385-ap.dts new file +10 -0

+				phy-mode = "sgmii";
+			};
+
+			ethernet at 70000 {
+				pinctrl-names = "default";
+
+				/*
+				 * The Reference Clock 0 is used to
+				 * provide a clock to the PHY
+				 */

Does this clock need enabling? Should it be listed in the clocks property?

From what I understood, this clock is always running, it's just exposed to some external pin, and hence needs some muxing.

arch/arm/boot/dts/armada-385-ap.dts line 47

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arch/arm/boot/dts/armada-385-ap.dts new file +6 -0

+				spi-flash at 0 {
+					#address-cells = <1>;
+					#size-cells = <1>;
+					compatible = "st,m25p128";
+					reg = <0>; /* Chip select 0 */
+					spi-max-frequency = <108000000>;

The SPI flahs used on the AP board is the same that the one used on the GP board:
M25P128-VMF6P and the maximum frequency it can handle is 50MHz.

arch/arm/boot/dts/armada-385-ap.dts line 66

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arch/arm/boot/dts/armada-385-ap.dts new file +5 -0

+
+			mdio at 72004 {
+				pinctrl-names = <&mdio_pins>;
+
+				phy0: ethernet-phy at 0 {

Why don't you use the PHY address after the '@' ?
Here I expected something like
phy0: ethernet-phy at 1 {

arch/arm/boot/dts/armada-385-ap.dts line 70

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arch/arm/boot/dts/armada-385-ap.dts new file +4 -0

+					reg = <1>;
+				};
+
+				phy1: ethernet-phy at 1 {

and here:
phy0: ethernet-phy at 6 {

arch/arm/boot/dts/armada-385-ap.dts line 74

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arch/arm/boot/dts/armada-385-ap.dts new file +4 -0

+					reg = <6>;
+				};
+
+				phy2: ethernet-phy at 2 {

and here:
phy0: ethernet-phy at 4 {