ARM: tegra: Use PMC scratch register 40 for tegra_resume() location store

PATCH In review Dmitry Osipenko 4 participants 11 messages Dec 21, 2014 – Jan 9, 2015

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Stable branch Arm (32-bit) Arm sub-architectures Tegra architecture support

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Dmitry Osipenko

author

2014-12-21 22:52 UTC #0 lore raw

PATCH 1/1 ARM: tegra: Use PMC scratch register 40 for tegra_resume() location store

Commit 7232398abc6a ("ARM: tegra: Convert PMC to a driver") changed tegra_resume() location storing from late to early and as result broke suspend on tegra20. PMC scratch register 41 was used by tegra lp1 suspend core code for storing physical memory address of common resume function and in the same time used by tegra20 cpuidle driver for storing cpu1 "resettable" status, so it implied strict order of scratch register use. Fix it by using scratch 40 instead of 41 for tegra_resume() location store.

Signed-off-by Dmitry Osipenko <[email protected]>

Fixes 7232398abc6a (ARM: tegra: Convert PMC to a driver)

Cc <[email protected]> # v3.17+

---
I see 2 other solutions:

1) Replace PMC driver PM ops with syscore
2) Move tegra_resume() storing back to tegra arch suspend code

For me originally proposed solution looks best, but I'm not aware of any special use of scratch 40 outside kernel and bootloader, so please let me know if there is any issue with it. It works just fine on my tablet.

 arch/arm/mach-tegra/sleep-tegra20.S | 4 ++--
 arch/arm/mach-tegra/sleep-tegra30.S | 4 ++--
 arch/arm/mach-tegra/sleep.h         | 1 +
 drivers/soc/tegra/pmc.c             | 6 +++---
 4 files changed, 8 insertions(+), 7 deletions(-)

arch/arm/mach-tegra/sleep-tegra20.S +2 -2

index be4bc5f..3574785 100644
@@ -327,7 +327,7 @@ tegra20_iram_start:
  * system clock running on the same PLL that it suspended at), and
  * jumps to tegra_resume to restore virtual addressing and PLLX.
  * The physical address of tegra_resume expected to be stored in
- * PMC_SCRATCH41.
+ * PMC_SCRATCH40.
  *
  * NOTE: THIS *MUST* BE RELOCATED TO TEGRA_IRAM_LPx_RESUME_AREA.
  */

@@ -401,7 +401,7 @@ exit_selfrefresh_loop:
 	str	r1, [r0, #EMC_REQ_CTRL]
 
 	mov32	r0, TEGRA_PMC_BASE
-	ldr	r0, [r0, #PMC_SCRATCH41]
+	ldr	r0, [r0, #PMC_SCRATCH40]
 	ret	r0			@ jump to tegra_resume
 ENDPROC(tegra20_lp1_reset)

arch/arm/mach-tegra/sleep-tegra30.S +2 -2

index 5d8d13a..234959c 100644
@@ -314,7 +314,7 @@ tegra30_iram_start:
  * system clock running on the same PLL that it suspended at), and
  * jumps to tegra_resume to restore virtual addressing.
  * The physical address of tegra_resume expected to be stored in
- * PMC_SCRATCH41.
+ * PMC_SCRATCH40.
  *
  * NOTE: THIS *MUST* BE RELOCATED TO TEGRA_IRAM_LPx_RESUME_AREA.
  */

@@ -529,7 +529,7 @@ zcal_done:
 __no_dual_emc_chanl:
 
 	mov32	r0, TEGRA_PMC_BASE
-	ldr	r0, [r0, #PMC_SCRATCH41]
+	ldr	r0, [r0, #PMC_SCRATCH40]
 	ret	r0			@ jump to tegra_resume
 ENDPROC(tegra30_lp1_reset)

arch/arm/mach-tegra/sleep.h +1 -0

index 92d46ec..23c42d0 100644
@@ -33,6 +33,7 @@
 #define PMC_SCRATCH37	0x130
 #define PMC_SCRATCH38	0x134
 #define PMC_SCRATCH39	0x138
+#define PMC_SCRATCH40	0x13C
 #define PMC_SCRATCH41	0x140
 
 #ifdef CONFIG_ARCH_TEGRA_2x_SOC

drivers/soc/tegra/pmc.c +3 -3

index a2c0ceb..51bfdeb 100644
@@ -68,7 +68,7 @@
 #define PMC_CPUPWRGOOD_TIMER		0xc8
 #define PMC_CPUPWROFF_TIMER		0xcc
 
-#define PMC_SCRATCH41			0x140
+#define PMC_SCRATCH40			0x13C
 
 #define IO_DPD_REQ			0x1b8
 #define  IO_DPD_REQ_CODE_IDLE		(0 << 30)

@@ -742,14 +742,14 @@ static int tegra_pmc_probe(struct platform_device *pdev)
 #ifdef CONFIG_PM_SLEEP
 static int tegra_pmc_suspend(struct device *dev)
 {
-	tegra_pmc_writel(virt_to_phys(tegra_resume), PMC_SCRATCH41);
+	tegra_pmc_writel(virt_to_phys(tegra_resume), PMC_SCRATCH40);
 
 	return 0;
 }
 
 static int tegra_pmc_resume(struct device *dev)
 {
-	tegra_pmc_writel(0x0, PMC_SCRATCH41);
+	tegra_pmc_writel(0x0, PMC_SCRATCH40);
 
 	return 0;
 }

Signature · 1 line

2.2.0

Stephen Warren

2014-12-22 16:17 UTC #1 lore raw

Quoted 7 lines · Dmitry Osipenko

Commit 7232398abc6a ("ARM: tegra: Convert PMC to a driver") changed tegra_resume() location storing from late to early and as result broke suspend on tegra20. PMC scratch register 41 was used by tegra lp1 suspend core code for storing physical memory address of common resume function and in the same time used by tegra20 cpuidle driver for storing cpu1 "resettable" status, so it implied strict order of scratch register use. Fix it by using scratch 40 instead of 41 for tegra_resume() location store.

You likely can't simply change the PMC scratch register usage arbitrarily; specific registers are designated for specific purposes, and code outside the Linux kernel (bootloaders, LP0 resume code, secure monitors, etc.) may depend on those specific values being in those registers. Without significant research, I'd suggest not changing the PMC scratch register usage.

Dmitry Osipenko

author

2014-12-22 17:27 UTC #2 lore raw

22.12.2014 19:17, Stephen Warren ?????:

Quoted 10 lines · Dmitry Osipenko

Quoted 8 lines
Commit 7232398abc6a ("ARM: tegra: Convert PMC to a driver") changed tegra_resume()
location storing from late to early and as result broke suspend on tegra20. PMC scratch register 41 was used by tegra lp1 suspend core code for storing physical memory address of common resume function and in the same time used by tegra20 cpuidle driver for storing cpu1 "resettable" status, so it implied strict order of scratch register use. Fix it by using scratch 40 instead of 41 for tegra_resume() location store.

Quoted 5 lines

You likely can't simply change the PMC scratch register usage arbitrarily; specific registers are designated for specific purposes, and code outside the Linux kernel (bootloaders, LP0 resume code, secure monitors, etc.) may depend on those specific values being in those registers. Without significant research, I'd suggest not changing the PMC scratch register usage.

Sure, that's why I asked to verify if scratch register 40 is in use in the comment after commit message. I've checked that u-boot doesn't use it (since upstream kernel doesn't care about any other bootloader), but no idea about secure monitor. It's definitely safer to avoid changing scratch regs usage, I thought that proposed solution would be best from the pure code point of view. So, I'm considering your answer as a rejection of the patch (please, let me know if I'm wrong) and will prepare another one. Btw, it would be nice to have scratch registers usage publicly documented somewhere (on "Tegra Public Application Notes" webpage for example), if it's possible, of course.

Signature · 1 line

Dmitry

Stephen Warren

2014-12-22 18:00 UTC #3 lore raw

Quoted 11 lines · Dmitry Osipenko

22.12.2014 19:17, Stephen Warren пишет:
Quoted 10 lines · Dmitry Osipenko
Quoted 8 lines
Commit 7232398abc6a ("ARM: tegra: Convert PMC to a driver") changed tegra_resume()
location storing from late to early and as result broke suspend on tegra20. PMC scratch register 41 was used by tegra lp1 suspend core code for storing physical memory address of common resume function and in the same time used by tegra20 cpuidle driver for storing cpu1 "resettable" status, so it implied strict order of scratch register use. Fix it by using scratch 40 instead of 41 for tegra_resume() location store.

Quoted 8 lines

Quoted 5 lines
You likely can't simply change the PMC scratch register usage arbitrarily; specific registers are designated for specific purposes, and code outside the Linux kernel (bootloaders, LP0 resume code, secure monitors, etc.) may depend on those specific values being in those registers. Without significant research, I'd suggest not changing the PMC scratch register usage.
Sure, that's why I asked to verify if scratch register 40 is in use in the comment after commit message.

Sorry, I didn't notice that.

Quoted 8 lines

I've checked that u-boot doesn't use it (since
upstream kernel doesn't care about any other bootloader), but no idea about secure monitor. It's definitely safer to avoid changing scratch regs usage, I thought that proposed solution would be best from the pure code point of view. So, I'm considering your answer as a rejection of the patch (please, let me know if I'm wrong) and will prepare another one. Btw, it would be nice to have scratch registers usage publicly documented somewhere (on "Tegra Public Application Notes" webpage for example), if it's possible, of course.

At this stage in Tegra20 development, I think it'd be best to avoid changing any scratch register usage if at all possible.

Thierry Reding

2015-01-08 10:57 UTC #4 lore raw

Quoted 32 lines · Stephen Warren

Quoted 11 lines · Dmitry Osipenko
22.12.2014 19:17, Stephen Warren ?????:
Quoted 10 lines · Dmitry Osipenko
Quoted 8 lines
Commit 7232398abc6a ("ARM: tegra: Convert PMC to a driver") changed tegra_resume()
location storing from late to early and as result broke suspend on tegra20. PMC scratch register 41 was used by tegra lp1 suspend core code for storing physical memory address of common resume function and in the same time used by tegra20 cpuidle driver for storing cpu1 "resettable" status, so it implied strict order of scratch register use. Fix it by using scratch 40 instead of 41 for tegra_resume() location store.
Quoted 8 lines
Quoted 5 lines
You likely can't simply change the PMC scratch register usage arbitrarily; specific registers are designated for specific purposes, and code outside the Linux kernel (bootloaders, LP0 resume code, secure monitors, etc.) may depend on those specific values being in those registers. Without significant research, I'd suggest not changing the PMC scratch register usage.
Sure, that's why I asked to verify if scratch register 40 is in use in the comment after commit message.
Sorry, I didn't notice that.
Quoted 8 lines
I've checked that u-boot doesn't use it (since
upstream kernel doesn't care about any other bootloader), but no idea about secure monitor. It's definitely safer to avoid changing scratch regs usage, I thought that proposed solution would be best from the pure code point of view. So, I'm considering your answer as a rejection of the patch (please, let me know if I'm wrong) and will prepare another one. Btw, it would be nice to have scratch registers usage publicly documented somewhere (on "Tegra Public Application Notes" webpage for example), if it's possible, of course.

Quoted 2 lines

At this stage in Tegra20 development, I think it'd be best to avoid changing any scratch register usage if at all possible.

Sorry, I had completely missed this discussion. When looking at the code it doesn't look like this particular "resettable" status needs to be stored in a PMC scratch register. It can't be stored in RAM because that goes into self-refresh as part of LP1, but how about just putting it into IRAM? That stays on in both LP1 and LP2, so should be suitable for this use-case. It would make the code slightly more complex but using a single scratch register for multiple purposes sounds brittle and easy to break (as evidenced by the offending commit).

Otherwise it would seem that PMC_SCRATCH40 is only used to store EMC configuration data across LP0 suspend/resume, so I wouldn't think it'd cause problems if we used that instead of PMC_SCRATCH41 to store the "resettable" state.

Changing the storage location for tegra_resume() isn't such a good idea since that's a documented use of PMC_SCRATCH41.

Thierry
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Peter De Schrijver

2015-01-08 12:37 UTC #5 lore raw

Quoted 47 lines · Thierry Reding

* PGP Signed by an unknown key
Quoted 32 lines · Stephen Warren
Quoted 11 lines · Dmitry Osipenko
22.12.2014 19:17, Stephen Warren ?????:
Quoted 10 lines · Dmitry Osipenko
Quoted 8 lines
Commit 7232398abc6a ("ARM: tegra: Convert PMC to a driver") changed tegra_resume()
location storing from late to early and as result broke suspend on tegra20. PMC scratch register 41 was used by tegra lp1 suspend core code for storing physical memory address of common resume function and in the same time used by tegra20 cpuidle driver for storing cpu1 "resettable" status, so it implied strict order of scratch register use. Fix it by using scratch 40 instead of 41 for tegra_resume() location store.
Quoted 8 lines
Quoted 5 lines
You likely can't simply change the PMC scratch register usage arbitrarily; specific registers are designated for specific purposes, and code outside the Linux kernel (bootloaders, LP0 resume code, secure monitors, etc.) may depend on those specific values being in those registers. Without significant research, I'd suggest not changing the PMC scratch register usage.
Sure, that's why I asked to verify if scratch register 40 is in use in the comment after commit message.
Sorry, I didn't notice that.
Quoted 8 lines
I've checked that u-boot doesn't use it (since
upstream kernel doesn't care about any other bootloader), but no idea about secure monitor. It's definitely safer to avoid changing scratch regs usage, I thought that proposed solution would be best from the pure code point of view. So, I'm considering your answer as a rejection of the patch (please, let me know if I'm wrong) and will prepare another one. Btw, it would be nice to have scratch registers usage publicly documented somewhere (on "Tegra Public Application Notes" webpage for example), if it's possible, of course.
Quoted 2 lines
At this stage in Tegra20 development, I think it'd be best to avoid changing any scratch register usage if at all possible.
Sorry, I had completely missed this discussion. When looking at the code it doesn't look like this particular "resettable" status needs to be stored in a PMC scratch register. It can't be stored in RAM because that goes into self-refresh as part of LP1, but how about just putting it into IRAM? That stays on in both LP1 and LP2, so should be suitable for this use-case. It would make the code slightly more complex but using a single scratch register for multiple purposes sounds brittle and easy to break (as evidenced by the offending commit).

Quoted 5 lines

Otherwise it would seem that PMC_SCRATCH40 is only used to store EMC configuration data across LP0 suspend/resume, so I wouldn't think it'd cause problems if we used that instead of PMC_SCRATCH41 to store the "resettable" state.

No. Usually the scratch registers for EMC config data are setup once by the bootloader and never touched by the kernel after that. So I would not recommend reusing those registers for different purposes.

Cheers,

Peter.

Thierry Reding

2015-01-09 09:51 UTC #6 lore raw

Quoted 54 lines · Peter De Schrijver

Quoted 47 lines · Thierry Reding
* PGP Signed by an unknown key
Quoted 32 lines · Stephen Warren
Quoted 11 lines · Dmitry Osipenko
22.12.2014 19:17, Stephen Warren ?????:
Quoted 10 lines · Dmitry Osipenko
Quoted 8 lines
Commit 7232398abc6a ("ARM: tegra: Convert PMC to a driver") changed tegra_resume()
location storing from late to early and as result broke suspend on tegra20. PMC scratch register 41 was used by tegra lp1 suspend core code for storing physical memory address of common resume function and in the same time used by tegra20 cpuidle driver for storing cpu1 "resettable" status, so it implied strict order of scratch register use. Fix it by using scratch 40 instead of 41 for tegra_resume() location store.
Quoted 8 lines
Quoted 5 lines
You likely can't simply change the PMC scratch register usage arbitrarily; specific registers are designated for specific purposes, and code outside the Linux kernel (bootloaders, LP0 resume code, secure monitors, etc.) may depend on those specific values being in those registers. Without significant research, I'd suggest not changing the PMC scratch register usage.
Sure, that's why I asked to verify if scratch register 40 is in use in the comment after commit message.
Sorry, I didn't notice that.
Quoted 8 lines
I've checked that u-boot doesn't use it (since
upstream kernel doesn't care about any other bootloader), but no idea about secure monitor. It's definitely safer to avoid changing scratch regs usage, I thought that proposed solution would be best from the pure code point of view. So, I'm considering your answer as a rejection of the patch (please, let me know if I'm wrong) and will prepare another one. Btw, it would be nice to have scratch registers usage publicly documented somewhere (on "Tegra Public Application Notes" webpage for example), if it's possible, of course.
Quoted 2 lines
At this stage in Tegra20 development, I think it'd be best to avoid changing any scratch register usage if at all possible.
Sorry, I had completely missed this discussion. When looking at the code it doesn't look like this particular "resettable" status needs to be stored in a PMC scratch register. It can't be stored in RAM because that goes into self-refresh as part of LP1, but how about just putting it into IRAM? That stays on in both LP1 and LP2, so should be suitable for this use-case. It would make the code slightly more complex but using a single scratch register for multiple purposes sounds brittle and easy to break (as evidenced by the offending commit).
Quoted 5 lines
Otherwise it would seem that PMC_SCRATCH40 is only used to store EMC configuration data across LP0 suspend/resume, so I wouldn't think it'd cause problems if we used that instead of PMC_SCRATCH41 to store the "resettable" state.

Quoted 3 lines

No. Usually the scratch registers for EMC config data are setup once by the bootloader and never touched by the kernel after that. So I would not recommend reusing those registers for different purposes.

Right, I misread the code in the downstream kernel. Though it's not the bootloader that does it (at least on Tegra20), but some early code in the kernel.

IRAM sounds like a good candidate still. Or do you know of anything that would exclude IRAM as storage location for this data?

Peter De Schrijver

2015-01-09 10:29 UTC #7 lore raw

Quoted 61 lines · Thierry Reding

* PGP Signed by an unknown key
Quoted 54 lines · Peter De Schrijver
Quoted 47 lines · Thierry Reding
Quoted 1 line
Old Signed by an unknown key
Quoted 32 lines · Stephen Warren
Quoted 11 lines · Dmitry Osipenko
22.12.2014 19:17, Stephen Warren ?????:
Quoted 10 lines · Dmitry Osipenko
Quoted 8 lines
Commit 7232398abc6a ("ARM: tegra: Convert PMC to a driver") changed tegra_resume()
location storing from late to early and as result broke suspend on tegra20. PMC scratch register 41 was used by tegra lp1 suspend core code for storing physical memory address of common resume function and in the same time used by tegra20 cpuidle driver for storing cpu1 "resettable" status, so it implied strict order of scratch register use. Fix it by using scratch 40 instead of 41 for tegra_resume() location store.
Quoted 8 lines
Quoted 5 lines
You likely can't simply change the PMC scratch register usage arbitrarily; specific registers are designated for specific purposes, and code outside the Linux kernel (bootloaders, LP0 resume code, secure monitors, etc.) may depend on those specific values being in those registers. Without significant research, I'd suggest not changing the PMC scratch register usage.
Sure, that's why I asked to verify if scratch register 40 is in use in the comment after commit message.
Sorry, I didn't notice that.
Quoted 8 lines
I've checked that u-boot doesn't use it (since
upstream kernel doesn't care about any other bootloader), but no idea about secure monitor. It's definitely safer to avoid changing scratch regs usage, I thought that proposed solution would be best from the pure code point of view. So, I'm considering your answer as a rejection of the patch (please, let me know if I'm wrong) and will prepare another one. Btw, it would be nice to have scratch registers usage publicly documented somewhere (on "Tegra Public Application Notes" webpage for example), if it's possible, of course.
Quoted 2 lines
At this stage in Tegra20 development, I think it'd be best to avoid changing any scratch register usage if at all possible.
Sorry, I had completely missed this discussion. When looking at the code it doesn't look like this particular "resettable" status needs to be stored in a PMC scratch register. It can't be stored in RAM because that goes into self-refresh as part of LP1, but how about just putting it into IRAM? That stays on in both LP1 and LP2, so should be suitable for this use-case. It would make the code slightly more complex but using a single scratch register for multiple purposes sounds brittle and easy to break (as evidenced by the offending commit).
Quoted 5 lines
Otherwise it would seem that PMC_SCRATCH40 is only used to store EMC configuration data across LP0 suspend/resume, so I wouldn't think it'd cause problems if we used that instead of PMC_SCRATCH41 to store the "resettable" state.
Quoted 3 lines
No. Usually the scratch registers for EMC config data are setup once by the bootloader and never touched by the kernel after that. So I would not recommend reusing those registers for different purposes.

Quoted 6 lines

Right, I misread the code in the downstream kernel. Though it's not the bootloader that does it (at least on Tegra20), but some early code in the kernel.
IRAM sounds like a good candidate still. Or do you know of anything that would exclude IRAM as storage location for this data?

No. I can't think of a reason this flag could not be in IRAM.

Cheers,

Peter.

Dmitry Osipenko

author

2015-01-09 14:36 UTC #8 lore raw

09.01.2015 13:29, Peter De Schrijver ?????:

Quoted 66 lines · Thierry Reding

Quoted 65 lines
* PGP Signed by an unknown key
Quoted 54 lines · Peter De Schrijver
Quoted 47 lines · Thierry Reding
Quoted 1 line
Old Signed by an unknown key
Quoted 32 lines · Stephen Warren
Quoted 11 lines · Dmitry Osipenko
22.12.2014 19:17, Stephen Warren ?????:
Quoted 10 lines · Dmitry Osipenko
Quoted 8 lines
Commit 7232398abc6a ("ARM: tegra: Convert PMC to a driver") changed tegra_resume()
location storing from late to early and as result broke suspend on tegra20. PMC scratch register 41 was used by tegra lp1 suspend core code for storing physical memory address of common resume function and in the same time used by tegra20 cpuidle driver for storing cpu1 "resettable" status, so it implied strict order of scratch register use. Fix it by using scratch 40 instead of 41 for tegra_resume() location store.
Quoted 8 lines
Quoted 5 lines
You likely can't simply change the PMC scratch register usage arbitrarily; specific registers are designated for specific purposes, and code outside the Linux kernel (bootloaders, LP0 resume code, secure monitors, etc.) may depend on those specific values being in those registers. Without significant research, I'd suggest not changing the PMC scratch register usage.
Sure, that's why I asked to verify if scratch register 40 is in use in the comment after commit message.
Sorry, I didn't notice that.
Quoted 8 lines
I've checked that u-boot doesn't use it (since
upstream kernel doesn't care about any other bootloader), but no idea about secure monitor. It's definitely safer to avoid changing scratch regs usage, I thought that proposed solution would be best from the pure code point of view. So, I'm considering your answer as a rejection of the patch (please, let me know if I'm wrong) and will prepare another one. Btw, it would be nice to have scratch registers usage publicly documented somewhere (on "Tegra Public Application Notes" webpage for example), if it's possible, of course.
Quoted 2 lines
At this stage in Tegra20 development, I think it'd be best to avoid changing any scratch register usage if at all possible.
Sorry, I had completely missed this discussion. When looking at the code it doesn't look like this particular "resettable" status needs to be stored in a PMC scratch register. It can't be stored in RAM because that goes into self-refresh as part of LP1, but how about just putting it into IRAM? That stays on in both LP1 and LP2, so should be suitable for this use-case. It would make the code slightly more complex but using a single scratch register for multiple purposes sounds brittle and easy to break (as evidenced by the offending commit).
Quoted 5 lines
Otherwise it would seem that PMC_SCRATCH40 is only used to store EMC configuration data across LP0 suspend/resume, so I wouldn't think it'd cause problems if we used that instead of PMC_SCRATCH41 to store the "resettable" state.
Quoted 3 lines
No. Usually the scratch registers for EMC config data are setup once by the bootloader and never touched by the kernel after that. So I would not recommend reusing those registers for different purposes.
Right, I misread the code in the downstream kernel. Though it's not the bootloader that does it (at least on Tegra20), but some early code in the kernel.

Quoted 9 lines

Quoted 2 lines
IRAM sounds like a good candidate still. Or do you know of anything that would exclude IRAM as storage location for this data?
No. I can't think of a reason this flag could not be in IRAM.
Cheers,
Peter.

IRAM is a good candidate. Just tested draft patch version in QEMU, will give it more testing and polish during weekend and send next week.

Signature · 1 line

Dmitry

Stephen Warren

2015-01-09 16:56 UTC #9 lore raw

In reply to Peter De Schrijver

Quoted 62 lines · Peter De Schrijver

Quoted 61 lines · Thierry Reding
* PGP Signed by an unknown key
Quoted 57 lines · Peter De Schrijver
Quoted 47 lines · Thierry Reding
Quoted 1 line
Old Signed by an unknown key
Quoted 32 lines · Stephen Warren
Quoted 11 lines · Dmitry Osipenko
22.12.2014 19:17, Stephen Warren пишет:
Quoted 10 lines · Dmitry Osipenko
Quoted 8 lines
Commit 7232398abc6a ("ARM: tegra: Convert PMC to a driver") changed tegra_resume()
location storing from late to early and as result broke suspend on tegra20. PMC scratch register 41 was used by tegra lp1 suspend core code for storing physical memory address of common resume function and in the same time used by tegra20 cpuidle driver for storing cpu1 "resettable" status, so it implied strict order of scratch register use. Fix it by using scratch 40 instead of 41 for tegra_resume() location store.
Quoted 8 lines
Quoted 5 lines
You likely can't simply change the PMC scratch register usage arbitrarily; specific registers are designated for specific purposes, and code outside the Linux kernel (bootloaders, LP0 resume code, secure monitors, etc.) may depend on those specific values being in those registers. Without significant research, I'd suggest not changing the PMC scratch register usage.
Sure, that's why I asked to verify if scratch register 40 is in use in the comment after commit message.
Sorry, I didn't notice that.
Quoted 8 lines
I've checked that u-boot doesn't use it (since
upstream kernel doesn't care about any other bootloader), but no idea about secure monitor. It's definitely safer to avoid changing scratch regs usage, I thought that proposed solution would be best from the pure code point of view. So, I'm considering your answer as a rejection of the patch (please, let me know if I'm wrong) and will prepare another one. Btw, it would be nice to have scratch registers usage publicly documented somewhere (on "Tegra Public Application Notes" webpage for example), if it's possible, of course.
Quoted 2 lines
At this stage in Tegra20 development, I think it'd be best to avoid changing any scratch register usage if at all possible.
Sorry, I had completely missed this discussion. When looking at the code it doesn't look like this particular "resettable" status needs to be stored in a PMC scratch register. It can't be stored in RAM because that goes into self-refresh as part of LP1, but how about just putting it into IRAM? That stays on in both LP1 and LP2, so should be suitable for this use-case. It would make the code slightly more complex but using a single scratch register for multiple purposes sounds brittle and easy to break (as evidenced by the offending commit).
Quoted 5 lines
Otherwise it would seem that PMC_SCRATCH40 is only used to store EMC configuration data across LP0 suspend/resume, so I wouldn't think it'd cause problems if we used that instead of PMC_SCRATCH41 to store the "resettable" state.
No. Usually the scratch registers for EMC config data are setup once by the bootloader and never touched by the kernel after that. So I would not recommend reusing those registers for different purposes.

Quoted 8 lines

Quoted 6 lines
Right, I misread the code in the downstream kernel. Though it's not the bootloader that does it (at least on Tegra20), but some early code in the kernel.
IRAM sounds like a good candidate still. Or do you know of anything that would exclude IRAM as storage location for this data?
No. I can't think of a reason this flag could not be in IRAM.

The only thing you might want to watch out for is whether something else is using IRAM. For example, our product SW stacks use the AVP as a media co-processor and that runs at least some of its code from IRAM. To support something similar, you'd need to make sure to save/restore the IRAM content when using it for other purposes rather than just blindly over-writing it (and of course synchronize with any driver for the AVP execution, to ensure it was shut down first and brought back up last after any power saving event). Of course, we don't actually support loading code onto the AVP upstream at the moment, so perhaps we can defer handling that for now.

Dmitry Osipenko

author

2015-01-09 17:07 UTC #10 lore raw

09.01.2015 19:57, Stephen Warren ?????:

Quoted 82 lines · Peter De Schrijver

Quoted 72 lines · Thierry Reding
Quoted 71 lines
* PGP Signed by an unknown key
Quoted 67 lines · Peter De Schrijver
Quoted 57 lines · Thierry Reding
Quoted 1 line
Old Signed by an unknown key
Quoted 42 lines · Stephen Warren
Quoted 24 lines · Dmitry Osipenko
22.12.2014 19:17, Stephen Warren ?????:
Quoted 14 lines · Dmitry Osipenko
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Commit 7232398abc6a ("ARM: tegra: Convert PMC to a driver") changed tegra_resume()
location storing from late to early and as result broke suspend on tegra20.
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PMC scratch register 41 was used by tegra lp1 suspend core code for storing
physical memory address of common resume function and in the same time used by
tegra20 cpuidle driver for storing cpu1 "resettable" status, so it implied strict order of scratch register use. Fix it by using scratch 40 instead of 41
for tegra_resume() location store.
Quoted 8 lines
You likely can't simply change the PMC scratch register usage arbitrarily; specific registers are designated for specific purposes, and code outside the
Linux kernel (bootloaders, LP0 resume code, secure monitors, etc.) may depend on
those specific values being in those registers. Without significant research,
I'd suggest not changing the PMC scratch register usage.
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Sure, that's why I asked to verify if scratch register 40 is in use in the comment after commit message.
Sorry, I didn't notice that.
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I've checked that u-boot doesn't use it (since
upstream kernel doesn't care about any other bootloader), but no idea about secure monitor. It's definitely safer to avoid changing scratch regs usage, I
thought that proposed solution would be best from the pure code point of view.
So, I'm considering your answer as a rejection of the patch (please, let me know
if I'm wrong) and will prepare another one. Btw, it would be nice to have scratch registers usage publicly documented somewhere (on "Tegra Public Application Notes" webpage for example), if it's possible, of course.
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At this stage in Tegra20 development, I think it'd be best to avoid changing any scratch register usage if at all possible.
Sorry, I had completely missed this discussion. When looking at the code it doesn't look like this particular "resettable" status needs to be stored in a PMC scratch register. It can't be stored in RAM because that goes into self-refresh as part of LP1, but how about just putting it into IRAM? That stays on in both LP1 and LP2, so should be suitable for this use-case. It would make the code slightly more complex but using a single scratch register for multiple purposes sounds brittle and easy to break (as evidenced by the offending commit).
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Otherwise it would seem that PMC_SCRATCH40 is only used to store EMC configuration data across LP0 suspend/resume, so I wouldn't think it'd cause problems if we used that instead of PMC_SCRATCH41 to store the "resettable" state.
No. Usually the scratch registers for EMC config data are setup once by the bootloader and never touched by the kernel after that. So I would not recommend reusing those registers for different purposes.
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Right, I misread the code in the downstream kernel. Though it's not the bootloader that does it (at least on Tegra20), but some early code in the kernel.
IRAM sounds like a good candidate still. Or do you know of anything that would exclude IRAM as storage location for this data?
No. I can't think of a reason this flag could not be in IRAM.

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The only thing you might want to watch out for is whether something else is using IRAM. For example, our product SW stacks use the AVP as a media co-processor and that runs at least some of its code from IRAM. To support something similar, you'd need to make sure to save/restore the IRAM content when using it for other purposes rather than just blindly over-writing it (and of course synchronize with any driver for the AVP execution, to ensure it was shut down first and brought back up last after any power saving event). Of course, we don't actually support loading code onto the AVP upstream at the moment, so perhaps we can defer handling that for now.

Sure, currently I placed "resettable" variable in IRAM reset handler area for that reason. As I wrote before, I'll give patch more polish and send after.

Signature · 1 line

Dmitry