video: Add support for SSD2828 (parallel LCD to MIPI bridge)

index 7d6d075..12a2e77 100644
@@ -189,6 +189,7 @@ void sunxi_board_init(void)
 	power_failed |= axp221_set_aldo1(CONFIG_AXP221_ALDO1_VOLT);
 	power_failed |= axp221_set_aldo2(CONFIG_AXP221_ALDO2_VOLT);
 	power_failed |= axp221_set_aldo3(CONFIG_AXP221_ALDO3_VOLT);
+	power_failed |= axp221_set_eldo3(CONFIG_AXP221_ELDO3_VOLT);
 #endif
 
 	printf("DRAM:");

57 lines not on this page · raw message

index e9552f6..da63891 100644
@@ -26,6 +26,9 @@
 #define AXP221_OUTPUT_CTRL1_ALDO1_EN	(1 << 6)
 #define AXP221_OUTPUT_CTRL1_ALDO2_EN	(1 << 7)
 #define AXP221_OUTPUT_CTRL2	0x12
+#define AXP221_OUTPUT_CTRL2_ELDO1_EN	(1 << 0)
+#define AXP221_OUTPUT_CTRL2_ELDO2_EN	(1 << 1)
+#define AXP221_OUTPUT_CTRL2_ELDO3_EN	(1 << 2)
 #define AXP221_OUTPUT_CTRL2_DLDO1_EN	(1 << 3)
 #define AXP221_OUTPUT_CTRL2_DLDO2_EN	(1 << 4)
 #define AXP221_OUTPUT_CTRL2_DLDO3_EN	(1 << 5)

@@ -37,6 +40,9 @@
 #define AXP221_DLDO2_CTRL	0x16
 #define AXP221_DLDO3_CTRL	0x17
 #define AXP221_DLDO4_CTRL	0x18
+#define AXP221_ELDO1_CTRL	0x19
+#define AXP221_ELDO2_CTRL	0x1a
+#define AXP221_ELDO3_CTRL	0x1b
 #define AXP221_DCDC1_CTRL	0x21
 #define AXP221_DCDC2_CTRL	0x22
 #define AXP221_DCDC3_CTRL	0x23

@@ -62,5 +68,8 @@ int axp221_set_dldo4(unsigned int mvolt);
 int axp221_set_aldo1(unsigned int mvolt);
 int axp221_set_aldo2(unsigned int mvolt);
 int axp221_set_aldo3(unsigned int mvolt);
+int axp221_set_eldo1(unsigned int mvolt);
+int axp221_set_eldo2(unsigned int mvolt);
+int axp221_set_eldo3(unsigned int mvolt);
 int axp221_init(void);
 int axp221_get_sid(unsigned int *sid);

new file mode 100644
index 0000000..ddcc8ca
@@ -0,0 +1,130 @@
+/*
+ * Defines for Mobile Industry Processor Interface (MIPI(R))
+ * Display Working Group standards: DSI, DCS, DBI, DPI
+ *
+ * Copyright (C) 2010 Guennadi Liakhovetski <[email protected]>
+ * Copyright (C) 2006 Nokia Corporation
+ * Author: Imre Deak <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef MIPI_DISPLAY_H
+#define MIPI_DISPLAY_H
+
+/* MIPI DSI Processor-to-Peripheral transaction types */
+enum {
+	MIPI_DSI_V_SYNC_START				= 0x01,
+	MIPI_DSI_V_SYNC_END				= 0x11,
+	MIPI_DSI_H_SYNC_START				= 0x21,
+	MIPI_DSI_H_SYNC_END				= 0x31,
+
+	MIPI_DSI_COLOR_MODE_OFF				= 0x02,
+	MIPI_DSI_COLOR_MODE_ON				= 0x12,
+	MIPI_DSI_SHUTDOWN_PERIPHERAL			= 0x22,
+	MIPI_DSI_TURN_ON_PERIPHERAL			= 0x32,
+
+	MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM		= 0x03,
+	MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM		= 0x13,
+	MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM		= 0x23,
+
+	MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM		= 0x04,
+	MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM		= 0x14,
+	MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM		= 0x24,
+
+	MIPI_DSI_DCS_SHORT_WRITE			= 0x05,
+	MIPI_DSI_DCS_SHORT_WRITE_PARAM			= 0x15,
+
+	MIPI_DSI_DCS_READ				= 0x06,
+
+	MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE		= 0x37,
+
+	MIPI_DSI_END_OF_TRANSMISSION			= 0x08,
+
+	MIPI_DSI_NULL_PACKET				= 0x09,
+	MIPI_DSI_BLANKING_PACKET			= 0x19,
+	MIPI_DSI_GENERIC_LONG_WRITE			= 0x29,
+	MIPI_DSI_DCS_LONG_WRITE				= 0x39,
+
+	MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20	= 0x0c,
+	MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24		= 0x1c,
+	MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16		= 0x2c,
+
+	MIPI_DSI_PACKED_PIXEL_STREAM_30			= 0x0d,
+	MIPI_DSI_PACKED_PIXEL_STREAM_36			= 0x1d,
+	MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12		= 0x3d,
+
+	MIPI_DSI_PACKED_PIXEL_STREAM_16			= 0x0e,
+	MIPI_DSI_PACKED_PIXEL_STREAM_18			= 0x1e,
+	MIPI_DSI_PIXEL_STREAM_3BYTE_18			= 0x2e,
+	MIPI_DSI_PACKED_PIXEL_STREAM_24			= 0x3e,
+};
+
+/* MIPI DSI Peripheral-to-Processor transaction types */
+enum {
+	MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT	= 0x02,
+	MIPI_DSI_RX_END_OF_TRANSMISSION			= 0x08,
+	MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE	= 0x11,
+	MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE	= 0x12,
+	MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE		= 0x1a,
+	MIPI_DSI_RX_DCS_LONG_READ_RESPONSE		= 0x1c,
+	MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE	= 0x21,
+	MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE	= 0x22,
+};
+
+/* MIPI DCS commands */
+enum {
+	MIPI_DCS_NOP			= 0x00,
+	MIPI_DCS_SOFT_RESET		= 0x01,
+	MIPI_DCS_GET_DISPLAY_ID		= 0x04,
+	MIPI_DCS_GET_RED_CHANNEL	= 0x06,
+	MIPI_DCS_GET_GREEN_CHANNEL	= 0x07,
+	MIPI_DCS_GET_BLUE_CHANNEL	= 0x08,
+	MIPI_DCS_GET_DISPLAY_STATUS	= 0x09,
+	MIPI_DCS_GET_POWER_MODE		= 0x0A,
+	MIPI_DCS_GET_ADDRESS_MODE	= 0x0B,
+	MIPI_DCS_GET_PIXEL_FORMAT	= 0x0C,
+	MIPI_DCS_GET_DISPLAY_MODE	= 0x0D,
+	MIPI_DCS_GET_SIGNAL_MODE	= 0x0E,
+	MIPI_DCS_GET_DIAGNOSTIC_RESULT	= 0x0F,
+	MIPI_DCS_ENTER_SLEEP_MODE	= 0x10,
+	MIPI_DCS_EXIT_SLEEP_MODE	= 0x11,
+	MIPI_DCS_ENTER_PARTIAL_MODE	= 0x12,
+	MIPI_DCS_ENTER_NORMAL_MODE	= 0x13,
+	MIPI_DCS_EXIT_INVERT_MODE	= 0x20,
+	MIPI_DCS_ENTER_INVERT_MODE	= 0x21,
+	MIPI_DCS_SET_GAMMA_CURVE	= 0x26,
+	MIPI_DCS_SET_DISPLAY_OFF	= 0x28,
+	MIPI_DCS_SET_DISPLAY_ON		= 0x29,
+	MIPI_DCS_SET_COLUMN_ADDRESS	= 0x2A,
+	MIPI_DCS_SET_PAGE_ADDRESS	= 0x2B,
+	MIPI_DCS_WRITE_MEMORY_START	= 0x2C,
+	MIPI_DCS_WRITE_LUT		= 0x2D,
+	MIPI_DCS_READ_MEMORY_START	= 0x2E,
+	MIPI_DCS_SET_PARTIAL_AREA	= 0x30,
+	MIPI_DCS_SET_SCROLL_AREA	= 0x33,
+	MIPI_DCS_SET_TEAR_OFF		= 0x34,
+	MIPI_DCS_SET_TEAR_ON		= 0x35,
+	MIPI_DCS_SET_ADDRESS_MODE	= 0x36,
+	MIPI_DCS_SET_SCROLL_START	= 0x37,
+	MIPI_DCS_EXIT_IDLE_MODE		= 0x38,
+	MIPI_DCS_ENTER_IDLE_MODE	= 0x39,
+	MIPI_DCS_SET_PIXEL_FORMAT	= 0x3A,
+	MIPI_DCS_WRITE_MEMORY_CONTINUE	= 0x3C,
+	MIPI_DCS_READ_MEMORY_CONTINUE	= 0x3E,
+	MIPI_DCS_SET_TEAR_SCANLINE	= 0x44,
+	MIPI_DCS_GET_SCANLINE		= 0x45,
+	MIPI_DCS_READ_DDB_START		= 0xA1,
+	MIPI_DCS_READ_DDB_CONTINUE	= 0xA8,
+};
+
+/* MIPI DCS pixel formats */
+#define MIPI_DCS_PIXEL_FMT_24BIT	7
+#define MIPI_DCS_PIXEL_FMT_18BIT	6
+#define MIPI_DCS_PIXEL_FMT_16BIT	5
+#define MIPI_DCS_PIXEL_FMT_12BIT	3
+#define MIPI_DCS_PIXEL_FMT_8BIT		2
+#define MIPI_DCS_PIXEL_FMT_3BIT		1
+
+#endif

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index c3fc732..f11b241 100644
@@ -850,6 +850,9 @@ static void sunxi_mode_set(const struct ctfb_res_modes *mode,
 		sunxi_lcdc_tcon0_mode_set(mode);
 		sunxi_composer_enable();
 		sunxi_lcdc_enable();
+#ifdef CONFIG_VIDEO_LCD_SSD2828
+		sunxi_ssd2828_init(mode);
+#endif
 		sunxi_lcdc_backlight_enable();
 		break;
 	case sunxi_monitor_vga:

index 9ebaff2..cdde639 100644
@@ -11,6 +11,8 @@
 #include <asm/arch/gpio.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
+#include "sunxi_lcd_panel.h"
+#include "ssd2828.h"
 
 #ifdef CONFIG_VIDEO_LCD_PANEL_HITACHI_TX18D42VM
 

@@ -66,3 +68,39 @@ void sunxi_lcd_panel_hitachi_tx18d42vm_init(void)
 }
 
 #endif
+
+#ifdef CONFIG_VIDEO_LCD_SSD2828
+
+int sunxi_ssd2828_init(const struct ctfb_res_modes *mode)
+{
+	struct ssd2828_config cfg = {
+		.csx_pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SPI_CS),
+		.sck_pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SPI_SCLK),
+		.sdi_pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SPI_MOSI),
+		.sdo_pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SPI_MISO),
+		.reset_pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SSD2828_RESET),
+		.ssd2828_tx_clk_khz                      = 27000,
+		.ssd2828_color_depth                     = 24,
+#ifdef CONFIG_VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
+		.mipi_dsi_number_of_data_lanes           = 4,
+		.mipi_dsi_bitrate_per_data_lane_mbps     = 513,
+		.mipi_dsi_delay_after_exit_sleep_mode_ms = 100,
+		.mipi_dsi_delay_after_set_display_on_ms  = 200
+#else
+#error MIPI LCD panel needs configuration parameters
+#endif
+	};
+
+	if (cfg.csx_pin == -1 || cfg.sck_pin == -1 || cfg.sdi_pin == -1) {
+		printf("SSD2828: SPI pins are not properly configured\n");
+		return 1;
+	}
+	if (cfg.reset_pin == -1) {
+		printf("SSD2828: Reset pin is not properly configured\n");
+		return 1;
+	}
+
+	return ssd2828_init(&cfg, mode);
+}
+
+#endif

index 1fb9f1e..8b1bc14 100644
@@ -6,4 +6,7 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
+struct ctfb_res_modes;
+
 void sunxi_lcd_panel_hitachi_tx18d42vm_init(void);
+int sunxi_ssd2828_init(const struct ctfb_res_modes *mode);

index 566ec19..702afd9 100644
@@ -339,7 +339,7 @@ static int ssd2828_configure_video_interface(const struct ssd2828_config *cfg,
 int ssd2828_init(const struct ssd2828_config *cfg,
 		 const struct ctfb_res_modes *mode)
 {
-	u32 lp_div, pll_freq_kbps, pll_config;
+	u32 lp_div, pll_freq_kbps, reference_freq_khz, pll_config;
 	/* The LP clock speed is limited by 10MHz */
 	const u32 mipi_dsi_low_power_clk_khz = 10000;
 	/*

@@ -373,6 +373,20 @@ int ssd2828_init(const struct ssd2828_config *cfg,
 	}
 
 	/*
+	 * Pick the reference clock for PLL. If we know the exact 'tx_clk'
+	 * clock speed, then everything is good. If not, then we can fallback
+	 * to 'pclk' (pixel clock from the parallel LCD interface). In the
+	 * case of using this fallback, it is necessary to have parallel LCD
+	 * already initialized and running at this point.
+	 */
+	reference_freq_khz = cfg->ssd2828_tx_clk_khz;
+	if (reference_freq_khz  == 0) {
+		reference_freq_khz = mode->pixclock_khz;
+		/* Use 'pclk' as the reference clock for PLL */
+		cfgr_reg |= SSD2828_CFGR_CSS;
+	}
+
+	/*
 	 * Setup the parallel LCD timings in the appropriate registers.
 	 */
 	if (ssd2828_configure_video_interface(cfg, mode) != 0) {

@@ -389,10 +403,10 @@ int ssd2828_init(const struct ssd2828_config *cfg,
 	/* PLL Configuration Register */
 	pll_config = construct_pll_config(
 				cfg->mipi_dsi_bitrate_per_data_lane_mbps * 1000,
-				cfg->ssd2828_tx_clk_khz);
+				reference_freq_khz);
 	write_hw_register(cfg, SSD2828_PLCR, pll_config);
 
-	pll_freq_kbps = decode_pll_config(pll_config, cfg->ssd2828_tx_clk_khz);
+	pll_freq_kbps = decode_pll_config(pll_config, reference_freq_khz);
 	lp_div = DIV_ROUND_UP(pll_freq_kbps, mipi_dsi_low_power_clk_khz * 8);
 
 	/* VC Control Register */

index 14b96c5..1af6fa4 100644
@@ -47,8 +47,12 @@ struct ssd2828_config {
 	 * to TX_CLK_XIO/TX_CLK_XIN pins), which is necessary at least for
 	 * clocking SPI after reset. The exact clock speed is not strictly,
 	 * defined, but the datasheet says that it must be somewhere in the
-	 * 8MHz - 30MHz range (see "TX_CLK Timing" section). It is used as
-	 * a reference clock for PLL and must be set correctly.
+	 * 8MHz - 30MHz range (see "TX_CLK Timing" section). It can be also
+	 * used as a reference clock for PLL. If the exact clock frequency
+	 * is known, then it can be specified here. If it is unknown, or the
+	 * information is not trustworthy, then it can be set to 0.
+	 *
+	 * If unsure, set to 0.
 	 */
 	int ssd2828_tx_clk_khz;
 

@@ -115,7 +119,8 @@ struct ssd2828_config {
  * The right place to insert this function call is after the parallel LCD
  * interface is initialized and before turning on the backlight. This is
  * advised in the "Example for system sleep in and out" section of the
- * SSD2828 datasheet.
+ * SSD2828 datasheet. And also SS2828 may use 'pclk' as the clock source
+ * for PLL, which means that the input signal must be already there.
  */
 int ssd2828_init(const struct ssd2828_config *cfg,
 		 const struct ctfb_res_modes *mode);

index cdde639..ebc0ca5 100644
@@ -79,7 +79,6 @@ int sunxi_ssd2828_init(const struct ctfb_res_modes *mode)
 		.sdi_pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SPI_MOSI),
 		.sdo_pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SPI_MISO),
 		.reset_pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SSD2828_RESET),
-		.ssd2828_tx_clk_khz                      = 27000,
 		.ssd2828_color_depth                     = 24,
 #ifdef CONFIG_VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
 		.mipi_dsi_number_of_data_lanes           = 4,

index 702afd9..cfebedd 100644
@@ -98,6 +98,9 @@
 #define	SSD2828_CFGR_LPE				(1 << 10)
 #define	SSD2828_CFGR_TXD				(1 << 11)
 
+#define	SSD2828_ISR_READ_DATA_READY			(1 << 0)
+#define	SSD2828_ISR_BTA_RESPONSE			(1 << 2)
+
 #define	SSD2828_VIDEO_MODE_NON_BURST_WITH_SYNC_PULSES	(0 << 2)
 #define	SSD2828_VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS	(1 << 2)
 #define	SSD2828_VIDEO_MODE_BURST			(2 << 2)

@@ -167,6 +170,30 @@ static void write_hw_register(const struct ssd2828_config *cfg, u8 regnum,
 	soft_spi_xfer_24bit_3wire(cfg, 0x720000 | val);
 }
 
+static int await_completion(const struct ssd2828_config *cfg,
+			    u8 reg, u32 mask, u32 val)
+{
+	unsigned long tmo = timer_get_us() + 100000;
+
+	while ((read_hw_register(cfg, reg) & mask) != val) {
+		if (timer_get_us() > tmo)
+			return 1;
+	}
+	return 0;
+}
+
+static int await_bits_set(const struct ssd2828_config *cfg,
+			  u8 reg, u32 val)
+{
+	return await_completion(cfg, reg, val, val);
+}
+
+static int await_bits_clear(const struct ssd2828_config *cfg,
+			    u8 reg, u32 val)
+{
+	return await_completion(cfg, reg, val, 0);
+}
+
 /*
  * Send MIPI command to the LCD panel (cmdnum < 0xB0)
  */

@@ -179,6 +206,79 @@ static void send_mipi_dcs_command(const struct ssd2828_config *cfg, u8 cmdnum)
 }
 
 /*
+ * Sends a MIPI DCS command to retrieve information from the LCD panel.
+ */
+static int send_mipi_dcs_read_command(const struct ssd2828_config *cfg,
+				      u8                           cmdnum,
+				      u8                          *result_buf,
+				      int                          bufsize)
+{
+	int size, i, result = 0;
+	/* Save CFGR register */
+	u32 old_cfgr = read_hw_register(cfg, SSD2828_CFGR);
+
+	/* Set the read enable bit */
+	write_hw_register(cfg, SSD2828_CFGR, old_cfgr | SSD2828_CFGR_REN);
+	/* Clear buffers and bring the state machine to its initial state */
+	write_hw_register(cfg, SSD2828_OCR, 1);
+	if (await_bits_clear(cfg, SSD2828_OCR, 1) != 0)
+		goto err;
+	/* Clear the RW1C bits in the ISR register */
+	write_hw_register(cfg, SSD2828_ISR, read_hw_register(cfg, SSD2828_ISR));
+
+	/* Set the payload size (only the DCS command itself) */
+	write_hw_register(cfg, SSD2828_PSCR1, 1);
+	/* Set maximum return size */
+	write_hw_register(cfg, SSD2828_MRSR, bufsize);
+	/* Write the command */
+	write_hw_register(cfg, SSD2828_PDR, cmdnum);
+
+	/* Wait for the response */
+	if (await_bits_set(cfg, SSD2828_ISR, SSD2828_ISR_BTA_RESPONSE) != 0)
+		goto err; /* Timeout */
+
+	/* Check if there is anything in the read buffer */
+	if (!(read_hw_register(cfg, SSD2828_ISR) & SSD2828_ISR_READ_DATA_READY))
+		goto err; /* There is no data to read */
+
+	/* The size of the response packet */
+	size = read_hw_register(cfg, SSD2828_RDCR);
+	if (size > bufsize) {
+		debug("SSD2828: Suspicious packet size.\n");
+		size = bufsize;
+	}
+	result = size;
+
+	/*
+	 * This is somewhat special and does not seem to be well documented:
+	 * 1) In order to properly read the data, all the buffer must be read
+	 *    in one go without any interruptions. For example, using individual
+	 *    reads done by the "read_hw_register" function only result in
+	 *    repeatedly getting all the same first 16-bits of data without
+	 *    advancing.
+	 * 2) In order to empty the buffer, it is necessary to read as much
+	 *    data as was initially configured in the MRSR register. The real
+	 *    size of the packet in the RDCR register just indicates how much
+	 *    of it is actually valid.
+	 */
+	soft_spi_xfer_24bit_3wire(cfg, 0x700000 | SSD2828_RR);
+	for (i = 0; i < (bufsize + 1) / 2; i++) {
+		u16 data = soft_spi_xfer_24bit_3wire(cfg, 0x730000);
+		if (size-- > 0)
+			*result_buf++ = data & 0xFF;
+		if (size-- > 0)
+			*result_buf++ = (data >> 8) & 0xFF;
+	}
+
+	if (read_hw_register(cfg, SSD2828_ISR) & SSD2828_ISR_READ_DATA_READY)
+		debug("SSD2828: There is still some bogus unread data.\n");
+err:
+	/* Restore CFGR register */
+	write_hw_register(cfg, SSD2828_CFGR, old_cfgr);
+	return result;
+}
+
+/*
  * Reset SSD2828
  */
 static void ssd2828_reset(const struct ssd2828_config *cfg)

@@ -336,6 +436,42 @@ static int ssd2828_configure_video_interface(const struct ssd2828_config *cfg,
 	return 0;
 }
 
+static void ssd2828_report_dcs_read_result(const struct ssd2828_config *cfg,
+					   u8 cmd)
+{
+	u8 buf[64];
+	int size, i;
+	size = send_mipi_dcs_read_command(cfg, cmd, buf, sizeof(buf));
+	if (size > 0) {
+		printf("DCS command 0x%02X returned %2d bytes:", cmd, size);
+		for (i = 0; i < size; i++)
+			printf(" %02X", buf[i]);
+		printf("\n");
+	}
+}
+
+/*
+ * Try to use different DCS commands to identify the panel id and
+ * report it in the log.
+ */
+static void ssd2828_report_panel_id(const struct ssd2828_config *cfg)
+{
+	printf("Trying standard MIPI DSI commands to identify LCD panel:\n");
+
+	ssd2828_report_dcs_read_result(cfg, MIPI_DCS_GET_DISPLAY_ID);
+	ssd2828_report_dcs_read_result(cfg, MIPI_DCS_READ_DDB_START);
+
+	printf("Trying nonstandard MIPI DSI commands to identify LCD panel:\n");
+
+	/* Used by some LG panels (for example, LH350WS1-SD02.pdf) */
+	ssd2828_report_dcs_read_result(cfg, 0xB1);
+
+	/* Used by many LCD panels (for example, DA8620.pdf) */
+	ssd2828_report_dcs_read_result(cfg, 0xDA);
+	ssd2828_report_dcs_read_result(cfg, 0xDB);
+	ssd2828_report_dcs_read_result(cfg, 0xDC);
+}
+
 int ssd2828_init(const struct ssd2828_config *cfg,
 		 const struct ctfb_res_modes *mode)
 {

@@ -424,6 +560,10 @@ int ssd2828_init(const struct ssd2828_config *cfg,
 	send_mipi_dcs_command(cfg, MIPI_DCS_EXIT_SLEEP_MODE);
 	mdelay(cfg->mipi_dsi_delay_after_exit_sleep_mode_ms);
 
+	/* If it is possible to read back, then try to retrieve the panel id */
+	if (cfg->sdo_pin != -1)
+		ssd2828_report_panel_id(cfg);
+
 	send_mipi_dcs_command(cfg, MIPI_DCS_SET_DISPLAY_ON);
 	mdelay(cfg->mipi_dsi_delay_after_set_display_on_ms);