Skip to contentSkip to conversation

ARM: at91: dts: sama5d3/sama5d4: reduce NFC command registers memory region

PATCH New Josh Wu 3 participants 7 messages Jan 15, 2015 – Mar 5, 2015 Device tree bindings

lore
Share & tools
lore

Josh Wu

author
#0 lore raw

PATCH 1/1 ARM: at91: dts: sama5d3/sama5d4: reduce NFC command registers memory region

To get NFC status, we need to read the NFC command registers, which is a 256M memory mapping address. To check the status, you just read such address from NFC command registers.
For example, to check NFCBUSY (bit 27), you need to read 0x08000000 (bit 27 is set to 1) of the NFC command register.
If you want to check NFCBUSY (bit 27) and NFCWR (bit 26) in same time, you need to read 0x0c000000 (bit 27 and bit 26 are set to 1).

But mapping such huge memory address only for multiple NFC status check is not very economic.

The economic way is we check the NFC status one bit a time, then we don't have to mapping such huge address.

Now we reduce the memory mapping from 256M to 128M+4 (include 0x08000000), the only difference is NFCBUSY (bit 27) status. You cannot check NFCBUSY bit with other NFC status bit.

Since current atmel_nand driver check the NFCBUSY status without combine other bits, so this change (reduce 256M to 128M+4) will not be harmful.

---

 arch/arm/boot/dts/sama5d3.dtsi | 2 +-
 arch/arm/boot/dts/sama5d4.dtsi | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)
arch/arm/boot/dts/sama5d3.dtsi +1 -1
index d701ddd..d243732 100644
@@ -1426,7 +1426,7 @@
 				#address-cells = <1>;
 				#size-cells = <1>;
 				reg = <
-					0x70000000 0x10000000	/* NFC Command Registers */
+					0x70000000 0x08000004	/* NFC Command Registers */
 					0xffffc000 0x00000070	/* NFC HSMC regs */
 					0x00200000 0x00100000	/* NFC SRAM banks */
 					>;
arch/arm/boot/dts/sama5d4.dtsi +1 -1
index 0a2477f..05b096b 100644
@@ -288,7 +288,7 @@
 				#address-cells = <1>;
 				#size-cells = <1>;
 				reg = <
-					0x90000000 0x10000000	/* NFC Command Registers */
+					0x90000000 0x08000004	/* NFC Command Registers */
 					0xfc05c000 0x00000070	/* NFC HSMC regs */
 					0x00100000 0x00100000	/* NFC SRAM banks */
                                          >;
Signature · 1 line
1.9.1
#1 lore raw

PATCH 1/1 ARM: at91: dts: sama5d3/sama5d4: reduce NFC command registers memory region

Hi Josh,

Quoted 7 lines · On Thu, 15 Jan 2015 15:08:03 +0800 Josh Wu <[email protected]> wrote:

To get NFC status, we need to read the NFC command registers, which is a 256M memory mapping address. To check the status, you just read such address from NFC command registers.
For example, to check NFCBUSY (bit 27), you need to read 0x08000000 (bit 27 is set to 1) of the NFC command register.
If you want to check NFCBUSY (bit 27) and NFCWR (bit 26) in same time, you need to read 0x0c000000 (bit 27 and bit 26 are set to 1).

Are NFCBUSY and NFCWR found in NFCDATA_STATUS and those found in HSMC_SR representing the same thing.
If they are, I think you can just use HSMC_SR instead of NFCDATA_STATUS to check the status [1] and drop the last bit in the NFC Command Resgiters range.

Quoted 27 lines

But mapping such huge memory address only for multiple NFC status check is not very economic.

The economic way is we check the NFC status one bit a time, then we don't have to mapping such huge address.

Now we reduce the memory mapping from 256M to 128M+4 (include 0x08000000), the only difference is NFCBUSY (bit 27) status. You cannot check NFCBUSY bit with other NFC status bit.

Since current atmel_nand driver check the NFCBUSY status without combine other bits, so this change (reduce 256M to 128M+4) will not be harmful.

---

 arch/arm/boot/dts/sama5d3.dtsi | 2 +-
 arch/arm/boot/dts/sama5d4.dtsi | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)
arch/arm/boot/dts/sama5d3.dtsi +0 -0
index d701ddd..d243732 100644

arch/arm/boot/dts/sama5d3.dtsi line 1429

Quoted 5 lines
arch/arm/boot/dts/sama5d3.dtsi +1 -1
@@ -1426,7 +1426,7 @@
 				#address-cells = <1>;
 				#size-cells = <1>;
 				reg = <
-					0x70000000 0x10000000	/* NFC Command Registers */
+					0x70000000 0x08000004	/* NFC Command Registers */

This would give the following range:

					0x70000000 0x08000000

Best Regards,

Boris

[1]http://code.bulix.org/2noozv-87724

Signature · 3 lines
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
author
#2 lore raw

PATCH 1/1 ARM: at91: dts: sama5d3/sama5d4: reduce NFC command registers memory region

Hi? Boris

Thanks for the review.

Quoted 12 lines · Boris Brezillon

Hi Josh,

Quoted 7 lines · On Thu, 15 Jan 2015 15:08:03 +0800 Josh Wu <[email protected]> wrote:

To get NFC status, we need to read the NFC command registers, which is a 256M memory mapping address. To check the status, you just read such address from NFC command registers.
For example, to check NFCBUSY (bit 27), you need to read 0x08000000 (bit 27 is set to 1) of the NFC command register.
If you want to check NFCBUSY (bit 27) and NFCWR (bit 26) in same time, you need to read 0x0c000000 (bit 27 and bit 26 are set to 1).

Quoted 2 lines

Are NFCBUSY and NFCWR found in NFCDATA_STATUS and those found in HSMC_SR representing the same thing.

yes. it is. I just check with IP team. The NFCBUSY of NFCDATA_STATUS is also refer to NFC_BUSY of HSMC_SR.

Quoted 3 lines

If they are, I think you can just use HSMC_SR instead of NFCDATA_STATUS to check the status [1] and drop the last bit in the NFC Command Resgiters range.

Thank you. your code works (just need some typo change).
I want to send [1] code with your signed-off and my acked to mtd list. Is it okay for you?

Quoted 34 lines
Quoted 27 lines

But mapping such huge memory address only for multiple NFC status check is not very economic.

The economic way is we check the NFC status one bit a time, then we don't have to mapping such huge address.

Now we reduce the memory mapping from 256M to 128M+4 (include 0x08000000), the only difference is NFCBUSY (bit 27) status. You cannot check NFCBUSY bit with other NFC status bit.

Since current atmel_nand driver check the NFCBUSY status without combine other bits, so this change (reduce 256M to 128M+4) will not be harmful.

---

  arch/arm/boot/dts/sama5d3.dtsi | 2 +-
  arch/arm/boot/dts/sama5d4.dtsi | 2 +-
  2 files changed, 2 insertions(+), 2 deletions(-)
arch/arm/boot/dts/sama5d3.dtsi +0 -0
index d701ddd..d243732 100644

arch/arm/boot/dts/sama5d3.dtsi line 1429

Quoted 5 lines
arch/arm/boot/dts/sama5d3.dtsi +1 -1
@@ -1426,7 +1426,7 @@
  				#address-cells = <1>;
  				#size-cells = <1>;
  				reg = <
-					0x70000000 0x10000000	/* NFC Command Registers */
+					0x70000000 0x08000004	/* NFC Command Registers */

This would give the following range:

Quoted 1 line
					0x70000000 0x08000000

This is also right if we apply above code change.

So after above patch for mtd list is accepted I'll send out the dts changes patch.

Quoted 9 lines

Best Regards,

Boris

[1]http://code.bulix.org/2noozv-87724

Best Regards,
Josh Wu

#3 lore raw

PATCH 1/1 ARM: at91: dts: sama5d3/sama5d4: reduce NFC command registers memory region

Hi Josh,

Quoted 22 lines · On Thu, 15 Jan 2015 17:59:15 +0800 Josh Wu <[email protected]> wrote:

Hi? Boris

Thanks for the review.

Quoted 12 lines · Boris Brezillon

Hi Josh,

Quoted 7 lines · On Thu, 15 Jan 2015 15:08:03 +0800 Josh Wu <[email protected]> wrote:

To get NFC status, we need to read the NFC command registers, which is a 256M memory mapping address. To check the status, you just read such address from NFC command registers.
For example, to check NFCBUSY (bit 27), you need to read 0x08000000 (bit 27 is set to 1) of the NFC command register.
If you want to check NFCBUSY (bit 27) and NFCWR (bit 26) in same time, you need to read 0x0c000000 (bit 27 and bit 26 are set to 1).

Quoted 2 lines

Are NFCBUSY and NFCWR found in NFCDATA_STATUS and those found in HSMC_SR representing the same thing.

yes. it is. I just check with IP team. The NFCBUSY of NFCDATA_STATUS is also refer to NFC_BUSY of HSMC_SR.

Quoted 6 lines
Quoted 3 lines

If they are, I think you can just use HSMC_SR instead of NFCDATA_STATUS to check the status [1] and drop the last bit in the NFC Command Resgiters range.

Thank you. your code works (just need some typo change).
I want to send [1] code with your signed-off and my acked to mtd list. Is it okay for you?

Sure, no problem.

Signature · 3 lines
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
#4 lore raw

PATCH 1/1 ARM: at91: dts: sama5d3/sama5d4: reduce NFC command registers memory region

Le 15/01/2015 11:05, Boris Brezillon a ?crit :

Quoted 27 lines

Hi Josh,

Quoted 22 lines · On Thu, 15 Jan 2015 17:59:15 +0800 Josh Wu <[email protected]> wrote:

Hi? Boris

Thanks for the review.

Quoted 12 lines · Boris Brezillon

Hi Josh,

Quoted 7 lines · On Thu, 15 Jan 2015 15:08:03 +0800 Josh Wu <[email protected]> wrote:

To get NFC status, we need to read the NFC command registers, which is a 256M memory mapping address. To check the status, you just read such address from NFC command registers.
For example, to check NFCBUSY (bit 27), you need to read 0x08000000 (bit 27 is set to 1) of the NFC command register.
If you want to check NFCBUSY (bit 27) and NFCWR (bit 26) in same time, you need to read 0x0c000000 (bit 27 and bit 26 are set to 1).

Quoted 2 lines

Are NFCBUSY and NFCWR found in NFCDATA_STATUS and those found in HSMC_SR representing the same thing.

yes. it is. I just check with IP team. The NFCBUSY of NFCDATA_STATUS is also refer to NFC_BUSY of HSMC_SR.

Quoted 8 lines
Quoted 6 lines
Quoted 3 lines

If they are, I think you can just use HSMC_SR instead of NFCDATA_STATUS to check the status [1] and drop the last bit in the NFC Command Resgiters range.

Thank you. your code works (just need some typo change).
I want to send [1] code with your signed-off and my acked to mtd list. Is it okay for you?

Sure, no problem.

Hi Josh,

What is the status of this patch set?

Bye,

Signature · 1 line
Nicolas Ferre
author
#5 lore raw

PATCH 1/1 ARM: at91: dts: sama5d3/sama5d4: reduce NFC command registers memory region

Hi, Nicolas

Quoted 31 lines · Nicolas Ferre

Le 15/01/2015 11:05, Boris Brezillon a ?crit :

Quoted 30 lines

Hi Josh,

Quoted 25 lines · On Thu, 15 Jan 2015 17:59:15 +0800 Josh Wu <[email protected]> wrote:

Hi? Boris

Thanks for the review.

Quoted 12 lines · Boris Brezillon

Hi Josh,

Quoted 7 lines · On Thu, 15 Jan 2015 15:08:03 +0800 Josh Wu <[email protected]> wrote:

To get NFC status, we need to read the NFC command registers, which is a 256M memory mapping address. To check the status, you just read such address from NFC command registers.
For example, to check NFCBUSY (bit 27), you need to read 0x08000000 (bit 27 is set to 1) of the NFC command register.
If you want to check NFCBUSY (bit 27) and NFCWR (bit 26) in same time, you need to read 0x0c000000 (bit 27 and bit 26 are set to 1).

Quoted 2 lines

Are NFCBUSY and NFCWR found in NFCDATA_STATUS and those found in HSMC_SR representing the same thing.

yes. it is. I just check with IP team. The NFCBUSY of NFCDATA_STATUS is also refer to NFC_BUSY of HSMC_SR.

Quoted 3 lines

If they are, I think you can just use HSMC_SR instead of NFCDATA_STATUS to check the status [1] and drop the last bit in the NFC Command Resgiters range.

Quoted 7 lines
Quoted 4 lines
Quoted 3 lines

Thank you. your code works (just need some typo change).
I want to send [1] code with your signed-off and my acked to mtd list. Is it okay for you?

Sure, no problem.

Hi Josh,

What is the status of this patch set?

The v2 of this patch is sent. But it's not taken by Brain. I just ping Brain yesterday. Check the v2 patch here:
http://patchwork.ozlabs.org/patch/431752/

Best Regards,
Josh Wu

Quoted 2 lines

Bye,

#6 lore raw

PATCH 1/1 ARM: at91: dts: sama5d3/sama5d4: reduce NFC command registers memory region

Le 05/03/2015 02:52, Josh Wu a ?crit :

Quoted 37 lines

Hi, Nicolas

Quoted 34 lines · Nicolas Ferre

Le 15/01/2015 11:05, Boris Brezillon a ?crit :

Quoted 33 lines

Hi Josh,

Quoted 28 lines · On Thu, 15 Jan 2015 17:59:15 +0800 Josh Wu <[email protected]> wrote:

Hi? Boris

Thanks for the review.

Quoted 12 lines · Boris Brezillon

Hi Josh,

Quoted 7 lines · On Thu, 15 Jan 2015 15:08:03 +0800 Josh Wu <[email protected]> wrote:

To get NFC status, we need to read the NFC command registers, which is a 256M memory mapping address. To check the status, you just read such address from NFC command registers.
For example, to check NFCBUSY (bit 27), you need to read 0x08000000 (bit 27 is set to 1) of the NFC command register.
If you want to check NFCBUSY (bit 27) and NFCWR (bit 26) in same time, you need to read 0x0c000000 (bit 27 and bit 26 are set to 1).

Quoted 2 lines

Are NFCBUSY and NFCWR found in NFCDATA_STATUS and those found in HSMC_SR representing the same thing.

yes. it is. I just check with IP team. The NFCBUSY of NFCDATA_STATUS is also refer to NFC_BUSY of HSMC_SR.

Quoted 3 lines

If they are, I think you can just use HSMC_SR instead of NFCDATA_STATUS to check the status [1] and drop the last bit in the NFC Command Resgiters range.

Thank you. your code works (just need some typo change).
I want to send [1] code with your signed-off and my acked to mtd list. Is it okay for you?

Quoted 8 lines
Quoted 4 lines
Quoted 1 line

Sure, no problem.

Hi Josh,

What is the status of this patch set?

The v2 of this patch is sent. But it's not taken by Brain. I just ping Brain yesterday. Check the v2 patch here:
http://patchwork.ozlabs.org/patch/431752/

Ok, thanks for the information Josh.

Bye,

Signature · 1 line
Nicolas Ferre