ARM: shmobile: r8a73a4: Correct mask for GIC PPI interrupts

Hi Simon, Magnus,

This patch series corrects the masks in the second interrupt cells for Private Peripheral Interrupts in dtsi files for members of the shmobile family of SoCs containing big.LITTLE configurations.

This mask should reflect the actual number of CPU cores the interrupt is wired too. Hence on big.LITTLE configurations with four Cortex-A15 cores and four Cortex-A7 cores, like r8a7790 and r8a73a4, it should be "GIC_CPU_MASK_SIMPLE(8)", not "GIC_CPU_MASK_SIMPLE(4)".

Note that incorrect masks for GIC PPI interrupts are not limited to shmobile. Presumably the interrupt specifiers got copied around a lot, cfr. the proliferation of "GIC_CPU_MASK_SIMPLE(4)" (and the older hardcoded "0xf0x" variant) in various dtsi files, not always limited to quad-core CPUs.

Changes compared to v1:
- Dropped patches for r8a7791 and r8a7794 that have been applied by Simon,
- Dropped RFC status after receiving confirmation from Liviu Dudau.

This was untested on real hardware.

Thanks!

Geert Uytterhoeven (2):
ARM: shmobile: r8a73a4: Correct mask for GIC PPI interrupts
ARM: shmobile: r8a7790: Correct mask for GIC PPI interrupts

 arch/arm/boot/dts/r8a73a4.dtsi | 10 +++++-----
 arch/arm/boot/dts/r8a7790.dtsi | 10 +++++-----
 2 files changed, 10 insertions(+), 10 deletions(-)

1.9.1

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds

R-Mobile APE6 (r8a73a4) contains four Cortex-A15 and four Cortex-A7 cores, hence the second interrupt specifier cell for Private Peripheral Interrupts should use "GIC_CPU_MASK_SIMPLE(8)", so GIC interrupts are delivered to all 8 processor cores.

---
Untested

v2:
- Drop RFC status after receiving confirmation from Liviu Dudau.

---
 arch/arm/boot/dts/r8a73a4.dtsi | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

index 38136d9f6d95a16e..424c189640812c91 100644
@@ -32,10 +32,10 @@
 
 	timer {
 		compatible = "arm,armv7-timer";
-		interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			     <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			     <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			     <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+		interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <1 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <1 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <1 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
 	};
 
 	dbsc1: memory-controller at e6790000 {

@@ -375,6 +375,6 @@
 			<0 0xf1002000 0 0x1000>,
 			<0 0xf1004000 0 0x2000>,
 			<0 0xf1006000 0 0x2000>;
-		interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+		interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 	};
 };

1.9.1

R-Car H2 (r8a7790) contains four Cortex-A15 and four Cortex-A7 cores, hence the second interrupt specifier cell for Private Peripheral Interrupts should use "GIC_CPU_MASK_SIMPLE(8)", to make sure interrupts can be delivered to all 8 processor cores.

---
Untested

v2:
- Drop RFC status after receiving confirmation from Liviu Dudau.

---
 arch/arm/boot/dts/r8a7790.dtsi | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

index 4b38fc92011472e0..1405064ff0245f47 100644
@@ -120,7 +120,7 @@
 			<0 0xf1002000 0 0x1000>,
 			<0 0xf1004000 0 0x2000>,
 			<0 0xf1006000 0 0x2000>;
-		interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+		interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 	};
 
 	gpio0: gpio at e6050000 {

@@ -204,10 +204,10 @@
 
 	timer {
 		compatible = "arm,armv7-timer";
-		interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			     <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			     <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			     <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+		interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <1 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <1 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <1 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
 	};
 
 	cmt0: timer at ffca0000 {

1.9.1

Hi Geert,

Thanks for your work on this.

I see the "untested" word above which makes me think we should test both Big and Little boot modes on r8a7790. The default "Big" mode where CA15 is used usually gets a lot of attention, but little mode with CA7 boot should also work with the same kernel image.

Cheers,

/ magnus

For now I have marked these as deferred pending testing.