sunxi: Initial A80 support

As the comment says now that we have SPL support this is no longer necessary, as PLL6 is already setup with the exact same parameters by the SPL.

Signed-off-by Hans de Goede <[email protected]>

sun4i - sun8i have (aprox.) the same iomem layout, but sun9i is quite different, so add a wrapper cpu.h which includes the right mach specific cpu_sun#i.h based on mach, like we already do with clock.h and dram.h .

Note for reviewers, cpu.h is effectively renamed tp cpu_sun4i.h by this commit, the only change is the #ifndef ... #endif guard around the file.

Signed-off-by Hans de Goede <[email protected]>

Which pll-s are available depends on the machine type, move the clock_get_pllX / clock_set_pllX prototypes to the clock_sun?i.h header files so that we only declare what is actually available. e.g. clock_get_pll5p() is not available on sun6i / sun8i, and with sun9i we get a completely different set of plls.

Signed-off-by Hans de Goede <[email protected]>

The DRAM Base differs between sun9i and the others and we cannot use math in various places like the environment setting and linker scripts, so "simply" define everything which contains the SDRAM_BASE twice.

Quoted 3 lines · Hans de Goede

The DRAM Base differs between sun9i and the others and we cannot use math in various places like the environment setting and linker scripts, so "simply" define everything which contains the SDRAM_BASE twice.

Is it really not possible to use maths in linker scripts? How have I never noticed that...

Anyway, given that things only differ in the most significant nibble of the RAM base address I think something like this might work:

/* NB: find out if one of these is already available somewhere */ #define __stringify(x) #x
#define stringify(x) __stringify(x)

#define SDRAM_OFFSET(x) 0x2##x /* or 0x4 */ #define CONFIG_SYS_SDRAM_BASE SDRAM_OFFSET(0000000)

#define MEM_LAYOUT_ENV_SETTINGS \
	"kernel_addr_r=" stringify(SDRAM_OFFSET(200000)) "\0"
         ...

Quoted 3 lines · Hans de Goede

The DRAM Base differs between sun9i and the others and we cannot use math in various places like the environment setting and linker scripts, so "simply" define everything which contains the SDRAM_BASE twice.

Is it really not possible to use maths in linker scripts? How have I never noticed that...

Anyway, given that things only differ in the most significant nibble of the RAM base address I think something like this might work:

/* NB: find out if one of these is already available somewhere */ #define __stringify(x) #x
#define stringify(x) __stringify(x)

#define SDRAM_OFFSET(x) 0x2##x /* or 0x4 */ #define CONFIG_SYS_SDRAM_BASE SDRAM_OFFSET(0000000)

#define MEM_LAYOUT_ENV_SETTINGS \
	"kernel_addr_r=" stringify(SDRAM_OFFSET(200000)) "\0"
         ...

According to the "Cortex-A7 MPCore Technical Reference Manual":

"You must ensure this bit is set to 1 before the caches and MMU are enabled, or any cache and TLB maintenance operations are performed."

Since arch/arm/cpu/armv7/start.S: cpu_init_cp15 does several cache operations, we should thus enable the SMP bit earlier, and the only chance to do that is to do it at save_boot_params time.

This does not seem to make any noticable difference, but:

1) According to the manual it is the right thing to do
2) We need to do other magic really early on for sun9i (A80) support, so we need to introduce a lowlevel_init.S / save_boot_params function anyways

Signed-off-by Hans de Goede <[email protected]>

---
 arch/arm/cpu/armv7/sunxi/Makefile        |  1 +
 arch/arm/cpu/armv7/sunxi/board.c         |  8 --------
 arch/arm/cpu/armv7/sunxi/lowlevel_init.S | 23 +++++++++++++++++++++++
 3 files changed, 24 insertions(+), 8 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/sunxi/lowlevel_init.S

arch/arm/cpu/armv7/sunxi/Makefile +1 -0

index 1720f7d..3a6aa6d 100644
@@ -7,6 +7,7 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 #
+obj-y	+= lowlevel_init.o
 obj-y	+= timer.o
 obj-y	+= board.o
 obj-y	+= clock.o

arch/arm/cpu/armv7/sunxi/board.c +0 -8

index bc98c56..4449942 100644
@@ -120,14 +120,6 @@ void s_init(void)
 	 * access gets messed up (seems cache related) */
 	setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
 #endif
-#if !defined CONFIG_SPL_BUILD && (defined CONFIG_MACH_SUN7I || \
-		defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I)
-	/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
-	asm volatile(
-		"mrc p15, 0, r0, c1, c0, 1\n"
-		"orr r0, r0, #1 << 6\n"
-		"mcr p15, 0, r0, c1, c0, 1\n");
-#endif
 
 	clock_init();
 	timer_init();

arch/arm/cpu/armv7/sunxi/lowlevel_init.S new file +23 -0

new file mode 100644
index 0000000..b80b3eb
@@ -0,0 +1,23 @@
+/*
+ * (C) Copyright 2015 Hans de Goede <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <version.h>
+#include <linux/linkage.h>
+
+/*
+ * On sunxi we need to do some setup *before* cpu_init_cp15 from start.S
+ * runs, we (ab)use save_boot_params for this.
+ */
+ENTRY(save_boot_params)
+#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN7I || \
+    defined CONFIG_MACH_SUN8I
+	mrc	p15, 0, r0, c1, c0, 1
+	orr	r0, r0, #(1<<6)
+	mcr	p15, 0, r0, c1, c0, 1
+#endif
+	bx	lr
+ENDPROC(save_boot_params)

Quoted 4 lines · Hans de Goede

According to the "Cortex-A7 MPCore Technical Reference Manual":

"You must ensure this bit is set to 1 before the caches and MMU are enabled, or any cache and TLB maintenance operations are performed."

Given that this is a feature of the Cortex-A7 (actually, I believe it applies to at least Cortex-A15 too) and not really specific to sunxi, perhaps we can make this more generic?

Quoted 4 lines

Since arch/arm/cpu/armv7/start.S: cpu_init_cp15 does several cache operations, we should thus enable the SMP bit earlier, and the only chance to do that is to do it at save_boot_params time.

Would it be so terrible to add an ifdef CORTEX_A7 here, or to call out to (or call as a macro) a soc_init_cp15?

I'm cc-ing Albert for input these questions.

FWIW I notice there is some OMAP specific code right before the "bl cpu_init_cp15", although that looks like an even more special case, so perhaps not really precedent.

Quoted 1 line

This does not seem to make any noticable difference, but:

"noticeable"

Quoted 64 lines

1) According to the manual it is the right thing to do
2) We need to do other magic really early on for sun9i (A80) support, so we need to introduce a lowlevel_init.S / save_boot_params function anyways

Signed-off-by Hans de Goede <[email protected]>

---
  arch/arm/cpu/armv7/sunxi/Makefile        |  1 +
  arch/arm/cpu/armv7/sunxi/board.c         |  8 --------
  arch/arm/cpu/armv7/sunxi/lowlevel_init.S | 23 +++++++++++++++++++++++
  3 files changed, 24 insertions(+), 8 deletions(-)

create mode 100644 arch/arm/cpu/armv7/sunxi/lowlevel_init.S

arch/arm/cpu/armv7/sunxi/Makefile +1 -0

index 1720f7d..3a6aa6d 100644
@@ -7,6 +7,7 @@
  #
  # SPDX-License-Identifier:	GPL-2.0+
  #
+obj-y	+= lowlevel_init.o
  obj-y	+= timer.o
  obj-y	+= board.o
  obj-y	+= clock.o

arch/arm/cpu/armv7/sunxi/board.c +0 -8

index bc98c56..4449942 100644
@@ -120,14 +120,6 @@ void s_init(void)
  	 * access gets messed up (seems cache related) */
  	setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
  #endif
-#if !defined CONFIG_SPL_BUILD && (defined CONFIG_MACH_SUN7I || \
-		defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I)
-	/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
-	asm volatile(
-		"mrc p15, 0, r0, c1, c0, 1\n"
-		"orr r0, r0, #1 << 6\n"
-		"mcr p15, 0, r0, c1, c0, 1\n");
-#endif
 
  	clock_init();
  	timer_init();

arch/arm/cpu/armv7/sunxi/lowlevel_init.S new file +15 -0

new file mode 100644
index 0000000..b80b3eb
@@ -0,0 +1,23 @@
+/*
+ * (C) Copyright 2015 Hans de Goede <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <version.h>
+#include <linux/linkage.h>
+
+/*
+ * On sunxi we need to do some setup *before* cpu_init_cp15 from start.S
+ * runs, we (ab)use save_boot_params for this.
+ */
+ENTRY(save_boot_params)

arch/arm/cpu/armv7/sunxi/lowlevel_init.S line 23

Quoted 8 lines

arch/arm/cpu/armv7/sunxi/lowlevel_init.S new file +8 -0

+#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN7I || \
+    defined CONFIG_MACH_SUN8I
+	mrc	p15, 0, r0, c1, c0, 1
+	orr	r0, r0, #(1<<6)
+	mcr	p15, 0, r0, c1, c0, 1
+#endif
+	bx	lr
+ENDPROC(save_boot_params)

Hi,

Quoted 9 lines · Ian Campbell

Quoted 4 lines · Hans de Goede

According to the "Cortex-A7 MPCore Technical Reference Manual":

"You must ensure this bit is set to 1 before the caches and MMU are enabled, or any cache and TLB maintenance operations are performed."

Given that this is a feature of the Cortex-A7 (actually, I believe it applies to at least Cortex-A15 too) and not really specific to sunxi, perhaps we can make this more generic?

Strange enough the bit is different between the A7 and A15, for the A7 the docs say it must be set before doing anything with caches, on the A15 it only needs to be set for the core to accept cache management operations from other cpu cores (or so the docs say), which is likely why it is not in the standard init sequence yet, as for u-boot it seems to only be necessary to do this on a Cortex A7. I agree that it would be good to move this to the generic start.S though, Albert ?

Quoted 4 lines

Quoted 3 lines

Since arch/arm/cpu/armv7/start.S: cpu_init_cp15 does several cache operations, we should thus enable the SMP bit earlier, and the only chance to do that is to do it at save_boot_params time.

Quoted 2 lines

Would it be so terrible to add an ifdef CORTEX_A7 here, or to call out to (or call as a macro) a soc_init_cp15?

From my pov no that would not be too terrible, but ...

Quoted 2 lines

I'm cc-ing Albert for input these questions.

That indeed is Albert's call.

Hi,

Quoted 9 lines · Ian Campbell

Quoted 4 lines · Hans de Goede

According to the "Cortex-A7 MPCore Technical Reference Manual":

"You must ensure this bit is set to 1 before the caches and MMU are enabled, or any cache and TLB maintenance operations are performed."

Given that this is a feature of the Cortex-A7 (actually, I believe it applies to at least Cortex-A15 too) and not really specific to sunxi, perhaps we can make this more generic?

Strange enough the bit is different between the A7 and A15, for the A7 the docs say it must be set before doing anything with caches, on the A15 it only needs to be set for the core to accept cache management operations from other cpu cores (or so the docs say), which is likely why it is not in the standard init sequence yet, as for u-boot it seems to only be necessary to do this on a Cortex A7. I agree that it would be good to move this to the generic start.S though, Albert ?

Quoted 7 lines

Quoted 4 lines

Since arch/arm/cpu/armv7/start.S: cpu_init_cp15 does several cache operations, we should thus enable the SMP bit earlier, and the only chance to do that is to do it at save_boot_params time.

Would it be so terrible to add an ifdef CORTEX_A7 here, or to call out to (or call as a macro) a soc_init_cp15?

From my pov no that would not be too terrible, but ...

Quoted 2 lines

I'm cc-ing Albert for input these questions.

That indeed is Albert's call.

Note that solving this still leaves the A80 magic sram controller poke which also needs to happen really really early or otherwise the entire SoC just resets as if the watchdog has triggered, I'm fine with using save_boot_params for that, it is not its intended purpose, but it works fine for it, so I see no reason to complicate things with yet another callback.

Hi,

Quoted 9 lines · Ian Campbell

Quoted 4 lines · Hans de Goede

According to the "Cortex-A7 MPCore Technical Reference Manual":

"You must ensure this bit is set to 1 before the caches and MMU are enabled, or any cache and TLB maintenance operations are performed."

Given that this is a feature of the Cortex-A7 (actually, I believe it applies to at least Cortex-A15 too) and not really specific to sunxi, perhaps we can make this more generic?

Strange enough the bit is different between the A7 and A15, for the A7 the docs say it must be set before doing anything with caches, on the A15 it only needs to be set for the core to accept cache management operations from other cpu cores (or so the docs say), which is likely why it is not in the standard init sequence yet, as for u-boot it seems to only be necessary to do this on a Cortex A7. I agree that it would be good to move this to the generic start.S though, Albert ?

Quoted 4 lines

Quoted 3 lines

Since arch/arm/cpu/armv7/start.S: cpu_init_cp15 does several cache operations, we should thus enable the SMP bit earlier, and the only chance to do that is to do it at save_boot_params time.

Quoted 2 lines

Would it be so terrible to add an ifdef CORTEX_A7 here, or to call out to (or call as a macro) a soc_init_cp15?

From my pov no that would not be too terrible, but ...

Quoted 2 lines

I'm cc-ing Albert for input these questions.

That indeed is Albert's call.

Note that solving this still leaves the A80 magic sram controller poke which also needs to happen really really early or otherwise the entire SoC just resets as if the watchdog has triggered, I'm fine with using save_boot_params for that, it is not its intended purpose, but it works fine for it, so I see no reason to complicate things with yet another callback.

Regards,

Hans

Hello Hans,

Quoted 20 lines · Hans de Goede

Hi,

Quoted 9 lines · Ian Campbell

Quoted 4 lines · Hans de Goede

According to the "Cortex-A7 MPCore Technical Reference Manual":

"You must ensure this bit is set to 1 before the caches and MMU are enabled, or any cache and TLB maintenance operations are performed."

Given that this is a feature of the Cortex-A7 (actually, I believe it applies to at least Cortex-A15 too) and not really specific to sunxi, perhaps we can make this more generic?

Strange enough the bit is different between the A7 and A15, for the A7 the docs say it must be set before doing anything with caches, on the A15 it only needs to be set for the core to accept cache management operations from other cpu cores (or so the docs say), which is likely why it is not in the standard init sequence yet, as for u-boot it seems to only be necessary to do this on a Cortex A7. I agree that it would be good to move this to the generic start.S though, Albert ?

[...]

Quoted 4 lines

Quoted 4 lines

Quoted 3 lines

Since arch/arm/cpu/armv7/start.S: cpu_init_cp15 does several cache operations, we should thus enable the SMP bit earlier, and the only chance to do that is to do it at save_boot_params time.

Quoted 8 lines

Quoted 2 lines

Would it be so terrible to add an ifdef CORTEX_A7 here, or to call out to (or call as a macro) a soc_init_cp15?

From my pov no that would not be too terrible, but ...

Quoted 2 lines

I'm cc-ing Albert for input these questions.

That indeed is Albert's call.

I don't like the idea of #ifdef'ing that much.

OTOH, if we do introduce soc_init_cp15, then we end up with two CP15 init functions, soc_init_cp15 and cpu_init_cp15, with all sorts of questions on which should be called first and whether one could break the other's work, and what happens in-between, etc.

Either way, setting CP15 registers is something that all ARM CPUs, and SoCs require, not just armv7. It's just that other start.S files touch cp15 directly.

I'm leaning toward grouping all CP15 inits (including cache(s) and TLB disabling and maybe VBAR setting) in a single CP15 call to a single soc_init_cp15 function.

Now, SoCs with the same CPU will have a common CP15 init part, and that part could go into a <cpu>_init_cp15 function which soc_init_cp15 would call. Of course, since we're doing this way before we have any stack, we will have to handle nested calls by saving and restoring LR in intermediate function contexts.

Quoted 5 lines

Note that solving this still leaves the A80 magic sram controller poke which also needs to happen really really early or otherwise the entire SoC just resets as if the watchdog has triggered, I'm fine with using save_boot_params for that, it is not its intended purpose, but it works fine for it, so I see no reason to complicate things with yet another callback.

Maybe we could turn soc_init_cp15 into a more general soc_init function which would do whatever is needed, on cp15 or otherwise.

(I see there is one soc_init defined, for spear600, but it is actually empty and could/should be removed. Patch anyone?)

Hi,

Quoted 18 lines · Albert ARIBAUD

Hello Hans,

I'm leaning toward grouping all CP15 inits (including cache(s) and TLB disabling and maybe VBAR setting) in a single CP15 call to a single soc_init_cp15 function.

Now, SoCs with the same CPU will have a common CP15 init part, and that part could go into a <cpu>_init_cp15 function which soc_init_cp15 would call. Of course, since we're doing this way before we have any stack, we will have to handle nested calls by saving and restoring LR in intermediate function contexts.

Quoted 5 lines

Note that solving this still leaves the A80 magic sram controller poke which also needs to happen really really early or otherwise the entire SoC just resets as if the watchdog has triggered, I'm fine with using save_boot_params for that, it is not its intended purpose, but it works fine for it, so I see no reason to complicate things with yet another callback.

Quoted 5 lines

Maybe we could turn soc_init_cp15 into a more general soc_init function which would do whatever is needed, on cp15 or otherwise.

(I see there is one soc_init defined, for spear600, but it is actually empty and could/should be removed. Patch anyone?)

Hmm, so if I'm reading the above correctly, then I think you want to do the following:

1) Rename cpu_init_cp15 to cpu_init_cp15_common
2) Add a new soc_init function, with a weak default which just calls cpu_init_cp15_common
3) Add a a7_init_cp15 which sets the smp bit
4) Have Cortex A7 SoCs override soc_init with one which first calls a7_init_cp15 and then calls cpu_init_cp15_common
5) And on SoC's which need to do something special before or after cp15 init, they can do so by overriding soc_init and do what ever they need to do there before *or* after calling cpu_init_cp15_common

Have I got that right ?

If so I can try to write a patch-set for this, my arm asm is a bit weak, but I should be able to cobble this together using existing code as an example.

Regards,

Hans

Add a headerfile with all the base addresses from the sun9i blocks.

Signed-off-by Hans de Goede <[email protected]>

Add a headerfile with the sun9i ccu register layout.

Signed-off-by Hans de Goede <[email protected]>

Add initial sun9i (A80) clock setup support, enough to get the uart + mmc going.

Signed-off-by Hans de Goede <[email protected]>

Wait 1 second for the sdcard to respond, rather then waiting for 0xfffff milliseconds.

Signed-off-by Hans de Goede <[email protected]>

---
 drivers/mmc/sunxi_mmc.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

drivers/mmc/sunxi_mmc.c +0 -0

index 6234981..ee8ad5c 100644

drivers/mmc/sunxi_mmc.c +1 -0

+	error = mmc_rint_wait(mmc, timeout_msecs, SUNXI_MMC_RINT_COMMAND_DONE, "cmd");
 	if (error)
 		goto out;
 

The clocks on the A80 are hooked up slightly different, add support for this.

Signed-off-by Hans de Goede <[email protected]>

---
 arch/arm/include/asm/arch-sunxi/mmc.h |  5 ++++-
 drivers/mmc/sunxi_mmc.c               | 14 ++++++++++++--
 2 files changed, 16 insertions(+), 3 deletions(-)

arch/arm/include/asm/arch-sunxi/mmc.h +0 -0

index 537f145..0120045 100644

Quoted 3 lines · Hans de Goede

The clocks on the A80 are hooked up slightly different, add support for this.

Signed-off-by Hans de Goede <[email protected]>

Acked-by Ian Campbell <[email protected]>

Couple of minor comments:

Quoted 5 lines

---
  arch/arm/include/asm/arch-sunxi/mmc.h |  5 ++++-
  drivers/mmc/sunxi_mmc.c               | 14 ++++++++++++--
  2 files changed, 16 insertions(+), 3 deletions(-)

arch/arm/include/asm/arch-sunxi/mmc.h struct sunxi_mmc { · line 49

Quoted 13 lines

arch/arm/include/asm/arch-sunxi/mmc.h +1 -1

index 537f145..0120045 100644
@@ -43,7 +43,7 @@ struct sunxi_mmc {
  	u32 chda;		/* 0x90 */
  	u32 cbda;		/* 0x94 */
  	u32 res1[26];
-#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I)
+#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN9I)
  	u32 res2[64];
  #endif
  	u32 fifo;		/* 0x100 (0x200 on sun6i) FIFO access address */

This comment is now two generations behind.

[...]

arch/arm/include/asm/arch-sunxi/mmc.h

Quoted 2 lines

arch/arm/include/asm/arch-sunxi/mmc.h +1 -1

-#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || defined(CONFIG_MACH_SUN8I)
+#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN9I)

Can you wrap this a bit please (and perhaps run checkpatch.pl in case there are more which my eye wasn't drawn too).

Add initial sun9i (A80) support, only uart + mmc are supported for now.

Signed-off-by Hans de Goede <[email protected]>

+#define CONFIG_SYS_PROMPT "sun9i# "

Quoted 3 lines · Hans de Goede

Add initial sun9i (A80) support, only uart + mmc are supported for now.

Signed-off-by Hans de Goede <[email protected]>

Acked-by Ian Campbell <[email protected]>

Quoted 1 line

+#define CONFIG_SYS_PROMPT "sun9i# "

Should we make all these say "sunxi# " in the common header instead (the precise SoC is printed in the banner anyhow),

Hi,

Quoted 5 lines · Ian Campbell

Quoted 3 lines · Hans de Goede

Add initial sun9i (A80) support, only uart + mmc are supported for now.

Signed-off-by Hans de Goede <[email protected]>

Quoted 6 lines

Acked-by Ian Campbell <[email protected]>

Quoted 1 line

+#define CONFIG_SYS_PROMPT "sun9i# "

Should we make all these say "sunxi# " in the common header instead (the precise SoC is printed in the banner anyhow),

Yeah that sounds like a good idea, care to submit a patch for that ?

Regards,

Hans

Signed-off-by Hans de Goede <[email protected]>

---
 configs/Merrii_A80_Optimus_defconfig | 6 ++++++

 1 file changed, 6 insertions(+)
 create mode 100644 configs/Merrii_A80_Optimus_defconfig

configs/Merrii_A80_Optimus_defconfig new file +6 -0

new file mode 100644
index 0000000..5329f8a
@@ -0,0 +1,6 @@
+CONFIG_FDTFILE="sun9i-a80-optimus.dtb"
+CONFIG_VIDEO=n
+CONFIG_USB_KEYBOARD=n
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN9I=y