x86: Add support for MTRRs

This should default to the size of the ROM for faster execution before relocation.

Signed-off-by Simon Glass <[email protected]>

---

Changes in v2: None

We don't need this in U-Boot since we calculate it based on available memory.

Signed-off-by Simon Glass <[email protected]>

---

Changes in v2:
- Remove CONFIG_RAMTOP from mtrr.h in this patch

 arch/x86/Kconfig            | 4 ----
 arch/x86/include/asm/mtrr.h | 8 --------
 2 files changed, 12 deletions(-)

arch/x86/Kconfig +0 -4

index 7d007bb..e992e64 100644
@@ -47,10 +47,6 @@ config RAMBASE
        hex
        default 0x100000
 
-config RAMTOP
-       hex
-       default 0x200000
-
 config XIP_ROM_SIZE
        hex
        default ROM_SIZE

arch/x86/include/asm/mtrr.h +0 -4

index 5f05a48..dcc995d 100644
@@ -100,10 +100,6 @@ static inline long x86_mtrr_rom_cache_var_index(void) { return -1; }
 
 #endif
 
-#if !defined(CONFIG_RAMTOP)
-# error "CONFIG_RAMTOP not defined"
-#endif
-
 #if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE - 1)) != 0)
 # error "CONFIG_XIP_ROM_SIZE is not a power of 2"
 #endif

Quoted 46 lines · Simon Glass

We don't need this in U-Boot since we calculate it based on available memory.

Signed-off-by Simon Glass <[email protected]>

---

Changes in v2:
- Remove CONFIG_RAMTOP from mtrr.h in this patch

 arch/x86/Kconfig            | 4 ----
 arch/x86/include/asm/mtrr.h | 8 --------
 2 files changed, 12 deletions(-)

arch/x86/Kconfig +0 -4

index 7d007bb..e992e64 100644
@@ -47,10 +47,6 @@ config RAMBASE
        hex
        default 0x100000
 
-config RAMTOP
-       hex
-       default 0x200000
-
 config XIP_ROM_SIZE
        hex
        default ROM_SIZE

arch/x86/include/asm/mtrr.h +0 -4

index 5f05a48..dcc995d 100644
@@ -100,10 +100,6 @@ static inline long x86_mtrr_rom_cache_var_index(void) { return -1; }
 
 #endif
 
-#if !defined(CONFIG_RAMTOP)
-# error "CONFIG_RAMTOP not defined"
-#endif
-
 #if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE - 1)) != 0)
 # error "CONFIG_XIP_ROM_SIZE is not a power of 2"
 #endif

@@ -114,8 +110,4 @@ static inline long x86_mtrr_rom_cache_var_index(void) { return -1; }
 
 #define CACHE_ROM_BASE (((1 << 20) - (CONFIG_CACHE_ROM_SIZE >> 12)) << 12)
 

arch/x86/include/asm/mtrr.h static inline long x86_mtrr_rom_cache_var_index(void) { return -1; }

Quoted 6 lines

arch/x86/include/asm/mtrr.h +0 -5

-#if (CONFIG_RAMTOP & (CONFIG_RAMTOP - 1)) != 0
-# error "CONFIG_RAMTOP must be a power of 2"
-#endif
-
 #endif
--

Reviewed-by Bin Meng <[email protected]>

This currently assumes that U-Boot resides at the start of ROM. Update it to remove this assumption.

Signed-off-by Simon Glass <[email protected]>

Tested-by Bin Meng <[email protected]>

---

Changes in v2: None

 tools/ifdtool.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Some machines are very slow to scroll their displays. To cope with this, support the CONFIG_CONSOLE_SCROLL_LINES option. Setting this to 5 allows the display to operate at an acceptable speed by scrolling 5 lines at a time.

This same option is available for LCDs so when these systems are unified this code can be unified also.

Signed-off-by Simon Glass <[email protected]>

---

Changes in v2: None

 drivers/video/cfb_console.c | 26 +++++++++++++++++---------
 1 file changed, 17 insertions(+), 9 deletions(-)

drivers/video/cfb_console.c +17 -10

index a653bb4..75cdf61 100644
@@ -312,7 +312,11 @@ void console_cursor(int state);
 #define CONSOLE_ROW_SECOND     (video_console_address + CONSOLE_ROW_SIZE)
 #define CONSOLE_ROW_LAST       (video_console_address + CONSOLE_SIZE - CONSOLE_ROW_SIZE)
 #define CONSOLE_SIZE           (CONSOLE_ROW_SIZE * CONSOLE_ROWS)
-#define CONSOLE_SCROLL_SIZE    (CONSOLE_SIZE - CONSOLE_ROW_SIZE)
+
+/* By default we scroll by a single line */
+#ifndef CONFIG_CONSOLE_SCROLL_LINES
+#define CONFIG_CONSOLE_SCROLL_LINES 1
+#endif
 
 /* Macros */
 #ifdef VIDEO_FB_LITTLE_ENDIAN

@@ -753,26 +757,33 @@ static void console_clear_line(int line, int begin, int end)
 
 static void console_scrollup(void)
 {
+       const int rows = CONFIG_CONSOLE_SCROLL_LINES;
+       int i;
+
        /* copy up rows ignoring the first one */
 
 #ifdef VIDEO_HW_BITBLT
        video_hw_bitblt(VIDEO_PIXEL_SIZE,       /* bytes per pixel */
                        0,                      /* source pos x */
                        video_logo_height +
-                               VIDEO_FONT_HEIGHT, /* source pos y */
+                               VIDEO_FONT_HEIGHT * rows, /* source pos y */
                        0,                      /* dest pos x */
                        video_logo_height,      /* dest pos y */
                        VIDEO_VISIBLE_COLS,     /* frame width */
                        VIDEO_VISIBLE_ROWS
                        - video_logo_height
-                       - VIDEO_FONT_HEIGHT     /* frame height */
+                       - VIDEO_FONT_HEIGHT * rows      /* frame height */
                );
 #else
-       memcpyl(CONSOLE_ROW_FIRST, CONSOLE_ROW_SECOND,
-               CONSOLE_SCROLL_SIZE >> 2);
+       memcpyl(CONSOLE_ROW_FIRST, CONSOLE_ROW_FIRST + rows * CONSOLE_ROW_SIZE,
+               (CONSOLE_SIZE - CONSOLE_ROW_SIZE * rows) >> 2);
 #endif
        /* clear the last one */
-       console_clear_line(CONSOLE_ROWS - 1, 0, CONSOLE_COLS - 1);
+       for (i = 1; i <= rows; i++)
+               console_clear_line(CONSOLE_ROWS - i, 0, CONSOLE_COLS - 1);
+
+       /* Decrement row number */
+       console_row -= rows;
 }
 
 static void console_back(void)

@@ -884,9 +895,6 @@ static void console_newline(int n)
        if (console_row >= CONSOLE_ROWS) {
                /* Scroll everything up */
                console_scrollup();
-
-               /* Decrement row number */
-               console_row = CONSOLE_ROWS - 1;
        }
 }
 
--

2.2.0.rc0.207.ga3a616c

Hi Anatolij,

Quoted 5 lines · Simon Glass

Some machines are very slow to scroll their displays. To cope with this, support the CONFIG_CONSOLE_SCROLL_LINES option. Setting this to 5 allows the display to operate at an acceptable speed by scrolling 5 lines at a time.

Quoted 4 lines

This same option is available for LCDs so when these systems are unified this code can be unified also.

Signed-off-by Simon Glass <[email protected]>

Are you happy with this patch? If so, is it OK for me to pick it up via x86?

Hi Simon,

Quoted 8 lines · On Mon, 19 Jan 2015 17:33:08 -0700 Simon Glass <[email protected]> wrote:

Hi Anatolij,

Quoted 5 lines · Simon Glass

Some machines are very slow to scroll their displays. To cope with this, support the CONFIG_CONSOLE_SCROLL_LINES option. Setting this to 5 allows the display to operate at an acceptable speed by scrolling 5 lines at a time.

Quoted 6 lines

Quoted 4 lines

This same option is available for LCDs so when these systems are unified this code can be unified also.

Signed-off-by Simon Glass <[email protected]>

Are you happy with this patch? If so, is it OK for me to pick it up via x86?

yes, it is OK for me.

Some machines are very slow to scroll their displays. To cope with this, support the CONFIG_CONSOLE_SCROLL_LINES option. Setting this to 5 allows the display to operate at an acceptable speed by scrolling 5 lines at a time.

This same option is available for LCDs so when these systems are unified this code can be unified also.

Signed-off-by Simon Glass <[email protected]>

---

Changes in v2: None

 drivers/video/cfb_console.c | 26 +++++++++++++++++---------
 1 file changed, 17 insertions(+), 9 deletions(-)

Scrolling a line at a time is very slow for reasons that I don't understand. It seems to take about 100ms to copy 4MB of RAM in the frame buffer. To cope with this, scroll 5 lines each time.

Signed-off-by Simon Glass <[email protected]>

---

Changes in v2: None

 include/configs/x86-common.h | 1 +
 1 file changed, 1 insertion(+)

Provide a way to display this address when booting.

Signed-off-by Simon Glass <[email protected]>

---

Changes in v2: None

 drivers/video/x86_fb.c | 1 +
 1 file changed, 1 insertion(+)

If the video has not been set up, we should not return a success code. This can be detected by seeing if any of the variables are non-zero.

Signed-off-by Simon Glass <[email protected]>

---

Changes in v2: None

 drivers/pci/pci_rom.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

This can be very slow - typically 80ms even on a fast machine since it uses the SPI flash to read the data. Add an option to display the time taken.

Signed-off-by Simon Glass <[email protected]>

Reviewed-by Bin Meng <[email protected]>

---

Changes in v2: None

 drivers/pci/pci_rom.c | 3 +++
 1 file changed, 3 insertions(+)

This takes about about 700ms on link when running natively and 900ms when running using the emulator. It is a waste of time if video is not enabled, so don't bother running the video BIOS in that case.

We could add a command to run the video BIOS later when needed, but this is not considered at present.

Signed-off-by Simon Glass <[email protected]>

---

Changes in v2:
- Use CONFIG_VIDEO directly to control running the video BIOS

 arch/x86/cpu/ivybridge/gma.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

arch/x86/cpu/ivybridge/gma.c +4 -0

index 3d7f740..cf4f87c 100644
@@ -15,6 +15,7 @@
 #include <asm/pci.h>
 #include <asm/arch/pch.h>
 #include <asm/arch/sandybridge.h>
+#include <linux/kconfig.h>
 
 struct gt_powermeter {
        u16 reg;

@@ -730,6 +731,9 @@ static int int15_handler(void)
 int gma_func0_init(pci_dev_t dev, struct pci_controller *hose,
                   const void *blob, int node)
 {
+#ifdef CONFIG_VIDEO
+       ulong start;
+#endif
        void *gtt_bar;
        u32 reg32;
        int ret;

@@ -745,8 +749,11 @@ int gma_func0_init(pci_dev_t dev, struct pci_controller *hose,
        if (ret)
                return ret;
 

Quoted 42 lines · Simon Glass

This takes about about 700ms on link when running natively and 900ms when running using the emulator. It is a waste of time if video is not enabled, so don't bother running the video BIOS in that case.

We could add a command to run the video BIOS later when needed, but this is not considered at present.

Signed-off-by Simon Glass <[email protected]>

---

Changes in v2:
- Use CONFIG_VIDEO directly to control running the video BIOS

 arch/x86/cpu/ivybridge/gma.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

arch/x86/cpu/ivybridge/gma.c +4 -0

index 3d7f740..cf4f87c 100644
@@ -15,6 +15,7 @@
 #include <asm/pci.h>
 #include <asm/arch/pch.h>
 #include <asm/arch/sandybridge.h>
+#include <linux/kconfig.h>
 
 struct gt_powermeter {
        u16 reg;

@@ -730,6 +731,9 @@ static int int15_handler(void)
 int gma_func0_init(pci_dev_t dev, struct pci_controller *hose,
                   const void *blob, int node)
 {
+#ifdef CONFIG_VIDEO
+       ulong start;
+#endif
        void *gtt_bar;
        u32 reg32;
        int ret;

@@ -745,8 +749,11 @@ int gma_func0_init(pci_dev_t dev, struct pci_controller *hose,
        if (ret)
                return ret;
 

arch/x86/cpu/ivybridge/gma.c int gma_func0_init(pci_dev_t dev, struct pci_controller *hose,

Quoted 10 lines

arch/x86/cpu/ivybridge/gma.c +4 -2

+#ifdef CONFIG_VIDEO
+       start = get_timer(0);
        ret = pci_run_vga_bios(dev, int15_handler, false);
-
+       debug("BIOS ran in %lums\n", get_timer(start));
+#endif
        /* Post VBIOS init */
        ret = gma_pm_init_post_vbios(gtt_bar, blob, node);
        if (ret)
--

Reviewed-by Bin Meng <[email protected]>

There is no need to run with the cache disabled, and there is no point in clearing the display frame buffer since U-Boot does it later.

Signed-off-by Simon Glass <[email protected]>

---

Changes in v2: None

 arch/x86/lib/bios.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

There are some bits which should be ignored when displaying the mode number. Make sure that they are not included in the mode that is displayed.

Signed-off-by Simon Glass <[email protected]>

---

Changes in v2: None

 arch/x86/lib/bios.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

The hex value is more commonly understood, so use that instead of decimal. Add a 0x prefix to avoid confusion.

Signed-off-by Simon Glass <[email protected]>

Reviewed-by Bin Meng <[email protected]>

---

Changes in v2: None

 drivers/pci/pci_rom.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

This is set up along with CAR (Cache-as-RAM) anyway. When we relocate we don't really need ROM caching (we read the VGA BIOS from ROM but that is about it)

Drop it.

Signed-off-by Simon Glass <[email protected]>

---

Changes in v2: None

 arch/x86/cpu/ivybridge/cpu.c | 25 -------------------------
 1 file changed, 25 deletions(-)

Memory Type Range Registers are used to tell the CPU whether memory is cacheable and if so the cache write mode to use.

Clean up the existing header file to follow style, and remove the unneeded code.

These can speed up booting so should be supported. Add these to global_data so they can be requested while booting. We will apply the changes during relocation (in a later commit).

Signed-off-by Simon Glass <[email protected]>

---

Changes in v2: None

 arch/x86/cpu/Makefile              |   1 +
 arch/x86/cpu/coreboot/coreboot.c   |  22 +++---
 arch/x86/cpu/ivybridge/car.S       |  12 +--
 arch/x86/cpu/mtrr.c                |  81 +++++++++++++++++++
 arch/x86/include/asm/global_data.h |  15 ++++
 arch/x86/include/asm/mtrr.h        | 157 +++++++++++++++++--------------------
 6 files changed, 187 insertions(+), 101 deletions(-)
 create mode 100644 arch/x86/cpu/mtrr.c

Set the frame buffer to write-combining. This makes it faster, although for scrolling write-through is even faster for U-Boot.

Signed-off-by Simon Glass <[email protected]>

---

Changes in v2:
- Remove definition of 'ulong start' from this patch

 arch/x86/cpu/ivybridge/gma.c | 7 +++++++
 1 file changed, 7 insertions(+)

arch/x86/cpu/ivybridge/gma.c +2 -0

index cf4f87c..6cf9654 100644
@@ -12,6 +12,7 @@
 #include <fdtdec.h>
 #include <pci_rom.h>
 #include <asm/io.h>
+#include <asm/mtrr.h>
 #include <asm/pci.h>
 #include <asm/arch/pch.h>
 #include <asm/arch/sandybridge.h>

@@ -735,6 +736,7 @@ int gma_func0_init(pci_dev_t dev, struct pci_controller *hose,
        ulong start;
 #endif
        void *gtt_bar;
+       ulong base;
        u32 reg32;
        int ret;
 

@@ -743,6 +745,11 @@ int gma_func0_init(pci_dev_t dev, struct pci_controller *hose,
        reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
        pci_write_config32(dev, PCI_COMMAND, reg32);

Hi Simon,

Quoted 36 lines · Simon Glass

Set the frame buffer to write-combining. This makes it faster, although for scrolling write-through is even faster for U-Boot.

Signed-off-by Simon Glass <[email protected]>

---

Changes in v2:
- Remove definition of 'ulong start' from this patch

 arch/x86/cpu/ivybridge/gma.c | 7 +++++++
 1 file changed, 7 insertions(+)

arch/x86/cpu/ivybridge/gma.c +2 -0

index cf4f87c..6cf9654 100644
@@ -12,6 +12,7 @@
 #include <fdtdec.h>
 #include <pci_rom.h>
 #include <asm/io.h>
+#include <asm/mtrr.h>
 #include <asm/pci.h>
 #include <asm/arch/pch.h>
 #include <asm/arch/sandybridge.h>

@@ -735,6 +736,7 @@ int gma_func0_init(pci_dev_t dev, struct pci_controller *hose,
        ulong start;
 #endif
        void *gtt_bar;
+       ulong base;
        u32 reg32;
        int ret;
 

@@ -743,6 +745,11 @@ int gma_func0_init(pci_dev_t dev, struct pci_controller *hose,
        reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
        pci_write_config32(dev, PCI_COMMAND, reg32);
 

arch/x86/cpu/ivybridge/gma.c int gma_func0_init(pci_dev_t dev, struct pci_controller *hose,

Quoted 9 lines

arch/x86/cpu/ivybridge/gma.c +5 -1

+       /* Use write-combining for the graphics memory, 256MB */
+       base = pci_read_bar32(hose, dev, 2);
+       mtrr_add_request(MTRR_TYPE_WRCOMB, base, 256 << 20);
+       mtrr_commit(true);
+
        gtt_bar = (void *)pci_read_bar32(pci_bus_to_hose(0), dev, 0);
        debug("GT bar %p\n", gtt_bar);
        ret = gma_pm_init_pre_vbios(gtt_bar);
--

Do you have any comments regarding to what I said in
http://lists.denx.de/pipermail/u-boot/2014-December/199955.html?

Hi Bin,

Quoted 39 lines · Bin Meng

Hi Simon,

Quoted 36 lines · Simon Glass

Set the frame buffer to write-combining. This makes it faster, although for scrolling write-through is even faster for U-Boot.

Signed-off-by Simon Glass <[email protected]>

---

Changes in v2:
- Remove definition of 'ulong start' from this patch

 arch/x86/cpu/ivybridge/gma.c | 7 +++++++
 1 file changed, 7 insertions(+)

arch/x86/cpu/ivybridge/gma.c +2 -0

index cf4f87c..6cf9654 100644
@@ -12,6 +12,7 @@
 #include <fdtdec.h>
 #include <pci_rom.h>
 #include <asm/io.h>
+#include <asm/mtrr.h>
 #include <asm/pci.h>
 #include <asm/arch/pch.h>
 #include <asm/arch/sandybridge.h>

@@ -735,6 +736,7 @@ int gma_func0_init(pci_dev_t dev, struct pci_controller *hose,
        ulong start;
 #endif
        void *gtt_bar;
+       ulong base;
        u32 reg32;
        int ret;
 

@@ -743,6 +745,11 @@ int gma_func0_init(pci_dev_t dev, struct pci_controller *hose,
        reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
        pci_write_config32(dev, PCI_COMMAND, reg32);
 

Quoted 12 lines

arch/x86/cpu/ivybridge/gma.c int gma_func0_init(pci_dev_t dev, struct pci_controller *hose,

Quoted 9 lines

arch/x86/cpu/ivybridge/gma.c +5 -1

+       /* Use write-combining for the graphics memory, 256MB */
+       base = pci_read_bar32(hose, dev, 2);
+       mtrr_add_request(MTRR_TYPE_WRCOMB, base, 256 << 20);
+       mtrr_commit(true);
+
        gtt_bar = (void *)pci_read_bar32(pci_bus_to_hose(0), dev, 0);
        debug("GT bar %p\n", gtt_bar);
        ret = gma_pm_init_pre_vbios(gtt_bar);
--

Do you have any comments regarding to what I said in
http://lists.denx.de/pipermail/u-boot/2014-December/199955.html?

Ah yes I meant to say that I did look at a function to return the BAR size, but it involves changing the BAR. I have a patch out to convert PCI to driver model and there we will be able to store the size. So perhaps we should revisit this later?

Hi Simon,

Quoted 55 lines · Simon Glass

Hi Bin,

Quoted 51 lines · Bin Meng

Hi Simon,

Quoted 35 lines · Simon Glass

Set the frame buffer to write-combining. This makes it faster, although for scrolling write-through is even faster for U-Boot.

Signed-off-by Simon Glass <[email protected]>

---

Changes in v2:
- Remove definition of 'ulong start' from this patch

 arch/x86/cpu/ivybridge/gma.c | 7 +++++++
 1 file changed, 7 insertions(+)

arch/x86/cpu/ivybridge/gma.c +2 -0

index cf4f87c..6cf9654 100644
@@ -12,6 +12,7 @@
 #include <fdtdec.h>
 #include <pci_rom.h>
 #include <asm/io.h>
+#include <asm/mtrr.h>
 #include <asm/pci.h>
 #include <asm/arch/pch.h>
 #include <asm/arch/sandybridge.h>

@@ -735,6 +736,7 @@ int gma_func0_init(pci_dev_t dev, struct pci_controller *hose,
        ulong start;
 #endif
        void *gtt_bar;
+       ulong base;
        u32 reg32;
        int ret;
 

@@ -743,6 +745,11 @@ int gma_func0_init(pci_dev_t dev, struct pci_controller *hose,
        reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
        pci_write_config32(dev, PCI_COMMAND, reg32);

arch/x86/cpu/ivybridge/gma.c int gma_func0_init(pci_dev_t dev, struct pci_controller *hose,

Quoted 10 lines

arch/x86/cpu/ivybridge/gma.c +5 -1

 
+       /* Use write-combining for the graphics memory, 256MB */
+       base = pci_read_bar32(hose, dev, 2);
+       mtrr_add_request(MTRR_TYPE_WRCOMB, base, 256 << 20);
+       mtrr_commit(true);
+
        gtt_bar = (void *)pci_read_bar32(pci_bus_to_hose(0), dev, 0);
        debug("GT bar %p\n", gtt_bar);
        ret = gma_pm_init_pre_vbios(gtt_bar);
--

Do you have any comments regarding to what I said in
http://lists.denx.de/pipermail/u-boot/2014-December/199955.html?

Quoted 5 lines

Ah yes I meant to say that I did look at a function to return the BAR size, but it involves changing the BAR. I have a patch out to convert PCI to driver model and there we will be able to store the size. So perhaps we should revisit this later?

Sounds good. Let's revisit it later.

For bare platforms we turn off ROM-caching before calling board_init_f_r() It is then very slow to copy U-Boot from ROM to RAM. So adjust the order so that the copying happens before we turn off ROM-caching.

Signed-off-by Simon Glass <[email protected]>

---

Changes in v2: None

 common/board_f.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

We should use MTRRs to speed up execution. Add a list of MTRR requests which will dealt with when we relocate and run from RAM.

We set RAM as cacheable (with write-back) and registers as non-cacheable.

Signed-off-by Simon Glass <[email protected]>

---

Changes in v2: None

 arch/x86/cpu/ivybridge/sdram.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

Once we stop running from ROM we should set up the MTTRs to speed up execution. This is only needed for platforms that don't have an FSP. Also in the Coreboot case, the MTRRs are set up for us.

Signed-off-by Simon Glass <[email protected]>

---

Changes in v2: None

 arch/x86/lib/init_helpers.c | 8 ++++++++
 1 file changed, 8 insertions(+)

Cache-as-RAM should be turned off when we relocate since we want to run from RAM. Add a function to perform this task.

Signed-off-by Simon Glass <[email protected]>

---

Changes in v2:
- Remove unused Lhlt code
- Use a simple 'ret' instruction to return

 arch/x86/cpu/ivybridge/car.S | 46 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 46 insertions(+)

For platforms with CAR we should disable it before relocation. Check if this function is available and call it if so.

Signed-off-by Simon Glass <[email protected]>

---

Changes in v2:
- Use a simple call instruction to call car_uninit

 arch/x86/cpu/start.S | 9 +++++++++
 1 file changed, 9 insertions(+)

arch/x86/cpu/start.S +0 -0

index 125782c..be8a2dc 100644

Hi Simon,

Quoted 20 lines · Simon Glass

For platforms with CAR we should disable it before relocation. Check if this function is available and call it if so.

Signed-off-by Simon Glass <[email protected]>

---

Changes in v2:
- Use a simple call instruction to call car_uninit

 arch/x86/cpu/start.S | 9 +++++++++
 1 file changed, 9 insertions(+)

arch/x86/cpu/start.S +0 -0

index 125782c..be8a2dc 100644
@@ -205,6 +205,15 @@ board_init_f_r_trampoline:
        /* Setup global descriptor table so gd->xyz works */
        call    setup_gdt
 

arch/x86/cpu/start.S board_init_f_r_trampoline: · line 214

Quoted 7 lines

arch/x86/cpu/start.S +7 -0

+       /* Set if we need to disable CAR */
+.weak  car_uninit
+       movl    $car_uninit, %eax
+       cmpl    $0, %eax
+       jz      1f
+
+       /* Pass return address in ebx */

The comment need to be fixed, or just simply remove this.

At present the normal update (which happens much later) does not work. This seems to have something to do with the 'no eviction' mode in the CAR, or at least moving the microcode update after that causes it not to work.

For now, do an update early on so that it definitely works. Also refuse to continue unless the microcode update check (later in boot) is successful.

Signed-off-by Simon Glass <[email protected]>

---

Changes in v2:
- Use constants for microcode MSRs and header length

 arch/x86/cpu/ivybridge/car.S                    | 16 +++++++++++++++
 arch/x86/cpu/ivybridge/cpu.c                    |  2 +-
 arch/x86/cpu/ivybridge/microcode_intel.c        | 26 ++++++++++++++++---------
 arch/x86/dts/link.dts                           |  3 ---
 arch/x86/include/asm/arch-ivybridge/microcode.h |  6 ++++++
 5 files changed, 40 insertions(+), 13 deletions(-)

It is useful to be able to see the MTRR setup in U-Boot. Add a command to list the state of the variable MTRR registers and allow them to be changed.

Update the documentation to list some of the available commands.

This does not support fixed MTRRs as yet.

Signed-off-by Simon Glass <[email protected]>

---

Changes in v2:
- Move cmd_mtrr to arch/x86/lib
- Correct 'platform' typo

 arch/x86/lib/Makefile   |   1 +
 arch/x86/lib/cmd_mtrr.c | 138 ++++++++++++++++++++++++++++++++++++++++++++++++
 doc/README.x86          |  18 ++++++-
 3 files changed, 156 insertions(+), 1 deletion(-)
 create mode 100644 arch/x86/lib/cmd_mtrr.c

arch/x86/lib/Makefile +1 -0

index 73262d7..32d7b98 100644
@@ -14,6 +14,7 @@ obj-$(CONFIG_HAVE_FSP) += cmd_hob.o
 obj-y  += gcc.o
 obj-y  += init_helpers.o
 obj-y  += interrupts.o
+obj-y += cmd_mtrr.o
 obj-$(CONFIG_SYS_PCAT_INTERRUPTS) += pcat_interrupts.o
 obj-$(CONFIG_SYS_PCAT_TIMER) += pcat_timer.o
 obj-$(CONFIG_PCI) += pci_type1.o

arch/x86/lib/cmd_mtrr.c new file +138 -0

new file mode 100644
index 0000000..7e0506b
@@ -0,0 +1,138 @@
+/*
+ * (C) Copyright 2014 Google, Inc
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/msr.h>
+#include <asm/mtrr.h>
+
+static const char *const mtrr_type_name[MTRR_TYPE_COUNT] = {
+       "Uncacheable",
+       "Combine",
+       "2",
+       "3",
+       "Through",
+       "Protect",
+       "Back",
+};
+
+static int do_mtrr_list(void)
+{
+       int i;
+
+       printf("Reg Valid Write-type   %-16s %-16s %-16s\n", "Base   ||",
+              "Mask   ||", "Size   ||");
+       for (i = 0; i < MTRR_COUNT; i++) {
+               const char *type = "Invalid";
+               uint64_t base, mask, size;
+               bool valid;
+
+               base = native_read_msr(MTRR_PHYS_BASE_MSR(i));
+               mask = native_read_msr(MTRR_PHYS_MASK_MSR(i));
+               size = ~mask & ((1ULL << CONFIG_CPU_ADDR_BITS) - 1);
+               size |= (1 << 12) - 1;
+               size += 1;
+               valid = mask & MTRR_PHYS_MASK_VALID;
+               type = mtrr_type_name[base & MTRR_BASE_TYPE_MASK];
+               printf("%d   %-5s %-12s %016llx %016llx %016llx\n", i,
+                      valid ? "Y" : "N", type, base, mask, size);
+       }
+
+       return 0;
+}
+
+static int do_mtrr_set(uint reg, int argc, char * const argv[])
+{
+       const char *typename = argv[0];
+       struct mtrr_state state;
+       uint32_t start, size;
+       uint64_t base, mask;
+       int i, type = -1;
+       bool valid;
+
+       if (argc < 3)
+               return CMD_RET_USAGE;
+       for (i = 0; i < MTRR_TYPE_COUNT; i++) {
+               if (*typename == *mtrr_type_name[i])
+                       type = i;
+       }
+       if (type == -1) {
+               printf("Invalid type name %s\n", typename);
+               return CMD_RET_USAGE;
+       }
+       start = simple_strtoul(argv[1], NULL, 16);
+       size = simple_strtoul(argv[2], NULL, 16);
+
+       base = start | type;
+       valid = native_read_msr(MTRR_PHYS_MASK_MSR(reg)) & MTRR_PHYS_MASK_VALID;
+       mask = ~((uint64_t)size - 1);
+       mask &= (1ULL << CONFIG_CPU_ADDR_BITS) - 1;
+       if (valid)
+               mask |= MTRR_PHYS_MASK_VALID;
+
+       printf("base=%llx, mask=%llx\n", base, mask);
+       mtrr_open(&state);
+       wrmsrl(MTRR_PHYS_BASE_MSR(reg), base);
+       wrmsrl(MTRR_PHYS_MASK_MSR(reg), mask);
+       mtrr_close(&state);
+
+       return 0;
+}
+
+static int mtrr_set_valid(int reg, bool valid)
+{
+       struct mtrr_state state;
+       uint64_t mask;
+
+       mtrr_open(&state);
+       mask = native_read_msr(MTRR_PHYS_MASK_MSR(reg));
+       if (valid)
+               mask |= MTRR_PHYS_MASK_VALID;
+       else
+               mask &= ~MTRR_PHYS_MASK_VALID;
+       wrmsrl(MTRR_PHYS_MASK_MSR(reg), mask);
+       mtrr_close(&state);
+
+       return 0;
+}
+
+static int do_mtrr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+       const char *cmd;
+       uint reg;
+
+       cmd = argv[1];
+       if (argc < 2 || *cmd == 'l')
+               return do_mtrr_list();
+       argc -= 2;
+       argv += 2;
+       if (argc <= 0)
+               return CMD_RET_USAGE;
+       reg = simple_strtoul(argv[0], NULL, 16);
+       if (reg >= MTRR_COUNT) {
+               printf("Invalid register number\n");
+               return CMD_RET_USAGE;
+       }
+       if (*cmd == 'e')
+               return mtrr_set_valid(reg, true);
+       else if (*cmd == 'd')
+               return mtrr_set_valid(reg, false);
+       else if (*cmd == 's')
+               return do_mtrr_set(reg, argc - 1, argv + 1);
+       else
+               return CMD_RET_USAGE;
+
+       return 0;
+}
+
+U_BOOT_CMD(
+       mtrr,   6,      1,      do_mtrr,
+       "Use x86 memory type range registers (32-bit only)",
+       "[list]        - list current registers\n"
+       "set <reg> <type> <start> <size>   - set a register\n"
+       "\t<type> is Uncacheable, Combine, Through, Protect, Back\n"
+       "disable <reg>      - disable a register\n"
+       "ensable <reg>      - enable a register"
+);

doc/README.x86 +14 -0

index 5fab044..b474161 100644
@@ -110,9 +110,25 @@ be turned on. Not every device on the board is configured via devie tree, but
 more and more devices will be added as time goes by. Check out the directory
 arch/x86/dts/ for these device tree source files.
 
+Useful Commands
+---------------
+
+In keeping with the U-Boot philosophy of providing functions to check and
+adjust internal settings, there are several x86-specific commands that may be
+useful:
+
+hob  - Display information about Firmware Support Package (FSP) Hand-off
+        Block. This is only available on platforms which use FSP, mostly
+        Atom.
+iod  - Display I/O memory
+iow  - Write I/O memory
+mtrr - List and set the Memory Type Range Registers (MTRR). These are used to
+        tell the CPU whether memory is cacheable and if so the cache write

Quoted 21 lines · Simon Glass

It is useful to be able to see the MTRR setup in U-Boot. Add a command to list the state of the variable MTRR registers and allow them to be changed.

Update the documentation to list some of the available commands.

This does not support fixed MTRRs as yet.

Signed-off-by Simon Glass <[email protected]>

---

Changes in v2:
- Move cmd_mtrr to arch/x86/lib
- Correct 'platform' typo

 arch/x86/lib/Makefile   |   1 +
 arch/x86/lib/cmd_mtrr.c | 138 ++++++++++++++++++++++++++++++++++++++++++++++++
 doc/README.x86          |  18 ++++++-
 3 files changed, 156 insertions(+), 1 deletion(-)
 create mode 100644 arch/x86/lib/cmd_mtrr.c

Tested-by Bin Meng <[email protected]>