Add support for G2C1 mx28 board (which has no battery)

index d29b9aa..2a5f817 100644
@@ -147,6 +147,7 @@ void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr,
 	mxs_iomux_setup_multiple_pads(iomux_setup, iomux_size);
 
 	mxs_spl_console_init();
+	debug("SPL: Serial Console Initialised\n");
 
 	mxs_power_init();
 

index cdfcddd..9e6f24a 100644
@@ -18,6 +18,8 @@ void mxs_lradc_init(void)
 {
 	struct mxs_lradc_regs *regs = (struct mxs_lradc_regs *)MXS_LRADC_BASE;
 
+	debug("SPL: Initialisating LRADC");
+
 	writel(LRADC_CTRL0_SFTRST, &regs->hw_lradc_ctrl0_clr);
 	writel(LRADC_CTRL0_CLKGATE, &regs->hw_lradc_ctrl0_clr);
 	writel(LRADC_CTRL0_ONCHIP_GROUNDREF, &regs->hw_lradc_ctrl0_clr);

@@ -37,9 +39,15 @@ void mxs_lradc_enable_batt_measurement(void)
 {
 	struct mxs_lradc_regs *regs = (struct mxs_lradc_regs *)MXS_LRADC_BASE;
 
+	debug("SPL: Enabling LRADC battery measurement\n");
+
 	/* Check if the channel is present at all. */
-	if (!(readl(&regs->hw_lradc_status) & LRADC_STATUS_CHANNEL7_PRESENT))
+	if (!(readl(&regs->hw_lradc_status) & LRADC_STATUS_CHANNEL7_PRESENT)) {
+		debug("SPL: LRADC channel 7 is not present - aborting\n");
 		return;
+	}
+
+	debug("SPL: LRADC channel 7 is present - configuring\n");
 
 	writel(LRADC_CTRL1_LRADC7_IRQ_EN, &regs->hw_lradc_ctrl1_clr);
 	writel(LRADC_CTRL1_LRADC7_IRQ, &regs->hw_lradc_ctrl1_clr);

@@ -65,6 +73,7 @@ void mxs_lradc_enable_batt_measurement(void)
 		100, &regs->hw_lradc_delay3);
 
 	writel(0xffffffff, &regs->hw_lradc_ch7_clr);
-
 	writel(LRADC_DELAY_KICK, &regs->hw_lradc_delay3_set);
+
+	debug("SPL: LRADC channel 7 configuration complete\n");
 }

index 97ef67d..a744e5d 100644
@@ -92,6 +92,7 @@ static uint32_t dram_vals[] = {
 
 __weak void mxs_adjust_memory_params(uint32_t *dram_vals)
 {
+	debug("SPL: Using default SDRAM parameters\n");
 }
 
 #ifdef CONFIG_MX28

@@ -99,8 +100,10 @@ static void initialize_dram_values(void)
 {
 	int i;
 
+	debug("SPL: Setting mx28 board specific SDRAM parameters\n");
 	mxs_adjust_memory_params(dram_vals);
 
+	debug("SPL: Applying SDRAM parameters\n");
 	for (i = 0; i < ARRAY_SIZE(dram_vals); i++)
 		writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
 }

@@ -109,6 +112,7 @@ static void initialize_dram_values(void)
 {
 	int i;
 
+	debug("SPL: Setting mx23 board specific SDRAM parameters\n");
 	mxs_adjust_memory_params(dram_vals);
 
 	/*

@@ -120,6 +124,7 @@ static void initialize_dram_values(void)
 	 * HW_DRAM_CTL8 is setup as the last element.
 	 * So skip the initialization of these HW_DRAM_CTL registers.
 	 */
+	debug("SPL: Applying SDRAM parameters\n");
 	for (i = 0; i < ARRAY_SIZE(dram_vals); i++) {
 		if (i == 8 || i == 27 || i == 28 || i == 35)
 			continue;

@@ -146,6 +151,8 @@ static void mxs_mem_init_clock(void)
 	const unsigned char divider = 21;
 #endif
 
+	debug("SPL: Initialising FRAC0\n");
+
 	/* Gate EMI clock */
 	writeb(CLKCTRL_FRAC_CLKGATE,
 		&clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_EMI]);

@@ -170,6 +177,7 @@ static void mxs_mem_init_clock(void)
 		&clkctrl_regs->hw_clkctrl_clkseq_clr);
 
 	early_delay(10000);
+	debug("SPL: FRAC0 Initialised\n");
 }
 
 static void mxs_mem_setup_cpu_and_hbus(void)

@@ -177,6 +185,8 @@ static void mxs_mem_setup_cpu_and_hbus(void)
 	struct mxs_clkctrl_regs *clkctrl_regs =
 		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 
+	debug("SPL: Setting CPU and HBUS clock frequencies\n");
+
 	/* Set fractional divider for ref_cpu to 480 * 18 / 19 = 454MHz
 	 * and ungate CPU clock */
 	writeb(19 & CLKCTRL_FRAC_FRAC_MASK,

@@ -209,6 +219,8 @@ static void mxs_mem_setup_vdda(void)
 	struct mxs_power_regs *power_regs =
 		(struct mxs_power_regs *)MXS_POWER_BASE;
 
+	debug("SPL: Configuring VDDA\n");
+
 	writel((0xc << POWER_VDDACTRL_TRG_OFFSET) |
 		(0x7 << POWER_VDDACTRL_BO_OFFSET_OFFSET) |
 		POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW,

@@ -240,6 +252,8 @@ static void mx23_mem_setup_vddmem(void)
 	struct mxs_power_regs *power_regs =
 		(struct mxs_power_regs *)MXS_POWER_BASE;
 
+	debug("SPL: Setting mx23 VDDMEM\n");
+
 	/* We must wait before and after disabling the current limiter! */
 	early_delay(10000);
 

@@ -252,6 +266,8 @@ static void mx23_mem_setup_vddmem(void)
 
 static void mx23_mem_init(void)
 {
+	debug("SPL: Initialising mx23 SDRAM Controller\n");
+
 	/*
 	 * Reset/ungate the EMI block. This is essential, otherwise the system
 	 * suffers from memory instability. This thing is mx23 specific and is

@@ -297,6 +313,8 @@ static void mx28_mem_init(void)
 	struct mxs_pinctrl_regs *pinctrl_regs =
 		(struct mxs_pinctrl_regs *)MXS_PINCTRL_BASE;
 
+	debug("SPL: Initialising mx28 SDRAM Controller\n");
+
 	/* Set DDR2 mode */
 	writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2,
 		&pinctrl_regs->hw_pinctrl_emi_ds_ctrl_set);

357 lines not on this page · raw message

index 7fb734e..e469381 100644
@@ -14,6 +14,22 @@
 
 #include "mxs_init.h"
 
+#if defined(CONFIG_MX28)
+/*
+ * The minimum DCDC operating voltage for i.MX28 with loading is 3.3V.
+ * we will set the BRWNOUT_LVL bitfield the 3.2V value for 0.1V margin.
+ */
+#define BATTERY_BRWNOUT_BITFIELD_VALUE 20 /* 20 = 3.2V */
+#else
+/*
+ * At the time of this writing, 3V is greater than the minimum DCDC
+ * operating voltage for i.MX233 as listed in by the "Battery / DCDC Input
+ * Voltage" parameter listed in the reference manual so we will set the
+ * BRWNOUT_LVL bitfield to 3V value.
+ */
+#define BATTERY_BRWNOUT_BITFIELD_VALUE 15 /* 15 = 3.0V */
+#endif
+
 /**
  * mxs_power_clock2xtal() - Switch CPU core clock source to 24MHz XTAL
  *

@@ -88,6 +104,7 @@ static void mxs_power_set_auto_restart(void)
 	while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_CLKGATE)
 		;
 
+#ifdef CONFIG_SYS_MXS_VDD5V_ONLY
 	/* Do nothing if flag already set */
 	if (readl(&rtc_regs->hw_rtc_persistent0) & RTC_PERSISTENT0_AUTO_RESTART)
 		return;

@@ -103,6 +120,7 @@ static void mxs_power_set_auto_restart(void)
 		;
 	while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_STALE_REGS_MASK)
 		;
+#endif
 }
 
 /**

@@ -135,6 +153,7 @@ static void mxs_power_set_linreg(void)
 			POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW);
 }
 
+#ifndef CONFIG_SYS_MXS_VDD5V_ONLY
 /**
  * mxs_get_batt_volt() - Measure battery input voltage
  *

@@ -217,6 +236,7 @@ static int mxs_is_batt_good(void)
 	debug("SPL: Battery Voltage too low\n");
 	return 0;
 }
+#endif
 
 /**
  * mxs_power_setup_5v_detect() - Start the 5V input detection comparator

@@ -301,10 +321,19 @@ static void mxs_power_init_4p2_params(void)
 		POWER_5VCTRL_HEADROOM_ADJ_MASK,
 		0x4 << POWER_5VCTRL_HEADROOM_ADJ_OFFSET);
 
+#ifdef CONFIG_SYS_MXS_VDD5V_ONLY
+	debug("SPL: Configuring 4P2 VDD5V only regulator params\n");
+	clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
+			POWER_DCDC4P2_DROPOUT_CTRL_MASK,
+			POWER_DCDC4P2_DROPOUT_CTRL_100MV |
+			POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2);
+#else
+	debug("SPL: Configuring VDD5V + Battery 4P2 regulator params\n");
 	clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
 		POWER_DCDC4P2_DROPOUT_CTRL_MASK,
 		POWER_DCDC4P2_DROPOUT_CTRL_100MV |
 		POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL);
+#endif
 
 	clrsetbits_le32(&power_regs->hw_power_5vctrl,
 		POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,

@@ -387,9 +416,11 @@ static void mxs_enable_4p2_dcdc_input(int xfer)
 	if (!pwd_bo)
 		clrbits_le32(&power_regs->hw_power_minpwr, POWER_MINPWR_PWD_BO);
 
-	while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ)
-		writel(POWER_CTRL_VBUS_VALID_IRQ,
-			&power_regs->hw_power_ctrl_clr);
+	if (xfer)
+		while (readl(&power_regs->hw_power_ctrl) &
+			POWER_CTRL_VBUS_VALID_IRQ)
+			writel(POWER_CTRL_VBUS_VALID_IRQ,
+			       &power_regs->hw_power_ctrl_clr);
 
 	if (prev_5v_brnout) {
 		writel(POWER_5VCTRL_PWDN_5VBRNOUT,

@@ -480,6 +511,23 @@ static void mxs_power_init_4p2_regulator(void)
 			POWER_DCDC4P2_BO_MASK,
 			22 << POWER_DCDC4P2_BO_OFFSET);	/* 4.15V */
 
+#ifdef CONFIG_SYS_MXS_VDD5V_ONLY
+	debug("SPL: Ramping up current limit (VDD5V only)\n");
+
+	tmp = (readl(&power_regs->hw_power_5vctrl) &
+		POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK) >>
+		POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
+	while (tmp < 0x3f) {
+		tmp++;
+		tmp2 = readl(&power_regs->hw_power_5vctrl);
+		tmp2 &= ~POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
+		tmp2 |= tmp <<
+				POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
+		writel(tmp2, &power_regs->hw_power_5vctrl);
+		early_delay(100);
+	}
+#else
+	debug("SPL: Ramping up current limit (VDD5V + Battery)\n");
 	if (!(readl(&power_regs->hw_power_sts) & POWER_STS_DCDC_4P2_BO)) {
 		setbits_le32(&power_regs->hw_power_5vctrl,
 			0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);

@@ -506,6 +554,30 @@ static void mxs_power_init_4p2_regulator(void)
 			}
 		}
 	}
+#endif
+	/*
+	 * TODO: If VDD5V is sourced from USB VBUS, we need to set the
+	 * current limit so we don't exceed the USB specifications. The
+	 * USB standard states that a device can only draw 100mA unless it
+	 * requests more from the host - after which it may draw up to
+	 * 500mA. Then we have Charging Ports which may deliver up to 1.5A
+	 * (without needing a request from the device).
+	 *
+	 * NOTE: The source code for the Freescale bootlets seems to be
+	 * internally inconsistent - The printf() claims 100mA, while
+	 * VBUS_CURRENT_LIMIT is defined as 400mA.
+	 *
+	 * NOTE: We should also limit the CPU clock frequency in order to
+	 * reduce the likelyhood of the USB VBUS current limit being exceeded
+	 *
+	 * The following would limit the USB VBUS current draw to 100mA
+	 *
+	 *	clrsetbits_le32(&power_regs->hw_power_5vctrl,
+	 *		POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
+	 *		0x10 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
+	 *
+	 *	early_delay(10000);
+	 */
 
 	clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK);
 	writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);

@@ -524,11 +596,13 @@ static void mxs_power_init_dcdc_4p2_source(void)
 
 	debug("SPL: Switching DC-DC converters to 4P2\n");
 
+#ifndef CONFIG_SYS_MXS_VDD5V_ONLY
 	if (!(readl(&power_regs->hw_power_dcdc4p2) &
 		POWER_DCDC4P2_ENABLE_DCDC)) {
 		debug("SPL: Already switched - aborting\n");
 		hang();
 	}
+#endif
 
 	mxs_enable_4p2_dcdc_input(1);
 

@@ -576,6 +650,14 @@ static void mxs_power_enable_4p2(void)
 	mxs_power_init_4p2_regulator();
 
 	/* Shutdown battery (none present) */
+#ifdef CONFIG_SYS_MXS_VDD5V_ONLY
+	clrbits_le32(&power_regs->hw_power_dcdc4p2,
+		     POWER_DCDC4P2_BO_MASK);
+	writel(POWER_CTRL_DCDC4P2_BO_IRQ,
+	       &power_regs->hw_power_ctrl_clr);
+	writel(POWER_CTRL_ENIRQ_DCDC4P2_BO,
+	       &power_regs->hw_power_ctrl_set);
+#else
 	if (!mxs_is_batt_ready()) {
 		clrbits_le32(&power_regs->hw_power_dcdc4p2,
 				POWER_DCDC4P2_BO_MASK);

@@ -584,6 +666,7 @@ static void mxs_power_enable_4p2(void)
 		writel(POWER_CTRL_ENIRQ_DCDC4P2_BO,
 				&power_regs->hw_power_ctrl_clr);
 	}
+#endif
 
 	mxs_power_init_dcdc_4p2_source();
 

@@ -661,6 +744,7 @@ static void mxs_powerdown(void)
 		&power_regs->hw_power_reset);
 }
 
+#ifndef CONFIG_SYS_MXS_VDD5V_ONLY
 /**
  * mxs_batt_boot() - Configure the power block to boot from battery input
  *

@@ -714,6 +798,7 @@ static void mxs_batt_boot(void)
 
 	mxs_power_enable_4p2();
 }
+#endif
 
 /**
  * mxs_handle_5v_conflict() - Test if the 5V input is reliable

@@ -757,6 +842,7 @@ static void mxs_handle_5v_conflict(void)
 			break;
 		}
 
+#ifndef CONFIG_SYS_MXS_VDD5V_ONLY
 		/*
 		 * TODO: I can't see this being reached. We'll either
 		 * powerdown or boot from a stable 5V supply.

@@ -766,6 +852,7 @@ static void mxs_handle_5v_conflict(void)
 			mxs_batt_boot();
 			break;
 		}
+#endif
 	}
 }
 

@@ -803,6 +890,7 @@ static void mxs_5v_boot(void)
 	mxs_handle_5v_conflict();
 }
 
+#ifndef CONFIG_SYS_MXS_VDD5V_ONLY
 /**
  * mxs_init_batt_bo() - Configure battery brownout threshold
  *

@@ -824,6 +912,7 @@ static void mxs_init_batt_bo(void)
 	writel(POWER_CTRL_BATT_BO_IRQ, &power_regs->hw_power_ctrl_clr);
 	writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
 }
+#endif
 
 /**
  * mxs_switch_vddd_to_dcdc_source() - Switch VDDD rail to DC-DC converter

@@ -858,7 +947,12 @@ static void mxs_switch_vddd_to_dcdc_source(void)
  */
 static void mxs_power_configure_power_source(void)
 {
+#ifndef CONFIG_SYS_MXS_VDD5V_ONLY
 	int batt_ready, batt_good;
+#else
+	struct mxs_rtc_regs *rtc_regs =
+		(struct mxs_rtc_regs *)MXS_RTC_BASE;
+#endif
 	struct mxs_power_regs *power_regs =
 		(struct mxs_power_regs *)MXS_POWER_BASE;
 	struct mxs_lradc_regs *lradc_regs =

@@ -868,6 +962,44 @@ static void mxs_power_configure_power_source(void)
 
 	mxs_src_power_init();
 
+#ifdef CONFIG_SYS_MXS_VDD5V_ONLY
+	/*
+	 * device configured for no source to DCDC_BATT input (5V only power
+	 * source).  This boot option doesn't waste time looking for a good
+	 * battery.  Battery powered operation and automatic voltage
+	 * measurements are disabled.
+	 */
+
+	/* TODO: Find out what the purpose of these two lines is */
+	setbits_le32(&rtc_regs->hw_rtc_persistent1,
+		     TC_PERSISTENT1_GENERAL_USB_BOOT_PLAYER);
+	clrbits_le32(&rtc_regs->hw_rtc_persistent1,
+		     RTC_PERSISTENT1_GENERAL_ENUM_500MA_2X);
+
+	/*
+	 * Disable automatic battery voltage measurements which seem
+	 * unnecessary for this configuration.
+	 */
+	debug("SPL: Disabling automatic battery voltage measurements\n");
+	setbits_le32(&power_regs->hw_power_battmonitor,
+		     POWER_BATTMONITOR_EN_BATADJ);
+	writel(LRADC_CONVERSION_AUTOMATIC,
+	       &lradc_regs->hw_lradc_conversion_clr);
+	writel(525 << POWER_BATTMONITOR_BATT_VAL_OFFSET,
+	       &power_regs->hw_power_battmonitor);
+
+	clrsetbits_le32(&power_regs->hw_power_battmonitor,
+			POWER_BATTMONITOR_BRWNOUT_LVL_MASK,
+			BATTERY_BRWNOUT_BITFIELD_VALUE <<
+			POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET);
+	mxs_5v_boot();
+
+	/*
+	 * TODO: Do not switch CPU clock to PLL if we are VDD5V is sourced
+	 * from USB VBUS
+	 */
+	mxs_power_clock2pll();
+#else
 	if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
 		batt_ready = mxs_is_batt_ready();
 		if (batt_ready) {

@@ -896,6 +1028,7 @@ static void mxs_power_configure_power_source(void)
 	mxs_power_clock2pll();
 
 	mxs_init_batt_bo();
+#endif
 
 	mxs_switch_vddd_to_dcdc_source();
 

@@ -1197,9 +1330,24 @@ void mxs_power_init(void)
 {
 	struct mxs_power_regs *power_regs =
 		(struct mxs_power_regs *)MXS_POWER_BASE;
+#ifdef CONFIG_SYS_MXS_VDD5V_ONLY
+	struct mxs_pinctrl_regs *pinctrl_regs =
+		(struct mxs_pinctrl_regs *)MXS_PINCTRL_BASE;
+	struct mxs_lradc_regs *lradc_regs =
+		(struct mxs_lradc_regs *)MXS_LRADC_BASE;
+#endif
 
 	debug("SPL: Initialising Power Block\n");
 
+#ifdef CONFIG_SYS_MXS_VDD5V_ONLY
+	debug("SPL: Configured for VDD 5V only (no battery)\n");
+	/* Set high drive strength to SSP0 */
+	clrsetbits_le32(&pinctrl_regs->hw_pinctrl_drive8,
+			0x33333333, 0x22222222);
+	clrsetbits_le32(&pinctrl_regs->hw_pinctrl_drive9,
+			0x333, 0x222);
+#endif
+
 	mxs_ungate_power();
 
 	mxs_power_clock2xtal();

@@ -1215,12 +1363,26 @@ void mxs_power_init(void)
 	debug("SPL: Setting VDDIO to 3V3 (brownout @ 3v15)\n");
 	mxs_power_set_vddx(&mxs_vddio_cfg, 3300, 3150);
 
+#ifdef CONFIG_SYS_MXS_VDD5V_ONLY
+	setbits_le32(&power_regs->hw_power_vddioctrl,
+		     0x7 << POWER_VDDIOCTRL_BO_OFFSET_OFFSET);
+	clrbits_le32(&power_regs->hw_power_vddioctrl,
+		     0x1 << POWER_VDDIOCTRL_BO_OFFSET_OFFSET);
+
+	debug("SPL: Setting VDDD to 1V35 (brownout @ 1v2)\n");
+	mxs_power_set_vddx(&mxs_vddd_cfg, 1350, 1200);
+#ifdef CONFIG_MX23
+	debug("SPL: Setting VDDMEM to 3V3 (brownout @ 3v15)\n");
+	mxs_power_set_vddx(&mxs_vddmem_cfg, 3300, 3150);
+#endif
+#else
 	debug("SPL: Setting VDDD to 1V5 (brownout @ 1v0)\n");
 	mxs_power_set_vddx(&mxs_vddd_cfg, 1500, 1000);
 #ifdef CONFIG_MX23
 	debug("SPL: Setting mx23 VDDMEM to 2V5 (brownout @ 1v7)\n");
 	mxs_power_set_vddx(&mxs_vddmem_cfg, 2500, 1700);
 #endif
+#endif
 	writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
 		POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ |
 		POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ |

@@ -1228,6 +1390,28 @@ void mxs_power_init(void)
 
 	writel(POWER_5VCTRL_PWDN_5VBRNOUT, &power_regs->hw_power_5vctrl_set);
 
+#ifdef CONFIG_SYS_MXS_VDD5V_ONLY
+#if defined(CONFIG_MX28)
+	/*
+	 * On i.MX28, a new bit has been added to allow automatic hardware
+	 * shutdown if VDD4P2 browns out.  If we permanently only have a VDD5V
+	 * source, we want to enable this bit.  For devices with dead batteries,
+	 * we could also temporarily set this bit until the kernel battery
+	 * charger sufficiently charges the battery but we won't do this for
+	 * now as the latest release kernel versions aren't aware of  it
+	 * and thus don't handle the proper setting/clearing of this bit.
+	 */
+	writel(1<<7, &power_regs->hw_power_refctrl);
+#endif
+	setbits_le32(&power_regs->hw_power_battmonitor,
+		     POWER_BATTMONITOR_PWDN_BATTBRNOUT_5VDETECT_EN |
+		     POWER_BATTMONITOR_EN_BATADJ |
+		     POWER_BATTMONITOR_PWDN_BATTBRNOUT);
+	clrsetbits_le32(&lradc_regs->hw_lradc_ctrl4,
+			LRADC_CTRL4_LRADC6SELECT_MASK,
+			LRADC_CTRL4_LRADC6SELECT_CHANNEL6);
+#endif
+
 	early_delay(1000);
 }
 

index 2a5f817..7bfc623 100644
@@ -157,6 +157,12 @@ void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr,
 	data->boot_mode_idx = bootmode;
 
 	mxs_power_wait_pswitch();
+
+
+	if (mxs_boot_modes[data->boot_mode_idx].boot_pads == 0x06) {
+		debug("SPL: Waiting for JTAG user\n");
+		asm volatile ("x: b x");
+	}
 }
 
 /* Support aparatus */

index a744e5d..af4ed8c 100644
@@ -340,10 +340,41 @@ static void mx28_mem_init(void)
 }
 #endif
 
+/**
+ * mxs_mem_powerup_pll() - Powerup PLL0
+ *
+ * This function turns on power to PLL0. The CPU clock will be switched to
+ * PLL0 after the fractional divider and SDRAM have been configured.
+ */
+static void mxs_mem_powerup_pll(void)
+{
+	struct mxs_clkctrl_regs *clkctrl_regs =
+		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
+
+	/* Power up PLL0 */
+	debug("SPL: Powering up PLL0\n");
+	setbits_le32(&clkctrl_regs->hw_clkctrl_pll0ctrl0,
+		     CLKCTRL_PLL0CTRL0_POWER);
+
+	/* Toggle FORCE_LOCK to initiate the PLL lock procedure */
+	setbits_le32(&clkctrl_regs->hw_clkctrl_pll0ctrl1,
+		     CLKCTRL_PLL0CTRL1_FORCE_LOCK);
+
+	clrbits_le32(&clkctrl_regs->hw_clkctrl_pll0ctrl1,
+		     CLKCTRL_PLL0CTRL1_FORCE_LOCK);
+
+	/* Wait until the PLL has a stable lock - takes ~50us */
+	while (!(readl(&clkctrl_regs->hw_clkctrl_pll0ctrl1) &
+		 CLKCTRL_PLL0CTRL1_LOCK))
+		;
+}
+
 void mxs_mem_init(void)
 {
 	early_delay(11000);
 
+	mxs_mem_powerup_pll();
+
 	mxs_mem_init_clock();
 
 	mxs_mem_setup_vdda();

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