Documentation: DT bindings: update DT binding docs with Tegra chips
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v2 cover Documentation: DT bindings: update DT binding docs with Tegra chips
Update some of the DT binding documentation text files, per Mark's comments at:
http://marc.info/?l=linux-tegra&m=142201349727836&w=2
The primary goal with this series is to avoid checkpatch.pl warnings and align to the policy that Mark described. This series also updates Documentation/devicetree/bindings/submitting-patches.txt to formally document this policy.
These patches apply on next-20150123.
This second version incorporates some revisions based on feedback from Rob Herring.
- Paul
PATCH v2 1/3 Documentation: DT: document compatible string existence requirement
DT maintainers require all compatible strings used in chip or board DTS file to be previously documented somewhere in Documentation/devicetree/bindings, per:
http://marc.info/?l=linux-tegra&m=142201349727836&w=2
Document this requirement in the DT patch submission requirements text file.
This second version updates the documentation to align with Rob's comments here:
http://marc.info/?l=devicetree&m=142255654213019&w=2
--- .../devicetree/bindings/submitting-patches.txt | 23 ++++++++++++++++++++ 1 file changed, 23 insertions(+)
Documentation/devicetree/bindings/submitting-patches.txt +23 -0
@@ -15,6 +15,29 @@ I. For patch submitters 3) The Documentation/ portion of the patch should come in the series before the code implementing the binding. + 4) Any compatible strings used in a chip or board DTS file must be + previously documented in the corresponding DT binding text file + in Documentation/devicetree/bindings. This rule applies even if + the Linux device driver does not yet match on the compatible + string. [ checkpatch will emit warnings if this step is not + followed as of commit bff5da4335256513497cc8c79f9a9d1665e09864 + ("checkpatch: add DT compatible string documentation checks"). ] + + 5) The wildcard "<chip>" may be used in compatible strings, as in + the following example: + + - compatible: Must contain '"nvidia,<chip>-pcie", + "nvidia,tegra20-pcie"' where <chip> is tegra30, tegra132, ... + + As in the above example, the known values of "<chip>" should be + documented if it is used. + + 6) If a documented compatible string is not yet matched by the + driver, the documentation should also include a compatible + string that is matched by the driver (as in the "nvidia,tegra20-pcie" + example above). + + II. For kernel maintainers 1) If you aren't comfortable reviewing a given binding, reply to it and ask
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PATCH v2 2/3 Documentation: DT bindings: add more Tegra chip compatible strings
In reply to Paul WalmsleyAlign compatible strings for several IP blocks present on Tegra chips with the latest doctrine from the DT maintainers:
http://marc.info/?l=devicetree&m=142255654213019&w=2
The primary objective here is to avoid checkpatch warnings, per:
http://marc.info/?l=linux-tegra&m=142201349727836&w=2
DT binding text files have been updated for the following IP blocks:
- PCIe
- SOR
- SoC timers
- AHB "gizmo"
- APB_MISC
- pinmux control
- UART
- PWM
- I2C
- SPI
- RTC
- PMC
- eFuse
- AHCI
- HDA
- XUSB_PADCTRL
- SDHCI
- SOC_THERM
- AHUB
- I2S
- EHCI
- USB PHY
N.B. The nvidia,tegra20-timer compatible string is removed from the nvidia,tegra30-timer.txt documentation file because it's already mentioned in the nvidia,tegra20-timer.txt documentation file.
This second version takes into account the following requests from Rob Herring <[email protected]>:
- Per-IP block patches have been combined into a single patch
- Explicit documentation about which compatible strings are actually matched by the driver has been removed. In its place is implicit documentation that loosely follows Rob's prescribed format:
"Must contain '"nvidia,<chip>-pcie", "nvidia,tegra20-pcie"' where
<chip> is tegra30, tegra132, ..." [...] "You should attempt to document known values of <chip> if you use it"
--- .../bindings/arm/tegra/nvidia,tegra20-ahb.txt | 5 ++++- .../bindings/arm/tegra/nvidia,tegra20-pmc.txt | 6 +++++- .../devicetree/bindings/ata/tegra-sata.txt | 4 +++- .../bindings/fuse/nvidia,tegra20-fuse.txt | 10 +++++----- .../bindings/gpu/nvidia,tegra20-host1x.txt | 8 ++++++-- .../devicetree/bindings/i2c/nvidia,tegra20-i2c.txt | 10 +++++----- .../bindings/misc/nvidia,tegra20-apbmisc.txt | 9 ++++----- .../bindings/mmc/nvidia,tegra20-sdhci.txt | 6 +++++- .../bindings/pci/nvidia,tegra20-pcie.txt | 8 ++++---- .../bindings/pinctrl/nvidia,tegra124-pinmux.txt | 3 ++- .../pinctrl/nvidia,tegra124-xusb-padctl.txt | 4 +++- .../devicetree/bindings/pwm/nvidia,tegra20-pwm.txt | 7 ++++--- .../devicetree/bindings/rtc/nvidia,tegra20-rtc.txt | 4 +++- .../devicetree/bindings/serial/of-serial.txt | 5 ++++- .../bindings/sound/nvidia,tegra30-ahub.txt | 5 ++++- .../bindings/sound/nvidia,tegra30-hda.txt | 4 +++- .../bindings/sound/nvidia,tegra30-i2s.txt | 5 ++++- .../bindings/spi/nvidia,tegra114-spi.txt | 4 +++- .../devicetree/bindings/thermal/tegra-soctherm.txt | 4 +++- .../bindings/timer/nvidia,tegra30-timer.txt | 4 +++- .../bindings/usb/nvidia,tegra20-ehci.txt | 5 ++++- .../bindings/usb/nvidia,tegra20-usb-phy.txt | 5 ++++- 22 files changed, 85 insertions(+), 40 deletions(-)
Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-ahb.txt +4 -1
@@ -1,7 +1,10 @@ NVIDIA Tegra AHB Required properties: -- compatible : "nvidia,tegra20-ahb" or "nvidia,tegra30-ahb" +- compatible : For Tegra20, must contain "nvidia,tegra20-ahb". For + Tegra30, must contain "nvidia,tegra30-ahb". Otherwise, must contain + '"nvidia,<chip>-ahb", "nvidia,tegra30-ahb"' where <chip> is tegra124, + tegra132, or tegra210. - reg : Should contain 1 register ranges(address and length) Example:
Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt +5 -1
@@ -6,7 +6,11 @@ modes. It provides power-gating controllers for SoC and CPU power-islands. Required properties: - name : Should be pmc -- compatible : Should contain "nvidia,tegra<chip>-pmc". +- compatible : For Tegra20, must contain "nvidia,tegra20-pmc". For Tegra30, + must contain "nvidia,tegra30-pmc". For Tegra114, must contain + "nvidia,tegra114-pmc". For Tegra124, must contain "nvidia,tegra124-pmc". + Otherwise, must contain "nvidia,<chip>-pmc", plus at least one of the + above, where <chip> is tegra132. - reg : Offset and length of the register set for the device - clocks : Must contain an entry for each entry in clock-names. See ../clocks/clock-bindings.txt for details.
Documentation/devicetree/bindings/ata/tegra-sata.txt +3 -1
@@ -1,7 +1,9 @@ Tegra124 SoC SATA AHCI controller Required properties : -- compatible : "nvidia,tegra124-ahci". +- compatible : For Tegra124, must contain "nvidia,tegra124-ahci". Otherwise, + must contain '"nvidia,<chip>-ahci", "nvidia,tegra124-ahci"', where <chip> + is tegra132. - reg : Should contain 2 entries: - AHCI register set (SATA BAR5) - SATA register set
Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt +5 -5
@@ -1,11 +1,11 @@ NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 fuse block. Required properties: -- compatible : should be: - "nvidia,tegra20-efuse" - "nvidia,tegra30-efuse" - "nvidia,tegra114-efuse" - "nvidia,tegra124-efuse" +- compatible : For Tegra20, must contain "nvidia,tegra20-efuse". For Tegra30, + must contain "nvidia,tegra30-efuse". For Tegra114, must contain + "nvidia,tegra114-efuse". For Tegra124, must contain "nvidia,tegra124-efuse". + Otherwise, must contain "nvidia,<chip>-efuse", plus one of the above, where + <chip> is tegra132. Details: nvidia,tegra20-efuse: Tegra20 requires using APB DMA to read the fuse data due to a hardware bug. Tegra20 also lacks certain information which is
Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt +6 -2
@@ -197,7 +197,9 @@ of the following host1x client modules: - sor: serial output resource Required properties: - - compatible: "nvidia,tegra124-sor" + - compatible: For Tegra124, must contain "nvidia,tegra124-sor". Otherwise, + must contain '"nvidia,<chip>-sor", "nvidia,tegra124-sor"', where <chip> + is tegra132. - reg: Physical base address and length of the controller's registers. - interrupts: The interrupt outputs from the controller. - clocks: Must contain an entry for each entry in clock-names.
@@ -222,7 +224,9 @@ of the following host1x client modules: - nvidia,dpaux: phandle to a DispayPort AUX interface - dpaux: DisplayPort AUX interface - - compatible: "nvidia,tegra124-dpaux" + - compatible: For Tegra124, must contain "nvidia,tegra124-dpaux". Otherwise, + must contain '"nvidia,<chip>-dpaux", "nvidia,tegra124-dpaux"', where + <chip> is tegra132. - reg: Physical base address and length of the controller's registers. - interrupts: The interrupt outputs from the controller. - clocks: Must contain an entry for each entry in clock-names.
Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt +5 -5
@@ -1,11 +1,11 @@ NVIDIA Tegra20/Tegra30/Tegra114 I2C controller driver. Required properties: -- compatible : should be: - "nvidia,tegra114-i2c" - "nvidia,tegra30-i2c" - "nvidia,tegra20-i2c" - "nvidia,tegra20-i2c-dvc" +- compatible : For Tegra20, must be one of "nvidia,tegra20-i2c-dvc" or + "nvidia,tegra20-i2c". For Tegra30, must be "nvidia,tegra30-i2c". + For Tegra114, must be "nvidia,tegra114-i2c". Otherwise, must be + "nvidia,<chip>-i2c", plus at least one of the above, where <chip> is + tegra124, tegra132, or tegra210. Details of compatible are as follows: nvidia,tegra20-i2c-dvc: Tegra20 has specific I2C controller called as DVC I2C controller. This only support master mode of I2C communication. Register
Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt +4 -5
@@ -1,11 +1,10 @@ NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 apbmisc block Required properties: -- compatible : should be: - "nvidia,tegra20-apbmisc" - "nvidia,tegra30-apbmisc" - "nvidia,tegra114-apbmisc" - "nvidia,tegra124-apbmisc" +- compatible : For Tegra20, must be "nvidia,tegra20-apbmisc". For Tegra30, + must be "nvidia,tegra30-apbmisc". Otherwise, must contain + "nvidia,<chip>-apbmisc", plus one of the above, where <chip> is tegra114, + tegra124, tegra132. - reg: Should contain 2 entries: the first entry gives the physical address and length of the registers which contain revision and debug features. The second entry gives the physical address and length of the
Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt +5 -1
@@ -7,7 +7,11 @@ This file documents differences between the core properties described by mmc.txt and the properties used by the sdhci-tegra driver. Required properties: -- compatible : Should be "nvidia,<chip>-sdhci" +- compatible : For Tegra20, must contain "nvidia,tegra20-sdhci". + For Tegra30, must contain "nvidia,tegra30-sdhci". For Tegra114, + must contain "nvidia,tegra114-sdhci". For Tegra124, must contain + "nvidia,tegra124-sdhci". Otherwise, must contain "nvidia,<chip>-sdhci", + plus one of the above, where <chip> is tegra132 or tegra210. - clocks : Must contain one entry, for the module clock. See ../clocks/clock-bindings.txt for details. - resets : Must contain an entry for each entry in reset-names.
Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt +4 -4
@@ -1,10 +1,10 @@ NVIDIA Tegra PCIe controller Required properties: -- compatible: Must be one of: - - "nvidia,tegra20-pcie" - - "nvidia,tegra30-pcie" - - "nvidia,tegra124-pcie" +- compatible: For Tegra20, must contain "nvidia,tegra20-pcie". For Tegra30, + "nvidia,tegra30-pcie". For Tegra124, must contain "nvidia,tegra124-pcie". + Otherwise, must contain "nvidia,<chip>-pcie", plus one of the above, where + <chip> is tegra132 or tegra210. - device_type: Must be "pci" - reg: A list of physical base address and length for each set of controller registers. Must contain an entry for each entry in the reg-names property.
Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt +2 -1
@@ -6,7 +6,8 @@ nvidia,tegra30-pinmux.txt. In fact, this document assumes that binding as a baseline, and only documents the differences between the two bindings. Required properties: -- compatible: "nvidia,tegra124-pinmux" +- compatible: For Tegra124, must contain "nvidia,tegra124-pinmux". For + Tegra132, must contain '"nvidia,tegra132-pinmux", "nvidia-tegra124-pinmux"'. - reg: Should contain a list of base address and size pairs for: -- first entry - the drive strength and pad control registers. -- second entry - the pinmux registers
Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-xusb-padctl.txt +3 -1
@@ -13,7 +13,9 @@ how to describe and reference PHYs in device trees. Required properties: -------------------- -- compatible: should be "nvidia,tegra124-xusb-padctl" +- compatible: For Tegra124, must contain "nvidia,tegra124-xusb-padctl". + Otherwise, must contain '"nvidia,<chip>-xusb-padctl", + "nvidia-tegra124-xusb-padctl"', where <chip> is tegra132 or tegra210. - reg: Physical base address and length of the controller's registers. - resets: Must contain an entry for each entry in reset-names. See ../reset/reset.txt for details.
Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt +4 -3
@@ -1,9 +1,10 @@ Tegra SoC PWFM controller Required properties: -- compatible: should be one of: - - "nvidia,tegra20-pwm" - - "nvidia,tegra30-pwm" +- compatible: For Tegra20, must contain "nvidia,tegra20-pwm". For Tegra30, + must contain "nvidia,tegra30-pwm". Otherwise, must contain + "nvidia,<chip>-pwm", plus one of the above, where <chip> is tegra114, + tegra124, tegra132, or tegra210. - reg: physical base address and length of the controller's registers - #pwm-cells: should be 2. See pwm.txt in this directory for a description of the cells format.
Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt +3 -1
@@ -6,7 +6,9 @@ state. Required properties: -- compatible : should be "nvidia,tegra20-rtc". +- compatible : For Tegra20, must contain "nvidia,tegra20-rtc". Otherwise, + must contain '"nvidia,<chip>-rtc", "nvidia,tegra20-rtc"', where <chip> + can be tegra30, tegra114, tegra124, or tegra132. - reg : Specifies base physical address and size of the registers. - interrupts : A single interrupt specifier. - clocks : Must contain one entry, for the module clock.
Documentation/devicetree/bindings/serial/of-serial.txt +4 -1
@@ -8,7 +8,10 @@ Required properties: - "ns16550" - "ns16750" - "ns16850" - - "nvidia,tegra20-uart" + - For Tegra20, must contain "nvidia,tegra20-uart" + - For other Tegra, must contain '"nvidia,<chip>-uart", + "nvidia,tegra20-uart"' where <chip> is tegra30, tegra114, tegra124, + tegra132, or tegra210. - "nxp,lpc3220-uart" - "ralink,rt2880-uart" - "ibm,qpace-nwp-serial"
Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt +4 -1
@@ -1,7 +1,10 @@ NVIDIA Tegra30 AHUB (Audio Hub) Required properties: -- compatible : "nvidia,tegra30-ahub", "nvidia,tegra114-ahub", etc. +- compatible : For Tegra30, must contain "nvidia,tegra30-ahub". For Tegra114, + must contain "nvidia,tegra114-ahub". For Tegra124, must contain + "nvidia,tegra124-ahub". Otherwise, must contain "nvidia,<chip>-ahub", + plus at least one of the above, where <chip> is tegra132. - reg : Should contain the register physical address and length for each of the AHUB's register blocks. - Tegra30 requires 2 entries, for the APBIF and AHUB/AUDIO register blocks.
Documentation/devicetree/bindings/sound/nvidia,tegra30-hda.txt +3 -1
@@ -1,7 +1,9 @@ NVIDIA Tegra30 HDA controller Required properties: -- compatible : "nvidia,tegra30-hda" +- compatible : For Tegra30, must contain "nvidia,tegra30-hda". Otherwise, + must contain '"nvidia,<chip>-hda", "nvidia,tegra30-hda"', where <chip> is + tegra114, tegra124, or tegra132. - reg : Should contain the HDA registers location and length. - interrupts : The interrupt from the HDA controller. - clocks : Must contain an entry for each required entry in clock-names.
Documentation/devicetree/bindings/sound/nvidia,tegra30-i2s.txt +4 -1
@@ -1,7 +1,10 @@ NVIDIA Tegra30 I2S controller Required properties: -- compatible : "nvidia,tegra30-i2s" +- compatible : For Tegra30, must contain "nvidia,tegra30-i2s". For Tegra124, + must contain "nvidia,tegra124-i2s". Otherwise, must contain + "nvidia,<chip>-i2s" plus at least one of the above, where <chip> is + tegra114 or tegra132. - reg : Should contain I2S registers location and length - clocks : Must contain one entry, for the module clock. See ../clocks/clock-bindings.txt for details.
Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt +3 -1
@@ -1,7 +1,9 @@ NVIDIA Tegra114 SPI controller. Required properties: -- compatible : should be "nvidia,tegra114-spi". +- compatible : For Tegra114, must contain "nvidia,tegra114-spi". + Otherwise, must contain '"nvidia,<chip>-spi", "nvidia,tegra114-spi"' where + <chip> is tegra124, tegra132, or tegra210. - reg: Should contain SPI registers location and length. - interrupts: Should contain SPI interrupts. - clock-names : Must include the following entries:
Documentation/devicetree/bindings/thermal/tegra-soctherm.txt +3 -1
@@ -7,7 +7,9 @@ notifications. It is also used to manage emergency shutdown in an overheating situation. Required properties : -- compatible : "nvidia,tegra124-soctherm". +- compatible : For Tegra124, must contain "nvidia,tegra124-soctherm". + For Tegra132, must contain "nvidia,tegra132-soctherm". + For Tegra210, must contain "nvidia,tegra210-soctherm". - reg : Should contain 1 entry: - SOCTHERM register set - interrupts : Defines the interrupt used by SOCTHERM
Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt +3 -1
@@ -6,7 +6,9 @@ trigger a legacy watchdog reset. Required properties: -- compatible : should be "nvidia,tegra30-timer", "nvidia,tegra20-timer". +- compatible : For Tegra30, must contain "nvidia,tegra30-timer". Otherwise, + must contain '"nvidia,<chip>-timer", "nvidia,tegra30-timer"' where + <chip> is tegra124 or tegra132. - reg : Specifies base physical address and size of the registers. - interrupts : A list of 6 interrupts; one per each of timer channels 1 through 5, and one for the shared interrupt for the remaining channels.
Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt +4 -1
@@ -6,7 +6,10 @@ Practice : Universal Serial Bus" with the following modifications and additions : Required properties : - - compatible : Should be "nvidia,tegra20-ehci". + - compatible : For Tegra20, must contain "nvidia,tegra20-ehci". + For Tegra30, must contain "nvidia,tegra30-ehci". Otherwise, must contain + "nvidia,<chip>-ehci" plus at least one of the above, where <chip> is + tegra114, tegra124, tegra132, or tegra210. - nvidia,phy : phandle of the PHY that the controller is connected to. - clocks : Must contain one entry, for the module clock. See ../clocks/clock-bindings.txt for details.
Documentation/devicetree/bindings/usb/nvidia,tegra20-usb-phy.txt +4 -1
@@ -3,7 +3,10 @@ Tegra SOC USB PHY The device node for Tegra SOC USB PHY: Required properties : - - compatible : Should be "nvidia,tegra<chip>-usb-phy". + - compatible : For Tegra20, must contain "nvidia,tegra20-usb-phy". + For Tegra30, must contain "nvidia,tegra30-usb-phy". Otherwise, must contain + "nvidia,<chip>-usb-phy" plus at least one of the above, where <chip> is + tegra114, tegra124, tegra132, or tegra210. - reg : Defines the following set of registers, in the order listed: - The PHY's own register set. Always present.
Re: [PATCH v2 2/3] Documentation: DT bindings: add more Tegra chip compatible strings
Hey Paul!
Quoted 107 lines · Paul Walmsley
Align compatible strings for several IP blocks present on Tegra chips with the latest doctrine from the DT maintainers:
http://marc.info/?l=devicetree&m=142255654213019&w=2
The primary objective here is to avoid checkpatch warnings, per:
http://marc.info/?l=linux-tegra&m=142201349727836&w=2
DT binding text files have been updated for the following IP blocks:
- PCIe
- SOR
- SoC timers
- AHB "gizmo"
-APB_MISC
- pinmux control
- UART
- PWM
- I2C
- SPI
- RTC
- PMC
- eFuse
- AHCI
- HDA
-XUSB_PADCTRL
- SDHCI
-SOC_THERM
- AHUB
- I2S
- EHCI
- USB PHYN.B. The nvidia,tegra20-timer compatible string is removed from the nvidia,tegra30-timer.txt documentation file because it's already mentioned in the nvidia,tegra20-timer.txt documentation file.
This second version takes into account the following requests from Rob Herring <[email protected]>:
- Per-IP block patches have been combined into a single patch
- Explicit documentation about which compatible strings are actually matched by the driver has been removed. In its place is implicit documentation that loosely follows Rob's prescribed format:
"Must contain '"nvidia,<chip>-pcie", "nvidia,tegra20-pcie"' where
<chip> is tegra30, tegra132, ..." [...] "You should attempt to document known values of <chip> if you use it"Signed-off-by Paul Walmsley <[email protected]>Cc Alexandre Courbot <[email protected]>Cc Dylan Reid <[email protected]>Cc Eduardo Valentin <[email protected]>Cc Greg Kroah-Hartman <[email protected]>Cc Hans de Goede <[email protected]>Cc Ian Campbell <[email protected]>Cc Jingchang Lu <[email protected]>Cc John Crispin <[email protected]>Cc Kumar Gala <[email protected]>Cc Linus Walleij <[email protected]>Cc Mark Rutland <[email protected]>Cc Mikko Perttunen <[email protected]>Cc Murali Karicheri <[email protected]>Cc Paul Walmsley <[email protected]>Cc Pawel Moll <[email protected]>Cc Peter De Schrijver <[email protected]>Cc Peter Hurley <[email protected]>Cc Rob Herring <[email protected]>Cc Sean Paul <[email protected]>Cc Stephen Warren <[email protected]>Cc Takashi Iwai <[email protected]>Cc Tejun Heo <[email protected]>Cc "Terje Bergström" <[email protected]>Cc Thierry Reding <[email protected]>Cc Tuomas Tynkkynen <[email protected]>Cc Wolfram Sang <[email protected]>Cc Zhang Rui <[email protected]>--- .../bindings/arm/tegra/nvidia,tegra20-ahb.txt | 5 ++++- .../bindings/arm/tegra/nvidia,tegra20-pmc.txt | 6 +++++- .../devicetree/bindings/ata/tegra-sata.txt | 4 +++- .../bindings/fuse/nvidia,tegra20-fuse.txt | 10 +++++----- .../bindings/gpu/nvidia,tegra20-host1x.txt | 8 ++++++-- .../devicetree/bindings/i2c/nvidia,tegra20-i2c.txt | 10 +++++----- .../bindings/misc/nvidia,tegra20-apbmisc.txt | 9 ++++----- .../bindings/mmc/nvidia,tegra20-sdhci.txt | 6 +++++- .../bindings/pci/nvidia,tegra20-pcie.txt | 8 ++++---- .../bindings/pinctrl/nvidia,tegra124-pinmux.txt | 3 ++- .../pinctrl/nvidia,tegra124-xusb-padctl.txt | 4 +++- .../devicetree/bindings/pwm/nvidia,tegra20-pwm.txt | 7 ++++--- .../devicetree/bindings/rtc/nvidia,tegra20-rtc.txt | 4 +++- .../devicetree/bindings/serial/of-serial.txt | 5 ++++- .../bindings/sound/nvidia,tegra30-ahub.txt | 5 ++++- .../bindings/sound/nvidia,tegra30-hda.txt | 4 +++- .../bindings/sound/nvidia,tegra30-i2s.txt | 5 ++++- .../bindings/spi/nvidia,tegra114-spi.txt | 4 +++- .../devicetree/bindings/thermal/tegra-soctherm.txt | 4 +++-
<cut>
Quoted 5 lines
Documentation/devicetree/bindings/thermal/tegra-soctherm.txt +0
-0
Documentation/devicetree/bindings/thermal/tegra-soctherm.txt notifications. It is also used to manage emergency shutdown in an · line 15
Quoted 10 lines
Documentation/devicetree/bindings/thermal/tegra-soctherm.txt +3
-1@@ -7,7 +7,9 @@ notifications. It is also used to manage emergency shutdown in an overheating situation. Required properties : -- compatible : "nvidia,tegra124-soctherm". +- compatible : For Tegra124, must contain "nvidia,tegra124-soctherm". + For Tegra132, must contain "nvidia,tegra132-soctherm". + For Tegra210, must contain "nvidia,tegra210-soctherm". - reg : Should contain 1 entry: - SOCTHERM register set - interrupts : Defines the interrupt used by SOCTHERM
Considering that this is going into a single patch, you may add my
for what concerns the thermal bindings.
Cheers,
Eduardo Valentin
Re: [PATCH v2 2/3] Documentation: DT bindings: add more Tegra chip compatible strings
In reply to Paul WalmsleyHi Paul!
Quoted 4 lines · Paul Walmsley
Align compatible strings for several IP blocks present on Tegra chips with the latest doctrine from the DT maintainers:
OK, I am not sure if I like the direction, but having a rule of thumb here is definately a good thing. Thanks for the pointer!
So, for the I2C part:
PATCH v2 3/3 Documentation: DT bindings: add nvidia, tegra132-denver compatible string
In reply to Paul WalmsleyAdd a compatible string for the NVIDIA Denver CPU to the ARM CPU DT binding documentation file. The primary objective here is to keep checkpatch.pl from warning when the compatible string is used in an SoC DT file, per:
http://marc.info/?l=linux-tegra&m=142201349727836&w=2
This second version changes the string from "nvidia,denver" to "nvidia,tegra132-denver" to more precisely describe the revision of the Denver CPU complex that is present in the Tegra132 SoC.
--- Documentation/devicetree/bindings/arm/cpus.txt | 1 + 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/arm/cpus.txt +1 -0
@@ -175,6 +175,7 @@ nodes to be present and contain the properties described below. "marvell,pj4a" "marvell,pj4b" "marvell,sheeva-v5" + "nvidia,tegra132-denver" "qcom,krait" "qcom,scorpion" - enable-method
Quoted 11 lines · Paul Walmsley
Update some of the DT binding documentation text files, per Mark's comments at:
http://marc.info/?l=linux-tegra&m=142201349727836&w=2
The primary goal with this series is to avoid checkpatch.pl warnings and align to the policy that Mark described. This series also updates
Documentation/devicetree/bindings/submitting-patches.txtto formally document this policy.
Quoted 4 lines
These patches apply on next-20150123.
This second version incorporates some revisions based on feedback from Rob Herring.
Looks good. I've applied the series.
Rob