DMAEngine support for sun4i, sun5i & sun7i
Subsystems (3)
PATCH v4 1/1 DMAEngine support for sun4i, sun5i & sun7i
Hi everyone,
As part of Google Summer of Code 2014, I've worked on implementing DMA support for the earlier Allwinner platforms. This fourth round of patches is the result of said effort.
The previous versions of this set had some SPI patches, but I've chosen to send them separately this time for the sake of clarity. There were some DT patches as well, adding the corresponding nodes, but those have been merged some time ago so I'm not including them either. This leaves us with a single patch, which contains the actual driver.
All comments, reviews and tests are welcome!
Thanks!
Emilio
Emilio L?pez (1):
dma: sun4i: Add support for the DMA engine on sun[457]i SoCs
.../devicetree/bindings/dma/sun4i-dma.txt | 46 + drivers/dma/Kconfig | 11 + drivers/dma/Makefile | 1 + drivers/dma/sun4i-dma.c | 1264 ++++++++++++++++++++ 4 files changed, 1322 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/sun4i-dma.txt create mode 100644 drivers/dma/sun4i-dma.c
Signature · 1 line
2.2.2
PATCH v4 1/1 dma: sun4i: Add support for the DMA engine on sun[457]i SoCs
This patch adds support for the DMA engine present on Allwinner A10, A13, A10S and A20 SoCs. This engine has two kinds of channels: normal and dedicated. The main difference is in the mode of operation; while a single normal channel may be operating at any given time, dedicated channels may operate simultaneously provided there is no overlap of source or destination.
Hardware documentation can be found on A10 User Manual (section 12), A13 User Manual (section 14) and A20 User Manual (section 1.12)
---
(Partial?) changes from v3:
* Drop threaded IRQ to get lower latency
* Drop chancnt
* Fix crash on first use when using a DMA-aware bootloader (eg., one that supports NAND)
Changes from v2:
* Faster memcpy
* Quicker cyclic transfers
* Address some stylistic and locking comments from Maxime
* probably some more stuff I'm forgetting
Changes from v1:
* address comments from Chen-Yu and Maxime
* fix issue converting bus width
* switch to using a threaded IRQ instead of a tasklet on recommendation from Maxime
* fix issue setting magic timing parameter for SPI transfers
* fix an issue with list handling reported by the kbuild 0-DAY robot (thanks!)
* drop a lot of unused #define
* probably some more stuff I'm forgetting
.../devicetree/bindings/dma/sun4i-dma.txt | 46 + drivers/dma/Kconfig | 11 + drivers/dma/Makefile | 1 + drivers/dma/sun4i-dma.c | 1264 ++++++++++++++++++++ 4 files changed, 1322 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/sun4i-dma.txt create mode 100644 drivers/dma/sun4i-dma.c
Documentation/devicetree/bindings/dma/sun4i-dma.txt new file +46 -0
@@ -0,0 +1,46 @@ +Allwinner A10 DMA Controller + +This driver follows the generic DMA bindings defined in dma.txt. + +Required properties: + +- compatible: Must be "allwinner,sun4i-a10-dma" +- reg: Should contain the registers base address and length +- interrupts: Should contain a reference to the interrupt used by this device +- clocks: Should contain a reference to the parent AHB clock +- #dma-cells : Should be 2, first cell denoting normal or dedicated dma, + second cell holding the request line number. + +Example: + dma: dma-controller at 01c02000 { + compatible = "allwinner,sun4i-a10-dma"; + reg = <0x01c02000 0x1000>; + interrupts = <27>; + clocks = <&ahb_gates 6>; + #dma-cells = <2>; + }; + +Clients: + +DMA clients connected to the Allwinner A10 DMA controller must use the +format described in the dma.txt file, using a three-cell specifier for +each channel: a phandle plus two integer cells. +The three cells in order are: + +1. A phandle pointing to the DMA controller. +2. Whether it is using normal (0) or dedicated (1) channels +3. The port ID as specified in the datasheet + +Example: + spi2: spi at 01c17000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c17000 0x1000>; + interrupts = <0 12 4>; + clocks = <&ahb_gates 22>, <&spi2_clk>; + clock-names = "ahb", "mod"; + dmas = <&dma 1 29>, <&dma 1 28>; + dma-names = "rx", "tx"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + };
drivers/dma/Kconfig +11 -0
@@ -416,6 +416,17 @@ config NBPFAXI_DMA help Support for "Type-AXI" NBPF DMA IPs from Renesas +config SUN4I_DMA + tristate "Allwinner A10 DMA support" + depends on (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || (COMPILE_TEST && OF && ARM)) + default (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I) + select DMA_ENGINE + select DMA_OF + select DMA_VIRTUAL_CHANNELS + help + Enable support for the DMA controller present in the sun4i, + sun5i and sun7i Allwinner ARM SoCs. + config DMA_ENGINE bool
drivers/dma/Makefile +1 -0
@@ -50,3 +50,4 @@ obj-y += xilinx/ obj-$(CONFIG_INTEL_MIC_X100_DMA) += mic_x100_dma.o obj-$(CONFIG_NBPFAXI_DMA) += nbpfaxi.o obj-$(CONFIG_DMA_SUN6I) += sun6i-dma.o +obj-$(CONFIG_SUN4I_DMA) += sun4i-dma.o
drivers/dma/sun4i-dma.c new file +1264 -0
1,264 lines not on this page · raw message
Signature · 1 line
2.2.2
PATCH v4 1/1 dma: sun4i: Add support for the DMA engine on sun[457]i SoCs
Quoted 49 lines · Emilio L?pez
This patch adds support for the DMA engine present on Allwinner A10, A13, A10S and A20 SoCs. This engine has two kinds of channels:
normal and dedicated. The main difference is in the mode of operation; while a single normal channel may be operating at any given time, dedicated channels may operate simultaneously provided there is no overlap of source or destination.Hardware documentation can be found on A10 User Manual (section 12), A13 User Manual (section 14) and A20 User Manual (section 1.12)
Signed-off-by Emilio L?pez <[email protected]>---
(Partial?) changes from v3:
* Drop threaded IRQ to get lower latency
* Drop chancnt
* Fix crash on first use when using a DMA-aware bootloader (eg., one that supports NAND)Changes from v2:
* Faster memcpy
* Quicker cyclic transfers
* Address some stylistic and locking comments from Maxime
* probably some more stuff I'm forgettingChanges from v1:
* address comments from Chen-Yu and Maxime
* fix issue converting bus width
* switch to using a threaded IRQ instead of a tasklet on recommendation from Maxime
* fix issue setting magic timing parameter for SPI transfers
* fix an issue with list handling reported by the kbuild 0-DAY robot (thanks!)
* drop a lot of unused #define
* probably some more stuff I'm forgetting.../devicetree/bindings/dma/sun4i-dma.txt | 46 + drivers/dma/Kconfig | 11 + drivers/dma/Makefile | 1 + drivers/dma/sun4i-dma.c | 1264 ++++++++++++++++++++ 4 files changed, 1322 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/sun4i-dma.txt create mode 100644 drivers/dma/sun4i-dma.cDocumentation/devicetree/bindings/dma/sun4i-dma.txt new file +0
-0
Documentation/devicetree/bindings/dma/sun4i-dma.txt line 1
Quoted 1 line
Documentation/devicetree/bindings/dma/sun4i-dma.txt new file +1
-0@@ -0,0 +1,46 @@ +Allwinner A10 DMA Controller
Don't you want to mention A13, A10S and A20 too?
Quoted 14 lines
Documentation/devicetree/bindings/dma/sun4i-dma.txt new file +14
-0+ +This driver follows the generic DMA bindings defined in dma.txt. + +Required properties: + +- compatible: Must be "allwinner,sun4i-a10-dma" +- reg: Should contain the registers base address and length +- interrupts: Should contain a reference to the interrupt used by this device +- clocks: Should contain a reference to the parent AHB clock +- #dma-cells : Should be 2, first cell denoting normal or dedicated dma, + second cell holding the request line number. + +Example: + dma: dma-controller at 01c02000 {
Documentation/devicetree/bindings/dma/sun4i-dma.txt line 25
Quoted 10 lines
Documentation/devicetree/bindings/dma/sun4i-dma.txt new file +10
-0+ compatible = "allwinner,sun4i-a10-dma"; + reg = <0x01c02000 0x1000>; + interrupts = <27>; + clocks = <&ahb_gates 6>; + #dma-cells = <2>; + }; + +Clients: + +DMA clients connected to the Allwinner A10 DMA controller must use the
Ditto.
Quoted 27 lines
Documentation/devicetree/bindings/dma/sun4i-dma.txt new file +1
-0+format described in the dma.txt file, using a three-cell specifierfor
Documentation/devicetree/bindings/dma/sun4i-dma.txt new file +20
-0+each channel: a phandle plus two integer cells. +The three cells in order are: + +1. A phandle pointing to the DMA controller. +2. Whether it is using normal (0) or dedicated (1) channels +3. The port ID as specified in the datasheet + +Example: + spi2: spi at 01c17000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c17000 0x1000>; + interrupts = <0 12 4>; + clocks = <&ahb_gates 22>, <&spi2_clk>; + clock-names = "ahb", "mod"; + dmas = <&dma 1 29>, <&dma 1 28>; + dma-names = "rx", "tx"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + };drivers/dma/Kconfig +0
-0
drivers/dma/Kconfig config NBPFAXI_DMA · line 420
Quoted 5 lines
drivers/dma/Kconfig +2
-0@@ -416,6 +416,17 @@ config NBPFAXI_DMA help Support for "Type-AXI" NBPF DMA IPs from Renesas +config SUN4I_DMA + tristate "Allwinner A10 DMA support"
Ditto.
Quoted 27 lines
drivers/dma/Kconfig +9
-0+ depends on (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || (COMPILE_TEST && OF && ARM)) + default (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I) + select DMA_ENGINE + select DMA_OF + select DMA_VIRTUAL_CHANNELS + help + Enable support for the DMA controller present in the sun4i, + sun5i and sun7i Allwinner ARM SoCs. + config DMA_ENGINE booldrivers/dma/Makefile +1
-0@@ -50,3 +50,4 @@ obj-y += xilinx/ obj-$(CONFIG_INTEL_MIC_X100_DMA) += mic_x100_dma.o obj-$(CONFIG_NBPFAXI_DMA) += nbpfaxi.o obj-$(CONFIG_DMA_SUN6I) += sun6i-dma.o +obj-$(CONFIG_SUN4I_DMA) += sun4i-dma.odrivers/dma/sun4i-dma.c new file +0
-0
drivers/dma/sun4i-dma.c line 2
Quoted 2 lines
drivers/dma/sun4i-dma.c new file +2
-0@@ -0,0 +1,1264 @@ +/* +* Copyright (C) 2014 Emilio L?pez
2014, 2015 ?
Quoted 22 lines
drivers/dma/sun4i-dma.c new file +22
-0+* Emilio L?pez <[email protected]> +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "virt-dma.h" +
[...]
Quoted 15 lines
+static struct
sun4i_dma_dev*to_sun4i_dma_dev(structdma_device*dev)drivers/dma/sun4i-dma.c new file +13
-0+{ + return container_of(dev, struct sun4i_dma_dev, slave); +} + +static struct sun4i_dma_vchan *to_sun4i_dma_vchan (struct dma_chan *chan) +{ + return container_of(chan, struct sun4i_dma_vchan, vc.chan); +} + +static struct sun4i_dma_contract *to_sun4i_dma_contract (struct virt_dma_desc *vd) +{ + return container_of(vd, struct sun4i_dma_contract, vd); +}
drivers/dma/sun4i-dma.c line 198
Quoted 10 lines
drivers/dma/sun4i-dma.c new file +10
-0+ +static struct device *chan2dev (struct dma_chan *chan) +{ +return &chan->dev->device; +} + +static int convert_burst (u32 maxburst) +{ +if (maxburst >8 ) +return -EINVAL ;
Would it make sense to add check for maxburst = 0 too?
Quoted 8 lines
drivers/dma/sun4i-dma.c new file +8
-0+ +/* 1 -> 0, 4 -> 1, 8 -> 2 */ +return (maxburst >>2 ); +} + +static int convert_buswidth (enum dma_slave_buswidth addr_width) +{ +if (addr_width >DMA_SLAVE_BUSWIDTH_4_BYTES )
drivers/dma/sun4i-dma.c line 216
Quoted 10 lines
drivers/dma/sun4i-dma.c new file +10
-0+return -EINVAL ; + +/* 8 (1 byte) -> 0, 16 (2 bytes) -> 1, 32 (4 bytes) -> 2 */ +return (addr_width >>1 ); +} + +static int choose_optimal_buswidth (dma_addr_t addr) +{ +/* On 32 bit aligned addresses, we can use a 32 bit bus width */ +if (addr %4 ==0 )
Not sure, whether it makes sense to optimize or not, but this can be calculated like this:
(addr & (4 - 1)) == 0
drivers/dma/sun4i-dma.c line 219
Quoted 3 lines
drivers/dma/sun4i-dma.c new file +3
-0+return DMA_SLAVE_BUSWIDTH_4_BYTES ; +/* On 16 bit aligned addresses, we can use a 16 bit bus width */ + else if (addr % 2 == 0)
(addr & (2 - 1)) == 0
Quoted 7 lines
drivers/dma/sun4i-dma.c new file +6
-0+return DMA_SLAVE_BUSWIDTH_2_BYTES ; + +/* Worst-case scenario, we need to do byte aligned reads */ +return DMA_SLAVE_BUSWIDTH_1_BYTE ; +} +
...
Quoted 64 lines
drivers/dma/sun4i-dma.c new file +63
-0+ +static void configure_pchan (struct sun4i_dma_pchan *pchan, +struct sun4i_dma_promise *d) +{ +/* +* Configure addresses and misc parameters depending on type +* DDMA has an extra field with timing parameters +*/ +if (pchan->is_dedicated) { +writel_relaxed (d->src, pchan->base +DDMA_SRC_ADDR_REG ); +writel_relaxed (d->dst, pchan->base +DDMA_DEST_ADDR_REG ); +writel_relaxed (d->len, pchan->base +DDMA_BYTE_COUNT_REG ); +writel_relaxed (d->para, pchan->base +DDMA_PARA_REG ); +writel_relaxed (d->cfg, pchan->base +DDMA_CFG_REG ); + }else { +writel_relaxed (d->src, pchan->base +NDMA_SRC_ADDR_REG ); +writel_relaxed (d->dst, pchan->base +NDMA_DEST_ADDR_REG ); +writel_relaxed (d->len, pchan->base +NDMA_BYTE_COUNT_REG ); +writel_relaxed (d->cfg, pchan->base +NDMA_CFG_REG ); + } +} + +static void set_pchan_interrupt (struct sun4i_dma_dev *priv, +struct sun4i_dma_pchan *pchan, +int half,int end) +{ +u32 reg; +int pchan_number = pchan - priv->pchans; +unsigned long flags; + +spin_lock_irqsave (&priv->lock, flags); + + reg =readl_relaxed (priv->base +DMA_IRQ_ENABLE_REG ); + +if (half) + reg |=BIT (pchan_number *2 ); +else + reg &= ~BIT (pchan_number *2 ); + +if (end) + reg |=BIT (pchan_number *2 +1 ); +else + reg &= ~BIT (pchan_number *2 +1 ); + +writel_relaxed (reg, priv->base +DMA_IRQ_ENABLE_REG ); + +spin_unlock_irqrestore (&priv->lock, flags); +} + +/** +* Generate a promise, to be used in a dedicated DMA contract. +* +* A DDMA promise contains all the information required to program the +* Dedicated part of the DMA Engine and get data copied. A non-executed +* promise will live in the demands list on a contract. Once it has been +* completed, it will be moved to the completed demands list for later freeing. +* All linked promises will be freed when the corresponding contract is freed +*/ +static struct sun4i_dma_promise * +generate_ddma_promise (struct dma_chan *chan,dma_addr_t src,dma_addr_t dest, +size_t len,struct dma_slave_config *sconfig) +{ +struct sun4i_dma_promise *promise;
drivers/dma/sun4i-dma.c line 355
Quoted 10 lines
drivers/dma/sun4i-dma.c new file +10
-0+int ret; + + promise =kzalloc (sizeof (*promise),GFP_NOWAIT ); +if (!promise) +return NULL ; + + promise->src = src; + promise->dst = dest; + promise->len = len; +
No timing parameters or this is just a quirk required for SPI?
Quoted 24 lines
promise->cfg = DDMA_CFG_LOADING |
DDMA_CFG_BYTE_COUNT_MODE_REMAIN;drivers/dma/sun4i-dma.c new file +22
-0+ +/* Source burst */ + ret =convert_burst (sconfig->src_maxburst); +if (IS_ERR_VALUE (ret)) + goto fail; + promise->cfg |=DDMA_CFG_SRC_BURST_LENGTH (ret); + +/* Destination burst */ + ret =convert_burst (sconfig->dst_maxburst); +if (IS_ERR_VALUE (ret)) + goto fail; + promise->cfg |=DDMA_CFG_DEST_BURST_LENGTH (ret); + +/* Source bus width */ + ret =convert_buswidth (sconfig->src_addr_width); +if (IS_ERR_VALUE (ret)) + goto fail; + promise->cfg |=DDMA_CFG_SRC_DATA_WIDTH (ret); + +/* Destination bus width */ + ret =convert_buswidth (sconfig->dst_addr_width); +if (IS_ERR_VALUE (ret))
drivers/dma/sun4i-dma.c line 533
Quoted 10 lines
drivers/dma/sun4i-dma.c new file +10
-0+ goto fail; + promise->cfg |=DDMA_CFG_DEST_DATA_WIDTH (ret); + +return promise; + +fail: +kfree (promise); +return NULL ; +} +
[...]
P?ikest,
Priit :)
PATCH v4 1/1 dma: sun4i: Add support for the DMA engine on sun[457]i SoCs
Hi,
El 01/02/15 a las 07:03, Priit Laes escibi?:
Quoted 12 lines · Emilio L?pez
Quoted 11 lines
This patch adds support for the DMA engine present on Allwinner A10, A13, A10S and A20 SoCs. This engine has two kinds of channels:
normal and dedicated. The main difference is in the mode of operation; while a single normal channel may be operating at any given time, dedicated channels may operate simultaneously provided there is no overlap of source or destination.Hardware documentation can be found on A10 User Manual (section 12), A13 User Manual (section 14) and A20 User Manual (section 1.12)
Signed-off-by Emilio L?pez <[email protected]>
(...)
Quoted 9 lines
Documentation/devicetree/bindings/dma/sun4i-dma.txt line 1
Quoted 7 lines
Documentation/devicetree/bindings/dma/sun4i-dma.txt new file +1
-0@@ -0,0 +1,46 @@ +Allwinner A10 DMA ControllerDon't you want to mention A13, A10S and A20 too?
What if a new SoC shows up with this controller? :) I'd rather give a single name to the IP, like we do with the compatible strings.
(...)
Quoted 10 lines
Quoted 10 lines
drivers/dma/Makefile +1
-0@@ -50,3 +50,4 @@ obj-y += xilinx/ obj-$(CONFIG_INTEL_MIC_X100_DMA) += mic_x100_dma.o obj-$(CONFIG_NBPFAXI_DMA) += nbpfaxi.o obj-$(CONFIG_DMA_SUN6I) += sun6i-dma.o +obj-$(CONFIG_SUN4I_DMA) += sun4i-dma.odrivers/dma/sun4i-dma.c new file mode 100644 renamed from drivers/dma/sun4i-dma.c +0
-0
Quoted 8 lines
drivers/dma/sun4i-dma.c line 2
Quoted 6 lines
index 0000000..a025405
drivers/dma/sun4i-dma.c new file +2
-0@@ -0,0 +1,1264 @@ +/* +* Copyright (C) 2014 Emilio L?pez 2014, 2015 ?
I guess so :)
(...)
Quoted 5 lines
drivers/dma/sun4i-dma.c line 198
Quoted 4 lines
drivers/dma/sun4i-dma.c new file +4
-0+static int convert_burst (u32 maxburst) +{ +if (maxburst >8 ) +return -EINVAL ;Would it make sense to add check for maxburst = 0 too?
I can add one if you feel it's needed.
Quoted 22 lines
Quoted 8 lines
drivers/dma/sun4i-dma.c new file +8
-0+ +/* 1 -> 0, 4 -> 1, 8 -> 2 */ +return (maxburst >>2 ); +} + +static int convert_buswidth (enum dma_slave_buswidth addr_width) +{ +if (addr_width >DMA_SLAVE_BUSWIDTH_4_BYTES )drivers/dma/sun4i-dma.c line 216
Quoted 10 lines
drivers/dma/sun4i-dma.c new file +10
-0+return -EINVAL ; + +/* 8 (1 byte) -> 0, 16 (2 bytes) -> 1, 32 (4 bytes) -> 2 */ +return (addr_width >>1 ); +} + +static int choose_optimal_buswidth (dma_addr_t addr) +{ +/* On 32 bit aligned addresses, we can use a 32 bit bus width */ +if (addr %4 ==0 )Not sure, whether it makes sense to optimize or not, but this can be calculated like this:
Quoted 1 line
(addr & (4 - 1)) == 0
It looks like IS_ALIGNED() in <linux/kernel.h> is what we need here.
Quoted 9 lines
Quoted 9 lines
drivers/dma/sun4i-dma.c new file +9
-0+static struct sun4i_dma_promise * +generate_ddma_promise (struct dma_chan *chan,dma_addr_t src,dma_addr_t dest, +size_t len,struct dma_slave_config *sconfig) +{ +struct sun4i_dma_promise *promise; +int ret; + + promise =kzalloc (sizeof (*promise),GFP_NOWAIT ); +if (!promise)
Quoted 8 lines
drivers/dma/sun4i-dma.c line 431
Quoted 6 lines
drivers/dma/sun4i-dma.c new file +6
-0+return NULL ; + + promise->src = src; + promise->dst = dest; + promise->len = len; +No timing parameters or this is just a quirk required for SPI?
They're filled together with the endpoints, in case we need different ones for some other device. There's a big comment block explaining the situation on top of their assignment.
Quoted 9 lines
drivers/dma/sun4i-dma.c line 508
Quoted 9 lines
promise->cfg = DDMA_CFG_LOADING |
DDMA_CFG_BYTE_COUNT_MODE_REMAIN;drivers/dma/sun4i-dma.c new file +7
-0+ +/* Source burst */ + ret =convert_burst (sconfig->src_maxburst); +if (IS_ERR_VALUE (ret)) + goto fail; + promise->cfg |=DDMA_CFG_SRC_BURST_LENGTH (ret); +
Thanks for reviewing this! :)
Emilio
[linux-sunxi] Re: [PATCH v4] dma: sun4i: Add support for the DMA engine on sun[457]i SoCs
Did you fix multiple simultaneous DMA transfers in this? And easy test is to start jack audio. Jack will start simultaneous cyclic transfers on both the ALSA input and output. Since cyclic transfers never end, multiple simultaneous transfers has to work. Last time I tried it I got an immediate GPF when the second cyclic transfer was started.
Quoted 150 lines · Emilio L?pez
Hi,
El 01/02/15 a las 07:03, Priit Laes escibi?:
Quoted 14 lines · Emilio L?pez
Quoted 12 lines
This patch adds support for the DMA engine present on Allwinner A10, A13, A10S and A20 SoCs. This engine has two kinds of channels:
normal and dedicated. The main difference is in the mode of operation; while a single normal channel may be operating at any given time, dedicated channels may operate simultaneously provided there is no overlap of source or destination.Hardware documentation can be found on A10 User Manual (section 12), A13 User Manual (section 14) and A20 User Manual (section 1.12)
Signed-off-by Emilio L?pez <[email protected]>(...)
Quoted 12 lines
Documentation/devicetree/bindings/dma/sun4i-dma.txt line 1
Quoted 9 lines
Documentation/devicetree/bindings/dma/sun4i-dma.txt new file +1
-0@@ -0,0 +1,46 @@ +Allwinner A10 DMA ControllerDon't you want to mention A13, A10S and A20 too?
What if a new SoC shows up with this controller? :) I'd rather give a single name to the IP, like we do with the compatible strings.
(...)
Quoted 12 lines
Quoted 12 lines
drivers/dma/Makefile +1
-0@@ -50,3 +50,4 @@ obj-y += xilinx/ obj-$(CONFIG_INTEL_MIC_X100_DMA) += mic_x100_dma.o obj-$(CONFIG_NBPFAXI_DMA) += nbpfaxi.o obj-$(CONFIG_DMA_SUN6I) += sun6i-dma.o +obj-$(CONFIG_SUN4I_DMA) += sun4i-dma.odrivers/dma/sun4i-dma.c new file renamed from drivers/dma/sun4i-dma.c +0
-0mode 100644
index 0000000..a025405Quoted 8 lines
drivers/dma/sun4i-dma.c line 2
Quoted 5 lines
drivers/dma/sun4i-dma.c new file +2
-0@@ -0,0 +1,1264 @@ +/* +* Copyright (C) 2014 Emilio L?pez 2014, 2015 ?
I guess so :)
(...)
Quoted 7 lines
drivers/dma/sun4i-dma.c line 198
Quoted 5 lines
drivers/dma/sun4i-dma.c new file +4
-0+static int convert_burst (u32 maxburst) +{ +if (maxburst >8 ) +return -EINVAL ;Would it make sense to add check for maxburst = 0 too?
I can add one if you feel it's needed.
Quoted 23 lines
Quoted 8 lines
drivers/dma/sun4i-dma.c new file +8
-0+ +/* 1 -> 0, 4 -> 1, 8 -> 2 */ +return (maxburst >>2 ); +} + +static int convert_buswidth (enum dma_slave_buswidth addr_width) +{ +if (addr_width >DMA_SLAVE_BUSWIDTH_4_BYTES )drivers/dma/sun4i-dma.c line 216
Quoted 10 lines
drivers/dma/sun4i-dma.c new file +10
-0+return -EINVAL ; + +/* 8 (1 byte) -> 0, 16 (2 bytes) -> 1, 32 (4 bytes) -> 2 */ +return (addr_width >>1 ); +} + +static int choose_optimal_buswidth (dma_addr_t addr) +{ +/* On 32 bit aligned addresses, we can use a 32 bit bus width */ +if (addr %4 ==0 )Not sure, whether it makes sense to optimize or not, but this can be calculated like this:
Quoted 1 line
(addr & (4 - 1)) == 0
It looks like
IS_ALIGNED()in <linux/kernel.h> is what we need here.Quoted 12 lines
Quoted 12 lines
drivers/dma/sun4i-dma.c new file +2
-0+static struct sun4i_dma_promise * +generate_ddma_promise(struct dma_chan *chan, dma_addr_t src, dma_addr_tdest,
+size_t
len, structdma_slave_config*sconfig)drivers/dma/sun4i-dma.c new file +7
-0+{ +struct sun4i_dma_promise *promise; +int ret; + + promise =kzalloc (sizeof (*promise),GFP_NOWAIT ); +if (!promise) +return NULL ;Quoted 8 lines
drivers/dma/sun4i-dma.c line 431
Quoted 5 lines
drivers/dma/sun4i-dma.c new file +5
-0+ + promise->src = src; + promise->dst = dest; + promise->len = len; +No timing parameters or this is just a quirk required for SPI?
They're filled together with the endpoints, in case we need different ones for some other device. There's a big comment block explaining the situation on top of their assignment.
Quoted 9 lines
drivers/dma/sun4i-dma.c line 508
Quoted 9 lines
promise->cfg = DDMA_CFG_LOADING |
DDMA_CFG_BYTE_COUNT_MODE_REMAIN;drivers/dma/sun4i-dma.c new file +7
-0+ +/* Source burst */ + ret =convert_burst (sconfig->src_maxburst); +if (IS_ERR_VALUE (ret)) + goto fail; + promise->cfg |=DDMA_CFG_SRC_BURST_LENGTH (ret); +Thanks for reviewing this! :)
Emilio
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Signature · 2 lines
Jon Smirl jonsmirl at gmail.com
[linux-sunxi] Re: [PATCH v4] dma: sun4i: Add support for the DMA engine on sun[457]i SoCs
Hi,
El 03/02/15 a las 16:39, jonsmirl at gmail.com escibi?:
Quoted 5 lines
Did you fix multiple simultaneous DMA transfers in this? And easy test is to start jack audio. Jack will start simultaneous cyclic transfers on both the ALSA input and output. Since cyclic transfers never end, multiple simultaneous transfers has to work. Last time I tried it I got an immediate GPF when the second cyclic transfer was started.
I didn't get a chance to test with jack yet, but I don't see any reason why two cyclic transfers wouldn't work, assuming they're on different vchans.
Were you by any chance booting off of NAND by the way? That caused a GPF because the bootloader left the hardware in a dirty state, but it should be fixed now.
Cheers,
Emilio
[linux-sunxi] Re: [PATCH v4] dma: sun4i: Add support for the DMA engine on sun[457]i SoCs
El 03/02/15 a las 17:18, Emilio L?pez escibi?:
Quoted 9 lines
Hi,
El 03/02/15 a las 16:39, jonsmirl at gmail.com escibi?:
Quoted 5 lines
Did you fix multiple simultaneous DMA transfers in this? And easy test is to start jack audio. Jack will start simultaneous cyclic transfers on both the ALSA input and output. Since cyclic transfers never end, multiple simultaneous transfers has to work. Last time I tried it I got an immediate GPF when the second cyclic transfer was started.
Quoted 7 lines
I didn't get a chance to test with jack yet, but I don't see any reason why two cyclic transfers wouldn't work, assuming they're on different vchans.
Were you by any chance booting off of NAND by the way? That caused a GPF because the bootloader left the hardware in a dirty state, but it should be fixed now.
A quick followup on this; I tried jack and found a bug on the way channels are terminated, it turns out sometimes IRQs can still trigger after the termination. Once I fixed that, I was able to get jack to produce a deafening tone with the following:
# jackd -dalsa --playback & # jackdmp 1.9.10 Copyright 2001-2005 Paul Davis and others. Copyright 2004-2014 Grame. jackdmp comes with ABSOLUTELY NO WARRANTY This is free software, and you are welcome to redistribute it under certain conditions; see the file COPYING for details JACK server starting in realtime mode with priority 10 self-connect-mode is "Don't restrict self connect requests" creating alsa driver ... hw:0|-|1024|2|48000|0|0|nomon|swmeter|-|32bit configuring for 48000Hz, period = 1024 frames (21.3 ms), buffer = 2 periods ALSA: final selected sample format for playback: 32bit integer little-endian ALSA: use 2 periods for playback # jack_simple_client
PATCH v4 1/1 dma: sun4i: Add support for the DMA engine on sun[457]i SoCs
In reply to Emilio LópezQuoted 34 lines · Emilio L?pez
drivers/dma/sun4i-dma.c new file +34
-0+/** Dedicated DMA register layout **/ + +/* Dedicated DMA configuration register layout */ +#define DDMA_CFG_LOADING BIT(31) +#define DDMA_CFG_BUSY BIT(30) +#define DDMA_CFG_CONT_MODE BIT(29) +#define DDMA_CFG_DEST_NON_SECURE BIT(28) +#define DDMA_CFG_DEST_DATA_WIDTH (width) ((width) << 25) +#define DDMA_CFG_DEST_BURST_LENGTH (len) ((len) << 23) +#define DDMA_CFG_DEST_ADDR_MODE (mode) ((mode) << 21) +#define DDMA_CFG_DEST_DRQ_TYPE (type) ((type) << 16) +#define DDMA_CFG_BYTE_COUNT_MODE_REMAIN BIT(15) +#define DDMA_CFG_SRC_NON_SECURE BIT(12) +#define DDMA_CFG_SRC_DATA_WIDTH (width) ((width) << 9) +#define DDMA_CFG_SRC_BURST_LENGTH (len) ((len) << 7) +#define DDMA_CFG_SRC_ADDR_MODE (mode) ((mode) << 5) +#define DDMA_CFG_SRC_DRQ_TYPE (type) ((type) << 0) + +/* Dedicated DMA parameter register layout */ +#define DDMA_PARA_DEST_DATA_BLK_SIZE (n) (((n) - 1) << 24) +#define DDMA_PARA_DEST_WAIT_CYCLES (n) (((n) - 1) << 16) +#define DDMA_PARA_SRC_DATA_BLK_SIZE (n) (((n) - 1) << 8) +#define DDMA_PARA_SRC_WAIT_CYCLES (n) (((n) - 1) << 0) + +/** DMA register offsets **/ + +/* General register offsets */ +#define DMA_IRQ_ENABLE_REG 0x0 +#define DMA_IRQ_PENDING_STATUS_REG 0x4 + +/* Normal DMA register offsets */ +#define NDMA_CHANNEL_REG_BASE (n) (0x100 + (n) * 0x20) +#define NDMA_CFG_REG 0x0 +#define NDMA_SRC_ADDR_REG 0x4
drivers/dma/sun4i-dma.c line 104
Quoted 10 lines
drivers/dma/sun4i-dma.c new file +10
-0+#define NDMA_DEST_ADDR_REG 0x8 +#define NDMA_BYTE_COUNT_REG 0xC + +/* Dedicated DMA register offsets */ +#define DDMA_CHANNEL_REG_BASE (n) (0x300 + (n) * 0x20) +#define DDMA_CFG_REG 0x0 +#define DDMA_SRC_ADDR_REG 0x4 +#define DDMA_DEST_ADDR_REG 0x8 +#define DDMA_BYTE_COUNT_REG 0xC +#define DDMA_PARA_REG 0x18
All these should be namespaced to avoid future conflicts
Quoted 12 lines
drivers/dma/sun4i-dma.c new file +12
-0+ +/** DMA Driver **/ + +/* +* Normal DMA has 8 channels, and Dedicated DMA has another 8, so that's +* 16 channels. As for endpoints, there's 29 and 21 respectively. Given +* that the Normal DMA endpoints (other than SDRAM) can be used as tx/rx, +* we need 78 vchans in total +*/ +#define NDMA_NR_MAX_CHANNELS 8 +#define DDMA_NR_MAX_CHANNELS 8 +#define DMA_NR_MAX_CHANNELS (NDMA_NR_MAX_CHANNELS + DDMA_NR_MAX_CHANNELS)
drivers/dma/sun4i-dma.c line 126
Quoted 10 lines
drivers/dma/sun4i-dma.c new file +10
-0+#define NDMA_NR_MAX_VCHANS (29 * 2 - 1) +#define DDMA_NR_MAX_VCHANS 21 +#define DMA_NR_MAX_VCHANS (NDMA_NR_MAX_VCHANS + DDMA_NR_MAX_VCHANS) + +/* This set of DDMA timing parameters were found experimentally while +* working with the SPI driver and seem to make it behave correctly */ +#define DDMA_MAGIC_SPI_PARAMETERS (DDMA_PARA_DEST_DATA_BLK_SIZE(1) | \ + DDMA_PARA_SRC_DATA_BLK_SIZE(1) | \ + DDMA_PARA_DEST_WAIT_CYCLES(2) | \ + DDMA_PARA_SRC_WAIT_CYCLES(2))
This should ideally be configurable from SPI
drivers/dma/sun4i-dma.c line 135
Quoted 9 lines
drivers/dma/sun4i-dma.c new file +9
-0+ +struct sun4i_dma_pchan { +/* Register base of channel */ +void __iomem *base; +/* vchan currently being serviced */ +struct sun4i_dma_vchan *vchan; +/* Is this a dedicated pchan? */ +int is_dedicated; +};
nitpick, it would be better if you follow kerneldoc for this struct comments or add to same line. This is bit non intuitive here, or use empty lines
drivers/dma/sun4i-dma.c line 193
Quoted 5 lines
drivers/dma/sun4i-dma.c new file +5
-0+ +static struct device *chan2dev (struct dma_chan *chan) +{ +return &chan->dev->device; +}
This should be in core..
Quoted 10 lines
drivers/dma/sun4i-dma.c new file +10
-0+static int __execute_vchan_pending (struct sun4i_dma_dev *priv, +struct sun4i_dma_vchan *vchan) +{ +struct sun4i_dma_promise *promise =NULL ; +struct sun4i_dma_contract *contract =NULL ; +struct sun4i_dma_pchan *pchan; +struct virt_dma_desc *vd; +int ret; + +lockdep_assert_held (&vchan->vc.lock);
drivers/dma/sun4i-dma.c line 359
Quoted 10 lines
drivers/dma/sun4i-dma.c new file +10
-0+ +/* We need a pchan to do anything, so secure one if available */ + pchan =find_and_use_pchan (priv, vchan); +if (!pchan) +return -EBUSY ; + +/* +* Channel endpoints must not be repeated, so if this vchan +* has already submitted some work, we can't do anything else +*/
and shouldn't the search take care of this for you...
Quoted 7 lines
drivers/dma/sun4i-dma.c new file +7
-0+static struct sun4i_dma_promise * +generate_ndma_promise (struct dma_chan *chan,dma_addr_t src,dma_addr_t dest, +size_t len,struct dma_slave_config *sconfig) +{ +struct sun4i_dma_promise *promise; +int ret; +
drivers/dma/sun4i-dma.c line 432
Quoted 10 lines
drivers/dma/sun4i-dma.c new file +10
-0+ promise =kzalloc (sizeof (*promise),GFP_NOWAIT ); +if (!promise) +return NULL ; + + promise->src = src; + promise->dst = dest; + promise->len = len; + promise->cfg =NDMA_CFG_LOADING |NDMA_CFG_BYTE_COUNT_MODE_REMAIN ; + +/* Use sensible default values if client is using undefined ones */
this doesn't make sense for slave
drivers/dma/sun4i-dma.c line 796
Quoted 10 lines
drivers/dma/sun4i-dma.c new file +10
-0+/* +* These are the magic DMA engine timings that keep SPI going. +* I haven't seen any interface on DMAEngine to configure +* timings, and so far they seem to work for everything we +* support, so I've kept them here. I don't know if other +* devices need different timings because, as usual, we only +* have the "para" bitfield meanings, but no comment on what +* the values should be when doing a certain operation :| +*/ + para =DDMA_MAGIC_SPI_PARAMETERS ;
and that is why these shouldn't be here
drivers/dma/sun4i-dma.c line 807
Quoted 11 lines
drivers/dma/sun4i-dma.c new file +11
-0+ +/* And make a suitable promise */ +if (vchan->is_dedicated) + promise =generate_ddma_promise (chan, srcaddr, dstaddr, +sg_dma_len (sg), sconfig); +else + promise =generate_ndma_promise (chan, srcaddr, dstaddr, +sg_dma_len (sg), sconfig); + +if (!promise) +return NULL ;/* TODO: should we free everything? */
yes otherwise you leak..
drivers/dma/sun4i-dma.c line 854
Quoted 3 lines
drivers/dma/sun4i-dma.c new file +3
-0+ +static int sun4i_dma_control (struct dma_chan *chan,enum dma_ctrl_cmd cmd, +unsigned long arg)
This needs to be updated to latest API..
Quoted 37 lines
drivers/dma/sun4i-dma.c new file +36
-0+{ +struct sun4i_dma_dev *priv =to_sun4i_dma_dev (chan->device); +struct sun4i_dma_vchan *vchan =to_sun4i_dma_vchan (chan); +int ret =0 ; + +switch (cmd) { +case DMA_RESUME : +case DMA_PAUSE : + ret = -EINVAL ; +break ; + +case DMA_TERMINATE_ALL : +dev_dbg (chan2dev (chan),"Terminating everything on channel\n" ); + ret =sun4i_dma_terminate_all (priv, vchan); +break ; + +case DMA_SLAVE_CONFIG : +memcpy (&vchan->cfg, (void *)arg,sizeof (vchan->cfg)); +break ; + +default : + ret = -ENXIO ; +break ; + } + +return ret; +} + + +static enum dma_status sun4i_dma_tx_status (struct dma_chan *chan, +dma_cookie_t cookie, +struct dma_tx_state *state) +{ +struct sun4i_dma_vchan *vchan =to_sun4i_dma_vchan (chan); +struct sun4i_dma_pchan *pchan = vchan->pchan; +struct sun4i_dma_contract *contract;
drivers/dma/sun4i-dma.c line 929
Quoted 10 lines
drivers/dma/sun4i-dma.c new file +10
-0+struct sun4i_dma_promise *promise; +struct virt_dma_desc *vd; +unsigned long flags; +enum dma_status ret; +size_t bytes =0 ; + + ret =dma_cookie_status (chan, cookie, state); +if (ret ==DMA_COMPLETE ) +return ret; +
before you proceed ahead check if state is null, if so bail out here.
drivers/dma/sun4i-dma.c line 1099
Quoted 4 lines
drivers/dma/sun4i-dma.c new file +4
-0+ +static int sun4i_dma_device_slave_caps (struct dma_chan *dchan, +struct dma_slave_caps *caps) +{
This needs update too
drivers/dma/sun4i-dma.c line 1236
Quoted 7 lines
drivers/dma/sun4i-dma.c new file +7
-0+ +static int sun4i_dma_remove (struct platform_device *pdev) +{ +struct sun4i_dma_dev *priv =platform_get_drvdata (pdev); + +/* Disable IRQ so no more work is scheduled */ +disable_irq (priv->irq);
how about your tasklets, how do you ensure they have been completed
Quoted 8 lines
drivers/dma/sun4i-dma.c new file +8
-0+ +of_dma_controller_free (pdev->dev.of_node); +dma_async_device_unregister (&priv->slave); + +clk_disable_unprepare (priv->clk); + +return 0 ; +}
Signature · 1 line
~Vinod