mtd: nand: dt binding documentation for digicolor NFC

The CX92755 SoC is one of Conexant Digicolor series of SoCs. This devicetree binding document describes the NAND flash controller the is shared by some SoCs in the Digicolor series.

Not all of the properties are currently actually used by the driver. Specifically, the driver doesn't make use of interrupts. This may change in the future.

Also worth noting that the only supported ECC mode is "hw_syndrome". In the future the driver may add support for additional modes.

---
 .../devicetree/bindings/mtd/digicolor-nand.txt     | 71 ++++++++++++++++++++++
 1 file changed, 71 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mtd/digicolor-nand.txt

new file mode 100644
index 000000000000..60e2d9085b7a
@@ -0,0 +1,71 @@
+Conexant Digicolor NAND Flash Controller (NFC)
+
+Required properties:
+- compatible : "cnxt,cx92755-nfc".
+- reg : shall contain registers location and length for data and reg.
+- interrupts : shall define the nand controller interrupt.
+- #address-cells: shall be set to 1. Encode the nand CS.
+- #size-cells : shall be set to 0.
+- clocks : shall reference nand controller clocks.
+
+Optional children nodes:
+Children nodes represent the available nand chips.
+
+Required children properties:
+- nand-ecc-mode : must be "hw_syndrome".
+- nand-ecc-strength : must be one of 6, 7, 8, 24, 28, 30.
+- nand-ecc-step-size : must be either 512 or 1024.
+
+see Documentation/devicetree/bindings/mtd/nand.txt for generic bindings.
+
+Each nand chip child node may optionally have partition sub-nodes. See
+Documentation/devicetree/bindings/mtd/partition.txt for partitions binding.
+
+Example:
+nfc: nfc at f00a4000 {
+	compatible = "cnxt,cx92755-nfc";
+	reg = <0xf00a4000 0x200>;
+	interrupts = <26>;
+	clocks = <&main_clk>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	nand at 0 {
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		nand-ecc-mode = "hw_syndrome";
+		nand-ecc-step-size = <1024>;
+		nand-ecc-strength = <28>;
+
+		partition at 0 {
+			label = "boot";
+			reg = <0x00000000 0x00700000>;
+		};
+
+		partition at 700000 {
+			label = "splash";
+			reg = <0x00700000 0x00500000>;
+		};
+
+		partition at c00000 {
+			label = "maint";
+			reg = <0x00c00000 0x00500000>;
+		};
+
+		partition at 1100000 {
+			label = "kernel";
+			reg = <0x01100000 0x00500000>;
+		};
+
+		partition at 1600000 {
+			label = "rootfs";
+			reg = <0x01600000 0x18000000>;
+		};
+
+		partition at 19600000 {
+			label = "data1";
+			reg = <0x19600000 0x66a00000>;
+		};
+	};
+};

2.1.4

This commit adds driver for the NAND flash controller on the CX92755 SoC. This SoC is one of the Conexant Digicolor series, and this driver should support other SoCs in this series.

Only hardware syndrome ECC mode is currently supported.

This driver was tested on the Equinox CX92755 EVK, with the Samsung K9GAG08U0E NAND chip (MLC, 8K pages, 436 bytes OOB). Test included attach of UBI volume, mount of UBIFS filesystem, and files read/write.

The driver was also tested by all MTD tests (except torturetest), and passed all of them. For oobtest the bitflip_limit parameter was set to 2.

---
v2:
* Address review comments of Boris Brezillon:
- Fix MODULE_DEVICE_TABLE name
- Remove digicolor_nfc_wait_ready() specific ops
- Extend the comment on CMD_NUMBER_BYTES definition
- Split bch_configs[] initialization from struct definition
- digicolor_nfc_cmd_write() returns error on timeout
- Differentiate between ETIMEDOUT and EIO in digicolor_nfc_ecc_status()
- Bail out of digicolor_nfc_read_page_syndrome() on ECC status timeout
- Remove redundant digicolor_nfc_dev_ready() after NAND_CMD_RESET
- Fallback to ecc_strength_ds/ecc_step_ds when there are no ECC configuration DT properties
- Add a comment explaining buffer tail handling in digicolor_nfc_rw_buf()
- Split per-NAND chip fields into a separate struct
- Use nand_sdr_timings to calculate signal timing configuration
- dev_ready() returns 1 only when the chip is actually ready

* Other changes:
- Use readl_poll_timeout() in digicolor_nfc_wait_ready() instead of open coding the same functionality
- Use memcpy() for buffer tail in digicolor_nfc_rw_buf()
- Add ecc.write_oob that does the equivalent of ecc.read_oob; this fixes mtd_oobtest
- Update commit message to reflect mtd tests status
- Allow up to 4 bitflips on average per 1K of blank page; fixes mtd_oobtest error

---
 drivers/mtd/nand/Kconfig          |   6 +
 drivers/mtd/nand/Makefile         |   1 +
 drivers/mtd/nand/digicolor_nand.c | 663 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 670 insertions(+)
 create mode 100644 drivers/mtd/nand/digicolor_nand.c

index 5b76a173cd95..6ea9098e290d 100644
@@ -529,4 +529,10 @@ config MTD_NAND_HISI504
 	help
 	  Enables support for NAND controller on Hisilicon SoC Hip04.
 
+config MTD_NAND_DIGICOLOR
+	tristate "Support for NAND on Conexant Digicolor SoCs"
+	depends on ARCH_DIGICOLOR
+	help
+	  Enables support for NAND Flash chips on Conexant Digicolor SoCs.
+
 endif # MTD_NAND

index 582bbd05aff7..1ae4cf0eec08 100644
@@ -52,5 +52,6 @@ obj-$(CONFIG_MTD_NAND_XWAY)		+= xway_nand.o
 obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH)	+= bcm47xxnflash/
 obj-$(CONFIG_MTD_NAND_SUNXI)		+= sunxi_nand.o
 obj-$(CONFIG_MTD_NAND_HISI504)	        += hisi504_nand.o
+obj-$(CONFIG_MTD_NAND_DIGICOLOR)	+= digicolor_nand.o
 
 nand-objs := nand_base.o nand_bbt.o nand_timings.o

2.1.4

Hi Baruch,

Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com