x86: Support machines with >4GB of RAM
Subsystems (3)
PATCH v2 1/6 x86: Support machines with >4GB of RAM
Some systems have more than 4GB of RAM. U-Boot can only place things below 4GB so any memory above that should not be used. Ignore any such memory so that the memory size will not exceed the maximum.
This prevents gd->ram_size exceeding 4GB which causes problems for PCI devices which use DMA.
---
Changes in v2: None
arch/x86/cpu/coreboot/sdram.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)
arch/x86/cpu/coreboot/sdram.c +4 -2
@@ -90,7 +90,8 @@ int dram_init(void)struct memrange *memrange = &lib_sysinfo.memrange[i];unsigned long long end = memrange->base + memrange->size; -if (memrange->type ==CB_MEM_RAM && end > ram_size) +if (memrange->type ==CB_MEM_RAM && end > ram_size && + memrange->base < (1ULL <<32 )) ram_size = end; } gd->ram_size = ram_size;
@@ -108,7 +109,8 @@ void dram_init_banksize(void)for (i =0 , j =0 ; i < lib_sysinfo.n_memranges; i++) {struct memrange *memrange = &lib_sysinfo.memrange[i]; -if (memrange->type ==CB_MEM_RAM ) { +if (memrange->type ==CB_MEM_RAM && + memrange->base < (1ULL <<32 )) { gd->bd->bi_dram[j].start = memrange->base; gd->bd->bi_dram[j].size = memrange->size; j++;
Signature · 1 line
2.2.0.rc0.207.ga3a616c
PATCH v2 2/6 x86: video: Allow keyboard presence to be controlled by device tree
At present a VGA console assumes a keyboard unless a CONFIG option is set. This difference can be dealt with by a device tree option, allowing boards that are otherwise the same to use the same configuration.
---
Changes in v2:
- Correct #ifdef setup to avoid build errors on non-x86 boards
doc/README.fdt-control | 16 ++++++++++++++++ drivers/video/cfb_console.c | 29 +++++++++++++++++++++-------- 2 files changed, 37 insertions(+), 8 deletions(-)
doc/README.fdt-control +16 -0
@@ -171,6 +171,22 @@ After board configuration is done, fdt supported u-boot can be build in two ways $ make DEVICE_TREE=<dts-file-name> +Configuration Options +--------------------- + +A number of run-time configuration options are provided in the /config node +of the control device tree. You can access these using fdtdec_get_config_int(), +fdtdec_get_config_bool() and fdtdec_get_config_string(). + +Available options are: + +silent-console + If present and non-zero, the console is silenced by default on boot. + +no-keyboard + Tells U-Boot not to expect an attached keyboard with a VGA console + + Limitations -----------
drivers/video/cfb_console.c +21 -8
@@ -87,6 +87,7 @@*/ #include <common.h> +#include <fdtdec.h> #include <version.h> #include <malloc.h> #include <linux/compiler.h>
@@ -2251,6 +2252,7 @@ int drv_video_init(void) {int skip_dev_init;struct stdio_dev console_dev; +bool have_keyboard;/* Check if video initialization should be skipped */ if (board_video_skip ())
@@ -2262,11 +2264,20 @@ int drv_video_init(void)if (board_cfb_skip ())return 0 ; +#if defined(CONFIG_VGA_AS_SINGLE_DEVICE ) + have_keyboard = false; +#elif defined(CONFIG_OF_CONTROL ) + have_keyboard = !fdtdec_get_config_bool (gd->fdt_blob, +"u-boot,no-keyboard" ); +#else + have_keyboard = true; +#endif +if (have_keyboard) { +debug ("KBD: Keyboard init ...\n" );#if !defined(CONFIG_VGA_AS_SINGLE_DEVICE ) -debug ("KBD: Keyboard init ...\n" ); - skip_dev_init |= (VIDEO_KBD_INIT_FCT ==-1 ); + skip_dev_init |= (VIDEO_KBD_INIT_FCT ==-1 );#endif - + }if (skip_dev_init)return 0 ;
@@ -2279,11 +2290,13 @@ int drv_video_init(void) console_dev.puts = video_puts;/* 'puts' function */ #if !defined(CONFIG_VGA_AS_SINGLE_DEVICE ) -/* Also init console device */ - console_dev.flags |=DEV_FLAGS_INPUT ; - console_dev.tstc =VIDEO_TSTC_FCT ;/* 'tstc' function */ - console_dev.getc =VIDEO_GETC_FCT ;/* 'getc' function */ -#endif /* CONFIG_VGA_AS_SINGLE_DEVICE */ +if (have_keyboard) { +/* Also init console device */ + console_dev.flags |=DEV_FLAGS_INPUT ; + console_dev.tstc =VIDEO_TSTC_FCT ;/* 'tstc' function */ + console_dev.getc =VIDEO_GETC_FCT ;/* 'getc' function */ + } +#endif if (stdio_register (&console_dev) !=0 )return 0 ;
Signature · 1 line
2.2.0.rc0.207.ga3a616c
PATCH v2 2/6 x86: video: Allow keyboard presence to be controlled by device tree
Quoted 5 lines · Simon Glass
At present a VGA console assumes a keyboard unless a CONFIG option is set. This difference can be dealt with by a device tree option, allowing boards that are otherwise the same to use the same configuration.
Signed-off-by Simon Glass <[email protected]>
Quoted 8 lines
---
Changes in v2:
- Correct #ifdef setup to avoid build errors on non-x86 boardsdoc/README.fdt-control | 16 ++++++++++++++++ drivers/video/cfb_console.c | 29 +++++++++++++++++++++-------- 2 files changed, 37 insertions(+), 8 deletions(-)
Applied to u-boot-dm/next.
PATCH v2 3/6 x86: pci: Add PCI IDs for lynxpoint
In reply to Simon GlassAdd some new device IDs used by this haswell-based chipset.
---
Changes in v2:
- Put this patch before the one that needs it
include/pci_ids.h | 2 ++ 1 file changed, 2 insertions(+)
include/pci_ids.h +2 -0
@@ -3016,6 +3016,8 @@#define PCI_DEVICE_ID_INTEL_TCF_UART_2 0x8813#define PCI_DEVICE_ID_INTEL_TCF_UART_3 0x8814#define PCI_DEVICE_ID_INTEL_IXP2800 0x9004 +#define PCI_DEVICE_ID_INTEL_LYNXPOINT_AHCI 0x9c03 +#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LPC 0x9c45#define PCI_DEVICE_ID_INTEL_S21152BB 0xb152#define PCI_VENDOR_ID_SCALEMP 0x8686
Signature · 1 line
2.2.0.rc0.207.ga3a616c
PATCH v2 3/6 x86: pci: Add PCI IDs for lynxpoint
Quoted 11 lines · Simon Glass
Add some new device IDs used by this haswell-based chipset.
Signed-off-by Simon Glass <[email protected]>Reviewed-by Bin Meng <[email protected]>---
Changes in v2:
- Put this patch before the one that needs itinclude/pci_ids.h | 2 ++ 1 file changed, 2 insertions(+)
Applied to u-boot-dm/next.
PATCH v2 4/6 x86: spi: Add support for lynxpoint
In reply to Simon GlassAdd Lynxpoint to the driver so that the Asus Chromebox can be supported.
---
Changes in v2: None
drivers/spi/ich.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
drivers/spi/ich.c +2 -1
@@ -185,7 +185,8 @@ static int get_ich_version(uint16_t device_id) device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX) || (device_id >=PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN && device_id <=PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX ) || - device_id == PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC) + device_id ==PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC || + device_id == PCI_DEVICE_ID_INTEL_LYNXPOINT_LPC) return 9;return 0 ;
Signature · 1 line
2.2.0.rc0.207.ga3a616c
PATCH v2 4/6 x86: spi: Add support for lynxpoint
Quoted 10 lines · Simon Glass
Add Lynxpoint to the driver so that the Asus Chromebox can be supported.
Signed-off-by Simon Glass <[email protected]>Reviewed-by Jagannadha Sutradharudu Teki <[email protected]>---
Changes in v2: None
drivers/spi/ich.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
Applied to u-boot-dm/next.
PATCH v2 5/6 x86: Move common Chromebook config into a separate file
In reply to Simon GlassSince Chromebooks mostly have similar configuration, put it in a common file.
---
Changes in v2: None
include/configs/chromebook_link.h | 61 +---------------------------------- include/configs/x86-chromebook.h | 68 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 69 insertions(+), 60 deletions(-) create mode 100644 include/configs/x86-chromebook.h
include/configs/chromebook_link.h +1 -60
@@ -14,65 +14,6 @@#define __CONFIG_H#include <configs/x86-common.h> - - -#define CONFIG_SYS_MONITOR_LEN (1 << 20) - -#define CONFIG_DCACHE_RAM_MRC_VAR_SIZE 0x4000 -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_MISC_INIT_R - -#define CONFIG_NR_DRAM_BANKS 8 -#define CONFIG_X86_MRC_ADDR 0xfffa0000 -#define CONFIG_CACHE_MRC_SIZE_KB 512 - -#define CONFIG_X86_SERIAL - -#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_INTEL, \ - PCI_DEVICE_ID_INTEL_NM10_AHCI}, \ - {PCI_VENDOR_ID_INTEL, \ - PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \ - {PCI_VENDOR_ID_INTEL, \ - PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \ - {PCI_VENDOR_ID_INTEL, \ - PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE} - -#define CONFIG_X86_OPTION_ROM_FILE pci8086,0166.bin -#define CONFIG_X86_OPTION_ROM_ADDR 0xfff90000 - -#define CONFIG_PCI_MEM_BUS 0xe0000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_PREF_BUS 0xd0000000 -#define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS -#define CONFIG_PCI_PREF_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x1000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0xefff - -#define CONFIG_SYS_EARLY_PCI_INIT -#define CONFIG_PCI_PNP - -#define CONFIG_BIOSEMU -#define VIDEO_IO_OFFSET 0 -#define CONFIG_X86EMU_RAW_IO - -#define CONFIG_CROS_EC -#define CONFIG_CROS_EC_LPC -#define CONFIG_CMD_CROS_EC -#define CONFIG_ARCH_EARLY_INIT_R - -#undef CONFIG_ENV_IS_NOWHERE -#undef CONFIG_ENV_SIZE -#define CONFIG_ENV_SIZE 0x1000 -#define CONFIG_ENV_SECT_SIZE 0x1000 -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_OFFSET 0x003f8000 - -#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \ - "stdout=vga,serial\0" \ - "stderr=vga,serial\0" +#include <configs/x86-chromebook.h> #endif /* __CONFIG_H */
include/configs/x86-chromebook.h new file +68 -0
68 lines not on this page · raw message
Signature · 1 line
2.2.0.rc0.207.ga3a616c
PATCH v2 5/6 x86: Move common Chromebook config into a separate file
Quoted 5 lines · Simon Glass
Since Chromebooks mostly have similar configuration, put it in a common file.
Signed-off-by Simon Glass <[email protected]>Reviewed-by Bin Meng <[email protected]>
Quoted 8 lines
---
Changes in v2: None
include/configs/chromebook_link.h | 61 +---------------------------------- include/configs/x86-chromebook.h | 68 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 69 insertions(+), 60 deletions(-) create mode 100644 include/configs/x86-chromebook.h
Applied to u-boot-dm/next.
PATCH v2 6/6 x86: Add support for panther (Asus Chromebox)
In reply to Simon GlassSupport running U-Boot as a coreboot payload. Tested peripherals include:
- Video (HDMI and DisplayPort)
- SATA disk
- Gigabit Ethernet
- SPI flash
USB3 does not work. This may be a problem with the USB3 PCI driver or something in the USB3 stack and has not been investigated So far this is disabled. The SD card slot also does not work.
For video, coreboot will need to run the OPROM to set this up.
With this board, bare support (running without coreboot) is not available as yet.
---
Changes in v2:
- Update Kconfig and MAINTAINERS file to build bare
- Use "intel,haswell" as the compatible name
arch/x86/Kconfig | 16 ++++++++ arch/x86/dts/Makefile | 1 + arch/x86/dts/chromebox_panther.dts | 64 ++++++++++++++++++++++++++++++ board/google/chromebox_panther/Kconfig | 34 ++++++++++++++++ board/google/chromebox_panther/MAINTAINERS | 6 +++ board/google/chromebox_panther/Makefile | 7 ++++ board/google/chromebox_panther/panther.c | 22 ++++++++++ configs/chromebox_panther_defconfig | 11 +++++ include/configs/chromebox_panther.h | 17 ++++++++ 9 files changed, 178 insertions(+) create mode 100644 arch/x86/dts/chromebox_panther.dts create mode 100644 board/google/chromebox_panther/Kconfig create mode 100644 board/google/chromebox_panther/MAINTAINERS create mode 100644 board/google/chromebox_panther/Makefile create mode 100644 board/google/chromebox_panther/panther.c create mode 100644 configs/chromebox_panther_defconfig create mode 100644 include/configs/chromebox_panther.h
arch/x86/Kconfig +16 -0
@@ -32,6 +32,20 @@ config TARGET_CHROMEBOOK_LINK and it provides a 2560x1700 high resolution touch-enabled LCD display. +config TARGET_CHROMEBOX_PANTHER + bool "Support Chromebox panther (not available)" + select n + help + Note: At present this must be used with Coreboot. See README.x86 + for instructions. + + This is the Asus Chromebox CN60 released in 2014. It uses an Intel + Haswell Celeron 2955U Dual Core CPU with 2GB of SDRAM. It has a + Lynx Point platform controller hub, PCIe WiFi and Bluetooth. It also + includes a USB SD reader, four USB3 ports, display port and HDMI + video output and a 16GB SATA solid state drive. There is no Chrome + OS EC on this model. + config TARGET_CROWNBAY bool "Support Intel Crown Bay CRB" help
@@ -435,6 +449,8 @@ source "board/coreboot/coreboot/Kconfig" source "board/google/chromebook_link/Kconfig" +source "board/google/chromebox_panther/Kconfig" + source "board/intel/crownbay/Kconfig" source "board/intel/minnowmax/Kconfig"
arch/x86/dts/Makefile +1 -0
@@ -1,4 +1,5 @@ dtb-y += chromebook_link.dtb \ + chromebox_panther.dtb \ crownbay.dtb \ galileo.dtb \ minnowmax.dtb
arch/x86/dts/chromebox_panther.dts new file +64 -0
64 lines not on this page · raw message
board/google/chromebox_panther/Kconfig new file +34 -0
@@ -0,0 +1,34 @@ +if TARGET_CHROMEBOX_PANTHER + +config SYS_BOARD + default "chromebox_panther" + +config SYS_VENDOR + default "google" + +config SYS_SOC + default "ivybridge" + +config SYS_CONFIG_NAME + default "chromebox_panther" + +# Panther actually uses haswell, not ivybridge, so this is just a placeholder +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select X86_RESET_VECTOR + select CPU_INTEL_SOCKET_RPGA989 + select NORTHBRIDGE_INTEL_IVYBRIDGE + select SOUTHBRIDGE_INTEL_C216 + select HAVE_ACPI_RESUME + select MARK_GRAPHICS_MEM_WRCOMB + select BOARD_ROMSIZE_KB_8192 + +config SYS_CAR_ADDR + hex + default 0xff7e0000 + +config SYS_CAR_SIZE + hex + default 0x20000 + +endif
board/google/chromebox_panther/MAINTAINERS new file +6 -0
@@ -0,0 +1,6 @@ +CHROMEBOX PANTHER BOARD +M: Simon Glass <[email protected]> +S: Maintained +F: board/google/chromebook_panther/ +F: include/configs/chromebox_panther.h +F: configs/chromebox_panther_defconfig
board/google/chromebox_panther/Makefile new file +7 -0
@@ -0,0 +1,7 @@ +# +# Copyright (c) 2015 Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += panther.o
board/google/chromebox_panther/panther.c new file +22 -0
@@ -0,0 +1,22 @@ +/* +* Copyright (C) 2015 Google, Inc +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <asm/arch/pch.h> + +int arch_early_init_r (void ) +{ +return 0 ; +} + +int board_early_init_f (void ) +{ +return 0 ; +} + +void setup_pch_gpios (u16 gpiobase,const struct pch_gpio_map *gpio) +{ +}
configs/chromebox_panther_defconfig new file +11 -0
@@ -0,0 +1,11 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xfff00000" +CONFIG_X86=y +CONFIG_TARGET_CHROMEBOX_PANTHER=y +CONFIG_OF_CONTROL=y +CONFIG_OF_SEPARATE=y +CONFIG_DEFAULT_DEVICE_TREE="chromebox_panther" +CONFIG_HAVE_MRC=y +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_VIDEO_VESA=y +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y +CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
include/configs/chromebox_panther.h new file +17 -0
@@ -0,0 +1,17 @@ +/* +* Copyright (c) 2011 The Chromium OS Authors. +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <configs/x86-common.h> +#include <configs/x86-chromebook.h> + +#define CONFIG_RTL8169 +/* Avoid a warning in the Realtek Ethernet driver */ +#define CONFIG_SYS_CACHELINE_SIZE 16 + +#endif /* __CONFIG_H */
Signature · 1 line
2.2.0.rc0.207.ga3a616c
PATCH v2 6/6 x86: Add support for panther (Asus Chromebox)
Quoted 16 lines · Simon Glass
Support running U-Boot as a coreboot payload. Tested peripherals include:
- Video (HDMI and DisplayPort)
- SATA disk
- Gigabit Ethernet
- SPI flashUSB3 does not work. This may be a problem with the USB3 PCI driver or something in the USB3 stack and has not been investigated So far this is disabled. The SD card slot also does not work.
For video, coreboot will need to run the OPROM to set this up.
With this board, bare support (running without coreboot) is not available as yet.
Quoted 6 lines
Signed-off-by Simon Glass <[email protected]>---
Changes in v2:
- UpdateKconfigandMAINTAINERSfile to build bare
- Use "intel,haswell" as the compatible name
Applied to u-boot-dm/next.
PATCH v2 1/6 x86: Support machines with >4GB of RAM
In reply to Simon GlassHi Simon,
Quoted 31 lines
Some systems have more than 4GB of RAM. U-Boot can only place things below 4GB so any memory above that should not be used. Ignore any such memory so that the memory size will not exceed the maximum.
This prevents
gd->ram_sizeexceeding 4GB which causes problems for PCI devices which use DMA.Signed-off-by Simon Glass <[email protected]>Reviewed-by Bin Meng <[email protected]>---
Changes in v2: None
arch/x86/cpu/coreboot/sdram.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)(quoted diff) +0
-0
b/arch/x86/cpu/coreboot/sdram.cindex e98a230..9c3ab81 100644arch/x86/cpu/coreboot/sdram.c +2
-1@@ -90,7 +90,8 @@ int dram_init(void)struct memrange *memrange = &lib_sysinfo.memrange[i];unsigned long long end = memrange->base + memrange->size; -if (memrange->type ==CB_MEM_RAM && end > ram_size) +if (memrange->type ==CB_MEM_RAM && end > ram_size && + memrange->base < (1ULL <<32 )) ram_size = end; } gd->ram_size = ram_size;
arch/x86/cpu/coreboot/sdram.c void dram_init_banksize(void) · line 116
Quoted 9 lines
arch/x86/cpu/coreboot/sdram.c +2
-1@@ -108,7 +109,8 @@ void dram_init_banksize(void)for (i =0 , j =0 ; i < lib_sysinfo.n_memranges; i++) {struct memrange *memrange = &lib_sysinfo.memrange[i]; -if (memrange->type ==CB_MEM_RAM ) { +if (memrange->type ==CB_MEM_RAM && + memrange->base < (1ULL <<32 )) { gd->bd->bi_dram[j].start = memrange->base; gd->bd->bi_dram[j].size = memrange->size; j++;
Signature · 5 lines
Best regards, Lukasz Majewski Samsung R&D Institute Poland (SRPOL) | Linux Platform Group
PATCH v2 1/6 x86: Support machines with >4GB of RAM
Quoted 36 lines · Lukasz Majewski
Hi Simon,
Quoted 34 lines
Some systems have more than 4GB of RAM. U-Boot can only place things below 4GB so any memory above that should not be used. Ignore any such memory so that the memory size will not exceed the maximum.
This prevents
gd->ram_sizeexceeding 4GB which causes problems for PCI devices which use DMA.Signed-off-by Simon Glass <[email protected]>Reviewed-by Bin Meng <[email protected]>---
Changes in v2: None
arch/x86/cpu/coreboot/sdram.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)(quoted diff) +0
-0
b/arch/x86/cpu/coreboot/sdram.cindex e98a230..9c3ab81 100644arch/x86/cpu/coreboot/sdram.c +2
-1@@ -90,7 +90,8 @@ int dram_init(void)struct memrange *memrange = &lib_sysinfo.memrange[i];unsigned long long end = memrange->base + memrange->size; -if (memrange->type ==CB_MEM_RAM && end > ram_size) +if (memrange->type ==CB_MEM_RAM && end > ram_size && + memrange->base < (1ULL <<32 )) ram_size = end; } gd->ram_size = ram_size;@@ -108,7 +109,8 @@ void dram_init_banksize(void)for (i =0 , j =0 ; i < lib_sysinfo.n_memranges; i++) {struct memrange *memrange = &lib_sysinfo.memrange[i];
Quoted 8 lines
arch/x86/cpu/coreboot/sdram.c void dram_init_banksize(void) · line 116
Quoted 6 lines
arch/x86/cpu/coreboot/sdram.c +2
-1-if (memrange->type ==CB_MEM_RAM ) { +if (memrange->type ==CB_MEM_RAM && + memrange->base < (1ULL <<32 )) { gd->bd->bi_dram[j].start = memrange->base; gd->bd->bi_dram[j].size = memrange->size; j++;Reviewed-by Lukasz Majewski <[email protected]>
Applied to u-boot-dm/next.