Add SPL support for SoCFPGA

From: Dinh Nguyen <[email protected]>

Hello,

This is v2 of the patchset that adds all the SPL code that is necessary to support the SoCFPGA platform. For v2, here are the changes:

- SDRAM - further clean and addressing all comments. Simplified to only support DDR3, FULLRATE, and Hard PHY.
- SDRAM - Moved to drivers/ddr/altera
- Move extra code that maps SDRAM to 0x0 in board_init_f

I have pushed a branch to git://git.rocketboards.org/u-boot-socfpga-next.git
socfpga_for_next_spl_v2 for testing and reviewing.

Rebased to 2015.04-rc2.

Thanks,

Dinh Nguyen (20):
arm: socfpga: spl: Add main sdram code
arm: socfpga: spl: Add SRAM section
arm: socfpga: spl: put SPL in sram
arm: socfpga: add functions to bring sdram, timer, and uart out of
reset
arm: socfpga: spl: enable sdram, timer and uart
arm: socfpga: spl: Add call to timer_init
arm: socfpga: spl: allow bootrom to enable IOs after warm reset
arm: socfpga: spl: add sdram init and calibration
arm: socfpga: spl: printout sdram size
arm: socfpga: spl: Use common lowlevel_init
arm: socfpga: spl: Add s_init
arm: socfpga: spl: add the stack in OCRAM
arm: socfpga: spl: add CONFIG_SPL_STACK to socfpga_common.h
arm: socfpga: add sdram stack to SPL
arm: socfpga: spl: adjust SPL_MALLOC_SIZE to 256
arm: socfpga: spl: add a malloc section in sram
arm: socfpga: spl: Add SDRAM check
arm: socfpga: spl: add board_init_f to SPL
arm: socfpga: spl: update pll_config for dev kit
arm: socfpga: remove the need to map sdram in arch_early_init

 Makefile                                           |    1 +
 arch/arm/cpu/armv7/Makefile                        |    2 +-
 arch/arm/cpu/armv7/socfpga/Makefile                |    4 +-
 arch/arm/cpu/armv7/socfpga/lowlevel_init.S         |    4 -
 arch/arm/cpu/armv7/socfpga/misc.c                  |    3 -
 arch/arm/cpu/armv7/socfpga/reset_manager.c         |   24 +
 arch/arm/cpu/armv7/socfpga/s_init.c                |   37 +
 arch/arm/cpu/armv7/socfpga/spl.c                   |   47 +
 arch/arm/cpu/armv7/socfpga/system_manager.c        |    9 +
 arch/arm/cpu/armv7/socfpga/u-boot-spl.lds          |   29 +-
 arch/arm/include/asm/arch-socfpga/reset_manager.h  |    6 +
 arch/arm/include/asm/arch-socfpga/sdram.h          |  434 +++
 arch/arm/include/asm/arch-socfpga/sdram_config.h   |  100 +
 arch/arm/include/asm/arch-socfpga/system_manager.h |    1 +
 board/altera/socfpga/pll_config.h                  |    8 +-
 drivers/ddr/altera/Makefile                        |   12 +
 drivers/ddr/altera/sdram.c                         | 1307 +++++++
 drivers/ddr/altera/sequencer.c                     | 3972 ++++++++++++++++++++
 drivers/ddr/altera/sequencer.h                     |  359 ++
 drivers/ddr/altera/sequencer_auto.h                |  216 ++
 drivers/ddr/altera/sequencer_auto_ac_init.c        |   85 +
 drivers/ddr/altera/sequencer_auto_inst_init.c      |  270 ++
 drivers/ddr/altera/sequencer_defines.h             |  121 +
 include/configs/socfpga_common.h                   |   11 +-
 include/configs/socfpga_cyclone5.h                 |    1 +
 scripts/Makefile.spl                               |    1 +
 26 files changed, 7046 insertions(+), 18 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/socfpga/s_init.c
 create mode 100644 arch/arm/include/asm/arch-socfpga/sdram.h
 create mode 100644 arch/arm/include/asm/arch-socfpga/sdram_config.h
 create mode 100644 drivers/ddr/altera/Makefile
 create mode 100644 drivers/ddr/altera/sdram.c
 create mode 100644 drivers/ddr/altera/sequencer.c
 create mode 100644 drivers/ddr/altera/sequencer.h
 create mode 100644 drivers/ddr/altera/sequencer_auto.h
 create mode 100644 drivers/ddr/altera/sequencer_auto_ac_init.c
 create mode 100644 drivers/ddr/altera/sequencer_auto_inst_init.c
 create mode 100644 drivers/ddr/altera/sequencer_defines.h

2.2.1

From: Dinh Nguyen <[email protected]>

This adds the code to configure the SDRAM controller that is found in the SoCFGPA Cyclone5 and Arria5 platforms.

---
v2: moved to drivers/ddr/altera/
only supports DDR3 at FULLRATE

---
 Makefile                                         |    1 +
 arch/arm/include/asm/arch-socfpga/sdram.h        |  434 +++
 arch/arm/include/asm/arch-socfpga/sdram_config.h |  100 +
 drivers/ddr/altera/Makefile                      |   12 +
 drivers/ddr/altera/sdram.c                       | 1307 +++++++
 drivers/ddr/altera/sequencer.c                   | 3972 ++++++++++++++++++++++
 drivers/ddr/altera/sequencer.h                   |  359 ++
 drivers/ddr/altera/sequencer_auto.h              |  216 ++
 drivers/ddr/altera/sequencer_auto_ac_init.c      |   85 +
 drivers/ddr/altera/sequencer_auto_inst_init.c    |  270 ++
 drivers/ddr/altera/sequencer_defines.h           |  121 +
 include/configs/socfpga_cyclone5.h               |    1 +
 scripts/Makefile.spl                             |    1 +
 13 files changed, 6879 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-socfpga/sdram.h
 create mode 100644 arch/arm/include/asm/arch-socfpga/sdram_config.h
 create mode 100644 drivers/ddr/altera/Makefile
 create mode 100644 drivers/ddr/altera/sdram.c
 create mode 100644 drivers/ddr/altera/sequencer.c
 create mode 100644 drivers/ddr/altera/sequencer.h
 create mode 100644 drivers/ddr/altera/sequencer_auto.h
 create mode 100644 drivers/ddr/altera/sequencer_auto_ac_init.c
 create mode 100644 drivers/ddr/altera/sequencer_auto_inst_init.c
 create mode 100644 drivers/ddr/altera/sequencer_defines.h

index bd4abab..bd4b009 100644
@@ -636,6 +636,7 @@ libs-y += drivers/power/ \
 libs-y += drivers/spi/
 libs-$(CONFIG_FMAN_ENET) += drivers/net/fm/
 libs-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/
+libs-$(CONFIG_ALTERA_SDRAM) += drivers/ddr/altera/
 libs-y += drivers/serial/
 libs-y += drivers/usb/eth/
 libs-y += drivers/usb/gadget/

new file mode 100644
index 0000000..38fba57
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# (C) Copyright 2010, Thomas Chou <[email protected]>
+# Copyright (C) 2014 Altera Corporation <www.altera.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-$(CONFIG_ALTERA_SDRAM) += sdram.o sequencer.o sequencer_auto_ac_init.o \
+			  sequencer_auto_inst_init.o

index c3d958c..c79769c 100644

index fcacb7f..a04b286 100644

2.2.1

Part of the diff is not shown here. View the raw message.

Hi!

[...]

Can you define these registers using the struct-based access please ?

[...]

From: Dinh Nguyen <[email protected]>

Add a section of SRAM to the SPL linker file.

---
 arch/arm/cpu/armv7/socfpga/u-boot-spl.lds | 2 ++
 include/configs/socfpga_common.h          | 1 +
 2 files changed, 3 insertions(+)

index 569fa41..a868a36 100644
@@ -5,6 +5,8 @@
  */
 
 MEMORY { .sdram : ORIGIN = (0), LENGTH = (0xffffffff) }
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
+		LENGTH = CONFIG_SPL_MAX_SIZE }
 
 OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
 OUTPUT_ARCH(arm)

index ee227fe..d449a78 100644
@@ -294,6 +294,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #define CONFIG_SPL_TEXT_BASE		CONFIG_SYS_INIT_RAM_ADDR
 #define CONFIG_SYS_SPL_MALLOC_START	CONFIG_SYS_INIT_SP_ADDR
 #define CONFIG_SYS_SPL_MALLOC_SIZE	(5 * 1024)
+#define CONFIG_SPL_MAX_SIZE		(64 * 1024)
 
 #define CHUNKSZ_CRC32			(1 * 1024)	/* FIXME: ewww */
 #define CONFIG_CRC32_VERIFY

2.2.1

Hi!

Can we not use the generic SPL stuff ( ./arch/arm/cpu/u-boot-spl.lds ) here instead please ?

Best regards,
Marek Vasut

I looked at this, but I didn't see way to overlay in an SRAM section. Do you have an example of how to do this?

Thanks,
Dinh

Hi!

Is it really needed at all in the first place ? Why ?

Best regards,
Marek Vasut

Isn't this need to specify the SPL to be located in the sram section? I see other platforms doing the same thing, ie. zynq, sunxi.

Dinh

CONFIG_SPL_TEXT_BASE is what specifies the address to which the SPL is linked. This is the address where the BootROM should place the SPL and jump to it's first instruction.

I don't think you explicitly need to hack linker scripts to add this section.

btw. Tom Rini has a different email address (@konsulko) now.

btw2. is there any way I can help you with hacking on the SPL please ?

Best regards,
Marek Vasut

Ah yes, I think I can make use of it now.

Right...saw it right after I sent out this series.

Let me post a v3 within this week, and I would appreciate any help. Does posting the series to git repo help you to help me?

Dinh

From: Dinh Nguyen <[email protected]>

Update SPL linker file to use SRAM.

---
 arch/arm/cpu/armv7/socfpga/u-boot-spl.lds | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

index a868a36..730d154 100644
@@ -21,13 +21,13 @@ SECTIONS
 		*(.vectors)
 		arch/arm/cpu/armv7/start.o	(.text*)
 		*(.text*)
-	} >.sdram
+	} >.sram
 
 	. = ALIGN(4);
-	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } >.sdram
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } >.sram
 
 	. = ALIGN(4);
-	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sdram
+	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
 
 	. = ALIGN(4);
 	__image_copy_end = .;

@@ -43,5 +43,5 @@ SECTIONS
 		*(.bss*)
 		. = ALIGN(4);
 		__bss_end = .;
-	} >.sdram
+	} >.sram
 }

2.2.1

Hi!

Same comment applies as for 02/20 ( can't we use generic ./arch/arm/cpu/u-boot-spl.lds ?) Also, you can probably just combine this patch with 02/20 .

Best regards,
Marek Vasut

From: Dinh Nguyen <[email protected]>

These functions will be needed for use by the SPL for enabling the console and sdram initialization.

---
 arch/arm/cpu/armv7/socfpga/reset_manager.c        | 24 +++++++++++++++++++++++
 arch/arm/include/asm/arch-socfpga/reset_manager.h |  6 ++++++
 2 files changed, 30 insertions(+)

index 25921e7..45b352b 100644
@@ -113,3 +113,27 @@ void socfpga_spim_enable(void)
 	clrbits_le32(reset, (1 << RSTMGR_PERMODRST_SPIM0_LSB) |
 		     (1 << RSTMGR_PERMODRST_SPIM1_LSB));
 }
+
+/* Bring UART0 out of reset. */
+void socfpga_uart0_enable(void)
+{
+	const void *reset = &reset_manager_base->per_mod_reset;
+
+	clrbits_le32(reset, 1 << RSTMGR_PERMODRST_UART0_LSB);
+}
+
+/* Bring SDRAM controller out of reset. */
+void socfpga_sdram_enable(void)
+{
+	const void *reset = &reset_manager_base->per_mod_reset;
+
+	clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SDR_LSB);
+}
+
+/* Bring OSC1 timer out of reset. */
+void socfpga_osc1timer_enable(void)
+{
+	const void *reset = &reset_manager_base->per_mod_reset;
+
+	clrbits_le32(reset, 1 << RSTMGR_PERMODRST_OSC1TIMER0_LSB);
+}

index 034135b..d63a285 100644
@@ -15,6 +15,9 @@ void socfpga_bridges_reset(int enable);
 void socfpga_emac_reset(int enable);
 void socfpga_watchdog_reset(void);
 void socfpga_spim_enable(void);
+void socfpga_uart0_enable(void);
+void socfpga_sdram_enable(void);
+void socfpga_osc1timer_enable(void);
 
 struct socfpga_reset_manager {
 	u32	status;

@@ -36,7 +39,10 @@ struct socfpga_reset_manager {
 #define RSTMGR_PERMODRST_EMAC0_LSB	0
 #define RSTMGR_PERMODRST_EMAC1_LSB	1
 #define RSTMGR_PERMODRST_L4WD0_LSB	6
+#define RSTMGR_PERMODRST_OSC1TIMER0_LSB	8
+#define RSTMGR_PERMODRST_UART0_LSB	16
 #define RSTMGR_PERMODRST_SPIM0_LSB	18
 #define RSTMGR_PERMODRST_SPIM1_LSB	19
+#define RSTMGR_PERMODRST_SDR_LSB	29
 
 #endif /* _RESET_MANAGER_H_ */

2.2.1

From: Dinh Nguyen <[email protected]>

Add the calls in the spl_board_init to enable SDRAM, timer, and UART.

---
 arch/arm/cpu/armv7/socfpga/spl.c | 4 ++++
 1 file changed, 4 insertions(+)

index bd9f338..b123336 100644
@@ -145,6 +145,10 @@ void spl_board_init(void)
 	/* freeze all IO banks */
 	sys_mgr_frzctrl_freeze_req();
 
+	socfpga_sdram_enable();
+	socfpga_uart0_enable();
+	socfpga_osc1timer_enable();
+
 	debug("Reconfigure Clock Manager\n");
 	/* reconfigure the PLLs */
 	cm_basic_init(&cm_default_cfg);

2.2.1

From: Dinh Nguyen <[email protected]>

---
 arch/arm/cpu/armv7/socfpga/spl.c | 2 ++
 1 file changed, 2 insertions(+)

index b123336..bc6f8dd 100644
@@ -149,6 +149,8 @@ void spl_board_init(void)
 	socfpga_uart0_enable();
 	socfpga_osc1timer_enable();
 
+	timer_init();
+
 	debug("Reconfigure Clock Manager\n");
 	/* reconfigure the PLLs */
 	cm_basic_init(&cm_default_cfg);

2.2.1

Hi!

The common SPL framework , common/spl/spl.c , does such timer_init() call as well. Can we use the common SPL framework instead (preferred) ?

Also, please add descriptive commit messages to your patches.

Best regards,
Marek Vasut

From: Dinh Nguyen <[email protected]>

---
 arch/arm/cpu/armv7/socfpga/spl.c                   | 3 +++
 arch/arm/cpu/armv7/socfpga/system_manager.c        | 9 +++++++++
 arch/arm/include/asm/arch-socfpga/system_manager.h | 1 +
 3 files changed, 13 insertions(+)

index bc6f8dd..9ef2983 100644
@@ -155,6 +155,9 @@ void spl_board_init(void)
 	/* reconfigure the PLLs */
 	cm_basic_init(&cm_default_cfg);
 
+	/* Enable bootrom to configure IOs. */
+	sysmgr_enable_warmrstcfgio();
+
 	/* configure the IOCSR / IO buffer settings */
 	if (scan_mgr_configure_iocsr())
 		hang();

index 11f7bad..8126e0d 100644
@@ -66,3 +66,12 @@ void sysmgr_pinmux_init(void)
 
 	populate_sysmgr_fpgaintf_module();
 }
+
+/*
+ * This bit allows the bootrom to configure the IOs after a warm reset.
+ */
+void sysmgr_enable_warmrstcfgio(void)
+{
+	setbits_le32(&sysmgr_regs->romcodegrp_ctrl,
+		     SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO);
+}

index 071ec4f..51d9815 100644
@@ -10,6 +10,7 @@
 #ifndef __ASSEMBLY__
 
 void sysmgr_pinmux_init(void);
+void sysmgr_enable_warmrstcfgio(void);
 
 /* declaration for handoff table type */
 extern unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM];

2.2.1

From: Dinh Nguyen <[email protected]>

Add a call to checkboard along with sdram intilialization and calibration.

---
v2: Add a fail message

---
 arch/arm/cpu/armv7/socfpga/spl.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

index 9ef2983..71021f0 100644
@@ -16,6 +16,7 @@
 #include <asm/arch/freeze_controller.h>
 #include <asm/arch/clock_manager.h>
 #include <asm/arch/scan_manager.h>
+#include <asm/arch/sdram.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 

@@ -175,4 +176,15 @@ void spl_board_init(void)
 
 	/* enable console uart printing */
 	preloader_console_init();
+
+	if (sdram_mmr_init_full(0xffffffff) != 0) {
+		puts("SDRAM init failed\n");
+		hang();
+	}
+	puts("SDRAM: Calibrating PHY\n");
+	/* SDRAM calibration */
+	if (sdram_calibration_full() == 0) {
+		puts("SDRAM calibration failed!\n");
+		hang();
+	}
 }

2.2.1

From: Dinh Nguyen <[email protected]>

---
v2: Add a debug print

---
 arch/arm/cpu/armv7/socfpga/spl.c | 4 ++++
 1 file changed, 4 insertions(+)

index 71021f0..ea4a1fb 100644
@@ -55,6 +55,7 @@ u32 spl_boot_device(void)
  */
 void spl_board_init(void)
 {
+	unsigned long sdram_size;
 #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
 	cm_config_t cm_default_cfg = {
 		/* main group */

@@ -187,4 +188,7 @@ void spl_board_init(void)
 		puts("SDRAM calibration failed!\n");
 		hang();
 	}
+
+	sdram_size = sdram_calculate_size();
+	debug("SDRAM: %ld MiB\n", (sdram_size >> 20));
 }

2.2.1

From: Dinh Nguyen <[email protected]>

For SoCFGPA, use the common ARMv7 lowlevel_init.

---
 arch/arm/cpu/armv7/Makefile                | 2 +-
 arch/arm/cpu/armv7/socfpga/lowlevel_init.S | 4 ----
 2 files changed, 1 insertion(+), 5 deletions(-)

index b228ed6..924bcf4 100644
@@ -12,7 +12,7 @@ obj-y	+= cache_v7.o
 obj-y	+= cpu.o
 obj-y	+= syslib.o
 
-ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI),)
+ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI)$(CONFIG_SOCFPGA),)
 ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y)
 obj-y	+= lowlevel_init.o
 endif

index afed773..723508c 100644
@@ -7,10 +7,6 @@
 #include <config.h>
 #include <version.h>
 
-/* Set up the platform, once the cpu has been initialized */
-.globl lowlevel_init
-lowlevel_init:
-
 	/* Remap */
 #ifdef CONFIG_SPL_BUILD
 	/*

2.2.1

From: Dinh Nguyen <[email protected]>

Clear OCRAM's ECC.

---
v2: remove redundant code that is already in arch_early_init_r

---
 arch/arm/cpu/armv7/socfpga/Makefile |  4 ++--
 arch/arm/cpu/armv7/socfpga/s_init.c | 37 +++++++++++++++++++++++++++++++++++++
 2 files changed, 39 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/socfpga/s_init.c

index 8b6e108..ee0af9b 100644
@@ -8,6 +8,6 @@
 #
 
 obj-y	:= lowlevel_init.o
-obj-y	+= misc.o timer.o reset_manager.o system_manager.o clock_manager.o \
-	   fpga_manager.o
+obj-y	+= s_init.o misc.o timer.o reset_manager.o system_manager.o \
+	   clock_manager.o fpga_manager.o
 obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o scan_manager.o

new file mode 100644
index 0000000..bb159c6
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2014 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <watchdog.h>
+#include <asm/io.h>
+#include <asm/spl.h>
+#include <asm/arch/system_manager.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * First C function to initialize the critical hardware early
+ */
+void s_init(void)
+{
+#ifdef CONFIG_SPL_BUILD
+	struct socfpga_system_manager *sysmgr_regs =
+		(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+	unsigned long reg;
+	/*
+	 * First C code to run. Clear fake OCRAM ECC first as SBE
+	 * and DBE might triggered during power on
+	 */
+	reg = readl(&sysmgr_regs->eccgrp_ocram);
+	if (reg & SYSMGR_ECC_OCRAM_SERR)
+		writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN,
+			&sysmgr_regs->eccgrp_ocram);
+	if (reg & SYSMGR_ECC_OCRAM_DERR)
+		writel(SYSMGR_ECC_OCRAM_DERR  | SYSMGR_ECC_OCRAM_EN,
+			&sysmgr_regs->eccgrp_ocram);
+#endif	/* CONFIG_SPL_BUILD */
+}

2.2.1

From: Dinh Nguyen <[email protected]>

Allocate a stack in the OCRAM for the SPL to use.

---
 arch/arm/cpu/armv7/socfpga/u-boot-spl.lds | 7 +++++++
 include/configs/socfpga_common.h          | 1 +
 2 files changed, 8 insertions(+)

index 730d154..7c7f59c 100644
@@ -44,4 +44,11 @@ SECTIONS
 		. = ALIGN(4);
 		__bss_end = .;
 	} >.sram
+
+	.stack :
+	{
+		. = . + CONFIG_SPL_STACK_SIZE;
+		. = ALIGN(8);
+		__stack_start = .;
+	} >.sram
 }

index d449a78..ed83cb8 100644
@@ -295,6 +295,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #define CONFIG_SYS_SPL_MALLOC_START	CONFIG_SYS_INIT_SP_ADDR
 #define CONFIG_SYS_SPL_MALLOC_SIZE	(5 * 1024)
 #define CONFIG_SPL_MAX_SIZE		(64 * 1024)
+#define CONFIG_SPL_STACK_SIZE		0x1000
 
 #define CHUNKSZ_CRC32			(1 * 1024)	/* FIXME: ewww */
 #define CONFIG_CRC32_VERIFY

2.2.1

Hi!

Setting CONFIG_SPL_STACK to point to SRAM end will do exactly the same thing. You might need to use generic u-boot-spl.lds for that though.

Best regards,
Marek Vasut

From: Dinh Nguyen <[email protected]>

---
 include/configs/socfpga_common.h | 5 +++++
 1 file changed, 5 insertions(+)

index ed83cb8..042c65f 100644
@@ -308,6 +308,11 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #define CONFIG_SPL_WATCHDOG_SUPPORT
 #define CONFIG_SPL_SERIAL_SUPPORT
 
+/*
+ * Stack setup
+ */
+#define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR
+
 #ifdef CONFIG_SPL_BUILD
 #undef CONFIG_PARTITIONS
 #endif

2.2.1

This patch would invalidate the previous 12/20 , no ?

Best regards,
Marek Vasut

From: Dinh Nguyen <[email protected]>

Add a stack in the SDRAM to be able to use SPL_FAT_LOAD in later stages of the SPL.

---
 arch/arm/cpu/armv7/socfpga/u-boot-spl.lds | 7 +++++++
 include/configs/socfpga_common.h          | 1 +
 2 files changed, 8 insertions(+)

index 7c7f59c..739f3f1 100644
@@ -51,4 +51,11 @@ SECTIONS
 		. = ALIGN(8);
 		__stack_start = .;
 	} >.sram
+
+	.sdram_stack :
+	{
+		__sdram_stack_end = .;
+		. = . + CONFIG_SPL_SDRAM_STACK_SIZE;
+		__sdram_stack_start = .;
+	} >.sdram
 }

index 042c65f..43f20c9 100644
@@ -312,6 +312,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
  * Stack setup
  */
 #define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SPL_SDRAM_STACK_SIZE	(128 * 1024)
 
 #ifdef CONFIG_SPL_BUILD
 #undef CONFIG_PARTITIONS

2.2.1

Were you able to find out whether this is really needed for FATLOAD in SPL please ? Is the FATload is demanding ?

Best regards,
Marek Vasut

From: Dinh Nguyen <[email protected]>

---
 include/configs/socfpga_common.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

index 43f20c9..31c8961 100644
@@ -293,7 +293,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #define CONFIG_SPL_RAM_DEVICE
 #define CONFIG_SPL_TEXT_BASE		CONFIG_SYS_INIT_RAM_ADDR
 #define CONFIG_SYS_SPL_MALLOC_START	CONFIG_SYS_INIT_SP_ADDR
-#define CONFIG_SYS_SPL_MALLOC_SIZE	(5 * 1024)
+#define CONFIG_SYS_SPL_MALLOC_SIZE	256
 #define CONFIG_SPL_MAX_SIZE		(64 * 1024)
 #define CONFIG_SPL_STACK_SIZE		0x1000
 

2.2.1

Why did you do this change please ?

Best regards,
Marek Vasut

Hi Marek,

Sorry that it's taken me a while to get back to you on this, but this is why I had to adjust the SPL_MALLOC_SIZE to 256:

#define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100)

#define CONFIG_SYS_INIT_SP_ADDR                                 \
        (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE -  \
        GENERATED_GBL_DATA_SIZE)

Because of the above define I only have 0x100 left for SPL_MALLOC_SIZE.

I think I should rework this patch to be like this:

@@ -41,7 +41,7 @@
 #define CONFIG_SYS_MEMTEST_END         PHYS_SDRAM_1_SIZE
 
 #define CONFIG_SYS_INIT_RAM_ADDR       0xFFFF0000
-#define CONFIG_SYS_INIT_RAM_SIZE       (0x10000 - 0x100)
+#define CONFIG_SYS_INIT_RAM_SIZE       (0x10000 -

CONFIG_SYS_SPL_MALLOC_SIZE)

Dinh

Hi Dinh,

No worries, I'm also quite busy myself :)

From: Dinh Nguyen <[email protected]>

---
 arch/arm/cpu/armv7/socfpga/u-boot-spl.lds | 7 +++++++
 include/configs/socfpga_common.h          | 1 +
 2 files changed, 8 insertions(+)

index 739f3f1..f87e951 100644
@@ -45,6 +45,13 @@ SECTIONS
 		__bss_end = .;
 	} >.sram
 
+	.malloc :
+	{
+		. = . + CONFIG_SPL_MALLOC_SIZE;
+		. = ALIGN(8);
+		__malloc_start = .;
+	} >.sram
+
 	.stack :
 	{
 		. = . + CONFIG_SPL_STACK_SIZE;

index 31c8961..5d1343a 100644
@@ -296,6 +296,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #define CONFIG_SYS_SPL_MALLOC_SIZE	256
 #define CONFIG_SPL_MAX_SIZE		(64 * 1024)
 #define CONFIG_SPL_STACK_SIZE		0x1000
+#define CONFIG_SPL_MALLOC_SIZE		(5 * 1024)
 
 #define CHUNKSZ_CRC32			(1 * 1024)	/* FIXME: ewww */
 #define CONFIG_CRC32_VERIFY

2.2.1

From: Dinh Nguyen <[email protected]>

---
 arch/arm/cpu/armv7/socfpga/spl.c | 8 ++++++++
 1 file changed, 8 insertions(+)

index ea4a1fb..31ac789 100644
@@ -191,4 +191,12 @@ void spl_board_init(void)
 
 	sdram_size = sdram_calculate_size();
 	debug("SDRAM: %ld MiB\n", (sdram_size >> 20));
+
+	/* Sanity check ensure correct SDRAM size specified */
+	puts("SDRAM: Ensuring specified SDRAM size is correct ...");
+	if (get_ram_size(0, sdram_size) != sdram_size) {
+		puts("failed\n");
+		hang();
+	}
+	puts("passed\n");
 }

2.2.1

Yeah, I think that's fine.

Dinh

Cool, thanks!

Best regards,
Marek Vasut

From: Dinh Nguyen <[email protected]>

Remap SDRAM to 0x0 in board_init_f().

---
 arch/arm/cpu/armv7/socfpga/spl.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

index 31ac789..21023c2 100644
@@ -6,6 +6,7 @@
 
 #include <common.h>
 #include <asm/io.h>
+#include <asm/pl310.h>
 #include <asm/u-boot.h>
 #include <asm/utils.h>
 #include <version.h>

@@ -20,6 +21,9 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static struct pl310_regs *const pl310 =
+	(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+
 #define MAIN_VCO_BASE (					\
 	(CONFIG_HPS_MAINPLLGRP_VCO_DENOM <<		\
 		CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) |	\

@@ -45,6 +49,16 @@ DECLARE_GLOBAL_DATA_PTR;
 		CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET)	\
 	)
 
+void board_init_f(ulong dummy)
+{
+	memset(__bss_start, 0, __bss_end - __bss_start);
+	gd = &gdata;
+
+	writel(0x1, &pl310->pl310_addr_filter_start);
+
+	board_init_r(NULL, 0);
+}
+
 u32 spl_boot_device(void)
 {
 	return BOOT_DEVICE_RAM;

2.2.1

Best regards,
Marek Vasut

From: Dinh Nguyen <[email protected]>

This sets the CPU clocks to 925MHz and DDR to 400MHz.

---
 board/altera/socfpga/pll_config.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

index f0f59a9..3992ff7 100644
@@ -12,13 +12,13 @@
 /* PLL configuration data */
 /* Main PLL */
 #define CONFIG_HPS_MAINPLLGRP_VCO_DENOM			(0)
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER			(63)
+#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER			(73)
 #define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT		(0)
 #define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT		(0)
 #define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT		(0)
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT		(3)
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT	(3)
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT	(12)
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT		(4)
+#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT	(0)
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT	(14)
 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK		(1)
 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK		(1)
 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK		(1)

2.2.1

Best regards,
Marek Vasut

From: Dinh Nguyen <[email protected]>

Since we are already mapping sdram 0x0 in board_init_f, we can remove it here.

---
 arch/arm/cpu/armv7/socfpga/misc.c | 3 ---
 1 file changed, 3 deletions(-)

index 7873c38..3cee6ff 100644
@@ -205,9 +205,6 @@ int arch_early_init_r(void)
 	/* Configure the L2 controller to make SDRAM start at 0 */
 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 	writel(0x2, &nic301_regs->remap);
-#else
-	writel(0x1, &nic301_regs->remap);	/* remap.mpuzero */
-	writel(0x1, &pl310->pl310_addr_filter_start);
 #endif
 
 	/* Add device descriptor to FPGA device table */

2.2.1

Best regards,
Marek Vasut