mtd: nand: omap_gpmc: Make ready/busy pins configurable
Subsystems (2)
PATCH v2 1/1 mtd: nand: omap_gpmc: Make ready/busy pins configurable
From: Michal Sojka <[email protected]>
Commit fb384c4720ca7496775d6578f184bf628db73456 introduced the use of WAIT0 pin for determining whether the NAND is ready or not. This only works if all NAND chips are connected to WAIT0. If some chips are connected to the other available pin WAIT1, nand_wait() does not really wait and prints a WARN_ON message.
This patch allows the board to provide configuration of which chip is connected to which WAITx signal. For example, one can define in include/configs/foo.h:
#define CONFIG_NAND_OMAP_GPMC_WSCFG 0,0,1,1
This would mean that chips using to CS0 and 1 are connected to WAIT0 and chips with CS2 and 3 are connected to WAIT1.
--- drivers/mtd/nand/omap_gpmc.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-)
drivers/mtd/nand/omap_gpmc.c +14 -2
@@ -30,13 +30,22 @@ static u8 bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2,static uint8_t cs_next;static __maybe_unused struct nand_ecclayout omap_ecclayout; +#if defined(CONFIG_NAND_OMAP_GPMC_WSCFG ) +static const int8_t wscfg[CONFIG_SYS_MAX_NAND_DEVICE ] = + {CONFIG_NAND_OMAP_GPMC_WSCFG }; +#else +/* wscfg is preset to zero since its a static variable */ +static const int8_t wscfg[CONFIG_SYS_MAX_NAND_DEVICE ]; +#endif +/* * Driver configurations */ struct omap_nand_info {struct bch_control *control;enum omap_ecc ecc_scheme; -int cs; +uint8_t cs; +uint8_t ws;/* wait status pin (0,1) */ };/* We are wasting a bit of memory but al least we are safe */
@@ -76,7 +85,9 @@ static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd,/* Check wait pin as dev ready indicator */ static int omap_dev_ready (struct mtd_info *mtd) { -return gpmc_cfg->status & (1 <<8 ); + registerstruct nand_chip *this = mtd->priv; +struct omap_nand_info *info = this->priv; +return gpmc_cfg->status & (1 << (8 + info->ws)); }/*
@@ -962,6 +973,7 @@ int board_nand_init(struct nand_chip *nand) nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd; omap_nand_info[cs].control =NULL ; omap_nand_info[cs].cs = cs; + omap_nand_info[cs].ws = wscfg[cs]; nand->priv = &omap_nand_info[cs]; nand->cmd_ctrl = omap_nand_hwcontrol; nand->options |=NAND_NO_PADDING |NAND_CACHEPRG ;
Signature · 1 line
2.1.4
PATCH v2 1/1 mtd: nand: omap_gpmc: Make ready/busy pins configurable
Quoted 14 lines · Michal Sojka
From: Michal Sojka <[email protected]>
Commit
fb384c4720ca7496775d6578f184bf628db73456introduced the use of WAIT0 pin for determining whether the NAND is ready or not. This only works if all NAND chips are connected to WAIT0. If some chips are connected to the other available pin WAIT1,nand_wait()does not really wait and prints aWARN_ONmessage.This patch allows the board to provide configuration of which chip is connected to which WAITx signal. For example, one can define in
include/configs/foo.h:#define CONFIG_NAND_OMAP_GPMC_WSCFG 0,0,1,1
Quoted 8 lines
This would mean that chips using to CS0 and 1 are connected to WAIT0 and chips with CS2 and 3 are connected to WAIT1.
Signed-off-by Michal Sojka <[email protected]>Acked-by Stefan Roese <[email protected]>Tested-by Michal Vok?? <[email protected]>Cc Tom Rini <[email protected]>
Applied to u-boot/master, thanks!
Signature · 8 lines
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