ARM: sun9i: Add support for PRCM on Allwinner A80 SoC

This patch adds support for the PRCM on the A80 SoC. There is little to no document for this at the moment. Only register offsets are available. However with some testing, the clock and reset controls seem to be the similar to the ones on the A31.

One thing that needs verifying is whether the apbs divider is the same as the A31 or the A23. The lowest divider is different between those 2 implementations.

Signed-off-by Chen-Yu Tsai <[email protected]>

---
 .../devicetree/bindings/mfd/sun6i-prcm.txt         |  3 +-
 drivers/mfd/sun6i-prcm.c                           | 58 ++++++++++++++++++++++
 2 files changed, 60 insertions(+), 1 deletion(-)

Documentation/devicetree/bindings/mfd/sun6i-prcm.txt +2 -1

index 03c5a551da55..c100abfcb2a4 100644
@@ -4,7 +4,8 @@ PRCM is an MFD device exposing several Power Management related devices
 (like clks and reset controllers).
 
 Required properties:
- - compatible: "allwinner,sun6i-a31-prcm" or "allwinner,sun8i-a23-prcm"
+ - compatible: "allwinner,sun6i-a31-prcm", "allwinner,sun8i-a23-prcm",
+	       "allwinner,sun9i-a80-prcm"
  - reg: The PRCM registers range
 
 The prcm node may contain several subdevices definitions:

drivers/mfd/sun6i-prcm.c +58 -0

index 191173166d65..d067c77fb512 100644
@@ -33,6 +33,22 @@ static const struct resource sun6i_a31_apb0_clk_res[] = {
 	},
 };
 
+static const struct resource sun9i_a80_cpus_clk_res[] = {
+	{
+		.start = 0x10,
+		.end = 0x13,
+		.flags = IORESOURCE_MEM,
+	},
+};
+
+static const struct resource sun9i_a80_apbs_clk_res[] = {
+	{
+		.start = 0x1c,
+		.end = 0x1f,
+		.flags = IORESOURCE_MEM,
+	},
+};
+
 static const struct resource sun6i_a31_apb0_gates_clk_res[] = {
 	{
 		.start = 0x28,

@@ -111,6 +127,39 @@ static const struct mfd_cell sun8i_a23_prcm_subdevs[] = {
 	},
 };
 
+static const struct mfd_cell sun9i_a80_prcm_subdevs[] = {
+	{
+		.name = "sun6i-a31-ar100-clk",
+		.of_compatible = "allwinner,sun6i-a31-ar100-clk",
+		.num_resources = ARRAY_SIZE(sun9i_a80_cpus_clk_res),
+		.resources = sun9i_a80_cpus_clk_res,
+	},
+	{
+		.name = "sun8i-a23-apb0-clk",
+		.of_compatible = "allwinner,sun8i-a23-apb0-clk",
+		.num_resources = ARRAY_SIZE(sun9i_a80_apbs_clk_res),
+		.resources = sun9i_a80_apbs_clk_res,
+	},
+	{
+		.name = "sun6i-a31-apb0-gates-clk",
+		.of_compatible = "allwinner,sun9i-a80-apbs-gates-clk",
+		.num_resources = ARRAY_SIZE(sun6i_a31_apb0_gates_clk_res),
+		.resources = sun6i_a31_apb0_gates_clk_res,
+	},
+	{
+		.name = "sun6i-a31-ir-clk",
+		.of_compatible = "allwinner,sun4i-a10-mod0-clk",
+		.num_resources = ARRAY_SIZE(sun6i_a31_ir_clk_res),
+		.resources = sun6i_a31_ir_clk_res,
+	},
+	{
+		.name = "sun6i-a31-apb0-clock-reset",
+		.of_compatible = "allwinner,sun6i-a31-clock-reset",
+		.num_resources = ARRAY_SIZE(sun6i_a31_apb0_rstc_res),
+		.resources = sun6i_a31_apb0_rstc_res,
+	},
+};
+
 static const struct prcm_data sun6i_a31_prcm_data = {
 	.nsubdevs = ARRAY_SIZE(sun6i_a31_prcm_subdevs),
 	.subdevs = sun6i_a31_prcm_subdevs,

@@ -121,6 +170,11 @@ static const struct prcm_data sun8i_a23_prcm_data = {
 	.subdevs = sun8i_a23_prcm_subdevs,
 };
 
+static const struct prcm_data sun9i_a80_prcm_data = {
+	.nsubdevs = ARRAY_SIZE(sun9i_a80_prcm_subdevs),
+	.subdevs = sun9i_a80_prcm_subdevs,
+};
+
 static const struct of_device_id sun6i_prcm_dt_ids[] = {
 	{
 		.compatible = "allwinner,sun6i-a31-prcm",

@@ -130,6 +184,10 @@ static const struct of_device_id sun6i_prcm_dt_ids[] = {
 		.compatible = "allwinner,sun8i-a23-prcm",
 		.data = &sun8i_a23_prcm_data,
 	},
+	{
+		.compatible = "allwinner,sun9i-a80-prcm",
+		.data = &sun9i_a80_prcm_data,
+	},
 	{ /* sentinel */ },
 };
 

Hi everyone,

Some time ago I sent out an RFC series, which was not merged due to lack of matching documentation for the SoC. A few weeks back I sent out a request for the documents again. I have not received a response. So I'm sending out the series now.

This series adds support for the Power Reset and Clock Management module on Allwinner's A80 SoC. The PRCM manages clocks and resets for the "special" block of peripherals, or the R/RTC block in earlier SoCs. These peripherals include a standby processor core, a timer block, a watchdog, pin controller, 1 wire interface, PS/2 interface, a UART, the RSB controller, a DMA controller, a consumer IR receiver block, 2 I2C controllers, and 2 I2S controllers. We do not have documents for all the peripherals. Support will be added where possible.

Patch 1 adds support for the apbs (apb0 in earlier SoCs) gates.

Patch 2 adds sun9i-a80 support to the PRCM mfd driver

Patch 3 adds the clock and reset nodes for the PRCM to the A80 DTSI.

To Allwinner people:
If you have any related documents or comments, please send them out.

Hi Chen-Yu,

Quoted 20 lines · Chen-Yu Tsai

Hi everyone,

Some time ago I sent out an RFC series, which was not merged due to lack of matching documentation for the SoC. A few weeks back I sent out a request for the documents again. I have not received a response. So I'm sending out the series now.

This series adds support for the Power Reset and Clock Management module on Allwinner's A80 SoC. The PRCM manages clocks and resets for the "special" block of peripherals, or the R/RTC block in earlier SoCs. These peripherals include a standby processor core, a timer block, a watchdog, pin controller, 1 wire interface, PS/2 interface, a UART, the RSB controller, a DMA controller, a consumer IR receiver block, 2 I2C controllers, and 2 I2S controllers. We do not have documents for all the peripherals. Support will be added where possible.

Patch 1 adds support for the apbs (apb0 in earlier SoCs) gates.

Quoted 3 lines

Patch 2 adds sun9i-a80 support to the PRCM mfd driver

Patch 3 adds the clock and reset nodes for the PRCM to the A80 DTSI.

These three patches look fine to me. Have you seen that the new bootloader code has some interesting infos about RSB and PRCM?

If so, does it match what you did so far?

Quoted 2 lines

To Allwinner people:
If you have any related documents or comments, please send them out.

Kevin, Shuge, your input would be greatly appreciated.

Thanks!
Maxime

--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

Dear All,

I have requested to release the document for the PRCM, but need my boss support. I will try my best to convince them, and provide the document ASAP. If any progress, I will update to you immediately.

Hi, Maxime,

We have add the PRCM module description to the A80 document.
You can download it from the github: https://github.com/allwinner-zh/documents

Hi Kevin,

Quoted 4 lines · kevin at allwinnertech.com

Hi, Maxime,

We have add the PRCM module description to the A80 document.
You can download it from the github: https://github.com/allwinner-zh/documents

Awesome, thanks a lot.

We'll look into it.