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ARM: l2c: enforce use of cache-level property

PATCH New Florian Fainelli 3 participants 5 messages Mar 3, 2015 – Mar 10, 2015 Arm (32-bit)

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Florian Fainelli

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#0 lore raw

PATCH 1/1 ARM: l2c: enforce use of cache-level property

Make sure that we can read the "cache-level" property from the L2 cache controller node, and ensure its value is 2.

Signed-off-by Florian Fainelli <[email protected]>

---
Russell, Linus,

You may have seen that patch earlier, it was part of my attempt to parse the 'cache-size' and 'cache-sets' properties, and ultimately Linus' series went it, and this patch was lost ast see.

Thanks!

 arch/arm/mm/cache-l2x0.c | 7 +++++++
 1 file changed, 7 insertions(+)
arch/arm/mm/cache-l2x0.c +7 -0
index c6c7696b8db9..8b933dc43e24 100644
@@ -1648,6 +1648,7 @@ int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
 	struct device_node *np;
 	struct resource res;
 	u32 cache_id, old_aux;
+	u32 cache_level = 2;
 
 	np = of_find_matching_node(NULL, l2x0_ids);
 	if (!np)

@@ -1680,6 +1681,12 @@ int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
 	if (!of_property_read_bool(np, "cache-unified"))
 		pr_err("L2C: device tree omits to specify unified cache\n");
 
+	if (of_property_read_u32(np, "cache-level", &cache_level))
+		pr_err("L2C: device tree omits to specify cache-level\n");
+
+	if (cache_level != 2)
+		pr_err("L2C: device tree specifies invalid cache level\n");
+
 	/* Read back current (default) hardware configuration */
 	if (data->save)
 		data->save(l2x0_base);
Signature · 1 line
2.1.0
#1 lore raw

PATCH 1/1 ARM: l2c: enforce use of cache-level property

Quoted 4 lines · Florian Fainelli

Make sure that we can read the "cache-level" property from the L2 cache controller node, and ensure its value is 2.

Signed-off-by Florian Fainelli <[email protected]>

(...)

arch/arm/mm/cache-l2x0.c int __init l2x0_of_init(u32 aux_val, u32 aux_mask) · line 1686

Quoted 3 lines
arch/arm/mm/cache-l2x0.c +3 -0
+       if (of_property_read_u32(np, "cache-level", &cache_level))
+               pr_err("L2C: device tree omits to specify cache-level\n");
+

Is that really an error? Does ePAPR specify that this must always be present or what?

arch/arm/mm/cache-l2x0.c int __init l2x0_of_init(u32 aux_val, u32 aux_mask) · line 1688

Quoted 2 lines
arch/arm/mm/cache-l2x0.c +2 -0
+       if (cache_level != 2)
+               pr_err("L2C: device tree specifies invalid cache level\n");

This is an error however.

Yours,
Linus Walleij

#2 lore raw

PATCH 1/1 ARM: l2c: enforce use of cache-level property

Quoted 7 lines · Linus Walleij
Quoted 4 lines · Florian Fainelli

Make sure that we can read the "cache-level" property from the L2 cache controller node, and ensure its value is 2.

Signed-off-by Florian Fainelli <[email protected]>
Quoted 7 lines

(...)

arch/arm/mm/cache-l2x0.c int __init l2x0_of_init(u32 aux_val, u32 aux_mask) · line 1686

Quoted 3 lines
arch/arm/mm/cache-l2x0.c +3 -0
+       if (of_property_read_u32(np, "cache-level", &cache_level))
+               pr_err("L2C: device tree omits to specify cache-level\n");
+

Is that really an error? Does ePAPR specify that this must always be present or what?

See table 3-9. It appears to be a required property.

Signature · 2 lines
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#3 lore raw

PATCH 1/1 ARM: l2c: enforce use of cache-level property

In reply to Florian Fainelli
Quoted 10 lines · Florian Fainelli

Make sure that we can read the "cache-level" property from the L2 cache controller node, and ensure its value is 2.

Signed-off-by Florian Fainelli <[email protected]>

---
Russell, Linus,

You may have seen that patch earlier, it was part of my attempt to parse the 'cache-size' and 'cache-sets' properties, and ultimately Linus' series went it, and this patch was lost ast see.

Can you put it in the patch system please, and I'll get around to it once at some point during/after I've finished catching up?

Thanks.

Signature · 2 lines
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according to speedtest.net.
author
#4 lore raw

PATCH 1/1 ARM: l2c: enforce use of cache-level property

2015-03-09 9:03 GMT-07:00 Russell King - ARM Linux <[email protected]>:

Quoted 8 lines · Florian Fainelli
Quoted 7 lines

Make sure that we can read the "cache-level" property from the L2 cache controller node, and ensure its value is 2.

Signed-off-by Florian Fainelli <[email protected]>

---
Russell, Linus,

Quoted 6 lines
Quoted 3 lines

You may have seen that patch earlier, it was part of my attempt to parse the 'cache-size' and 'cache-sets' properties, and ultimately Linus' series went it, and this patch was lost ast see.

Can you put it in the patch system please, and I'll get around to it once at some point during/after I've finished catching up?

Added as http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=8309/1
thanks!

Signature · 1 line
Florian