arm64: qcom: Add support for Qualcomm MSM8916 SoC
Subsystems (5)
PATCH v3 1/4 arm64: qcom: Add support for Qualcomm MSM8916 SoC
From: Abhimanyu Kapur <[email protected]>
Add support for Qualcomm MSM8916 SoC in arm64 Kconfig and defconfig. Enable MSM8916 clock, pin control, and MSM serial driver utilized by MSM8916 and Qualcomm SoCs in general.
---
v3:
* Dropped ARCH_REQUIRE_GPIOLIB, COMMON_CLK_QCOM, and SOC_BUS
* Updated defconfig related to dropping various Kconfig options
v2:
* Dropped CONFIG_ARCH_QCOM_MSM8916, just use CONFIG_ARCH_QCOM
* Updated defconfig related to dropping CONFIG_ARCH_QCOM_MSM8916
arch/arm64/Kconfig | 6 ++++++ arch/arm64/configs/defconfig | 6 ++++++ 2 files changed, 12 insertions(+)
arch/arm64/Kconfig +6 -0
@@ -177,6 +177,12 @@ config ARCH_MEDIATEK help Support for Mediatek MT65xx & MT81xx ARMv8 SoCs +config ARCH_QCOM + bool "Qualcomm Platforms" + select PINCTRL + help + This enables support for the ARMv8 based Qualcomm chipsets. + config ARCH_SEATTLE bool "AMD Seattle SoC Family" help
arch/arm64/configs/defconfig +6 -0
@@ -33,6 +33,7 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_IOSCHED_DEADLINE is not set CONFIG_ARCH_FSL_LS2085A=y CONFIG_ARCH_MEDIATEK=y +CONFIG_ARCH_QCOM=y CONFIG_ARCH_THUNDER=y CONFIG_ARCH_VEXPRESS=y CONFIG_ARCH_XGENE=y
@@ -93,11 +94,14 @@ CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_MT6577=y CONFIG_SERIAL_AMBA_PL011=y CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_MSM=y +CONFIG_SERIAL_MSM_CONSOLE=y CONFIG_SERIAL_OF_PLATFORM=y CONFIG_VIRTIO_CONSOLE=y # CONFIG_HW_RANDOM is not set CONFIG_SPI=y CONFIG_SPI_PL022=y +CONFIG_PINCTRL_MSM8916=y CONFIG_GPIO_PL061=y CONFIG_GPIO_XGENE=y # CONFIG_HWMON is not set
@@ -127,6 +131,8 @@ CONFIG_RTC_DRV_EFI=y CONFIG_RTC_DRV_XGENE=y CONFIG_VIRTIO_BALLOON=y CONFIG_VIRTIO_MMIO=y +CONFIG_COMMON_CLK_QCOM=y +CONFIG_MSM_GCC_8916=y # CONFIG_IOMMU_SUPPORT is not set CONFIG_PHY_XGENE=y CONFIG_EXT2_FS=y
Signature · 3 lines
Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH v3 2/4 arm64: dts: Add Qualcomm MSM8916 SoC and evaluation board dts
Add initial device tree support for Qualcomm MSM8916 SoC and MTP8916 evaluation board. At the current time we only boot up a single processor.
---
v3:
* Removed qcom,msm-id and qcom,board-id
* Added top level compat for "qcom,msm8916-mtp-smb1360"
v2:
* Updated to dropping CONFIG_ARCH_QCOM_MSM8916
* Updated to use qcom-ids.h
arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/qcom/Makefile | 5 + arch/arm64/boot/dts/qcom/msm8916-mtp.dts | 21 ++++ arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi | 24 ++++ arch/arm64/boot/dts/qcom/msm8916.dtsi | 184 ++++++++++++++++++++++++++++++ 5 files changed, 235 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/Makefile create mode 100644 arch/arm64/boot/dts/qcom/msm8916-mtp.dts create mode 100644 arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi create mode 100644 arch/arm64/boot/dts/qcom/msm8916.dtsi
arch/arm64/boot/dts/Makefile +1 -0
@@ -5,5 +5,6 @@ dts-dirs += cavium dts-dirs += exynos dts-dirs += freescale dts-dirs += mediatek +dts-dirs += qcom subdir-y := $(dts-dirs)
arch/arm64/boot/dts/qcom/Makefile new file +5 -0
@@ -0,0 +1,5 @@ +dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb + +always := $(dtb-y) +subdir-y := $(dts-dirs) +clean-files := *.dtb
arch/arm64/boot/dts/qcom/msm8916-mtp.dts new file +21 -0
@@ -0,0 +1,21 @@ +/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 and +* only version 2 as published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +/dts-v1/; + +#include "msm8916-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. MSM 8916 MTP"; + compatible = "qcom,msm8916-mtp", "qcom,msm8916-mtp-smb1360", + "qcom,msm8916", "qcom,mtp"; +};
arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi new file +24 -0
@@ -0,0 +1,24 @@ +/* Copyright (c) 2014-2014, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "msm8916.dtsi" + +/ { + soc { + serial at 78b0000 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_uart2_default>; + pinctrl-1 = <&blsp1_uart2_sleep>; + }; + }; +};
arch/arm64/boot/dts/qcom/msm8916.dtsi new file +184 -0
184 lines not on this page · raw message
Signature · 3 lines
Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Mark Rutland
reviewerRe: [PATCH v3 2/4] arm64: dts: Add Qualcomm MSM8916 SoC and evaluation board dts
Hi Kumar,
arch/arm64/boot/dts/qcom/msm8916-mtp.dts line 21
Quoted 5 lines
arch/arm64/boot/dts/qcom/msm8916-mtp.dts new file +5
-0+/ { + model = "Qualcomm Technologies, Inc. MSM 8916 MTP"; + compatible = "qcom,msm8916-mtp", "qcom,msm8916-mtp-smb1360", + "qcom,msm8916", "qcom,mtp"; +};
No /chosen/stdout-path?
Does your UART driver support earlycon?
[...]
Quoted 18 lines
arch/arm64/boot/dts/qcom/msm8916.dtsi new file +18
-0+ cpus { + #address-cells = <1>; + #size-cells = <0>; + + CPU0: cpu at 0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0>; + }; + + CPU1: cpu at 1 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x1>; + }; + + CPU2: cpu at 2 { + device_type = "cpu";
arch/arm64/boot/dts/qcom/msm8916.dtsi line 51
Quoted 10 lines
arch/arm64/boot/dts/qcom/msm8916.dtsi new file +10
-0+ compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x2>; + }; + + CPU3: cpu at 3 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x3>; + }; + };
The secondary CPUs need an enable-method. Are you using PSCI or spin-table?
Which exception level do the CPUs enter the kernel?
arch/arm64/boot/dts/qcom/msm8916.dtsi line 54
Quoted 2 lines
arch/arm64/boot/dts/qcom/msm8916.dtsi new file +2
-0+ timer { + compatible = "arm,armv7-timer";
This should be "arm,armv8-timer".
arch/arm64/boot/dts/qcom/msm8916.dtsi line 60
Quoted 6 lines
arch/arm64/boot/dts/qcom/msm8916.dtsi new file +6
-0+ interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + clock-frequency = <19200000>; + };
NAK. CNTFRQ should be programmed on all CPUs prior to entering the kernel, per the boot protocol. You should not need clock-frequency here.
[...]
arch/arm64/boot/dts/qcom/msm8916.dtsi line 119
Quoted 2 lines
arch/arm64/boot/dts/qcom/msm8916.dtsi new file +2
-0+ intc: interrupt-controller at b000000 { + compatible = "qcom,msm-qgic2";
This string isn't documented (but seems to be supported by the GIC driver).
How does this differ from other GIC implementations?
arch/arm64/boot/dts/qcom/msm8916.dtsi line 123
Quoted 4 lines
arch/arm64/boot/dts/qcom/msm8916.dtsi new file +4
-0+ interrupt-controller; + #interrupt-cells = <3>; + reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; + };
No GICH, GICV, maintenance interrupt?
Minor nit, but I'd prefer if the reg entries were on individual lines as happens in other dts.
Thanks,
Mark.
Re: [PATCH v3 2/4] arm64: dts: Add Qualcomm MSM8916 SoC and evaluation board dts
Quoted 9 lines · Mark Rutland
Hi Kumar,
arch/arm64/boot/dts/qcom/msm8916-mtp.dts line 21
Quoted 5 lines
arch/arm64/boot/dts/qcom/msm8916-mtp.dts new file +5
-0+/ { + model = "Qualcomm Technologies, Inc. MSM 8916 MTP"; + compatible = "qcom,msm8916-mtp", "qcom,msm8916-mtp-smb1360", + "qcom,msm8916", "qcom,mtp"; +};No /chosen/stdout-path?
Nope ;).
Quoted 2 lines
Does your UART driver support earlycon?
It does.
Quoted 26 lines
[...]
Quoted 23 lines
arch/arm64/boot/dts/qcom/msm8916.dtsi new file +23
-0+ cpus { + #address-cells = <1>; + #size-cells = <0>; + + CPU0: cpu at 0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0>; + }; + + CPU1: cpu at 1 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x1>; + }; + + CPU2: cpu at 2 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x2>; + }; + + CPU3: cpu at 3 {
Quoted 8 lines
arch/arm64/boot/dts/qcom/msm8916.dtsi line 51
Quoted 5 lines
arch/arm64/boot/dts/qcom/msm8916.dtsi new file +5
-0+ device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x3>; + }; + };The secondary CPUs need an enable-method. Are you using PSCI or spin-table?
This is on purpose. We aren?t using either PSCI or spin-table. Right now the dts is for booting on a single core. I can drop CPU1..CPU3 if that helps.
Quoted 6 lines
Which exception level do the CPUs enter the kernel?
arch/arm64/boot/dts/qcom/msm8916.dtsi line 54
Quoted 2 lines
arch/arm64/boot/dts/qcom/msm8916.dtsi new file +2
-0+ timer { + compatible = "arm,armv7-timer";This should be "arm,armv8-timer?.
will change
Quoted 10 lines
arch/arm64/boot/dts/qcom/msm8916.dtsi line 60
Quoted 7 lines
arch/arm64/boot/dts/qcom/msm8916.dtsi new file +6
-0+ interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + clock-frequency = <19200000>; + };NAK. CNTFRQ should be programmed on all CPUs prior to entering the kernel, per the boot protocol. You should not need clock-frequency here.
Will drop clock-frequency.
Quoted 7 lines
[...]
arch/arm64/boot/dts/qcom/msm8916.dtsi line 119
Quoted 2 lines
arch/arm64/boot/dts/qcom/msm8916.dtsi new file +2
-0+ intc: interrupt-controller at b000000 { + compatible = "qcom,msm-qgic2";This string isn't documented (but seems to be supported by the GIC driver).
There?s a patch posted to add ?qcom,msm-qgic2? to the binding doc.
Quoted 1 line
How does this differ from other GIC implementations?
Not sure the exact details, just that its qcom?s on implementation of the GIC spec.
Quoted 7 lines
arch/arm64/boot/dts/qcom/msm8916.dtsi line 123
Quoted 5 lines
arch/arm64/boot/dts/qcom/msm8916.dtsi new file +4
-0+ interrupt-controller; + #interrupt-cells = <3>; + reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; + };No GICH, GICV, maintenance interrupt?
Nope.
Quoted 6 lines
Minor nit, but I'd prefer if the reg entries were on individual lines as happens in other dts.
Thanks,
Mark.
Signature · 3 lines
Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Mark Rutland
reviewerRe: [PATCH v3 2/4] arm64: dts: Add Qualcomm MSM8916 SoC and evaluation board dts
Quoted 32 lines
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arch/arm64/boot/dts/qcom/msm8916.dtsi new file +23
-0+ cpus { + #address-cells = <1>; + #size-cells = <0>; + + CPU0: cpu at 0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0>; + }; + + CPU1: cpu at 1 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x1>; + }; + + CPU2: cpu at 2 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x2>; + }; + + CPU3: cpu at 3 {Quoted 8 lines
arch/arm64/boot/dts/qcom/msm8916.dtsi line 51
Quoted 5 lines
arch/arm64/boot/dts/qcom/msm8916.dtsi new file +5
-0+ device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x3>; + }; + };The secondary CPUs need an enable-method. Are you using PSCI or spin-table?
Quoted 3 lines
This is on purpose. We aren?t using either PSCI or spin-table. Right now the dts is for booting on a single core. I can drop CPU1..CPU3 if that helps.
We won't poke the CPUs without an enable-method, so personally I'm not too worried either way about having the CPUs listed.
Which of spin-table/psci are you planning on using for SMP support, and when would that be likely to appear?
Which exception level do CPUs enter the kernel? Even without a virt-capable GIC booting at EL2 is less work for the FW and gives the kernel a better chance of fixing things up (e.g. CNTVOFF).
Thanks,
Mark.
Re: [PATCH v3 2/4] arm64: dts: Add Qualcomm MSM8916 SoC and evaluation board dts
Quoted 32 lines · Mark Rutland
Quoted 32 lines
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Quoted 18 lines
arch/arm64/boot/dts/qcom/msm8916.dtsi new file +18
-0+ cpus { + #address-cells = <1>; + #size-cells = <0>; + + CPU0: cpu at 0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0>; + }; + + CPU1: cpu at 1 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x1>; + }; + + CPU2: cpu at 2 { + device_type = "cpu";arch/arm64/boot/dts/qcom/msm8916.dtsi line 51
Quoted 10 lines
arch/arm64/boot/dts/qcom/msm8916.dtsi new file +10
-0+ compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x2>; + }; + + CPU3: cpu at 3 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x3>; + }; + };The secondary CPUs need an enable-method. Are you using PSCI or spin-table?
Quoted 6 lines
Quoted 3 lines
This is on purpose. We aren?t using either PSCI or spin-table. Right now the dts is for booting on a single core. I can drop CPU1..CPU3 if that helps.
We won't poke the CPUs without an enable-method, so personally I'm not too worried either way about having the CPUs listed.
That was my thinking, so left them in.
Quoted 2 lines
Which of spin-table/psci are you planning on using for SMP support, and when would that be likely to appear?
We have a qcom specific SMP enablement method for this device. This was one of our first devices so it utilized as much from arm 32-bit as possible.
Quoted 3 lines
Which exception level do CPUs enter the kernel? Even without a virt-capable GIC booting at EL2 is less work for the FW and gives the kernel a better chance of fixing things up (e.g. CNTVOFF).
I think the enter in EL1.
- k
Signature · 3 lines
Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Mark Rutland
reviewerRe: [PATCH v3 2/4] arm64: dts: Add Qualcomm MSM8916 SoC and evaluation board dts
Quoted 6 lines
Quoted 2 lines
Which of spin-table/psci are you planning on using for SMP support, and when would that be likely to appear?
We have a qcom specific SMP enablement method for this device. This was one of our first devices so it utilized as much from arm 32-bit as possible.
Implementation specific enable methods are something we really don't want to see for arm64. If PSCI is out of the question then a spin-table shim in your bootloader shouldn't be too hard to implement.
Quoted 5 lines
Quoted 3 lines
Which exception level do CPUs enter the kernel? Even without a virt-capable GIC booting at EL2 is less work for the FW and gives the kernel a better chance of fixing things up (e.g. CNTVOFF).
I think the enter in EL1.
That's unfortunate, but so long as they are consistent, it's not the end of the world.
Mark.
Catalin Marinas
maintainerRe: [PATCH v3 2/4] arm64: dts: Add Qualcomm MSM8916 SoC and evaluation board dts
Quoted 9 lines · Mark Rutland
Quoted 6 lines
Quoted 2 lines
Which of spin-table/psci are you planning on using for SMP support, and when would that be likely to appear?
We have a qcom specific SMP enablement method for this device. This was one of our first devices so it utilized as much from arm 32-bit as possible.
Implementation specific enable methods are something we really don't want to see for arm64.
I fully agree (and we've been stating this for over two years).
Quoted 2 lines
If PSCI is out of the question then a spin-table shim in your bootloader shouldn't be too hard to implement.
And I guess only WFI cpuidle supported in Linux.
Signature · 1 line
Catalin
PATCH v3 3/4 devicetree: bindings: Document qcom,msm-id and qcom,board-id
In reply to Kumar GalaThe top level qcom,msm-id and qcom,board-id are utilized by bootloaders on Qualcomm MSM platforms to determine which device tree should be utilized and passed to the kernel.
--- Documentation/devicetree/bindings/arm/msm/ids.txt | 65 +++++++++++++++++++++++ include/dt-bindings/arm/qcom-ids.h | 33 ++++++++++++ 2 files changed, 98 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/msm/ids.txt create mode 100644 include/dt-bindings/arm/qcom-ids.h
Documentation/devicetree/bindings/arm/msm/ids.txt new file +65 -0
@@ -0,0 +1,65 @@ +* MSM-ID + +The qcom,msm-id entry specifies the MSM chipset and hardware revision. It can +optionally be an array of these to indicate multiple hardware that use the same +device tree. It is expected that the bootloader will use this information at +boot-up to decide which device tree to use when given multiple device trees, +some of which may not be compatible with the actual hardware. It is the +bootloader's responsibility to pass the correct device tree to the kernel. + +PROPERTIES + +- qcom,msm-id: + Usage: required + Value type: <prop-encoded-array> (<chipset_id, rev_id> [, <c2, r2> ..]) + Definition: + The "chipset_id" consists of three fields as below: + + bits 0-15 = The unique MSM chipset id. + bits 16-31 = Reserved. Should be 0 + + chipset_id is an exact match value + + The "rev_id" is a chipset specific 32-bit id that represents + the version of the chipset. + + The rev_id is a best match id. The bootloader will look for + the closest possible patch. + +* BOARD-ID + +The qcom,board-id entry specifies the board type and revision information. It +can optionally be an array of these to indicate multiple boards that use the +same device tree. It is expected that the bootloader will use this information +at boot-up to decide which device tree to use when given multiple device trees, +some of which may not be compatible with the actual hardware. It is the +bootloader's responsibility to pass the correct device tree to the kernel. + +PROPERTIES + +- qcom,board-id: + Usage: required + Value type: <prop-encoded-array> (<board_id, subtype_id> [, <b2, s2> ..]) + Definition: + The "board_id" consists of three fields as below: + + bits 31-24 = Unusued. + bits 23-16 = Platform Version Major + bits 15-8 = Platfrom Version Minor + bits 7-0 = Platform Type + + Platform Type field is an exact match value. The Platform + Major/Minor field is a best match. The bootloader will look + for the closest possible match. + + The "subtype_id" is unique to a Platform Type/Chipset ID. For + a given Platform Type, there will typically only be a single + board and the subtype_id will be 0. However in some cases board + variants may need to be distinquished by different subtype_id + values. + + subtype_id is an exact match value. + +EXAMPLE: + qcom,board-id = <15 2>; + qcom,msm-id = <0x1007e 0>;
include/dt-bindings/arm/qcom-ids.h new file +33 -0
@@ -0,0 +1,33 @@ +/* Copyright (c) 2015, The Linux Foundation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 and +* only version 2 as published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ +#ifndef __DT_BINDINGS_QCOM_IDS_H +#define __DT_BINDINGS_QCOM_IDS_H + +/* qcom,msm-id */ +#define QCOM_ID_MSM8916 206 +#define QCOM_ID_APQ8016 247 +#define QCOM_ID_MSM8216 248 +#define QCOM_ID_MSM8116 249 +#define QCOM_ID_MSM8616 250 + +/* qcom,board-id */ +#define QCOM_BRD_ID (a, major, minor) \ + (((major & 0xff) << 16) | ((minor & 0xff) << 8) | QCOM_BRD_ID_##a) + +#define QCOM_BRD_ID_MTP 8 +#define QCOM_BRD_ID_DRAGONBRD 10 +#define QCOM_BRD_ID_SBC 24 + +#define QCOM_BRD_SUBTYPE_DEFAULT 0 +#define QCOM_BRD_SUBTYPE_MTP8916_SMB1360 1 + +#endif
Signature · 3 lines
Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH v3 4/4 arm64: dts: Add Qualcomm MSM8916 & MTP8916 ids
In reply to Kumar GalaAdd qcom,msm-id and qcom,board-id to allow bootloader to identify which device tree to boot on the MTP8916 boards.
--- arch/arm64/boot/dts/qcom/msm8916-mtp.dts | 3 +++ arch/arm64/boot/dts/qcom/msm8916.dtsi | 5 +++++ 2 files changed, 8 insertions(+)
arch/arm64/boot/dts/qcom/msm8916-mtp.dts +3 -0
@@ -12,10 +12,13 @@ /dts-v1/; +#include <dt-bindings/arm/qcom-ids.h> #include "msm8916-mtp.dtsi" / { model = "Qualcomm Technologies, Inc. MSM 8916 MTP"; compatible = "qcom,msm8916-mtp", "qcom,msm8916-mtp-smb1360", "qcom,msm8916", "qcom,mtp"; + qcom,board-id = <QCOM_BRD_ID(MTP, 1, 0) QCOM_BRD_SUBTYPE_DEFAULT>, + <QCOM_BRD_ID(MTP, 1, 0) QCOM_BRD_SUBTYPE_MTP8916_SMB1360>; };
arch/arm64/boot/dts/qcom/msm8916.dtsi +5 -0
@@ -14,10 +14,15 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/qcom,gcc-msm8916.h> #include <dt-bindings/reset/qcom,gcc-msm8916.h> +#include <dt-bindings/arm/qcom-ids.h> / { model = "Qualcomm Technologies, Inc. MSM8916"; compatible = "qcom,msm8916"; + qcom,msm-id = <QCOM_ID_MSM8916 0>, + <QCOM_ID_MSM8216 0>, + <QCOM_ID_MSM8116 0>, + <QCOM_ID_MSM8616 0>; interrupt-parent = <&intc>;
Signature · 3 lines
Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project