ZTE platform basic support
Subsystems (5)
cover ZTE platform basic support
This patch serial add basic support to ZTE ZX296702 platform.
Jun Nie (10):
ARM: zx: add basic support of ZTE ZX296702
ARM: zx: add low level debug support
MAINTAINERS: add entry for ZTE ARM architecture
ARM: zx: add initial L2CC initialization
ARM: zx: bring up the secondary core
ARM: zx: add cpu hotplug support dt/binding: Document ZTE zx296702 devicetree
ARM: dts: zx: add an initial dts for zx296702
ARM: zx: Add basic defconfig support to ZX296702
clk: zx: add zx296702 clock support
Documentation/devicetree/bindings/arm/zte.txt | 9 + .../devicetree/bindings/clock/zx296702-clk.txt | 35 ++ .../devicetree/bindings/vendor-prefixes.txt | 1 + MAINTAINERS | 10 + arch/arm/Kconfig | 2 + arch/arm/Kconfig.debug | 12 + arch/arm/Makefile | 1 + arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/zx296702-ad1.dts | 43 ++ arch/arm/boot/dts/zx296702.dtsi | 127 +++++ arch/arm/configs/zx_defconfig | 129 +++++ arch/arm/include/debug/zx.S | 35 ++ arch/arm/mach-zx/Kconfig | 21 + arch/arm/mach-zx/Makefile | 3 + arch/arm/mach-zx/core.h | 18 + arch/arm/mach-zx/headsmp.S | 38 ++ arch/arm/mach-zx/hotplug.c | 108 ++++ arch/arm/mach-zx/platsmp.c | 150 +++++ arch/arm/mach-zx/zx296702.c | 65 +++ drivers/clk/Makefile | 1 + drivers/clk/zte/Makefile | 2 + drivers/clk/zte/clk-pll.c | 211 +++++++ drivers/clk/zte/clk-zx296702.c | 611 +++++++++++++++++++++ drivers/clk/zte/clk.h | 30 + include/dt-bindings/clock/zx296702-clock.h | 158 ++++++ 25 files changed, 1821 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/zte.txt create mode 100644 Documentation/devicetree/bindings/clock/zx296702-clk.txt create mode 100644 arch/arm/boot/dts/zx296702-ad1.dts create mode 100644 arch/arm/boot/dts/zx296702.dtsi create mode 100644 arch/arm/configs/zx_defconfig create mode 100644 arch/arm/include/debug/zx.S create mode 100644 arch/arm/mach-zx/Kconfig create mode 100644 arch/arm/mach-zx/Makefile create mode 100644 arch/arm/mach-zx/core.h create mode 100644 arch/arm/mach-zx/headsmp.S create mode 100644 arch/arm/mach-zx/hotplug.c create mode 100644 arch/arm/mach-zx/platsmp.c create mode 100644 arch/arm/mach-zx/zx296702.c create mode 100644 drivers/clk/zte/Makefile create mode 100644 drivers/clk/zte/clk-pll.c create mode 100644 drivers/clk/zte/clk-zx296702.c create mode 100644 drivers/clk/zte/clk.h create mode 100644 include/dt-bindings/clock/zx296702-clock.h
Signature · 1 line
1.9.1
PATCH 1/10 ARM: zx: add basic support of ZTE ZX296702
Add basic code for ZTE ZX296702 platform.
--- arch/arm/Kconfig | 2 ++ arch/arm/Makefile | 1 + arch/arm/mach-zx/Kconfig | 21 +++++++++++++++++++++ arch/arm/mach-zx/Makefile | 1 + arch/arm/mach-zx/zx296702.c | 20 ++++++++++++++++++++ 5 files changed, 45 insertions(+) create mode 100644 arch/arm/mach-zx/Kconfig create mode 100644 arch/arm/mach-zx/Makefile create mode 100644 arch/arm/mach-zx/zx296702.c
arch/arm/Kconfig +2 -0
@@ -967,6 +967,8 @@ source "arch/arm/mach-vt8500/Kconfig" source "arch/arm/mach-w90x900/Kconfig" +source "arch/arm/mach-zx/Kconfig" + source "arch/arm/mach-zynq/Kconfig" # Definitions to make life easier
arch/arm/Makefile +1 -0
@@ -204,6 +204,7 @@ machine-$(CONFIG_ARCH_VERSATILE) += versatile machine-$(CONFIG_ARCH_VEXPRESS) += vexpress machine-$(CONFIG_ARCH_VT8500) += vt8500 machine-$(CONFIG_ARCH_W90X900) += w90x900 +machine-$(CONFIG_ARCH_ZX) += zx machine-$(CONFIG_ARCH_ZYNQ) += zynq machine-$(CONFIG_PLAT_SPEAR) += spear
arch/arm/mach-zx/Kconfig new file +21 -0
@@ -0,0 +1,21 @@ +config ARCH_ZX + bool "ZTE ZX family" if ARCH_MULTI_V7 + help + Support for ZTE ZX-based family of processors. TV + set-top-box processor is supported. More will be + added soon. + +menu "ZTE ZX options" + depends on ARCH_ZX + +config SOC_ZX296702 + bool "Enable support for ZX296702 SoC" + select ARM_GIC + select ARM_GLOBAL_TIMER + select HAVE_ARM_SCU if SMP + select HAVE_ARM_TWD if SMP + select MIGHT_HAVE_CACHE_L2X0 + help + Support for ZTE ZX296702 SoC which is a dual core CortexA9MP + +endmenu
arch/arm/mach-zx/Makefile new file +1 -0
@@ -0,0 +1 @@ +obj-$(CONFIG_SOC_ZX296702) += zx296702.o
arch/arm/mach-zx/zx296702.c new file +20 -0
@@ -0,0 +1,20 @@ +/* +* Copyright 2014 Linaro Ltd. +* Copyright (C) 2014 ZTE Corporation. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +*/ + +#include <asm/mach/arch.h> +#include <asm/mach/map.h> + +static const char *zx296702_dt_compat[]__initconst = { +"zte,zx296702" , +NULL , +}; + +DT_MACHINE_START (ZX ,"ZTE ZX296702 (Device Tree)" ) + .dt_compat = zx296702_dt_compat, +MACHINE_END
Signature · 1 line
1.9.1
Arnd Bergmann
maintainerPATCH 1/10 ARM: zx: add basic support of ZTE ZX296702
arch/arm/mach-zx/Kconfig line 9
Quoted 10 lines · On Saturday 14 March 2015 19:49:36 Jun Nie wrote:
arch/arm/mach-zx/Kconfig new file +9
-0@@ -0,0 +1,21 @@ +config ARCH_ZX + bool "ZTE ZX family" if ARCH_MULTI_V7 + help + Support for ZTE ZX-based family of processors. TV + set-top-box processor is supported. More will be + added soon. + +menu "ZTE ZX options" + depends on ARCH_ZX
Better use a "menuconfig" statement here.
arch/arm/mach-zx/Kconfig line 21
Quoted 11 lines
arch/arm/mach-zx/Kconfig new file +11
-0+config SOC_ZX296702 + bool "Enable support for ZX296702 SoC" + select ARM_GIC + select ARM_GLOBAL_TIMER + select HAVE_ARM_SCU if SMP + select HAVE_ARM_TWD if SMP + select MIGHT_HAVE_CACHE_L2X0 + help + Support for ZTE ZX296702 SoC which is a dual core CortexA9MP + +endmenu
MIGHT_HAVE_CACHE_L2X0 is implied by ARCH_MULTI_V7, so you can drop that here.
Arnd
PATCH 2/10 ARM: zx: add low level debug support
In reply to Jun NieUse the UART0 peripheral for low level debug. Only the UART port 0 is currently supported.
--- arch/arm/Kconfig.debug | 12 ++++++++++++ arch/arm/include/debug/zx.S | 35 +++++++++++++++++++++++++++++++++++ 2 files changed, 47 insertions(+) create mode 100644 arch/arm/include/debug/zx.S
arch/arm/Kconfig.debug +12 -0
@@ -1169,6 +1169,17 @@ choice For more details about semihosting, please see chapter 8 of DUI0203I_rvct_developer_guide.pdf from ARM Ltd. + config DEBUG_ZTE_ZX + bool "Use ZTE ZX UART" + depends on ARCH_ZX + help + Say Y here if you are enabling ZTE ZX296702 SOC and need + debug uart support. + + This option is preferred over the platform specific + options; the platform specific options are deprecated + and will be soon removed. + config DEBUG_LL_UART_8250 bool "Kernel low-level debugging via 8250 UART" help
@@ -1315,6 +1326,7 @@ config DEBUG_LL_INCLUDE default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT default "debug/vf.S" if DEBUG_VF_UART default "debug/vt8500.S" if DEBUG_VT8500_UART0 + default "debug/zx.S" if DEBUG_ZTE_ZX default "debug/zynq.S" if DEBUG_ZYNQ_UART0 || DEBUG_ZYNQ_UART1 default "debug/bcm63xx.S" if DEBUG_UART_BCM63XX default "debug/digicolor.S" if DEBUG_DIGICOLOR_UA0
arch/arm/include/debug/zx.S new file +35 -0
@@ -0,0 +1,35 @@ +/* + * Debugging macro include header + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#define UART01x_DR 0x04 /* Data read or write */ +#define UART01x_FR 0x14 /* Flag register (Read only) */ + +#define UART01x_FR_TXFF 0x020 + + +#define UART0_PADDR 0x09405000 +#define UART0_VADDR 0xfc705000 + + .macro addruart, rp, rv, tmp + ldr \rp, =UART0_PADDR @ physical + ldr \rv, =UART0_VADDR @ virtual + .endm + + .macro senduart,rd,rx + strb \rd, [\rx, #UART01x_DR] + .endm + + .macro waituart,rd,rx + .endm + + .macro busyuart,rd,rx +1001: ldr \rd, [\rx, #UART01x_FR] + tst \rd, #UART01x_FR_TXFF + bne 1001b + .endm
Signature · 1 line
1.9.1
PATCH 2/10 ARM: zx: add low level debug support
Quoted 53 lines · Jun Nie
Use the UART0 peripheral for low level debug. Only the UART port 0 is currently supported.
Signed-off-by Jun Nie <[email protected]>--- arch/arm/Kconfig.debug | 12 ++++++++++++ arch/arm/include/debug/zx.S | 35 +++++++++++++++++++++++++++++++++++ 2 files changed, 47 insertions(+) create mode 100644 arch/arm/include/debug/zx.Sarch/arm/Kconfig.debug +12
-0@@ -1169,6 +1169,17 @@ choice For more details about semihosting, please see chapter 8 of DUI0203I_rvct_developer_guide.pdf from ARM Ltd. + config DEBUG_ZTE_ZX + bool "Use ZTE ZX UART" + depends on ARCH_ZX + help + Say Y here if you are enabling ZTE ZX296702 SOC and need + debug uart support. + + This option is preferred over the platform specific + options; the platform specific options are deprecated + and will be soon removed. + config DEBUG_LL_UART_8250 bool "Kernel low-level debugging via 8250 UART" help@@ -1315,6 +1326,7 @@ config DEBUG_LL_INCLUDE default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT default "debug/vf.S" if DEBUG_VF_UART default "debug/vt8500.S" if DEBUG_VT8500_UART0 + default "debug/zx.S" if DEBUG_ZTE_ZX default "debug/zynq.S" if DEBUG_ZYNQ_UART0 || DEBUG_ZYNQ_UART1 default "debug/bcm63xx.S" if DEBUG_UART_BCM63XX default "debug/digicolor.S" if DEBUG_DIGICOLOR_UA0arch/arm/include/debug/zx.S new file +7
-0@@ -0,0 +1,35 @@ +/* + * Debugging macro include header + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + *
arch/arm/include/debug/zx.S line 17
Quoted 10 lines
arch/arm/include/debug/zx.S new file +10
-0+ */ + +#define UART01x_DR 0x04 /* Data read or write */ +#define UART01x_FR 0x14 /* Flag register (Read only) */ + +#define UART01x_FR_TXFF 0x020 + + +#define UART0_PADDR 0x09405000 +#define UART0_VADDR 0xfc705000
Why don't you use CONFIG_DEBUG_UART_VIRT and CONFIG_DEBUG_UART_PHYS?
Quoted 19 lines
arch/arm/include/debug/zx.S new file +18
-0+ + .macro addruart, rp, rv, tmp + ldr \rp, =UART0_PADDR @ physical + ldr \rv, =UART0_VADDR @ virtual + .endm + + .macro senduart,rd,rx + strb \rd, [\rx, #UART01x_DR] + .endm + + .macro waituart,rd,rx + .endm + + .macro busyuart,rd,rx +1001: ldr \rd, [\rx, #UART01x_FR] + tst \rd, #UART01x_FR_TXFF + bne 1001b + .endm
PATCH 2/10 ARM: zx: add low level debug support
In reply to Jun NieQuoted 2 lines · Jun Nie
Use the UART0 peripheral for low level debug. Only the UART port 0 is currently supported.
None of this code is necessary - in fact, you don't have to add one line of assembly code what so ever.
We have generic PL011 debug support. Please use that, you only need to ensure that the phys and virtual addresses are properly configured in arch/arm/Kconfig.debug and that the appropriate symbol is selected.
Thanks.
Signature · 2 lines
FTTC broadband for 0.8mile line: currently at 10.5Mbps down 400kbps up according to speedtest.net.
PATCH 2/10 ARM: zx: add low level debug support
Quoted 10 lines · Russell King - ARM Linux
Quoted 2 lines · Jun Nie
Use the UART0 peripheral for low level debug. Only the UART port 0 is currently supported.
None of this code is necessary - in fact, you don't have to add one line of assembly code what so ever.
We have generic PL011 debug support. Please use that, you only need to ensure that the phys and virtual addresses are properly configured in
arch/arm/Kconfig.debugand that the appropriate symbol is selected.
For some reason we never understood, ZTE designers chose to use a different offset on Data and Flag register, which make it difficult to reuse pl01x.S.
/* Data read or written from the interface. */
#define UART01x_DR 0x00
#define ZX_UART01x_DR 0x04
/* Flag register (Read only). */
#define ZX_UART01x_FR 0x14
#define UART01x_FR 0x18
We chose to duplicate the file to avoid churning generic pl01x.S. Would something like below be acceptable? Or any better idea?
arch/arm/include/debug/pl01x.S +7 -0
@@ -12,6 +12,13 @@ */ #include <linux/amba/serial.h> +#ifdef CONFIG_ARCH_ZX +#undef UART01x_DR +#undef UART01x_FR +#define UART01x_DR 0x04 +#define UART01x_FR 0x14 +#endif + #ifdef CONFIG_DEBUG_UART_PHYS .macro addruart, rp, rv, tmp ldr \rp, =CONFIG_DEBUG_UART_PHYS
Shawn
Arnd Bergmann
maintainerPATCH 2/10 ARM: zx: add low level debug support
Quoted 11 lines · On Monday 16 March 2015 10:37:42 Shawn Guo wrote:
We chose to duplicate the file to avoid churning generic
pl01x.S. Would something like below be acceptable? Or any better idea?arch/arm/include/debug/pl01x.S +0
-0@@ -12,6 +12,13 @@ */ #include <linux/amba/serial.h>
arch/arm/include/debug/pl01x.S line 23
Quoted 10 lines
arch/arm/include/debug/pl01x.S +7
-0+#ifdef CONFIG_ARCH_ZX +#undef UART01x_DR +#undef UART01x_FR +#define UART01x_DR 0x04 +#define UART01x_FR 0x14 +#endif + #ifdef CONFIG_DEBUG_UART_PHYS
This is almost right, but breaks a corner case where you want to debug the boot on a platform other than ZX, but in a kernel that also has ARCH_ZX enabled. I think the best way to solve this is to have CONFIG_DEBUG_ZTE_ZX select CONFIG_DEBUG_UART_PL01X, and then use #ifdef CONFIG_DEBUG_ZTE_ZX above rather than CONFIG_ARCH_ZX.
Arnd
PATCH 3/10 MAINTAINERS: add entry for ZTE ARM architecture
In reply to Jun NieAdd entry for ZTE ARM architecture
--- MAINTAINERS | 10 ++++++++++ 1 file changed, 10 insertions(+)
MAINTAINERS +10 -0
@@ -1590,6 +1590,16 @@ S: Maintained F: arch/arm/mach-pxa/z2.c F: arch/arm/mach-pxa/include/mach/z2.h +ARM/ZTE ARCHITECTURE +M: Jun Nie <[email protected]> +L: linux-arm-kernel at lists.infradead.org (moderated for non-subscribers) +S: Maintained +F: arch/arm/mach-zx/ +F: arch/arm/include/debug/zx.S +F: drivers/clk/zte/ +F: Documentation/devicetree/bindings/arm/zte.txt +F: Documentation/devicetree/bindings/clock/zx296702-clk.txt + ARM/ZYNQ ARCHITECTURE M: Michal Simek <[email protected]> R: S?ren Brinkmann <[email protected]>
Signature · 1 line
1.9.1
PATCH 4/10 ARM: zx: add initial L2CC initialization
In reply to Jun NieAdd an initial L2 Cache controller initialization.
--- arch/arm/mach-zx/zx296702.c | 44 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+)
arch/arm/mach-zx/zx296702.c +44 -0
@@ -7,9 +7,52 @@* published by the Free Software Foundation. */ +#include <linux/init.h> +#include <linux/of_address.h> +#include <linux/of_platform.h> + +#include <asm/hardware/cache-l2x0.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> +#include "core.h" + +static void __init zx_l2x0_init (void ) +{ +void __iomem *base; +struct device_node *np; +unsigned int val; + + np =of_find_compatible_node (NULL ,NULL ,"arm,pl310-cache" ); +if (!np) + goto out; + + base =of_iomap (np,0 ); +if (!base) { +of_node_put (np); + goto out; + } + + val =readl_relaxed (base +L310_PREFETCH_CTRL ); + val |=0x70800000 ; +writel_relaxed (val, base +L310_PREFETCH_CTRL ); + +writel_relaxed (L310_DYNAMIC_CLK_GATING_EN |L310_STNDBY_MODE_EN , + base +L310_POWER_CTRL ); + +iounmap (base); +of_node_put (np); + +out: +l2x0_of_init (0x7c433C01 ,0x8000c3fe ); +} + +static void __init zx296702_init_machine (void ) +{ +zx_l2x0_init (); +of_platform_populate (NULL , of_default_bus_match_table,NULL ,NULL ); +} +static const char *zx296702_dt_compat[]__initconst = {"zte,zx296702" ,NULL ,
@@ -17,4 +60,5 @@ static const char *zx296702_dt_compat[] __initconst = {DT_MACHINE_START (ZX ,"ZTE ZX296702 (Device Tree)" ) .dt_compat = zx296702_dt_compat, + .init_machine = zx296702_init_machine,MACHINE_END
Signature · 1 line
1.9.1
Arnd Bergmann
maintainerPATCH 4/10 ARM: zx: add initial L2CC initialization
Quoted 4 lines · On Saturday 14 March 2015 19:49:39 Jun Nie wrote:
Add an initial L2 Cache controller initialization.
Signed-off-by Jun Nie <[email protected]>
This should not be needed at all, we expect all platforms to describe the l2 cache controller in DT to the degree that is required to have it probed automatically.
Is there any special requirement about this platform that makes this impossible?
Arnd
PATCH 4/10 ARM: zx: add initial L2CC initialization
Quoted 6 lines · Arnd Bergmann
Quoted 4 lines · On Saturday 14 March 2015 19:49:39 Jun Nie wrote:
Add an initial L2 Cache controller initialization.
Signed-off-by Jun Nie <[email protected]>
Quoted 6 lines
This should not be needed at all, we expect all platforms to describe the l2 cache controller in DT to the degree that is required to have it probed automatically.
Is there any special requirement about this platform that makes this impossible?
The L2 device tree bindings do not cover PREFETCH_CTRL and POWER_CTRL registers. I do not remember, but there might be some reason that these registers are not defined by DT bindings, e.g. POWER_CTRL is not available on all pl310 revisions?
Shawn
PATCH 4/10 ARM: zx: add initial L2CC initialization
Hi Shawn,
Quoted 11 lines · On Sun, 15 Mar 2015 19:48:33 -0700 Shawn Guo <[email protected]> wrote:
Quoted 10 lines · Arnd Bergmann
Quoted 4 lines · On Saturday 14 March 2015 19:49:39 Jun Nie wrote:
Add an initial L2 Cache controller initialization.
Signed-off-by Jun Nie <[email protected]>This should not be needed at all, we expect all platforms to describe the l2 cache controller in DT to the degree that is required to have it probed automatically.
Quoted 7 lines
Quoted 2 lines
Is there any special requirement about this platform that makes this impossible?
The L2 device tree bindings do not cover
PREFETCH_CTRLandPOWER_CTRLregisters. I do not remember, but there might be some reason that these registers are not defined by DT bindings, e.g.POWER_CTRLis not available on all pl310 revisions?
The key may be PREFETCH_CTRL can only be accessed in Secure World. So the community require firmware/bootloader to do the setting rather than rely on linux kernel.
Thanks,
Jisheng
PATCH 4/10 ARM: zx: add initial L2CC initialization
In reply to Jun NieQuoted 5 lines · Jun Nie
arch/arm/mach-zx/zx296702.c +5
-0+static void __init zx_l2x0_init (void ) +{ +void __iomem *base; +struct device_node *np; +unsigned int val;
arch/arm/mach-zx/zx296702.c line 34
Quoted 10 lines
arch/arm/mach-zx/zx296702.c +10
-0+ + np =of_find_compatible_node (NULL ,NULL ,"arm,pl310-cache" ); +if (!np) + goto out; + + base =of_iomap (np,0 ); +if (!base) { +of_node_put (np); + goto out; + }
NAK, really, NAK. We're trying to get away from platforms doing crap like this.
arch/arm/mach-zx/zx296702.c line 38
Quoted 4 lines
arch/arm/mach-zx/zx296702.c +4
-0+ + val =readl_relaxed (base +L310_PREFETCH_CTRL ); + val |=0x70800000 ; +writel_relaxed (val, base +L310_PREFETCH_CTRL );
So that's:
L310_PREFETCH_CTRL_DBL_LINEFILL |
L310_PREFETCH_CTRL_INSTR_PREFETCH |
L310_PREFETCH_CTRL_DATA_PREFETCH |
L310_PREFETCH_CTRL_DBL_LINEFILL_INCR
which you can enable by adding:
arm,double-linefill
arm,double-linefill-incr
The prefetch enables are also accessible via the auxillary control register when the cache is not enabled (see below.)
arch/arm/mach-zx/zx296702.c line 41
Quoted 3 lines
arch/arm/mach-zx/zx296702.c +3
-0+ +writel_relaxed (L310_DYNAMIC_CLK_GATING_EN |L310_STNDBY_MODE_EN , + base +L310_POWER_CTRL );
These should be done by your boot loader - they're highly SoC specific.
arch/arm/mach-zx/zx296702.c line 47
Quoted 2 lines
arch/arm/mach-zx/zx296702.c +2
-0+out: +l2x0_of_init (0x7c433C01 ,0x8000c3fe );
Why these random values?
Firstly, the L2 code takes care of bits 0, 26, 27, 30 for you already. I fail to see why you would want to hard-code the cache size here either; the cache size is supposed to be configured by the hardware designers at implementation stage and the aux control register is supposed to take up that configuration at reset.
You see to be setting bits 10-13 inclusive, which include:
L310_AUX_CTRL_HIGHPRIO_SO_DEV L310_AUX_CTRL_STORE_LIMITATION L310_AUX_CTRL_EXCLUSIVE_CACHE
Are you sure you're supposed to be setting these bits?
Bits 28 and 29 are the same as bits 28 and 29 in the prefetch register (as in, you read or write those bits in either register and you're accessing the exact same bits.)
The only possible bits you should be playing around with here which we don't have a way to cater for are bits 22, 28, 29.
Signature · 2 lines
FTTC broadband for 0.8mile line: currently at 10.5Mbps down 400kbps up according to speedtest.net.
PATCH 5/10 ARM: zx: bring up the secondary core
In reply to Jun NieUse release_pen mechanism to bring up the secondary core.
--- arch/arm/mach-zx/Makefile | 1 + arch/arm/mach-zx/core.h | 17 +++++ arch/arm/mach-zx/headsmp.S | 38 ++++++++++++ arch/arm/mach-zx/platsmp.c | 147 ++++++++++++++++++++++++++++++++++++++++++++ arch/arm/mach-zx/zx296702.c | 1 + 5 files changed, 204 insertions(+) create mode 100644 arch/arm/mach-zx/core.h create mode 100644 arch/arm/mach-zx/headsmp.S create mode 100644 arch/arm/mach-zx/platsmp.c
arch/arm/mach-zx/Makefile +1 -0
@@ -1 +1,2 @@ obj-$(CONFIG_SOC_ZX296702) += zx296702.o +obj-$(CONFIG_SMP) += headsmp.o platsmp.o
arch/arm/mach-zx/core.h new file +17 -0
@@ -0,0 +1,17 @@ +/* +* Copyright 2014 Linaro Ltd. +* Copyright (C) 2014 ZTE Corporation. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +*/ + +#ifndef __MACH_ZX_CORE_H +#define __MACH_ZX_CORE_H + +extern struct smp_operations zx_smp_ops; + +void zx_secondary_startup (void ); + +#endif /* __MACH_ZX_CORE_H */
arch/arm/mach-zx/headsmp.S new file +38 -0
@@ -0,0 +1,38 @@ +/* + * Copyright 2014 Linaro Ltd. + * Copyright (C) 2014 ZTE Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/linkage.h> + +/* + * zx2967 specific entry point for secondary CPUs. This provides + * a "holding pen" into which all secondary cores are held until we're + * ready for them to initialise. + */ +ENTRY(zx_secondary_startup) + bl v7_invalidate_l1 + mrc p15, 0, r0, c0, c0, 5 + and r0, r0, #15 + adr r4, 1f + ldmia r4, {r5, r6} + sub r4, r4, r5 + add r6, r6, r4 +pen: ldr r7, [r6] + cmp r7, r0 + bne pen + + /* + * we've been released from the holding pen: secondary_stack + * should now contain the SVC stack for this core + */ + b secondary_startup +ENDPROC(zx_secondary_startup) + + .align 2 +1: .long . + .long pen_release
arch/arm/mach-zx/platsmp.c new file +147 -0
147 lines not on this page · raw message
arch/arm/mach-zx/zx296702.c +1 -0
@@ -59,6 +59,7 @@ static const char *zx296702_dt_compat[] __initconst = { };DT_MACHINE_START (ZX ,"ZTE ZX296702 (Device Tree)" ) + .smp = smp_ops(zx_smp_ops), .dt_compat = zx296702_dt_compat, .init_machine = zx296702_init_machine,MACHINE_END
Signature · 1 line
1.9.1
Arnd Bergmann
maintainerPATCH 5/10 ARM: zx: bring up the secondary core
arch/arm/mach-zx/platsmp.c line 116
Quoted 10 lines · On Saturday 14 March 2015 19:49:40 Jun Nie wrote:
arch/arm/mach-zx/platsmp.c new file +9
-0+ +/* +* This is really belt and braces; we hold unintended secondary +* CPUs in the holding pen until we're ready for them. However, +* since we haven't sent them a soft interrupt, they shouldn't +* be there. +*/ +write_pen_release (cpu); +
Why do you need the holding pen on this platform? Is there a firmware bug or just missing hardware support for proper SMP power management?
Arnd
PATCH 5/10 ARM: zx: bring up the secondary core
Quoted 14 lines · Arnd Bergmann
arch/arm/mach-zx/platsmp.c line 116
Quoted 10 lines · On Saturday 14 March 2015 19:49:40 Jun Nie wrote:
arch/arm/mach-zx/platsmp.c new file +9
-0+ +/* +* This is really belt and braces; we hold unintended secondary +* CPUs in the holding pen until we're ready for them. However, +* since we haven't sent them a soft interrupt, they shouldn't +* be there. +*/ +write_pen_release (cpu); +Why do you need the holding pen on this platform? Is there a firmware bug or just missing hardware support for proper SMP power management?
Arnd,
As this is how things are handled in vendor's kernel, we thought the hardware might be lack of SMP power management. But we will check with vendor to see if there is any level of hardware support for secondary core management, so that we can save the use of holding pen.
Thanks for the comment.
Shawn
PATCH 6/10 ARM: zx: add cpu hotplug support
In reply to Jun NieIt's a clone of vexpress cpu hotplug implementation.
--- arch/arm/mach-zx/Makefile | 1 + arch/arm/mach-zx/core.h | 1 + arch/arm/mach-zx/hotplug.c | 108 +++++++++++++++++++++++++++++++++++++++++++++ arch/arm/mach-zx/platsmp.c | 3 ++ 4 files changed, 113 insertions(+) create mode 100644 arch/arm/mach-zx/hotplug.c
arch/arm/mach-zx/Makefile +1 -0
@@ -1,2 +1,3 @@ obj-$(CONFIG_SOC_ZX296702) += zx296702.o obj-$(CONFIG_SMP) += headsmp.o platsmp.o +obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
arch/arm/mach-zx/core.h +1 -0
@@ -13,5 +13,6 @@extern struct smp_operations zx_smp_ops;void zx_secondary_startup (void ); +void zx_cpu_die (unsigned int cpu);#endif /* __MACH_ZX_CORE_H */
arch/arm/mach-zx/hotplug.c new file +108 -0
108 lines not on this page · raw message
arch/arm/mach-zx/platsmp.c +3 -0
@@ -144,4 +144,7 @@ struct smp_operations zx_smp_ops __initdata = { .smp_prepare_cpus = zx_smp_prepare_cpus, .smp_secondary_init = zx_secondary_init, .smp_boot_secondary = zx_boot_secondary, +#ifdef CONFIG_HOTPLUG_CPU + .cpu_die = zx_cpu_die, +#endif };
Signature · 1 line
1.9.1
Arnd Bergmann
maintainerPATCH 6/10 ARM: zx: add cpu hotplug support
Quoted 5 lines · On Saturday 14 March 2015 19:49:41 Jun Nie wrote:
It's a clone of vexpress cpu hotplug implementation.
Signed-off-by Shawn Guo <[email protected]>Signed-off-by Jun Nie <[email protected]>
Please explain exactly why you cannot use a proper CPU poweroff function here. Nobody should copy that code from vexpress for a real system.
Arnd
PATCH 7/10 dt/binding: Document ZTE zx296702 devicetree
In reply to Jun NieDocument the new compatible for zx296702 platform and clock control.
--- Documentation/devicetree/bindings/arm/zte.txt | 9 ++++++ .../devicetree/bindings/clock/zx296702-clk.txt | 35 ++++++++++++++++++++++ .../devicetree/bindings/vendor-prefixes.txt | 1 + 3 files changed, 45 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/zte.txt create mode 100644 Documentation/devicetree/bindings/clock/zx296702-clk.txt
Documentation/devicetree/bindings/arm/zte.txt new file +9 -0
@@ -0,0 +1,9 @@ +ZTE platforms device tree bindings +--------------------------------------- + +- ZX296702 board: + Required root node properties: + - compatible = "zte,zx296702-ad1", "zte,zx296702" + +Low power management required properties: + - compatible = "zte,aon-sysctrl"
Documentation/devicetree/bindings/clock/zx296702-clk.txt new file +35 -0
@@ -0,0 +1,35 @@ +Device Tree Clock bindings for ZTE zx296702 + +This binding uses the common clock binding[1]. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties: +- compatible : shall be one of the following: + "zte,zx296702-topcrm": + zx296702 top clock selection, divider and gating + + "zte,zx296702-lsp0crpm" or + "zte,zx296702-lsp1crpm": + zx296702 device level clock selection and gating + +- reg: Address and length of the register set + +The clock consumer should specify the desired clock by having the clock +ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx5-clock.h +for the full list of i.MX5 clock IDs. + + +clks: topcrm at 0x09800000 { + compatible = "zte,zx296702-topcrm"; + reg = <0x09800000 0x1000>; + #clock-cells = <1>; +}; + +uart0: serial at 0x09405000 { + compatible = "zte,zx296702-uart"; + reg = <0x09405000 0x1000>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks ZX296702_UART0_PCLK>; + status = "disabled"; +};
Documentation/devicetree/bindings/vendor-prefixes.txt +1 -0
@@ -197,3 +197,4 @@ xillybus Xillybus Ltd. xlnx Xilinx zyxel ZyXEL Communications Corp. zarlink Zarlink Semiconductor +zte ZTE Corp.
Signature · 1 line
1.9.1
PATCH 8/10 ARM: dts: zx: add an initial dts for zx296702
In reply to Jun NieAdd initial dts file for ZX296702 and board ZX296702-AD1. More peripherals will be added later.
--- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/zx296702-ad1.dts | 43 +++++++++++++ arch/arm/boot/dts/zx296702.dtsi | 127 +++++++++++++++++++++++++++++++++++++ 3 files changed, 171 insertions(+) create mode 100644 arch/arm/boot/dts/zx296702-ad1.dts create mode 100644 arch/arm/boot/dts/zx296702.dtsi
arch/arm/boot/dts/Makefile +1 -0
@@ -645,6 +645,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt6592-evb.dtb \ mt8127-moose.dtb \ mt8135-evbp1.dtb +dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb endif always := $(dtb-y)
arch/arm/boot/dts/zx296702-ad1.dts new file +43 -0
43 lines not on this page · raw message
arch/arm/boot/dts/zx296702.dtsi new file +127 -0
127 lines not on this page · raw message
Signature · 1 line
1.9.1
Arnd Bergmann
maintainerPATCH 8/10 ARM: dts: zx: add an initial dts for zx296702
arch/arm/boot/dts/zx296702.dtsi line 10
Quoted 10 lines · On Saturday 14 March 2015 19:49:43 Jun Nie wrote:
arch/arm/boot/dts/zx296702.dtsi new file +9
-0+#include "skeleton.dtsi" +#include <dt-bindings/clock/zx296702-clock.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + aliases { + serial0 = &uart0; + serial1 = &uart1; + };
Move the aliases to the board specific file: other boards might not have the same set of uarts visible to users.
Quoted 7 lines
arch/arm/boot/dts/zx296702.dtsi new file +7
-0+ cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu at 0 { + compatible = "arm,cortex-a9"; + device_type = "cpu";
arch/arm/boot/dts/zx296702.dtsi line 28
Quoted 10 lines
arch/arm/boot/dts/zx296702.dtsi new file +10
-0+ reg = <0>; + }; + + cpu at 1 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <1>; + }; + }; +
No enable-method?
arch/arm/boot/dts/zx296702.dtsi line 67
Quoted 4 lines
arch/arm/boot/dts/zx296702.dtsi new file +4
-0+ lsp1crpm: lsp1crpm at 0x09400000 { + compatible = "zte,zx296702-lsp1crpm"; + reg = <0x09400000 0x1000>; + };
What is an lsp1crpm?
Quoted 1 line
+ dwmmc0: dwmmc at
0x09408000{
The node name should be "mmc", not "dwmmc".
arch/arm/boot/dts/zx296702.dtsi line 107
Quoted 11 lines
arch/arm/boot/dts/zx296702.dtsi new file +11
-0+ + clks: topcrm at 0x09800000 { + compatible = "zte,zx296702-topcrm"; + reg = <0x09800000 0x1000>; + #clock-cells = <1>; + }; + + lsp0crpm: lsp0crpm at 0x0b000000 { + compatible = "zte,zx296702-lsp0crpm"; + reg = <0x0b000000 0x1000>; + };
What is a topcrm and an lsp0crpm?
Quoted 8 lines
arch/arm/boot/dts/zx296702.dtsi new file +8
-0+ dwmmc1: dwmmc at 0x0b003000 { + compatible = "snps,dw-mshc"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0b003000 0x1000>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + fifo-depth = <32>; + clocks = <&clks ZX296702_SDMMC1_PCLK>,
arch/arm/boot/dts/zx296702.dtsi line 126
Quoted 10 lines
arch/arm/boot/dts/zx296702.dtsi new file +10
-0+ <&clks ZX296702_SDMMC1_WCLK>; + clock-names = "biu", "ciu"; + status = "disabled"; + }; + + aon_sysctrl: aon-sysctrl at 0xa0007000 { + compatible = "zte,aon-sysctrl"; + reg = <0xa0007000 0x1000>; + }; + };
This looks like it's a system controller, so the node name should probably be "system-controller", not aon-sysctrl, and you may want to claim compatibility with "syscon" as well.
All the nodes need to have a documented binding.
Arnd
PATCH 9/10 ARM: zx: Add basic defconfig support to ZX296702
In reply to Jun NieAdd basic defconfig support to zx SOC, including uart, mmc
and other common config
--- arch/arm/configs/zx_defconfig | 129 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 129 insertions(+) create mode 100644 arch/arm/configs/zx_defconfig
arch/arm/configs/zx_defconfig new file +129 -0
@@ -0,0 +1,129 @@ +CONFIG_EXPERIMENTAL=y +CONFIG_SYSVIPC=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_CGROUPS=y +CONFIG_CGROUP_DEBUG=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_RESOURCE_COUNTERS=y +CONFIG_CGROUP_SCHED=y +CONFIG_RT_GROUP_SCHED=y +CONFIG_NAMESPACES=y +CONFIG_USER_NS=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS_ALL=y +CONFIG_EMBEDDED=y +CONFIG_PERF_EVENTS=y +CONFIG_SLAB=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_ARCH_ZX=y +CONFIG_SOC_ZX296702=y +# CONFIG_SWP_EMULATE is not set +CONFIG_ARM_ERRATA_754322=y +CONFIG_ARM_ERRATA_775420=y +CONFIG_SMP=y +CONFIG_VMSPLIT_2G=y +CONFIG_PREEMPT=y +CONFIG_AEABI=y +CONFIG_KSM=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_KERNEL_MODE_NEON=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HIBERNATION=y +CONFIG_PM_RUNTIME=y +CONFIG_PM_DEBUG=y +CONFIG_SUSPEND_TIME=y +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="root=/dev/nfs rootfstype=nfs nfsroot=192.168.2.100:/nfsroot/ ip=192.168.2.101:192.168.2.100::255.255.255.0::eth0:on console=ttyS0,115200 mem=128M earlyprintk" +#CONFIG_NET is not set +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=192 +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=1 +CONFIG_BLK_DEV_RAM_SIZE=8192 +CONFIG_UID_STAT=y +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_SG=y +CONFIG_CHR_DEV_SCH=y +CONFIG_SCSI_MULTI_LUN=y +CONFIG_MD=y +CONFIG_BLK_DEV_DM=y +CONFIG_DM_CRYPT=y +CONFIG_DM_UEVENT=y +CONFIG_DM_VERITY=y +CONFIG_NETDEVICES=y +# CONFIG_INPUT_MOUSE is not set +CONFIG_SERIO=y +CONFIG_SERIO_LIBPS2=y +CONFIG_SPI=y +CONFIG_LOGO=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_CONSOLE_POLL=y +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_OF_PLATFORM=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_HWMON is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_MMC=y +CONFIG_MMC_UNSAFE_RESUME=y +CONFIG_MMC_BLOCK_MINORS=16 +CONFIG_MMC_DW=y +CONFIG_MMC_DW_IDMAC=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_EXT4_DEBUG=y +CONFIG_FUSE_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=936 +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +#CONFIG_NFS_FS is not set +CONFIG_NLS_CODEPAGE_936=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_UTF8=y +CONFIG_PRINTK_TIME=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_PREEMPT is not set +CONFIG_DEBUG_INFO=y +CONFIG_FRAME_WARN=4096 +CONFIG_DEBUG_FS=y +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_PANIC_TIMEOUT=5 +# CONFIG_SCHED_DEBUG is not set +CONFIG_SCHEDSTATS=y +CONFIG_TIMER_STATS=y +CONFIG_DEBUG_RT_MUTEXES=y +CONFIG_DEBUG_SPINLOCK=y +CONFIG_DEBUG_MUTEXES=y +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +# CONFIG_FTRACE is not set +CONFIG_KGDB=y +CONFIG_KGDB_KDB=y +# CONFIG_ARM_UNWIND is not set +CONFIG_DEBUG_PREEMPT=y +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_LL=y +CONFIG_DYNAMIC_DEBUG=y +CONFIG_STACKTRACE=y +CONFIG_DEBUG_ZTE_ZX=y +CONFIG_EARLY_PRINTK=y +CONFIG_CRYPTO_LZO=y +CONFIG_GPIOLIB=y
Signature · 1 line
1.9.1
PATCH 9/10 ARM: zx: Add basic defconfig support to ZX296702
Quoted 6 lines · Jun Nie
Add basic defconfig support to zx SOC, including uart, mmc
and other common configSigned-off-by Jun Nie <[email protected]>--- arch/arm/configs/zx_defconfig | 129 ++++++++++++++++++++++++++++++++++++++++++
I see a warning with make zx_defconfig.
arch/arm/configs/zx_defconfig:121:warning: override: reassigning to symbol DEBUG_PREEMPT
Shawn
PATCH 10/10 clk: zx: add zx296702 clock support
In reply to Jun NieIt adds a clock driver for zx296702 SoC to register the clock tree to Common Clock Framework. All the clocks of bus topology and some the peripheral clocks are ready with this commit. Some missing leaf clocks for peripherals will be added later when needed.
--- drivers/clk/Makefile | 1 + drivers/clk/zte/Makefile | 2 + drivers/clk/zte/clk-pll.c | 211 ++++++++++ drivers/clk/zte/clk-zx296702.c | 611 +++++++++++++++++++++++++++++ drivers/clk/zte/clk.h | 30 ++ include/dt-bindings/clock/zx296702-clock.h | 158 ++++++++ 6 files changed, 1013 insertions(+) create mode 100644 drivers/clk/zte/Makefile create mode 100644 drivers/clk/zte/clk-pll.c create mode 100644 drivers/clk/zte/clk-zx296702.c create mode 100644 drivers/clk/zte/clk.h create mode 100644 include/dt-bindings/clock/zx296702-clock.h
drivers/clk/Makefile +1 -0
@@ -69,4 +69,5 @@ obj-$(CONFIG_ARCH_OMAP2PLUS) += ti/ obj-$(CONFIG_ARCH_U8500) += ux500/ obj-$(CONFIG_COMMON_CLK_VERSATILE) += versatile/ obj-$(CONFIG_X86) += x86/ +obj-$(CONFIG_ARCH_ZX) += zte/ obj-$(CONFIG_ARCH_ZYNQ) += zynq/
drivers/clk/zte/Makefile new file +2 -0
@@ -0,0 +1,2 @@ +obj-y := clk-pll.o +obj-$(CONFIG_SOC_ZX296702) += clk-zx296702.o
drivers/clk/zte/clk-pll.c new file +211 -0
211 lines not on this page · raw message
drivers/clk/zte/clk-zx296702.c new file +611 -0
611 lines not on this page · raw message
drivers/clk/zte/clk.h new file +30 -0
@@ -0,0 +1,30 @@ +/* +* Copyright 2014 Linaro Ltd. +* Copyright (C) 2014 ZTE Corporation. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +*/ + +#ifndef __ZTE_CLK_H +#define __ZTE_CLK_H + +struct zx_pll_config { +unsigned long rate; +u32 cfg0; +u32 cfg1; +}; + +struct clk_zx_pll { +struct clk_hw hw; +void __iomem *reg_base; +const struct zx_pll_config *lookup_table;/* order by rate asc */ +int count; +spinlock_t *lock; +}; + +struct clk *clk_register_zx_pll (const char *name,const char *parent_name, +unsigned long flags,void __iomem *reg_base, +const struct zx_pll_config *lookup_table,int count,spinlock_t *lock); +#endif
include/dt-bindings/clock/zx296702-clock.h new file +158 -0
158 lines not on this page · raw message
Signature · 1 line
1.9.1
Arnd Bergmann
maintainerPATCH 10/10 clk: zx: add zx296702 clock support
Quoted 7 lines · On Saturday 14 March 2015 19:49:45 Jun Nie wrote:
drivers/clk/zte/clk-zx296702.c new file +7
-0+ +static void __init zx296702_clocks_init (struct device_node *np) +{ +struct device_node *node; +int i; + + topcrm_base =of_iomap (np,0 );
drivers/clk/zte/clk-zx296702.c line 212
Quoted 10 lines
drivers/clk/zte/clk-zx296702.c new file +10
-0+WARN_ON (!topcrm_base); + + node =of_find_compatible_node (NULL ,NULL ,"zte,zx296702-lsp0crpm" ); + lsp0crpm_base =of_iomap (node,0 ); +WARN_ON (!lsp0crpm_base); + + node =of_find_compatible_node (NULL ,NULL ,"zte,zx296702-lsp1crpm" ); + lsp1crpm_base =of_iomap (node,0 ); +WARN_ON (!lsp1crpm_base); +
Could you make this three separate clock controllers instead?
Arnd
PATCH 10/10 clk: zx: add zx296702 clock support
In reply to Jun NieQuoted 9 lines · Jun Nie
drivers/clk/zte/clk-pll.c new file +9
-0+static int hw_to_idx (struct clk_zx_pll *zx_pll) +{ +const struct zx_pll_config *config = zx_pll->lookup_table; +u32 hw_cfg0, hw_cfg1; +unsigned long flags =0 ; +int i; + +if (zx_pll->lock) +spin_lock_irqsave (zx_pll->lock, flags);
drivers/clk/zte/clk-pll.c line 55
Quoted 10 lines
drivers/clk/zte/clk-pll.c new file +10
-0+ + hw_cfg0 =readl (zx_pll->reg_base); + hw_cfg1 =readl (zx_pll->reg_base +4 ); + +if (zx_pll->lock) +spin_unlock_irqrestore (zx_pll->lock, flags); + +/* For matching the value in lookup table */ + hw_cfg0 &= ~BIT (30 );/* clear lock bit */ + hw_cfg0 |=BIT (31 );/* set PD bit */
Use definitions for these bits rather than BIT(n) and a comment.
Quoted 5 lines
drivers/clk/zte/clk-pll.c new file +5
-0+static int zx_pll_set_rate (struct clk_hw *hw,unsigned long rate, +unsigned long parent_rate) +{ +/* Assume current cpu is not running on current PLL */ +struct clk_zx_pll *zx_pll =to_clk_zx_pll (hw);
drivers/clk/zte/clk-pll.c line 103
Quoted 10 lines
drivers/clk/zte/clk-pll.c new file +10
-0+const struct zx_pll_config *config; +unsigned long flags =0 ; +int idx; +u32 reg; + + idx =rate_to_idx (zx_pll, rate); + config = &zx_pll->lookup_table[idx]; + +if (zx_pll->lock) +spin_lock_irqsave (zx_pll->lock, flags);
Is this code ever safe without having a lock to take?
drivers/clk/zte/clk-pll.c line 106
Quoted 3 lines
drivers/clk/zte/clk-pll.c new file +3
-0+ +writel (config->cfg0, zx_pll->reg_base); +writel (config->cfg1, zx_pll->reg_base +4 );
Use a definition for this +4 (and also for the first register too.)
drivers/clk/zte/clk-pll.c line 109
Quoted 3 lines
drivers/clk/zte/clk-pll.c new file +3
-0+ reg =readl (zx_pll->reg_base); + reg &= ~BIT (31 ); +writel (reg, zx_pll->reg_base);
You've only just written zx_pll->reg_base - why do you need to read it back? Wouldn't this be better (and in any case, using relaxed accessors is probably a good idea):
writel_relaxed(config->cfg0, zx_pll->reg_base); writel_relaxed(config->cfg1, zx_pll->reg_base + 4); writel_relaxed(config->cfg0 & ~ZX_PLL_PD, zx_pll->reg_base);
Looks nicer, doesn't it?
In any case, why should setting the rate enable the PLL? I notice you use the PD bit below in the enable/disable functions, so this seems rather silly - it looks like it should be preserved, and then the wait for the PLL to lock (below) should be conditional on the PLL being enabled.
Review
Quoted 2 lines
(quoted diff) +2
-0+ while (!(readl(zx_pll->reg_base) & BIT(30))) + cpu_relax();
What if the bit never sets? You can probably use readl_relaxed() here.
Quoted 10 lines
drivers/clk/zte/clk-pll.c new file +10
-0+ +if (zx_pll->lock) +spin_unlock_irqrestore (zx_pll->lock, flags); + +return 0 ; +} + +static int zx_pll_enable (struct clk_hw *hw) +{ +struct clk_zx_pll *zx_pll =to_clk_zx_pll (hw);
drivers/clk/zte/clk-pll.c line 131
Quoted 10 lines
drivers/clk/zte/clk-pll.c new file +10
-0+unsigned long flags =0 ; +u32 reg; + +if (zx_pll->lock) +spin_lock_irqsave (zx_pll->lock, flags); + + reg =readl (zx_pll->reg_base); +writel (reg & ~BIT (31 ), zx_pll->reg_base); +while (!(readl (zx_pll->reg_base) &BIT (30 ))) +cpu_relax ();
What if the bit never sets?
Quoted 26 lines
drivers/clk/zte/clk-pll.c new file +26
-0+ +if (zx_pll->lock) +spin_unlock_irqrestore (zx_pll->lock, flags); + +return 0 ; +} + +static void zx_pll_disable (struct clk_hw *hw) +{ +struct clk_zx_pll *zx_pll =to_clk_zx_pll (hw); +unsigned long flags =0 ; +u32 reg; + +if (zx_pll->lock) +spin_lock_irqsave (zx_pll->lock, flags); + + reg =readl (zx_pll->reg_base); +writel (reg |BIT (31 ), zx_pll->reg_base); + +if (zx_pll->lock) +spin_unlock_irqrestore (zx_pll->lock, flags); +} + +static int zx_pll_is_enabled (struct clk_hw *hw) +{ +struct clk_zx_pll *zx_pll =to_clk_zx_pll (hw);
drivers/clk/zte/clk-pll.c line 167
Quoted 10 lines
drivers/clk/zte/clk-pll.c new file +10
-0+unsigned long flags =0 ; +u32 reg; + +if (zx_pll->lock) +spin_lock_irqsave (zx_pll->lock, flags); + + reg =readl (zx_pll->reg_base); + +if (zx_pll->lock) +spin_unlock_irqrestore (zx_pll->lock, flags);
You don't need locking to read from a single register.
Quoted 25 lines
drivers/clk/zte/clk-pll.c new file +25
-0+ +return !(reg &BIT (31 )); +} + +static const struct clk_ops zx_pll_ops = { + .recalc_rate = zx_pll_recalc_rate, + .round_rate = zx_pll_round_rate, + .set_rate = zx_pll_set_rate, + .enable = zx_pll_enable, + .disable = zx_pll_disable, + .is_enabled = zx_pll_is_enabled, +}; + +struct clk *clk_register_zx_pll (const char *name,const char *parent_name, +unsigned long flags,void __iomem *reg_base, +const struct zx_pll_config *lookup_table,int count,spinlock_t *lock) +{ +struct clk_zx_pll *zx_pll; +struct clk *clk; +struct clk_init_data init; + + zx_pll =kzalloc (sizeof (*zx_pll),GFP_KERNEL ); +if (!zx_pll) +return ERR_PTR (-ENOMEM ); +
drivers/clk/zte/clk-pll.c line 202
Quoted 10 lines
drivers/clk/zte/clk-pll.c new file +10
-0+ init.name = name; + init.ops = &zx_pll_ops; + init.flags = flags; + init.parent_names = (parent_name ? &parent_name :NULL ); + init.num_parents = (parent_name ?1 :0 ); + + zx_pll->reg_base = reg_base; + zx_pll->lookup_table = lookup_table; + zx_pll->count = count; + zx_pll->lock = lock;
As mentioned above, I think this is unsafe if lock is NULL. You probably want to subsitute a lock specific to the PLL if none was provided.
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