powerpc: drop some non-generic boards

This has not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.)

Signed-off-by Masahiro Yamada <[email protected]>

This has not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.)

Signed-off-by Masahiro Yamada <[email protected]>

Cc Stephen Williams <[email protected]>

They have not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.)

Signed-off-by Masahiro Yamada <[email protected]>

They have not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.)

Signed-off-by Masahiro Yamada <[email protected]>

Cc Erik Theisen <[email protected]>

This has not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.)

Signed-off-by Masahiro Yamada <[email protected]>

Cc Eric Millbrandt <[email protected]>

This has not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.)

Signed-off-by Masahiro Yamada <[email protected]>

Cc Larry Johnson <[email protected]>

Remove MPC8308RDB, MPC8313ERDB, MPC8315ERDB, MPC8323ERDB, MPC832XEMDS, MPC8349EMDS, MPC8349ITX, and MPC837XEMDS.

They have not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.)

Signed-off-by Masahiro Yamada <[email protected]>

Cc Ilya Yanok <[email protected]>

Cc Dave Liu <[email protected]>

Cc Michael Barkowski <[email protected]>

Cc Kim Phillips <[email protected]>

---

  arch/powerpc/cpu/mpc83xx/Kconfig          |  33 --
  board/freescale/common/pq-mds-pib.c       |  26 -
  board/freescale/mpc8308rdb/Kconfig        |  12 -
  board/freescale/mpc8308rdb/MAINTAINERS    |   6 -
  board/freescale/mpc8308rdb/Makefile       |  10 -
  board/freescale/mpc8308rdb/mpc8308rdb.c   | 192 -------
  board/freescale/mpc8308rdb/sdram.c        |  81 ---
  board/freescale/mpc8313erdb/Kconfig       |  12 -
  board/freescale/mpc8313erdb/MAINTAINERS   |   9 -
  board/freescale/mpc8313erdb/Makefile      |   8 -
  board/freescale/mpc8313erdb/README        | 111 ----
  board/freescale/mpc8313erdb/mpc8313erdb.c | 157 ------
  board/freescale/mpc8313erdb/sdram.c       | 124 -----
  board/freescale/mpc8315erdb/Kconfig       |  12 -
  board/freescale/mpc8315erdb/MAINTAINERS   |   6 -
  board/freescale/mpc8315erdb/Makefile      |   8 -
  board/freescale/mpc8315erdb/README        | 105 ----
  board/freescale/mpc8315erdb/mpc8315erdb.c | 246 ---------
  board/freescale/mpc8315erdb/sdram.c       | 111 ----
  board/freescale/mpc8323erdb/Kconfig       |  12 -
  board/freescale/mpc8323erdb/MAINTAINERS   |   6 -
  board/freescale/mpc8323erdb/Makefile      |   8 -
  board/freescale/mpc8323erdb/README        |  71 ---
  board/freescale/mpc8323erdb/mpc8323erdb.c | 222 --------
  board/freescale/mpc832xemds/Kconfig       |  12 -
  board/freescale/mpc832xemds/MAINTAINERS   |  10 -
  board/freescale/mpc832xemds/Makefile      |   9 -
  board/freescale/mpc832xemds/README        | 128 -----
  board/freescale/mpc832xemds/mpc832xemds.c | 166 ------
  board/freescale/mpc832xemds/pci.c         | 146 ------
  board/freescale/mpc8349emds/Kconfig       |  12 -
  board/freescale/mpc8349emds/MAINTAINERS   |   6 -
  board/freescale/mpc8349emds/Makefile      |  10 -
  board/freescale/mpc8349emds/ddr.c         | 101 ----
  board/freescale/mpc8349emds/mpc8349emds.c | 285 -----------
  board/freescale/mpc8349emds/pci.c         | 192 -------
  board/freescale/mpc8349itx/Kconfig        |  12 -
  board/freescale/mpc8349itx/MAINTAINERS    |   8 -
  board/freescale/mpc8349itx/Makefile       |   8 -
  board/freescale/mpc8349itx/README         | 187 -------
  board/freescale/mpc8349itx/mpc8349itx.c   | 390 --------------
  board/freescale/mpc8349itx/pci.c          | 105 ----
  board/freescale/mpc837xemds/Kconfig       |  12 -
  board/freescale/mpc837xemds/MAINTAINERS   |   7 -
  board/freescale/mpc837xemds/Makefile      |   9 -
  board/freescale/mpc837xemds/README        | 104 ----
  board/freescale/mpc837xemds/mpc837xemds.c | 346 -------------
  board/freescale/mpc837xemds/pci.c         | 147 ------
  board/freescale/mpc837xemds/pci.h         |   6 -
  configs/MPC8308RDB_defconfig              |   3 -
  configs/MPC8313ERDB_33_defconfig          |   4 -
  configs/MPC8313ERDB_66_defconfig          |   4 -
  configs/MPC8313ERDB_NAND_33_defconfig     |   5 -
  configs/MPC8313ERDB_NAND_66_defconfig     |   5 -
  configs/MPC8315ERDB_defconfig             |   3 -
  configs/MPC8323ERDB_defconfig             |   3 -
  configs/MPC832XEMDS_ATM_defconfig         |   4 -
  configs/MPC832XEMDS_HOST_33_defconfig     |   4 -
  configs/MPC832XEMDS_HOST_66_defconfig     |   4 -
  configs/MPC832XEMDS_SLAVE_defconfig       |   4 -
  configs/MPC832XEMDS_defconfig             |   3 -
  configs/MPC8349EMDS_defconfig             |   3 -
  configs/MPC8349ITXGP_defconfig            |   4 -
  configs/MPC8349ITX_LOWBOOT_defconfig      |   4 -
  configs/MPC8349ITX_defconfig              |   4 -
  configs/MPC837XEMDS_HOST_defconfig        |   4 -
  configs/MPC837XEMDS_defconfig             |   3 -
  doc/README.scrapyard                      |   8 +
  include/configs/MPC8308RDB.h              | 582 ---------------------
  include/configs/MPC8313ERDB.h             | 719 --------------------------
  include/configs/MPC8315ERDB.h             | 659 ------------------------
  include/configs/MPC8323ERDB.h             | 555 --------------------
  include/configs/MPC832XEMDS.h             | 624 -----------------------
  include/configs/MPC8349EMDS.h             | 810 ------------------------------
  include/configs/MPC8349ITX.h              | 806 -----------------------------
  include/configs/MPC837XEMDS.h             | 719 --------------------------
  76 files changed, 8 insertions(+), 9548 deletions(-)

delete mode 100644 board/freescale/mpc8308rdb/Kconfig delete mode 100644 board/freescale/mpc8308rdb/MAINTAINERS delete mode 100644 board/freescale/mpc8308rdb/Makefile delete mode 100644 board/freescale/mpc8308rdb/mpc8308rdb.c delete mode 100644 board/freescale/mpc8308rdb/sdram.c delete mode 100644 board/freescale/mpc8313erdb/Kconfig delete mode 100644 board/freescale/mpc8313erdb/MAINTAINERS delete mode 100644 board/freescale/mpc8313erdb/Makefile delete mode 100644 board/freescale/mpc8313erdb/README delete mode 100644 board/freescale/mpc8313erdb/mpc8313erdb.c delete mode 100644 board/freescale/mpc8313erdb/sdram.c delete mode 100644 board/freescale/mpc8315erdb/Kconfig delete mode 100644 board/freescale/mpc8315erdb/MAINTAINERS delete mode 100644 board/freescale/mpc8315erdb/Makefile delete mode 100644 board/freescale/mpc8315erdb/README delete mode 100644 board/freescale/mpc8315erdb/mpc8315erdb.c delete mode 100644 board/freescale/mpc8315erdb/sdram.c delete mode 100644 board/freescale/mpc8323erdb/Kconfig delete mode 100644 board/freescale/mpc8323erdb/MAINTAINERS delete mode 100644 board/freescale/mpc8323erdb/Makefile delete mode 100644 board/freescale/mpc8323erdb/README delete mode 100644 board/freescale/mpc8323erdb/mpc8323erdb.c delete mode 100644 board/freescale/mpc832xemds/Kconfig delete mode 100644 board/freescale/mpc832xemds/MAINTAINERS delete mode 100644 board/freescale/mpc832xemds/Makefile delete mode 100644 board/freescale/mpc832xemds/README delete mode 100644 board/freescale/mpc832xemds/mpc832xemds.c delete mode 100644 board/freescale/mpc832xemds/pci.c delete mode 100644 board/freescale/mpc8349emds/Kconfig delete mode 100644 board/freescale/mpc8349emds/MAINTAINERS delete mode 100644 board/freescale/mpc8349emds/Makefile delete mode 100644 board/freescale/mpc8349emds/ddr.c delete mode 100644 board/freescale/mpc8349emds/mpc8349emds.c delete mode 100644 board/freescale/mpc8349emds/pci.c delete mode 100644 board/freescale/mpc8349itx/Kconfig delete mode 100644 board/freescale/mpc8349itx/MAINTAINERS delete mode 100644 board/freescale/mpc8349itx/Makefile delete mode 100644 board/freescale/mpc8349itx/README delete mode 100644 board/freescale/mpc8349itx/mpc8349itx.c delete mode 100644 board/freescale/mpc8349itx/pci.c delete mode 100644 board/freescale/mpc837xemds/Kconfig delete mode 100644 board/freescale/mpc837xemds/MAINTAINERS delete mode 100644 board/freescale/mpc837xemds/Makefile delete mode 100644 board/freescale/mpc837xemds/README delete mode 100644 board/freescale/mpc837xemds/mpc837xemds.c delete mode 100644 board/freescale/mpc837xemds/pci.c delete mode 100644 board/freescale/mpc837xemds/pci.h delete mode 100644 configs/MPC8308RDB_defconfig delete mode 100644 configs/MPC8313ERDB_33_defconfig delete mode 100644 configs/MPC8313ERDB_66_defconfig delete mode 100644 configs/MPC8313ERDB_NAND_33_defconfig delete mode 100644 configs/MPC8313ERDB_NAND_66_defconfig delete mode 100644 configs/MPC8315ERDB_defconfig delete mode 100644 configs/MPC8323ERDB_defconfig delete mode 100644 configs/MPC832XEMDS_ATM_defconfig delete mode 100644 configs/MPC832XEMDS_HOST_33_defconfig delete mode 100644 configs/MPC832XEMDS_HOST_66_defconfig delete mode 100644 configs/MPC832XEMDS_SLAVE_defconfig delete mode 100644 configs/MPC832XEMDS_defconfig delete mode 100644 configs/MPC8349EMDS_defconfig delete mode 100644 configs/MPC8349ITXGP_defconfig delete mode 100644 configs/MPC8349ITX_LOWBOOT_defconfig delete mode 100644 configs/MPC8349ITX_defconfig delete mode 100644 configs/MPC837XEMDS_HOST_defconfig delete mode 100644 configs/MPC837XEMDS_defconfig delete mode 100644 include/configs/MPC8308RDB.h delete mode 100644 include/configs/MPC8313ERDB.h delete mode 100644 include/configs/MPC8315ERDB.h delete mode 100644 include/configs/MPC8323ERDB.h delete mode 100644 include/configs/MPC832XEMDS.h delete mode 100644 include/configs/MPC8349EMDS.h delete mode 100644 include/configs/MPC8349ITX.h delete mode 100644 include/configs/MPC837XEMDS.h

arch/powerpc/cpu/mpc83xx/Kconfig +0 -33

index 4d6cb09..a7ff0d4 100644
@@ -19,31 +19,6 @@ config TARGET_VE8313
  config TARGET_VME8349
  	bool "Support vme8349"
 
-config TARGET_MPC8308RDB
-	bool "Support MPC8308RDB"
-
-config TARGET_MPC8313ERDB
-	bool "Support MPC8313ERDB"
-	select SUPPORT_SPL
-
-config TARGET_MPC8315ERDB
-	bool "Support MPC8315ERDB"
-
-config TARGET_MPC8323ERDB
-	bool "Support MPC8323ERDB"
-
-config TARGET_MPC832XEMDS
-	bool "Support MPC832XEMDS"
-
-config TARGET_MPC8349EMDS
-	bool "Support MPC8349EMDS"
-
-config TARGET_MPC8349ITX
-	bool "Support MPC8349ITX"
-
-config TARGET_MPC837XEMDS
-	bool "Support MPC837XEMDS"
-
  config TARGET_MPC837XERDB
  	bool "Support MPC837XERDB"
 

@@ -68,14 +43,6 @@ config TARGET_HRCON
  endchoice
 
  source "board/esd/vme8349/Kconfig"
-source "board/freescale/mpc8308rdb/Kconfig"
-source "board/freescale/mpc8313erdb/Kconfig"
-source "board/freescale/mpc8315erdb/Kconfig"
-source "board/freescale/mpc8323erdb/Kconfig"
-source "board/freescale/mpc832xemds/Kconfig"
-source "board/freescale/mpc8349emds/Kconfig"
-source "board/freescale/mpc8349itx/Kconfig"
-source "board/freescale/mpc837xemds/Kconfig"
  source "board/freescale/mpc837xerdb/Kconfig"
  source "board/ids/ids8313/Kconfig"
  source "board/keymile/km83xx/Kconfig"

board/freescale/common/pq-mds-pib.c +0 -26

index 1eb3786..4313ac3 100644
@@ -36,11 +36,7 @@ int pib_init(void)
  	i2c_write(0x26, 0x6, 1, &val8, 1);
  	val8 = 0x34;
  	i2c_write(0x26, 0x7, 1, &val8, 1);
-#if defined(CONFIG_MPC832XEMDS)
-	val8 = 0xf9;            /* PMC2, PMC3 slot to PCI bus */
-#else
  	val8 = 0xf3;		/* PMC1, PMC2, PMC3 slot to PCI bus */
-#endif
  	i2c_write(0x26, 0x2, 1, &val8, 1);
  	val8 = 0xff;
  	i2c_write(0x26, 0x3, 1, &val8, 1);

@@ -55,12 +51,8 @@ int pib_init(void)
 
  	eieio();
 
-#if defined(CONFIG_MPC832XEMDS)
-	printf("PCI 32bit bus on PMC2 &PMC3\n");
-#else
  	printf("PCI 32bit bus on PMC1 & PMC2 &PMC3\n");
  #endif
-#endif
 
  #if defined(CONFIG_PQ_MDS_PIB_ATM)
  #if defined(CONFIG_MPC8569MDS)

@@ -76,24 +68,6 @@ int pib_init(void)
  	eieio();
 
  	printf("QOC3 ATM card on PMC0\n");
-#elif defined(CONFIG_MPC832XEMDS)
-	val8 = 0;
-	i2c_write(0x26, 0x7, 1, &val8, 1);
-	val8 = 0xf7;
-	i2c_write(0x26, 0x3, 1, &val8, 1);
-
-	val8 = 0;
-	i2c_write(0x21, 0x6, 1, &val8, 1);
-	i2c_write(0x21, 0x7, 1, &val8, 1);
-
-	val8 = 0xdf;
-	i2c_write(0x21, 0x2, 1, &val8, 1);
-	val8 = 0xef;
-	i2c_write(0x21, 0x3, 1, &val8, 1);
-
-	eieio();
-
-	printf("QOC3 ATM card on PMC1\n");
  #endif
  #endif
  	/* Reset to original I2C bus */

board/freescale/mpc8308rdb/Kconfig deleted +0 -12

deleted file mode 100644
index 48d25e5..0000000
@@ -1,12 +0,0 @@
-if TARGET_MPC8308RDB
-
-config SYS_BOARD
-	default "mpc8308rdb"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "MPC8308RDB"
-
-endif

board/freescale/mpc8308rdb/MAINTAINERS deleted +0 -6

deleted file mode 100644
index 07ff2abd..0000000
@@ -1,6 +0,0 @@
-MPC8308RDB BOARD
-M:	Ilya Yanok <[email protected]>
-S:	Maintained
-F:	board/freescale/mpc8308rdb/
-F:	include/configs/MPC8308RDB.h
-F:	configs/MPC8308RDB_defconfig

board/freescale/mpc8308rdb/Makefile deleted +0 -10

deleted file mode 100644
index ec2b85d..0000000
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-# (C) Copyright 2010
-# Ilya Yanok, Emcraft Systems, yanok at emcraft.com
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= mpc8308rdb.o sdram.o

board/freescale/mpc8308rdb/mpc8308rdb.c deleted +0 -192

deleted file mode 100644
index 93e1c50..0000000
@@ -1,192 +0,0 @@
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok at emcraft.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <hwconfig.h>
-#include <i2c.h>
-#include <spi.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <pci.h>
-#include <mpc83xx.h>
-#include <vsc7385.h>
-#include <netdev.h>
-#include <fsl_esdhc.h>
-#include <asm/io.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_mpc83xx_serdes.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * The following are used to control the SPI chip selects for the SPI command.
- */
-#ifdef CONFIG_MPC8XXX_SPI
-
-#define SPI_CS_MASK	0x00400000
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
-	return bus == 0 && cs == 0;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
-	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-
-	/* active low */
-	clrbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
-	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-
-	/* inactive high */
-	setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
-}
-#endif /* CONFIG_MPC8XXX_SPI */
-
-#ifdef CONFIG_FSL_ESDHC
-int board_mmc_init(bd_t *bd)
-{
-	return fsl_esdhc_mmc_init(bd);
-}
-#endif
-
-static u8 read_board_info(void)
-{
-	u8 val8;
-	i2c_set_bus_num(0);
-
-	if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0)
-		return val8;
-	else
-		return 0;
-}
-
-int checkboard(void)
-{
-	static const char * const rev_str[] = {
-		"1.0",
-		"<reserved>",
-		"<reserved>",
-		"<reserved>",
-		"<unknown>",
-	};
-	u8 info;
-	int i;
-
-	info = read_board_info();
-	i = (!info) ? 4 : info & 0x03;
-
-	printf("Board: Freescale MPC8308RDB Rev %s\n", rev_str[i]);
-
-	return 0;
-}
-
-static struct pci_region pcie_regions_0[] = {
-	{
-		.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
-		.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
-		.size = CONFIG_SYS_PCIE1_MEM_SIZE,
-		.flags = PCI_REGION_MEM,
-	},
-	{
-		.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
-		.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
-		.size = CONFIG_SYS_PCIE1_IO_SIZE,
-		.flags = PCI_REGION_IO,
-	},
-};
-
-void pci_init_board(void)
-{
-	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-	sysconf83xx_t *sysconf = &immr->sysconf;
-	law83xx_t *pcie_law = sysconf->pcielaw;
-	struct pci_region *pcie_reg[] = { pcie_regions_0 };
-
-	fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
-					FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
-
-	/* Deassert the resets in the control register */
-	out_be32(&sysconf->pecr1, 0xE0008000);
-	udelay(2000);
-
-	/* Configure PCI Express Local Access Windows */
-	out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
-	out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
-
-	mpc83xx_pcie_init(1, pcie_reg);
-}
-/*
- * Miscellaneous late-boot configurations
- *
- * If a VSC7385 microcode image is present, then upload it.
-*/
-int misc_init_r(void)
-{
-#ifdef CONFIG_MPC8XXX_SPI
-	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-	sysconf83xx_t *sysconf = &immr->sysconf;
-
-	/*
-	 * Set proper bits in SICRH to allow SPI on header J8
-	 *
-	 * NOTE: this breaks the TSEC2 interface, attached to the Vitesse
-	 * switch. The pinmux configuration does not have a fine enough
-	 * granularity to support both simultaneously.
-	 */
-	clrsetbits_be32(&sysconf->sicrh, SICRH_GPIO_A_TSEC2, SICRH_GPIO_A_GPIO);
-	puts("WARNING: SPI enabled, TSEC2 support is broken\n");
-
-	/* Set header J8 SPI chip select output, disabled */
-	setbits_be32(&immr->gpio[0].dir, SPI_CS_MASK);
-	setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
-#endif
-
-#ifdef CONFIG_VSC7385_IMAGE
-	if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
-		CONFIG_VSC7385_IMAGE_SIZE)) {
-		puts("Failure uploading VSC7385 microcode.\n");
-		return 1;
-	}
-#endif
-
-	return 0;
-}
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-	fdt_fixup_dr_usb(blob, bd);
-	fdt_fixup_esdhc(blob, bd);
-
-	return 0;
-}
-#endif
-
-int board_eth_init(bd_t *bis)
-{
-	int rv, num_if = 0;
-
-	/* Initialize TSECs first */
-	rv = cpu_eth_init(bis);
-	if (rv >= 0)
-		num_if += rv;
-	else
-		printf("ERROR: failed to initialize TSECs.\n");
-
-	rv = pci_eth_init(bis);
-	if (rv >= 0)
-		num_if += rv;
-	else
-		printf("ERROR: failed to initialize PCI Ethernet.\n");
-
-	return num_if;
-}

board/freescale/mpc8308rdb/sdram.c deleted +0 -81

deleted file mode 100644
index 89b665e..0000000
@@ -1,81 +0,0 @@
-/*
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
- * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok at emcraft.com
- *
- * Authors: Nick.Spence at freescale.com
- *          Wilson.Lo at freescale.com
- *          scottwood at freescale.com
- *
- * This files is  mostly identical to the original from
- * board\freescale\mpc8315erdb\sdram.c
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc83xx.h>
-
-#include <asm/bitops.h>
-#include <asm/io.h>
-
-#include <asm/processor.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* Fixed sdram init -- doesn't use serial presence detect.
- *
- * This is useful for faster booting in configs where the RAM is unlikely
- * to be changed, or for things like NAND booting where space is tight.
- */
-static long fixed_sdram(void)
-{
-	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
-	u32 msize_log2 = __ilog2(msize);
-
-	out_be32(&im->sysconf.ddrlaw[0].bar,
-			CONFIG_SYS_DDR_SDRAM_BASE  & 0xfffff000);
-	out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
-	out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
-
-	out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
-	out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
-
-	/* Currently we use only one CS, so disable the other bank. */
-	out_be32(&im->ddr.cs_config[1], 0);
-
-	out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
-	out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
-	out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
-	out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
-	out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
-
-	out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
-	out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
-	out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
-	out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
-
-	out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
-	sync();
-
-	/* enable DDR controller */
-	setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
-	sync();
-
-	return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
-}
-
-phys_size_t initdram(int board_type)
-{
-	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-	u32 msize;
-
-	if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
-		return -1;
-
-	/* DDR SDRAM */
-	msize = fixed_sdram();
-
-	/* return total bus SDRAM size(bytes)  -- DDR */
-	return msize;
-}

board/freescale/mpc8313erdb/Kconfig deleted +0 -12

deleted file mode 100644
index 145608f..0000000
@@ -1,12 +0,0 @@
-if TARGET_MPC8313ERDB
-
-config SYS_BOARD
-	default "mpc8313erdb"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "MPC8313ERDB"
-
-endif

board/freescale/mpc8313erdb/MAINTAINERS deleted +0 -9

deleted file mode 100644
index 807fb0b..0000000
@@ -1,9 +0,0 @@
-MPC8313ERDB BOARD
-#M:	-
-S:	Maintained
-F:	board/freescale/mpc8313erdb/
-F:	include/configs/MPC8313ERDB.h
-F:	configs/MPC8313ERDB_33_defconfig
-F:	configs/MPC8313ERDB_66_defconfig
-F:	configs/MPC8313ERDB_NAND_33_defconfig
-F:	configs/MPC8313ERDB_NAND_66_defconfig

board/freescale/mpc8313erdb/Makefile deleted +0 -8

deleted file mode 100644
index 77fad75..0000000
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= mpc8313erdb.o sdram.o

board/freescale/mpc8313erdb/README deleted +0 -111

deleted file mode 100644
index be7ef32..0000000
@@ -1,111 +0,0 @@
-Freescale MPC8313ERDB Board
------------------------------------------
-
-1.	Board Switches and Jumpers
-
-	S3 is used to set CONFIG_SYS_RESET_SOURCE.
-
-	To boot the image at 0xFE000000 in NOR flash, use these DIP
-	switch settings for S3 S4:
-
-	+------+	+------+
-	|      |	| **** |
-	| **** |	|      |
-	+------+ ON	+------+ ON
-	  4321		  4321
-	(where the '*' indicates the position of the tab of the switch.)
-
-	To boot the image at the beginning of NAND flash, use these
-	DIP switch settings for S3 S4:
-
-	+------+	+------+
-	| *    |	|  *** |
-	|  *** |	| *    |
-	+------+ ON	+------+ ON
-	  4321		  4321
-	(where the '*' indicates the position of the tab of the switch.)
-
-	When booting from NAND, use u-boot-nand.bin, not u-boot.bin.
-
-2.	Memory Map
-	The memory map looks like this:
-
-	0x0000_0000	0x07ff_ffff	DDR		 128M
-	0x8000_0000	0x8fff_ffff	PCI MEM		 256M
-	0x9000_0000	0x9fff_ffff	PCI_MMIO	 256M
-	0xe000_0000	0xe00f_ffff	IMMR		 1M
-	0xe200_0000	0xe20f_ffff	PCI IO		 16M
-	0xe280_0000	0xe280_7fff	NAND FLASH (CS1) 32K
-	0xf000_0000	0xf001_ffff	VSC7385 (CS2)	 128K
-	0xfa00_0000	0xfa00_7fff	Board Status/	 32K
-					LED Control (CS3)
-	0xfe00_0000	0xfe7f_ffff	NOR FLASH (CS0)	 8M
-
-	When booting from NAND, NAND flash is CS0 and NOR flash
-	is CS1.
-
-3.	Definitions
-
-3.1	Explanation of NEW definitions in:
-
-	include/configs/MPC8313ERDB.h
-
-	CONFIG_MPC83xx		MPC83xx family
-	CONFIG_MPC831x		MPC831x specific
-	CONFIG_MPC8313ERDB	MPC8313ERDB board specific
-
-4.	Compilation
-
-	Assuming you're using BASH (or similar) as your shell:
-
-	export CROSS_COMPILE=your-cross-compiler-prefix-
-	make distclean
-	make MPC8313ERDB_XXX_config
-	(where XXX is:
-	   33 - 33 MHz oscillator, boot from NOR flash
-	   66 - 66 MHz oscillator, boot from NOR flash
-	   NAND_33 - 33 MHz oscillator, boot from NAND flash
-	   NAND_66 - 66 MHz oscillator, boot from NAND flash)
-	make
-
-5.	Downloading and Flashing Images
-
-5.1	Reflash U-boot Image using U-boot
-
-	NOR flash:
-
-	=>run tftpflash
-
-	You may want to try
-	=>tftpboot $loadaddr $uboot
-	first, to make sure that the TFTP load will succeed before it
-	goes ahead and wipes out your current firmware.  And of course,
-	have an alternate means of programming the flash available
-	if the new u-boot doesn't boot.
-
-	NAND flash:
-
-	=>tftpboot $loadaddr <filename>
-	=>nand erase 0 0x80000
-	=>nand write $loadaddr 0 0x80000
-
-	...where 0x80000 is the filesize rounded up to
-	the next 0x20000 increment.
-
-5.2	Downloading and Booting Linux Kernel
-
-	Ensure that all networking-related environment variables are set
-	properly (including ipaddr, serverip, gatewayip (if needed),
-	netmask, ethaddr, eth1addr, rootpath (if using NFS root),
-	fdtfile, and bootfile).
-
-	Then, do one of the following, depending on whether you
-	want an NFS root or a ramdisk root:
-
-	=>run nfsboot
-	or
-	=>run ramboot
-
-6	Notes
-
-	The console baudrate for MPC8313ERDB is 115200bps.

board/freescale/mpc8313erdb/mpc8313erdb.c deleted +0 -157

deleted file mode 100644
index eac193e..0000000
@@ -1,157 +0,0 @@
-/*
- * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
- *
- * Author: Scott Wood <[email protected]>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#if defined(CONFIG_OF_LIBFDT)
-#include <libfdt.h>
-#endif
-#include <pci.h>
-#include <mpc83xx.h>
-#include <vsc7385.h>
-#include <ns16550.h>
-#include <nand.h>
-#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
-#include <asm/gpio.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
-#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
-	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-
-	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
-		gd->flags |= GD_FLG_SILENT;
-#endif
-#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
-	mpc83xx_gpio_init_f();
-#endif
-
-	return 0;
-}
-
-int board_early_init_r(void)
-{
-#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
-	mpc83xx_gpio_init_r();
-#endif
-
-	return 0;
-}
-
-int checkboard(void)
-{
-	puts("Board: Freescale MPC8313ERDB\n");
-	return 0;
-}
-
-#ifndef CONFIG_SPL_BUILD
-static struct pci_region pci_regions[] = {
-	{
-		.bus_start = CONFIG_SYS_PCI1_MEM_BASE,
-		.phys_start = CONFIG_SYS_PCI1_MEM_PHYS,
-		.size = CONFIG_SYS_PCI1_MEM_SIZE,
-		.flags = PCI_REGION_MEM | PCI_REGION_PREFETCH
-	},
-	{
-		.bus_start = CONFIG_SYS_PCI1_MMIO_BASE,
-		.phys_start = CONFIG_SYS_PCI1_MMIO_PHYS,
-		.size = CONFIG_SYS_PCI1_MMIO_SIZE,
-		.flags = PCI_REGION_MEM
-	},
-	{
-		.bus_start = CONFIG_SYS_PCI1_IO_BASE,
-		.phys_start = CONFIG_SYS_PCI1_IO_PHYS,
-		.size = CONFIG_SYS_PCI1_IO_SIZE,
-		.flags = PCI_REGION_IO
-	}
-};
-
-void pci_init_board(void)
-{
-	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
-	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
-	struct pci_region *reg[] = { pci_regions };
-
-	/* Enable all 3 PCI_CLK_OUTPUTs. */
-	clk->occr |= 0xe0000000;
-
-	/*
-	 * Configure PCI Local Access Windows
-	 */
-	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
-	pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
-
-	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
-	pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
-
-	mpc83xx_pci_init(1, reg);
-}
-
-/*
- * Miscellaneous late-boot configurations
- *
- * If a VSC7385 microcode image is present, then upload it.
-*/
-int misc_init_r(void)
-{
-	int rc = 0;
-
-#ifdef CONFIG_VSC7385_IMAGE
-	if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
-		CONFIG_VSC7385_IMAGE_SIZE)) {
-		puts("Failure uploading VSC7385 microcode.\n");
-		rc = 1;
-	}
-#endif
-
-	return rc;
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI
-	ft_pci_setup(blob, bd);
-#endif
-
-	return 0;
-}
-#endif
-#else /* CONFIG_SPL_BUILD */
-void board_init_f(ulong bootflag)
-{
-	board_early_init_f();
-	NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
-		     CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
-	puts("NAND boot... ");
-	init_timebase();
-	initdram(0);
-	relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, (gd_t *)gd,
-		      CONFIG_SYS_NAND_U_BOOT_RELOC);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
-	nand_boot();
-}
-
-void putc(char c)
-{
-	if (gd->flags & GD_FLG_SILENT)
-		return;
-
-	if (c == '\n')
-		NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r');
-
-	NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c);
-}
-#endif

board/freescale/mpc8313erdb/sdram.c deleted +0 -124

deleted file mode 100644
index 6282c3d..0000000
@@ -1,124 +0,0 @@
-/*
- * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
- *
- * Authors: Nick.Spence at freescale.com
- *          Wilson.Lo at freescale.com
- *          scottwood at freescale.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc83xx.h>
-#include <spd_sdram.h>
-
-#include <asm/bitops.h>
-#include <asm/io.h>
-
-#include <asm/processor.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
-static void resume_from_sleep(void)
-{
-	u32 magic = *(u32 *)0;
-
-	typedef void (*func_t)(void);
-	func_t resume = *(func_t *)4;
-
-	if (magic == 0xf5153ae5)
-		resume();
-
-	gd->flags &= ~GD_FLG_SILENT;
-	puts("\nResume from sleep failed: bad magic word\n");
-}
-#endif
-
-/* Fixed sdram init -- doesn't use serial presence detect.
- *
- * This is useful for faster booting in configs where the RAM is unlikely
- * to be changed, or for things like NAND booting where space is tight.
- */
-static long fixed_sdram(void)
-{
-	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
-
-#ifndef CONFIG_SYS_RAMBOOT
-	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
-	u32 msize_log2 = __ilog2(msize);
-
-	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
-	im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
-	im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
-
-	/*
-	 * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
-	 * or the DDR2 controller may fail to initialize correctly.
-	 */
-	__udelay(50000);
-
-#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
-#warning Chip select bounds is only configurable in 16MB increments
-#endif
-	im->ddr.csbnds[0].csbnds =
-		((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
-		(((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
-			CSBNDS_EA);
-	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
-
-	/* Currently we use only one CS, so disable the other bank. */
-	im->ddr.cs_config[1] = 0;
-
-	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
-	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
-	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
-	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
-	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
-
-#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
-	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
-		im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG | SDRAM_CFG_BI;
-	else
-#endif
-		im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG;
-
-	im->ddr.sdram_cfg2 = CONFIG_SYS_SDRAM_CFG2;
-	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
-	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE_2;
-
-	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
-	sync();
-
-	/* enable DDR controller */
-	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
-#endif
-
-	return msize;
-}
-
-phys_size_t initdram(int board_type)
-{
-	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile fsl_lbc_t *lbc = &im->im_lbc;
-	u32 msize;
-
-	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
-		return -1;
-
-	/* DDR SDRAM - Main SODIMM */
-	msize = fixed_sdram();
-
-	/* Local Bus setup lbcr and mrtpr */
-	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
-	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
-	sync();
-
-#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
-	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
-		resume_from_sleep();
-#endif
-
-	/* return total bus SDRAM size(bytes)  -- DDR */
-	return msize;
-}

board/freescale/mpc8315erdb/Kconfig deleted +0 -12

deleted file mode 100644
index f76b0d1..0000000
@@ -1,12 +0,0 @@
-if TARGET_MPC8315ERDB
-
-config SYS_BOARD
-	default "mpc8315erdb"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "MPC8315ERDB"
-
-endif

board/freescale/mpc8315erdb/MAINTAINERS deleted +0 -6

deleted file mode 100644
index 938c152..0000000
@@ -1,6 +0,0 @@
-MPC8315ERDB BOARD
-M:	Dave Liu <[email protected]>
-S:	Maintained
-F:	board/freescale/mpc8315erdb/
-F:	include/configs/MPC8315ERDB.h
-F:	configs/MPC8315ERDB_defconfig

board/freescale/mpc8315erdb/Makefile deleted +0 -8

deleted file mode 100644
index fbb68c5..0000000
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= mpc8315erdb.o sdram.o

board/freescale/mpc8315erdb/README deleted +0 -105

deleted file mode 100644
index b32132d..0000000
@@ -1,105 +0,0 @@
-Freescale MPC8315ERDB Board
------------------------------------------
-
-1.	Board Switches and Jumpers
-
-	S3 is used to set CONFIG_SYS_RESET_SOURCE.
-
-	To boot the image at 0xFE000000 in NOR flash, use these DIP
-	switch settings for S3 S4:
-
-	+------+	+------+
-	|      |	| **** |
-	| **** |	|      |
-	+------+ ON	+------+ ON
-	  4321		  4321
-	(where the '*' indicates the position of the tab of the switch.)
-
-	To boot the image at the beginning of NAND flash, use these
-	DIP switch settings for S3 S4:
-
-	+------+	+------+
-	| *    |	|  *** |
-	|  *** |	| *    |
-	+------+ ON	+------+ ON
-	  4321		  4321
-	(where the '*' indicates the position of the tab of the switch.)
-
-	When booting from NAND, use u-boot-nand.bin, not u-boot.bin.
-
-2.	Memory Map
-	The memory map looks like this:
-
-	0x0000_0000	0x07ff_ffff	DDR		 128M
-	0x8000_0000	0x8fff_ffff	PCI MEM		 256M
-	0x9000_0000	0x9fff_ffff	PCI_MMIO	 256M
-	0xe000_0000	0xe00f_ffff	IMMR		 1M
-	0xe030_0000	0xe03f_ffff	PCI IO		 1M
-	0xe060_0000	0xe060_7fff	NAND FLASH (CS1) 32K
-	0xfe00_0000	0xfe7f_ffff	NOR FLASH (CS0)	 8M
-
-	When booting from NAND, NAND flash is CS0 and NOR flash
-	is CS1.
-
-3.	Definitions
-
-3.1	Explanation of NEW definitions in:
-
-	include/configs/MPC8315ERDB.h
-
-	CONFIG_MPC83xx		MPC83xx family
-	CONFIG_MPC831x		MPC831x specific
-	CONFIG_MPC8315		MPC8315 specific
-	CONFIG_MPC8315ERDB	MPC8315ERDB board specific
-
-4.	Compilation
-
-	Assuming you're using BASH (or similar) as your shell:
-
-	export CROSS_COMPILE=your-cross-compiler-prefix-
-	make distclean
-	make MPC8315ERDB_config (or MPC8315ERDB_NAND_config for u-boot-nand.bin)
-	make all
-
-5.	Downloading and Flashing Images
-
-5.1	Reflash U-boot Image using U-boot
-
-	NOR flash:
-
-	tftp 40000 u-boot.bin
-	protect off all
-	erase fe000000 fe1fffff
-
-	cp.b 40000 fe000000 xxxx
-	protect on all
-
-	You have to supply the correct byte count with 'xxxx'
-	from the TFTP result log.
-
-	NAND flash:
-
-	=>tftpboot $loadaddr <filename>
-	=>nand erase 0 0x80000
-	=>nand write $loadaddr 0 0x80000
-
-	...where 0x80000 is the filesize rounded up to
-	the next 0x20000 increment.
-
-5.2	Downloading and Booting Linux Kernel
-
-	Ensure that all networking-related environment variables are set
-	properly (including ipaddr, serverip, gatewayip (if needed),
-	netmask, ethaddr, eth1addr, rootpath (if using NFS root),
-	fdtfile, and bootfile).
-
-	Then, do one of the following, depending on whether you
-	want an NFS root or a ramdisk root:
-
-	=>run nfsboot
-	or
-	=>run ramboot
-
-6	Notes
-
-	The console baudrate for MPC8315ERDB is 115200bps.

board/freescale/mpc8315erdb/mpc8315erdb.c deleted +0 -246

deleted file mode 100644
index ed611c5..0000000
@@ -1,246 +0,0 @@
-/*
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
- *
- * Author: Scott Wood <[email protected]>
- *         Dave Liu <[email protected]>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <hwconfig.h>
-#include <i2c.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <pci.h>
-#include <mpc83xx.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <ns16550.h>
-#include <nand.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
-	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-
-	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
-		gd->flags |= GD_FLG_SILENT;
-
-	return 0;
-}
-
-#ifndef CONFIG_NAND_SPL
-
-static u8 read_board_info(void)
-{
-	u8 val8;
-	i2c_set_bus_num(0);
-
-	if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0)
-		return val8;
-	else
-		return 0;
-}
-
-int checkboard(void)
-{
-	static const char * const rev_str[] = {
-		"0.0",
-		"0.1",
-		"1.0",
-		"1.1",
-		"<unknown>",
-	};
-	u8 info;
-	int i;
-
-	info = read_board_info();
-	i = (!info) ? 4: info & 0x03;
-
-	printf("Board: Freescale MPC8315ERDB Rev %s\n", rev_str[i]);
-
-	return 0;
-}
-
-static struct pci_region pci_regions[] = {
-	{
-		bus_start: CONFIG_SYS_PCI_MEM_BASE,
-		phys_start: CONFIG_SYS_PCI_MEM_PHYS,
-		size: CONFIG_SYS_PCI_MEM_SIZE,
-		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
-	},
-	{
-		bus_start: CONFIG_SYS_PCI_MMIO_BASE,
-		phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
-		size: CONFIG_SYS_PCI_MMIO_SIZE,
-		flags: PCI_REGION_MEM
-	},
-	{
-		bus_start: CONFIG_SYS_PCI_IO_BASE,
-		phys_start: CONFIG_SYS_PCI_IO_PHYS,
-		size: CONFIG_SYS_PCI_IO_SIZE,
-		flags: PCI_REGION_IO
-	}
-};
-
-static struct pci_region pcie_regions_0[] = {
-	{
-		.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
-		.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
-		.size = CONFIG_SYS_PCIE1_MEM_SIZE,
-		.flags = PCI_REGION_MEM,
-	},
-	{
-		.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
-		.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
-		.size = CONFIG_SYS_PCIE1_IO_SIZE,
-		.flags = PCI_REGION_IO,
-	},
-};
-
-static struct pci_region pcie_regions_1[] = {
-	{
-		.bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
-		.phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
-		.size = CONFIG_SYS_PCIE2_MEM_SIZE,
-		.flags = PCI_REGION_MEM,
-	},
-	{
-		.bus_start = CONFIG_SYS_PCIE2_IO_BASE,
-		.phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
-		.size = CONFIG_SYS_PCIE2_IO_SIZE,
-		.flags = PCI_REGION_IO,
-	},
-};
-
-void pci_init_board(void)
-{
-	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile sysconf83xx_t *sysconf = &immr->sysconf;
-	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
-	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
-	volatile law83xx_t *pcie_law = sysconf->pcielaw;
-	struct pci_region *reg[] = { pci_regions };
-	struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
-
-	/* Enable all 3 PCI_CLK_OUTPUTs. */
-	clk->occr |= 0xe0000000;
-
-	/*
-	 * Configure PCI Local Access Windows
-	 */
-	pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
-	pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
-
-	pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
-	pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
-
-	mpc83xx_pci_init(1, reg);
-
-	/* Configure the clock for PCIE controller */
-	clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
-				    SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
-
-	/* Deassert the resets in the control register */
-	out_be32(&sysconf->pecr1, 0xE0008000);
-	out_be32(&sysconf->pecr2, 0xE0008000);
-	udelay(2000);
-
-	/* Configure PCI Express Local Access Windows */
-	out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
-	out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
-
-	out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
-	out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
-
-	mpc83xx_pcie_init(2, pcie_reg);
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-void fdt_tsec1_fixup(void *fdt, bd_t *bd)
-{
-	const char disabled[] = "disabled";
-	const char *path;
-	int ret;
-
-	if (hwconfig_arg_cmp("board_type", "tsec1")) {
-		return;
-	} else if (!hwconfig_arg_cmp("board_type", "ulpi")) {
-		printf("NOTICE: No or unknown board_type hwconfig specified.\n"
-		       "        Assuming board with TSEC1.\n");
-		return;
-	}
-
-	ret = fdt_path_offset(fdt, "/aliases");
-	if (ret < 0) {
-		printf("WARNING: can't find /aliases node\n");
-		return;
-	}
-
-	path = fdt_getprop(fdt, ret, "ethernet0", NULL);
-	if (!path) {
-		printf("WARNING: can't find ethernet0 alias\n");
-		return;
-	}
-
-	do_fixup_by_path(fdt, path, "status", disabled, sizeof(disabled), 1);
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI
-	ft_pci_setup(blob, bd);
-#endif
-	fdt_fixup_dr_usb(blob, bd);
-	fdt_tsec1_fixup(blob, bd);
-
-	return 0;
-}
-#endif
-
-int board_eth_init(bd_t *bis)
-{
-	cpu_eth_init(bis);	/* Initialize TSECs first */
-	return pci_eth_init(bis);
-}
-
-#else /* CONFIG_NAND_SPL */
-
-int checkboard(void)
-{
-	puts("Board: Freescale MPC8315ERDB\n");
-	return 0;
-}
-
-void board_init_f(ulong bootflag)
-{
-	board_early_init_f();
-	NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
-		     CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
-	puts("NAND boot... ");
-	init_timebase();
-	initdram(0);
-	relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd,
-		      CONFIG_SYS_NAND_U_BOOT_RELOC);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
-	nand_boot();
-}
-
-void putc(char c)
-{
-	if (gd->flags & GD_FLG_SILENT)
-		return;
-
-	if (c == '\n')
-		NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r');
-
-	NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c);
-}
-
-#endif /* CONFIG_NAND_SPL */

board/freescale/mpc8315erdb/sdram.c deleted +0 -111

deleted file mode 100644
index 6c94312..0000000
@@ -1,111 +0,0 @@
-/*
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
- *
- * Authors: Nick.Spence at freescale.com
- *          Wilson.Lo at freescale.com
- *          scottwood at freescale.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc83xx.h>
-#include <spd_sdram.h>
-
-#include <asm/bitops.h>
-#include <asm/io.h>
-
-#include <asm/processor.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void resume_from_sleep(void)
-{
-	u32 magic = *(u32 *)0;
-
-	typedef void (*func_t)(void);
-	func_t resume = *(func_t *)4;
-
-	if (magic == 0xf5153ae5)
-		resume();
-
-	gd->flags &= ~GD_FLG_SILENT;
-	puts("\nResume from sleep failed: bad magic word\n");
-}
-
-/* Fixed sdram init -- doesn't use serial presence detect.
- *
- * This is useful for faster booting in configs where the RAM is unlikely
- * to be changed, or for things like NAND booting where space is tight.
- */
-#ifndef CONFIG_SYS_RAMBOOT
-static long fixed_sdram(void)
-{
-	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
-	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
-	u32 msize_log2 = __ilog2(msize);
-
-	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE  & 0xfffff000;
-	im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
-	im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
-
-	/*
-	 * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
-	 * or the DDR2 controller may fail to initialize correctly.
-	 */
-	__udelay(50000);
-
-	im->ddr.csbnds[0].csbnds = (msize - 1) >> 24;
-	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
-
-	/* Currently we use only one CS, so disable the other bank. */
-	im->ddr.cs_config[1] = 0;
-
-	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
-	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
-	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
-	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
-	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
-
-	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
-		im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG | SDRAM_CFG_BI;
-	else
-		im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
-
-	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
-	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
-	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
-
-	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
-	sync();
-
-	/* enable DDR controller */
-	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
-	sync();
-
-	return msize;
-}
-#else
-static long fixed_sdram(void)
-{
-	return CONFIG_SYS_DDR_SIZE * 1024 * 1024;
-}
-#endif /* CONFIG_SYS_RAMBOOT */
-
-phys_size_t initdram(int board_type)
-{
-	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
-	u32 msize;
-
-	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
-		return -1;
-
-	/* DDR SDRAM */
-	msize = fixed_sdram();
-
-	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
-		resume_from_sleep();
-
-	/* return total bus SDRAM size(bytes)  -- DDR */
-	return msize;
-}

board/freescale/mpc8323erdb/Kconfig deleted +0 -12

deleted file mode 100644
index acf8122..0000000
@@ -1,12 +0,0 @@
-if TARGET_MPC8323ERDB
-
-config SYS_BOARD
-	default "mpc8323erdb"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "MPC8323ERDB"
-
-endif

board/freescale/mpc8323erdb/MAINTAINERS deleted +0 -6

deleted file mode 100644
index 05057c0..0000000
@@ -1,6 +0,0 @@
-MPC8323ERDB BOARD
-M:	Michael Barkowski <[email protected]>
-S:	Maintained
-F:	board/freescale/mpc8323erdb/
-F:	include/configs/MPC8323ERDB.h
-F:	configs/MPC8323ERDB_defconfig

board/freescale/mpc8323erdb/Makefile deleted +0 -8

deleted file mode 100644
index f2e7497..0000000
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= mpc8323erdb.o

board/freescale/mpc8323erdb/README deleted +0 -71

deleted file mode 100644
index 6f89829..0000000
@@ -1,71 +0,0 @@
-Freescale MPC8323ERDB Board
------------------------------------------
-
-1.	Memory Map
-	The memory map looks like this:
-
-	0x0000_0000	0x03ff_ffff	DDR		 64M
-	0x8000_0000	0x8fff_ffff	PCI MEM		 256M
-	0x9000_0000	0x9fff_ffff	PCI_MMIO	 256M
-	0xe000_0000	0xe00f_ffff	IMMR		 1M
-	0xd000_0000	0xd3ff_ffff	PCI IO		 64M
-	0xfe00_0000	0xfeff_ffff	NOR FLASH (CS0)	 16M
-
-2.	Compilation
-
-	Assuming you're using BASH (or similar) as your shell:
-
-	export CROSS_COMPILE=your-cross-compiler-prefix-
-	make distclean
-	make MPC8323ERDB_config
-	make
-
-3.	Downloading and Flashing Images
-
-3.1	Reflash U-boot Image using U-boot
-
-	N.b, have an alternate means of programming
-	the flash available if the new u-boot doesn't boot.
-
-	First try a:
-
-	tftpboot $loadaddr $uboot
-
-	to make sure that the TFTP load will succeed before
-	an erase goes ahead and wipes out your current firmware.
-	Then do a:
-
-	run tftpflash
-
-	which is a shorter version of the manual sequence:
-
-	tftp $loadaddr u-boot.bin
-	protect off fe000000 +$filesize
-	erase fe000000 +$filesize
-	cp.b $loadaddr fe000000 $filesize
-
-	To keep your old u-boot's environment variables, do a:
-
-	saveenv
-
-	prior to resetting the board.
-
-3.2	Downloading and Booting Linux Kernel
-
-	Ensure that all networking-related environment variables are set
-	properly (including ipaddr, serverip, gatewayip (if needed),
-	netmask, ethaddr, eth1addr, rootpath (if using NFS root),
-	fdtfile, and bootfile).
-
-	Then, do one of the following, depending on whether you
-	want an NFS root or a ramdisk root:
-
-	run nfsboot
-
-	or
-
-	run ramboot
-
-4	Notes
-
-	The console baudrate for MPC8323ERDB is 115200bps.

board/freescale/mpc8323erdb/mpc8323erdb.c deleted +0 -222

deleted file mode 100644
index 0a0152a..0000000
@@ -1,222 +0,0 @@
-/*
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
- *
- * Michael Barkowski <[email protected]>
- * Based on mpc832xmds file by Dave Liu <[email protected]>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc83xx.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <command.h>
-#include <libfdt.h>
-#if defined(CONFIG_PCI)
-#include <pci.h>
-#endif
-#include <asm/mmu.h>
-
-const qe_iop_conf_t qe_iop_conf_tab[] = {
-	/* UCC3 */
-	{1,  0, 1, 0, 1}, /* TxD0 */
-	{1,  1, 1, 0, 1}, /* TxD1 */
-	{1,  2, 1, 0, 1}, /* TxD2 */
-	{1,  3, 1, 0, 1}, /* TxD3 */
-	{1,  9, 1, 0, 1}, /* TxER */
-	{1, 12, 1, 0, 1}, /* TxEN */
-	{3, 24, 2, 0, 1}, /* TxCLK->CLK10 */
-
-	{1,  4, 2, 0, 1}, /* RxD0 */
-	{1,  5, 2, 0, 1}, /* RxD1 */
-	{1,  6, 2, 0, 1}, /* RxD2 */
-	{1,  7, 2, 0, 1}, /* RxD3 */
-	{1,  8, 2, 0, 1}, /* RxER */
-	{1, 10, 2, 0, 1}, /* RxDV */
-	{0, 13, 2, 0, 1}, /* RxCLK->CLK9 */
-	{1, 11, 2, 0, 1}, /* COL */
-	{1, 13, 2, 0, 1}, /* CRS */
-
-	/* UCC2 */
-	{0, 18, 1, 0, 1}, /* TxD0 */
-	{0, 19, 1, 0, 1}, /* TxD1 */
-	{0, 20, 1, 0, 1}, /* TxD2 */
-	{0, 21, 1, 0, 1}, /* TxD3 */
-	{0, 27, 1, 0, 1}, /* TxER */
-	{0, 30, 1, 0, 1}, /* TxEN */
-	{3, 23, 2, 0, 1}, /* TxCLK->CLK3 */
-
-	{0, 22, 2, 0, 1}, /* RxD0 */
-	{0, 23, 2, 0, 1}, /* RxD1 */
-	{0, 24, 2, 0, 1}, /* RxD2 */
-	{0, 25, 2, 0, 1}, /* RxD3 */
-	{0, 26, 1, 0, 1}, /* RxER */
-	{0, 28, 2, 0, 1}, /* Rx_DV */
-	{3, 21, 2, 0, 1}, /* RxCLK->CLK16 */
-	{0, 29, 2, 0, 1}, /* COL */
-	{0, 31, 2, 0, 1}, /* CRS */
-
-	{3,  4, 3, 0, 2}, /* MDIO */
-	{3,  5, 1, 0, 2}, /* MDC */
-
-	{0,  0, 0, 0, QE_IOP_TAB_END}, /* END of table */
-};
-
-int fixed_sdram(void);
-
-phys_size_t initdram(int board_type)
-{
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	u32 msize = 0;
-
-	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
-		return -1;
-
-	/* DDR SDRAM - Main SODIMM */
-	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
-
-	msize = fixed_sdram();
-
-	/* return total bus SDRAM size(bytes)  -- DDR */
-	return (msize * 1024 * 1024);
-}
-
-/*************************************************************************
- *  fixed sdram init -- doesn't use serial presence detect.
- ************************************************************************/
-int fixed_sdram(void)
-{
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	u32 msize = 0;
-	u32 ddr_size;
-	u32 ddr_size_log2;
-
-	msize = CONFIG_SYS_DDR_SIZE;
-	for (ddr_size = msize << 20, ddr_size_log2 = 0;
-	     (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
-		if (ddr_size & 1) {
-			return -1;
-		}
-	}
-	im->sysconf.ddrlaw[0].ar =
-	    LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
-	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
-	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
-	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
-	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
-	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
-	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
-	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
-	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
-	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
-	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
-	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
-	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
-	__asm__ __volatile__ ("sync");
-	udelay(200);
-
-	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
-	__asm__ __volatile__ ("sync");
-	return msize;
-}
-
-int checkboard(void)
-{
-	puts("Board: Freescale MPC8323ERDB\n");
-	return 0;
-}
-
-static struct pci_region pci_regions[] = {
-	{
-		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
-		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
-		size: CONFIG_SYS_PCI1_MEM_SIZE,
-		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
-	},
-	{
-		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
-		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
-		size: CONFIG_SYS_PCI1_MMIO_SIZE,
-		flags: PCI_REGION_MEM
-	},
-	{
-		bus_start: CONFIG_SYS_PCI1_IO_BASE,
-		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
-		size: CONFIG_SYS_PCI1_IO_SIZE,
-		flags: PCI_REGION_IO
-	}
-};
-
-void pci_init_board(void)
-{
-	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
-	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
-	struct pci_region *reg[] = { pci_regions };
-
-	/* Enable all 3 PCI_CLK_OUTPUTs. */
-	clk->occr |= 0xe0000000;
-
-	/* Configure PCI Local Access Windows */
-	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
-	pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
-
-	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
-	pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
-
-	mpc83xx_pci_init(1, reg);
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI
-	ft_pci_setup(blob, bd);
-#endif
-
-	return 0;
-}
-#endif
-
-#if defined(CONFIG_SYS_I2C_MAC_OFFSET)
-int mac_read_from_eeprom(void)
-{
-	uchar buf[28];
-	char str[18];
-	int i = 0;
-	unsigned int crc = 0;
-	unsigned char enetvar[32];
-
-	/* Read MAC addresses from EEPROM */
-	if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, CONFIG_SYS_I2C_MAC_OFFSET, buf, 28)) {
-		printf("\nEEPROM @ 0x%02x read FAILED!!!\n",
-		       CONFIG_SYS_I2C_EEPROM_ADDR);
-	} else {
-		uint32_t crc_buf;
-
-		memcpy(&crc_buf, &buf[24], sizeof(uint32_t));
-
-		if (crc32(crc, buf, 24) == crc_buf) {
-			printf("Reading MAC from EEPROM\n");
-			for (i = 0; i < 4; i++) {
-				if (memcmp(&buf[i * 6], "\0\0\0\0\0\0", 6)) {
-					sprintf(str,
-						"%02X:%02X:%02X:%02X:%02X:%02X",
-						buf[i * 6], buf[i * 6 + 1],
-						buf[i * 6 + 2], buf[i * 6 + 3],
-						buf[i * 6 + 4], buf[i * 6 + 5]);
-					sprintf((char *)enetvar,
-						i ? "eth%daddr" : "ethaddr", i);
-					setenv((char *)enetvar, str);
-				}
-			}
-		}
-	}
-	return 0;
-}
-#endif				/* CONFIG_I2C_MAC_OFFSET */

board/freescale/mpc832xemds/Kconfig deleted +0 -12

deleted file mode 100644
index e4cfa15..0000000
@@ -1,12 +0,0 @@
-if TARGET_MPC832XEMDS
-
-config SYS_BOARD
-	default "mpc832xemds"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "MPC832XEMDS"
-
-endif

board/freescale/mpc832xemds/MAINTAINERS deleted +0 -10

deleted file mode 100644
index 56d7073..0000000
@@ -1,10 +0,0 @@
-MPC832XEMDS BOARD
-M:	Dave Liu <[email protected]>
-S:	Maintained
-F:	board/freescale/mpc832xemds/
-F:	include/configs/MPC832XEMDS.h
-F:	configs/MPC832XEMDS_defconfig
-F:	configs/MPC832XEMDS_ATM_defconfig
-F:	configs/MPC832XEMDS_HOST_33_defconfig
-F:	configs/MPC832XEMDS_HOST_66_defconfig
-F:	configs/MPC832XEMDS_SLAVE_defconfig

board/freescale/mpc832xemds/Makefile deleted +0 -9

deleted file mode 100644
index 6676351..0000000
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y += mpc832xemds.o
-obj-$(CONFIG_PCI) += pci.o

board/freescale/mpc832xemds/README deleted +0 -128

deleted file mode 100644
index 4142aa9..0000000
@@ -1,128 +0,0 @@
-Freescale MPC832XEMDS Board
------------------------------------------
-1. Board Switches and Jumpers
-1.0 There are five Dual-In-Line Packages(DIP) Switches on MPC832XE SYS board
-	For some reason, the HW designers describe the switch settings
-	in terms of 0 and 1, and then map that to physical switches where
-	the label "On" refers to logic 0 and "Off" is logic 1.
-
-	Switch bits are numbered 1 through, like, 4 6 8 or 10, but the
-	bits may contribute to signals that are numbered based at 0,
-	and some of those signals may be high-bit-number-0 too.  Heed
-	well the names and labels and do not get confused.
-
-		"Off" == 1
-		"On"  == 0
-
-	SW3 is switch 18 as silk-screened onto the board.
-	SW4[8] is the bit labeled 8 on Switch 4.
-	SW5[1:6] refers to bits labeled 1 through 6 in order on switch 5.
-	SW6[7:1] refers to bits labeled 7 through 1 in order on switch 6.
-	SW7[1:8]= 0000_0001 refers to bits labeled 1 through 6 is set as "On"
-		and bits labeled 8 is set as "Off".
-
-1.1 For the MPC832XEMDS PROTO Board
-
-	First, make sure the board default setting is consistent with the document
-		 shipped with your board. Then apply the following setting:
-	SW3[1-8]= 0000_1000  (core PLL setting, core enable)
-	SW4[1-8]= 0001_0010  (Flash boot on local bus, system PLL setting)
-	SW5[1-8]= 0010_0110  (Boot from high end)
-	SW6[1-8]= 0011_0100  (Flash boot on 16 bit local bus)
-	SW7[1-8]= 1000_0011  (QE PLL setting)
-
-	ENET3/4 MII mode settings:
-	J1 1-2 (ETH3_TXER)
-	J2 2-3 (MII mode)
-	J3 2-3 (MII mode)
-	J4 2-3 (ADSL clockOscillator)
-	J5 1-2 (ETH4_TXER)
-	J6 2-3 (ClockOscillator)
-	JP1 removed (don't force PORESET)
-	JP2 mounted (ETH4/2 MII)
-	JP3 mounted (ETH3 MII)
-	JP4 mounted (HRCW from BCSR)
-
-	ENET3/4 RMII mode settings:
-	J1 1-2 (ETH3_TXER)
-	J2 1-2 (RMII mode)
-	J3 1-2 (RMII mode)
-	J4 2-3 (ADSL clockOscillator)
-	J5 1-2 (ETH4_TXER)
-	J6 2-3 (ClockOscillator)
-	JP1 removed (don't force PORESET)
-	JP2 removed (ETH4/2 RMII)
-	JP3 removed (ETH3 RMII)
-	JP4 removed (HRCW from FLASH)
-
-	on board Oscillator: 66M
-
-
-2. Memory Map
-
-2.1 The memory map should look pretty much like this:
-
-	0x0000_0000	0x7fff_ffff	DDR			2G
-	0x8000_0000	0x8fff_ffff	PCI MEM prefetch	256M
-	0x9000_0000	0x9fff_ffff	PCI MEM non-prefetch	256M
-	0xc000_0000	0xdfff_ffff	Empty			512M
-	0xe000_0000	0xe01f_ffff	Int Mem Reg Space	2M
-	0xe020_0000	0xe02f_ffff	Empty			1M
-	0xe030_0000	0xe03f_ffff	PCI IO			1M
-	0xe040_0000	0xefff_ffff	Empty			252M
-	0xf400_0000	0xf7ff_ffff	Empty			64M
-	0xf800_0000	0xf800_7fff	BCSR on CS1		32K
-	0xf800_8000	0xf800_ffff	PIB CS2			32K
-	0xf801_0000	0xf801_7fff	PIB CS3			32K
-	0xfe00_0000	0xfeff_ffff	FLASH on CS0		16M
-
-
-3. Definitions
-
-3.1 Explanation of NEW definitions in:
-
-	include/configs/MPC832XEPB.h
-
-    CONFIG_MPC83xx	MPC83xx family for MPC8349, MPC8360 and MPC832x
-    CONFIG_MPC832x	MPC832x specific
-    CONFIG_MPC832XEMDS	MPC832XEMDS board specific
-
-4. Compilation
-
-	Assuming you're using BASH shell:
-
-		export CROSS_COMPILE=your-cross-compile-prefix
-		cd u-boot
-		make distclean
-		make MPC832XEMDS_config
-		make
-
-	MPC832x support PCI 33MHz and PCI 66MHz, to make u-boot support PCI:
-
-		1)Make sure the DIP SW support PCI mode as described in Section 1.1.
-
-		2)To Make U-Boot image support PCI 33MHz, use
-			Make MPC832XEMDS_HOST_33_config
-
-		3)To Make U-Boot image support PCI 66MHz, use
-			Make MPC832XEMDS_HOST_66M_config
-
-5. Downloading and Flashing Images
-
-5.0 Download over network:
-
-	tftp 10000 u-boot.bin
-
-5.1 Reflash U-boot Image using U-boot
-
-	tftp 20000 u-boot.bin
-	protect off fe000000 fe0fffff
-	erase fe000000 fe0fffff
-	cp.b 20000 fe000000 xxxx
-
-You have to supply the correct byte count with 'xxxx' from the TFTP result log.
-Maybe 3ffff will work too, that corresponds to the erased sectors.
-
-
-6. Notes
-	1) The console baudrate for MPC832XEMDS is 115200bps.

board/freescale/mpc832xemds/mpc832xemds.c deleted +0 -166

deleted file mode 100644
index adf4254..0000000
@@ -1,166 +0,0 @@
-/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
- *
- * Dave Liu <[email protected]>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc83xx.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <command.h>
-#if defined(CONFIG_PCI)
-#include <pci.h>
-#endif
-#include <asm/mmu.h>
-#if defined(CONFIG_OF_LIBFDT)
-#include <libfdt.h>
-#endif
-#if defined(CONFIG_PQ_MDS_PIB)
-#include "../common/pq-mds-pib.h"
-#endif
-
-const qe_iop_conf_t qe_iop_conf_tab[] = {
-	/* ETH3 */
-	{1,  0, 1, 0, 1}, /* TxD0 */
-	{1,  1, 1, 0, 1}, /* TxD1 */
-	{1,  2, 1, 0, 1}, /* TxD2 */
-	{1,  3, 1, 0, 1}, /* TxD3 */
-	{1,  9, 1, 0, 1}, /* TxER */
-	{1, 12, 1, 0, 1}, /* TxEN */
-	{3, 24, 2, 0, 1}, /* TxCLK->CLK10 */
-
-	{1,  4, 2, 0, 1}, /* RxD0 */
-	{1,  5, 2, 0, 1}, /* RxD1 */
-	{1,  6, 2, 0, 1}, /* RxD2 */
-	{1,  7, 2, 0, 1}, /* RxD3 */
-	{1,  8, 2, 0, 1}, /* RxER */
-	{1, 10, 2, 0, 1}, /* RxDV */
-	{0, 13, 2, 0, 1}, /* RxCLK->CLK9 */
-	{1, 11, 2, 0, 1}, /* COL */
-	{1, 13, 2, 0, 1}, /* CRS */
-
-	/* ETH4 */
-	{1, 18, 1, 0, 1}, /* TxD0 */
-	{1, 19, 1, 0, 1}, /* TxD1 */
-	{1, 20, 1, 0, 1}, /* TxD2 */
-	{1, 21, 1, 0, 1}, /* TxD3 */
-	{1, 27, 1, 0, 1}, /* TxER */
-	{1, 30, 1, 0, 1}, /* TxEN */
-	{3,  6, 2, 0, 1}, /* TxCLK->CLK8 */
-
-	{1, 22, 2, 0, 1}, /* RxD0 */
-	{1, 23, 2, 0, 1}, /* RxD1 */
-	{1, 24, 2, 0, 1}, /* RxD2 */
-	{1, 25, 2, 0, 1}, /* RxD3 */
-	{1, 26, 1, 0, 1}, /* RxER */
-	{1, 28, 2, 0, 1}, /* Rx_DV */
-	{3, 31, 2, 0, 1}, /* RxCLK->CLK7 */
-	{1, 29, 2, 0, 1}, /* COL */
-	{1, 31, 2, 0, 1}, /* CRS */
-
-	{3,  4, 3, 0, 2}, /* MDIO */
-	{3,  5, 1, 0, 2}, /* MDC */
-
-	{0,  0, 0, 0, QE_IOP_TAB_END}, /* END of table */
-};
-
-int board_early_init_f(void)
-{
-	volatile u8 *bcsr = (volatile u8 *)CONFIG_SYS_BCSR;
-
-	/* Enable flash write */
-	bcsr[9] &= ~0x08;
-
-	return 0;
-}
-
-int board_early_init_r(void)
-{
-#ifdef CONFIG_PQ_MDS_PIB
-	pib_init();
-#endif
-	return 0;
-}
-
-int fixed_sdram(void);
-
-phys_size_t initdram(int board_type)
-{
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	u32 msize = 0;
-
-	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
-		return -1;
-
-	/* DDR SDRAM - Main SODIMM */
-	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
-
-	msize = fixed_sdram();
-
-	/* return total bus SDRAM size(bytes)  -- DDR */
-	return (msize * 1024 * 1024);
-}
-
-/*************************************************************************
- *  fixed sdram init -- doesn't use serial presence detect.
- ************************************************************************/
-int fixed_sdram(void)
-{
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	u32 msize = 0;
-	u32 ddr_size;
-	u32 ddr_size_log2;
-
-	msize = CONFIG_SYS_DDR_SIZE;
-	for (ddr_size = msize << 20, ddr_size_log2 = 0;
-	     (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
-		if (ddr_size & 1) {
-			return -1;
-		}
-	}
-	im->sysconf.ddrlaw[0].ar =
-	    LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
-#if (CONFIG_SYS_DDR_SIZE != 128)
-#warning Currenly any ddr size other than 128 is not supported
-#endif
-	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
-	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
-	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
-	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
-	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
-	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
-	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
-	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
-	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
-	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
-	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
-	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
-	__asm__ __volatile__ ("sync");
-	udelay(200);
-
-	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
-	__asm__ __volatile__ ("sync");
-	return msize;
-}
-
-int checkboard(void)
-{
-	puts("Board: Freescale MPC832XEMDS\n");
-	return 0;
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI
-	ft_pci_setup(blob, bd);
-#endif
-
-	return 0;
-}
-#endif

board/freescale/mpc832xemds/pci.c deleted +0 -146

deleted file mode 100644
index e8b2b11..0000000
@@ -1,146 +0,0 @@
-/*
- * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * PCI Configuration space access support for MPC83xx PCI Bridge
- */
-#include <asm/mmu.h>
-#include <asm/io.h>
-#include <common.h>
-#include <mpc83xx.h>
-#include <pci.h>
-#include <i2c.h>
-#include <asm/fsl_i2c.h>
-#include "../common/pq-mds-pib.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct pci_region pci1_regions[] = {
-	{
-		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
-		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
-		size: CONFIG_SYS_PCI1_MEM_SIZE,
-		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
-	},
-	{
-		bus_start: CONFIG_SYS_PCI1_IO_BASE,
-		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
-		size: CONFIG_SYS_PCI1_IO_SIZE,
-		flags: PCI_REGION_IO
-	},
-	{
-		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
-		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
-		size: CONFIG_SYS_PCI1_MMIO_SIZE,
-		flags: PCI_REGION_MEM
-	},
-};
-
-#ifdef CONFIG_MPC83XX_PCI2
-static struct pci_region pci2_regions[] = {
-	{
-		bus_start: CONFIG_SYS_PCI2_MEM_BASE,
-		phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
-		size: CONFIG_SYS_PCI2_MEM_SIZE,
-		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
-	},
-	{
-		bus_start: CONFIG_SYS_PCI2_IO_BASE,
-		phys_start: CONFIG_SYS_PCI2_IO_PHYS,
-		size: CONFIG_SYS_PCI2_IO_SIZE,
-		flags: PCI_REGION_IO
-	},
-	{
-		bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
-		phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
-		size: CONFIG_SYS_PCI2_MMIO_SIZE,
-		flags: PCI_REGION_MEM
-	},
-};
-#endif
-
-void pci_init_board(void)
-#ifdef CONFIG_PCISLAVE
-{
-	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
-	volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0];
-	struct pci_region *reg[] = { pci1_regions };
-
-	/* Configure PCI Local Access Windows */
-	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
-	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
-
-	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
-	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
-
-	mpc83xx_pci_init(1, reg);
-
-	/*
-	 * Configure PCI Inbound Translation Windows
-	 */
-	pci_ctrl[0].pitar0 = 0x0;
-	pci_ctrl[0].pibar0 = 0x0;
-	pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP |
-	    PIWAR_WTT_SNOOP | PIWAR_IWS_4K;
-
-	pci_ctrl[0].pitar1 = 0x0;
-	pci_ctrl[0].pibar1 = 0x0;
-	pci_ctrl[0].piebar1 = 0x0;
-	pci_ctrl[0].piwar1 &= ~PIWAR_EN;
-
-	pci_ctrl[0].pitar2 = 0x0;
-	pci_ctrl[0].pibar2 = 0x0;
-	pci_ctrl[0].piebar2 = 0x0;
-	pci_ctrl[0].piwar2 &= ~PIWAR_EN;
-
-	/* Unlock the configuration bit */
-	mpc83xx_pcislave_unlock(0);
-	printf("PCI:   Agent mode enabled\n");
-}
-#else
-{
-	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
-	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
-#ifndef CONFIG_MPC83XX_PCI2
-	struct pci_region *reg[] = { pci1_regions };
-#else
-	struct pci_region *reg[] = { pci1_regions, pci2_regions };
-#endif
-
-	/* initialize the PCA9555PW IO expander on the PIB board */
-	pib_init();
-
-#if defined(CONFIG_PCI_66M)
-	clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
-	printf("PCI clock is 66MHz\n");
-#elif defined(CONFIG_PCI_33M)
-	clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 |
-	    OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR;
-	printf("PCI clock is 33MHz\n");
-#else
-	clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
-	printf("PCI clock is 66MHz\n");
-#endif
-	udelay(2000);
-
-	/* Configure PCI Local Access Windows */
-	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
-	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
-
-	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
-	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;
-
-	udelay(2000);
-
-#ifndef CONFIG_MPC83XX_PCI2
-	mpc83xx_pci_init(1, reg);
-#else
-	mpc83xx_pci_init(2, reg);
-#endif
-}
-#endif				/* CONFIG_PCISLAVE */

board/freescale/mpc8349emds/Kconfig deleted +0 -12

deleted file mode 100644
index 51f0b34..0000000
@@ -1,12 +0,0 @@
-if TARGET_MPC8349EMDS
-
-config SYS_BOARD
-	default "mpc8349emds"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "MPC8349EMDS"
-
-endif

board/freescale/mpc8349emds/MAINTAINERS deleted +0 -6

deleted file mode 100644
index 141e77a..0000000
@@ -1,6 +0,0 @@
-MPC8349EMDS BOARD
-M:	Kim Phillips <[email protected]>
-S:	Maintained
-F:	board/freescale/mpc8349emds/
-F:	include/configs/MPC8349EMDS.h
-F:	configs/MPC8349EMDS_defconfig

board/freescale/mpc8349emds/Makefile deleted +0 -10

deleted file mode 100644
index 5c315f9..0000000
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y += mpc8349emds.o
-obj-$(CONFIG_PCI) += pci.o
-obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o

board/freescale/mpc8349emds/ddr.c deleted +0 -101

deleted file mode 100644
index aae003d..0000000
@@ -1,101 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-struct board_specific_parameters {
-	u32 n_ranks;
-	u32 datarate_mhz_high;
-	u32 clk_adjust;
-	u32 cpo;
-	u32 write_data_delay;
-	u32 force_2t;
-};
-
-/*
- * This table contains all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- */
-static const struct board_specific_parameters udimm0[] = {
-	/*
-	 * memory controller 0
-	 *   num|  hi|  clk| cpo|wrdata|2T
-	 * ranks| mhz|adjst|    | delay|
-	 */
-	{2,  300,    4,   4,    2,  0},
-	{2,  365,    4,   6,    2,  0},
-	{2,  450,    4,   7,    2,  0},
-	{2,  850,    4,  31,    2,  0},
-	{1,  300,    4,   4,    2,  0},
-	{1,  365,    4,   6,    2,  0},
-	{1,  450,    4,   7,    2,  0},
-	{1,  850,    4,  31,    2,  0},
-	{}
-};
-
-void fsl_ddr_board_options(memctl_options_t *popts,
-				dimm_params_t *pdimm,
-				unsigned int ctrl_num)
-{
-	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
-	unsigned int i;
-	ulong ddr_freq;
-
-	if (ctrl_num != 0)	/* we have only one controller */
-		return;
-	for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
-		if (pdimm[i].n_ranks)
-			break;
-	}
-	if (i >= CONFIG_DIMM_SLOTS_PER_CTLR)	/* no DIMM */
-		return;
-
-	pbsp = udimm0;
-
-	/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
-	 * freqency and n_banks specified in board_specific_parameters table.
-	 */
-	ddr_freq = get_ddr_freq(0) / 1000000;
-	while (pbsp->datarate_mhz_high) {
-		if (pbsp->n_ranks ==  pdimm[i].n_ranks) {
-			if (ddr_freq <= pbsp->datarate_mhz_high) {
-				popts->clk_adjust = pbsp->clk_adjust;
-				popts->cpo_override = pbsp->cpo;
-				popts->write_data_delay =
-					pbsp->write_data_delay;
-				popts->twot_en = pbsp->force_2t;
-				goto found;
-			}
-			pbsp_highest = pbsp;
-		}
-		pbsp++;
-	}
-
-	if (pbsp_highest) {
-		printf("Error: board specific timing not found "
-			"for data rate %lu MT/s!\n"
-			"Trying to use the highest speed (%u) parameters\n",
-			ddr_freq, pbsp_highest->datarate_mhz_high);
-		popts->clk_adjust = pbsp_highest->clk_adjust;
-		popts->cpo_override = pbsp_highest->cpo;
-		popts->write_data_delay = pbsp_highest->write_data_delay;
-		popts->twot_en = pbsp_highest->force_2t;
-	} else {
-		panic("DIMM is not supported by this board");
-	}
-
-found:
-	/*
-	 * Factors to consider for half-strength driver enable:
-	 *	- number of DIMMs installed
-	 */
-	popts->half_strength_driver_enable = 0;
-	popts->dqs_config = 0;	/* only true DQS signal is used on board */
-}

board/freescale/mpc8349emds/mpc8349emds.c deleted +0 -285

deleted file mode 100644
index 02b5040..0000000
@@ -1,285 +0,0 @@
-/*
- * (C) Copyright 2006
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc83xx.h>
-#include <asm/mpc8349_pci.h>
-#include <i2c.h>
-#include <spi.h>
-#include <miiphy.h>
-#ifdef CONFIG_SYS_FSL_DDR2
-#include <fsl_ddr_sdram.h>
-#else
-#include <spd_sdram.h>
-#endif
-
-#if defined(CONFIG_OF_LIBFDT)
-#include <libfdt.h>
-#endif
-
-int fixed_sdram(void);
-void sdram_init(void);
-
-#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx)
-void ddr_enable_ecc(unsigned int dram_size);
-#endif
-
-int board_early_init_f (void)
-{
-	volatile u8* bcsr = (volatile u8*)CONFIG_SYS_BCSR;
-
-	/* Enable flash write */
-	bcsr[1] &= ~0x01;
-
-#ifdef CONFIG_SYS_USE_MPC834XSYS_USB_PHY
-	/* Use USB PHY on SYS board */
-	bcsr[5] |= 0x02;
-#endif
-
-	return 0;
-}
-
-#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
-
-phys_size_t initdram (int board_type)
-{
-	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-	phys_size_t msize = 0;
-
-	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
-		return -1;
-
-	/* DDR SDRAM - Main SODIMM */
-	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
-#if defined(CONFIG_SPD_EEPROM)
-#ifndef CONFIG_SYS_FSL_DDR2
-	msize = spd_sdram() * 1024 * 1024;
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-	ddr_enable_ecc(msize);
-#endif
-#else
-	msize = fsl_ddr_sdram();
-#endif
-#else
-	msize = fixed_sdram() * 1024 * 1024;
-#endif
-	/*
-	 * Initialize SDRAM if it is on local bus.
-	 */
-	sdram_init();
-
-	/* return total bus SDRAM size(bytes)  -- DDR */
-	return msize;
-}
-
-#if !defined(CONFIG_SPD_EEPROM)
-/*************************************************************************
- *  fixed sdram init -- doesn't use serial presence detect.
- ************************************************************************/
-int fixed_sdram(void)
-{
-	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-	u32 msize = CONFIG_SYS_DDR_SIZE;
-	u32 ddr_size = msize << 20;	/* DDR size in bytes */
-	u32 ddr_size_log2 = __ilog2(ddr_size);
-
-	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
-	im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
-
-#if (CONFIG_SYS_DDR_SIZE != 256)
-#warning Currenly any ddr size other than 256 is not supported
-#endif
-#ifdef CONFIG_DDR_II
-	im->ddr.csbnds[2].csbnds = CONFIG_SYS_DDR_CS2_BNDS;
-	im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
-	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
-	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
-	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
-	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
-	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
-	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
-	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
-	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
-	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
-	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
-#else
-
-#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
-#warning Chip select bounds is only configurable in 16MB increments
-#endif
-	im->ddr.csbnds[2].csbnds =
-		((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
-		(((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
-				CSBNDS_EA_SHIFT) & CSBNDS_EA);
-	im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
-
-	/* currently we use only one CS, so disable the other banks */
-	im->ddr.cs_config[0] = 0;
-	im->ddr.cs_config[1] = 0;
-	im->ddr.cs_config[3] = 0;
-
-	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
-	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
-
-	im->ddr.sdram_cfg =
-		SDRAM_CFG_SREN
-#if defined(CONFIG_DDR_2T_TIMING)
-		| SDRAM_CFG_2T_EN
-#endif
-		| 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
-#if defined (CONFIG_DDR_32BIT)
-	/* for 32-bit mode burst length is 8 */
-	im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
-#endif
-	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
-
-	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
-#endif
-	udelay(200);
-
-	/* enable DDR controller */
-	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
-	return msize;
-}
-#endif/*!CONFIG_SYS_SPD_EEPROM*/
-
-
-int checkboard (void)
-{
-	/*
-	 * Warning: do not read the BCSR registers here
-	 *
-	 * There is a timing bug in the 8349E and 8349EA BCSR code
-	 * version 1.2 (read from BCSR 11) that will cause the CFI
-	 * flash initialization code to overwrite BCSR 0, disabling
-	 * the serial ports and gigabit ethernet
-	 */
-
-	puts("Board: Freescale MPC8349EMDS\n");
-	return 0;
-}
-
-/*
- * if MPC8349EMDS is soldered with SDRAM
- */
-#if defined(CONFIG_SYS_BR2_PRELIM)  \
-	&& defined(CONFIG_SYS_OR2_PRELIM) \
-	&& defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
-	&& defined(CONFIG_SYS_LBLAWAR2_PRELIM)
-/*
- * Initialize SDRAM memory on the Local Bus.
- */
-
-void sdram_init(void)
-{
-	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-	volatile fsl_lbc_t *lbc = &immap->im_lbc;
-	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
-
-	/*
-	 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
-	 */
-
-	/* setup mtrpt, lsrt and lbcr for LB bus */
-	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
-	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
-	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
-	asm("sync");
-
-	/*
-	 * Configure the SDRAM controller Machine Mode Register.
-	 */
-	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
-
-	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
-	asm("sync");
-	*sdram_addr = 0xff;
-	udelay(100);
-
-	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */
-	asm("sync");
-	/*1 times*/
-	*sdram_addr = 0xff;
-	udelay(100);
-	/*2 times*/
-	*sdram_addr = 0xff;
-	udelay(100);
-	/*3 times*/
-	*sdram_addr = 0xff;
-	udelay(100);
-	/*4 times*/
-	*sdram_addr = 0xff;
-	udelay(100);
-	/*5 times*/
-	*sdram_addr = 0xff;
-	udelay(100);
-	/*6 times*/
-	*sdram_addr = 0xff;
-	udelay(100);
-	/*7 times*/
-	*sdram_addr = 0xff;
-	udelay(100);
-	/*8 times*/
-	*sdram_addr = 0xff;
-	udelay(100);
-
-	/* 0x58636733; mode register write operation */
-	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
-	asm("sync");
-	*sdram_addr = 0xff;
-	udelay(100);
-
-	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
-	asm("sync");
-	*sdram_addr = 0xff;
-	udelay(100);
-}
-#else
-void sdram_init(void)
-{
-}
-#endif
-
-/*
- * The following are used to control the SPI chip selects for the SPI command.
- */
-#ifdef CONFIG_MPC8XXX_SPI
-
-#define SPI_CS_MASK	0x80000000
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
-	return bus == 0 && cs == 0;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
-	volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
-
-	iopd->dat &= ~SPI_CS_MASK;
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
-	volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
-
-	iopd->dat |=  SPI_CS_MASK;
-}
-#endif /* CONFIG_HARD_SPI */
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI
-	ft_pci_setup(blob, bd);
-#endif
-
-	return 0;
-}
-#endif

board/freescale/mpc8349emds/pci.c deleted +0 -192

deleted file mode 100644
index 9f7324f..0000000
@@ -1,192 +0,0 @@
-/*
- * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm/mmu.h>
-#include <asm/io.h>
-#include <common.h>
-#include <mpc83xx.h>
-#include <pci.h>
-#include <i2c.h>
-#include <asm/fsl_i2c.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct pci_region pci1_regions[] = {
-	{
-		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
-		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
-		size: CONFIG_SYS_PCI1_MEM_SIZE,
-		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
-	},
-	{
-		bus_start: CONFIG_SYS_PCI1_IO_BASE,
-		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
-		size: CONFIG_SYS_PCI1_IO_SIZE,
-		flags: PCI_REGION_IO
-	},
-	{
-		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
-		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
-		size: CONFIG_SYS_PCI1_MMIO_SIZE,
-		flags: PCI_REGION_MEM
-	},
-};
-
-#ifdef CONFIG_MPC83XX_PCI2
-static struct pci_region pci2_regions[] = {
-	{
-		bus_start: CONFIG_SYS_PCI2_MEM_BASE,
-		phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
-		size: CONFIG_SYS_PCI2_MEM_SIZE,
-		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
-	},
-	{
-		bus_start: CONFIG_SYS_PCI2_IO_BASE,
-		phys_start: CONFIG_SYS_PCI2_IO_PHYS,
-		size: CONFIG_SYS_PCI2_IO_SIZE,
-		flags: PCI_REGION_IO
-	},
-	{
-		bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
-		phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
-		size: CONFIG_SYS_PCI2_MMIO_SIZE,
-		flags: PCI_REGION_MEM
-	},
-};
-#endif
-
-#ifndef CONFIG_PCISLAVE
-void pib_init(void)
-{
-	u8 val8, orig_i2c_bus;
-	/*
-	 * Assign PIB PMC slot to desired PCI bus
-	 */
-	/* Switch temporarily to I2C bus #2 */
-	orig_i2c_bus = i2c_get_bus_num();
-	i2c_set_bus_num(1);
-
-	val8 = 0;
-	i2c_write(0x23, 0x6, 1, &val8, 1);
-	i2c_write(0x23, 0x7, 1, &val8, 1);
-	val8 = 0xff;
-	i2c_write(0x23, 0x2, 1, &val8, 1);
-	i2c_write(0x23, 0x3, 1, &val8, 1);
-
-	val8 = 0;
-	i2c_write(0x26, 0x6, 1, &val8, 1);
-	val8 = 0x34;
-	i2c_write(0x26, 0x7, 1, &val8, 1);
-#if defined(PCI_64BIT)
-	val8 = 0xf4;	/* PMC2:PCI1/64-bit */
-#elif defined(PCI_ALL_PCI1)
-	val8 = 0xf3;	/* PMC1:PCI1 PMC2:PCI1 PMC3:PCI1 */
-#elif defined(PCI_ONE_PCI1)
-	val8 = 0xf9;	/* PMC1:PCI1 PMC2:PCI2 PMC3:PCI2 */
-#else
-	val8 = 0xf5;	/* PMC1:PCI1 PMC2:PCI1 PMC3:PCI2 */
-#endif
-	i2c_write(0x26, 0x2, 1, &val8, 1);
-	val8 = 0xff;
-	i2c_write(0x26, 0x3, 1, &val8, 1);
-	val8 = 0;
-	i2c_write(0x27, 0x6, 1, &val8, 1);
-	i2c_write(0x27, 0x7, 1, &val8, 1);
-	val8 = 0xff;
-	i2c_write(0x27, 0x2, 1, &val8, 1);
-	val8 = 0xef;
-	i2c_write(0x27, 0x3, 1, &val8, 1);
-	asm("eieio");
-
-#if defined(PCI_64BIT)
-	printf("PCI1: 64-bit on PMC2\n");
-#elif defined(PCI_ALL_PCI1)
-	printf("PCI1: 32-bit on PMC1, PMC2, PMC3\n");
-#elif defined(PCI_ONE_PCI1)
-	printf("PCI1: 32-bit on PMC1\n");
-	printf("PCI2: 32-bit on PMC2, PMC3\n");
-#else
-	printf("PCI1: 32-bit on PMC1, PMC2\n");
-	printf("PCI2: 32-bit on PMC3\n");
-#endif
-	/* Reset to original I2C bus */
-	i2c_set_bus_num(orig_i2c_bus);
-}
-
-void pci_init_board(void)
-{
-	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
-	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
-#ifndef CONFIG_MPC83XX_PCI2
-	struct pci_region *reg[] = { pci1_regions };
-#else
-	struct pci_region *reg[] = { pci1_regions, pci2_regions };
-#endif
-
-	/* initialize the PCA9555PW IO expander on the PIB board */
-	pib_init();
-
-	/* Enable all 8 PCI_CLK_OUTPUTS */
-	clk->occr = 0xff000000;
-	udelay(2000);
-
-	/* Configure PCI Local Access Windows */
-	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
-	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
-
-	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
-	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
-
-	udelay(2000);
-
-#ifndef CONFIG_MPC83XX_PCI2
-	mpc83xx_pci_init(1, reg);
-#else
-	mpc83xx_pci_init(2, reg);
-#endif
-}
-
-#else
-void pci_init_board(void)
-{
-	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
-	volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0];
-	struct pci_region *reg[] = { pci1_regions };
-
-	/* Configure PCI Local Access Windows */
-	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
-	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
-
-	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
-	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
-
-	mpc83xx_pci_init(1, reg);
-
-	/* Configure PCI Inbound Translation Windows (3 1MB windows) */
-	pci_ctrl->pitar0 = 0x0;
-	pci_ctrl->pibar0 = 0x0;
-	pci_ctrl->piwar0 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
-			   PIWAR_WTT_SNOOP | PIWAR_IWS_1M;
-
-	pci_ctrl->pitar1  = 0x0;
-	pci_ctrl->pibar1  = 0x0;
-	pci_ctrl->piebar1 = 0x0;
-	pci_ctrl->piwar1  = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
-			    PIWAR_WTT_SNOOP | PIWAR_IWS_1M;
-
-	pci_ctrl->pitar2  = 0x0;
-	pci_ctrl->pibar2  = 0x0;
-	pci_ctrl->piebar2 = 0x0;
-	pci_ctrl->piwar2  = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
-			    PIWAR_WTT_SNOOP | PIWAR_IWS_1M;
-
-	/* Unlock the configuration bit */
-	mpc83xx_pcislave_unlock(0);
-	printf("PCI:   Agent mode enabled\n");
-}
-#endif /* CONFIG_PCISLAVE */

board/freescale/mpc8349itx/Kconfig deleted +0 -12

deleted file mode 100644
index ce3fffd..0000000
@@ -1,12 +0,0 @@
-if TARGET_MPC8349ITX
-
-config SYS_BOARD
-	default "mpc8349itx"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "MPC8349ITX"
-
-endif

board/freescale/mpc8349itx/MAINTAINERS deleted +0 -8

deleted file mode 100644
index d0388ad..0000000
@@ -1,8 +0,0 @@
-MPC8349ITX BOARD
-#M:	-
-S:	Maintained
-F:	board/freescale/mpc8349itx/
-F:	include/configs/MPC8349ITX.h
-F:	configs/MPC8349ITX_defconfig
-F:	configs/MPC8349ITX_LOWBOOT_defconfig
-F:	configs/MPC8349ITXGP_defconfig

board/freescale/mpc8349itx/Makefile deleted +0 -8

deleted file mode 100644
index e9092ad..0000000
@@ -1,8 +0,0 @@
-#
-# Copyright (C) Freescale Semiconductor, Inc. 2006.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y += mpc8349itx.o
-obj-$(CONFIG_PCI) += pci.o

board/freescale/mpc8349itx/README deleted +0 -187

deleted file mode 100644
index 48bbd50..0000000
@@ -1,187 +0,0 @@
-Freescale MPC8349E-mITX and MPC8349E-mITX-GP Boards
----------------------------------------------------
-
-1.	Board Description
-
-	The MPC8349E-mITX and MPC8349E-mITX-GP are reference boards featuring
-	the Freescale MPC8349E processor in a Mini-ITX form factor.
-
-	The MPC8349E-mITX-GP is an MPC8349E-mITX with the following differences:
-
-	A) One 8MB on-board flash EEPROM chip, instead of two.
-	B) No SATA controller
-	C) No Compact Flash slot
-	D) No Mini-PCI slot
-	E) No Vitesse 7385 5-port Ethernet switch
-	F) No 4-port USB Type-A interface
-
-2.	Board Switches and Jumpers
-
-2.0	Descriptions for all of the board jumpers can be found in the User
-	Guide.  Of particular interest to U-Boot developers is jumper J22:
-
-	Pos.	Name		Default		Description
-	-----------------------------------------------------------------------
-	A	LGPL0		ON (0)          HRCW source, bit 0
-	B       LGPL1           ON (0)          HRCW source, bit 1
-	C       LGPL3           ON (0)		HRCW source, bit 2
-	D       LGPL5           OFF (1)         PCI_SYNC_OUT frequency
-	E       BOOT1           ON (0)          Flash EEPROM boot device
-	F       PCI_M66EN       ON (0)          PCI 66MHz enable
-	G       I2C-WP          ON (0)          I2C EEPROM write protection
-	H       F_WP            OFF (1)         Flash EEPROM write protection
-
-	Jumper J22.E is only for the ITX, and it decides the configuration
-	of the flash chips.  If J22.E is ON (i.e. jumpered), then flash chip
-	U4 is located at address FE000000 and flash chip U7 is at FE800000.
-	If J22.E is OFF, then U7 is at FE000000 and U4 is at FE800000.
-
-	For U-Boot development, J22.E can be used to switch back-and-forth
-	between two U-Boot images.
-
-3.	Memory Map
-
-3.1.	The memory map should look pretty much like this:
-
-	0x0000_0000 - 0x0FFF_FFFF DDR SDRAM (256 MB)
-	0x8000_0000 - 0x9FFF_FFFF PCI1 memory space (512 MB)
-	0xA000_0000 - 0xBFFF_FFFF PCI2 memory space (512 MB)
-	0xE000_0000 - 0xEFFF_FFFF IMMR (1 MB)
-	0xE200_0000 - 0xE2FF_FFFF PCI1 I/O space (16 MB)
-	0xE300_0000 - 0xE3FF_FFFF PCI2 I/O space (16 MB)
-	0xF000_0000 - 0xF000_FFFF Compact Flash (ITX only)
-	0xF001_0000 - 0xF001_FFFF Local bus expansion slot
-	0xF800_0000 - 0xF801_FFFF Vitesse 7385 Parallel Interface (ITX only)
-	0xFE00_0000 - 0xFE7F_FFFF First 8MB bank of Flash memory
-	0xFE80_0000 - 0xFEFF_FFFF Second 8MB bank of Flash memory (ITX only)
-
-3.2	Flash EEPROM layout.
-
-	On the ITX, jumper J22.E is used to determine which flash chips are
-	at which address.  When J22.E is switched, addresses from FE000000
-	to FE7FFFFF are swapped with addresses from FE800000 to FEFFFFFF.
-
-	On the ITX, at the normal boot address (aka HIGHBOOT):
-
-	FE00_0000	HRCW
-	FE70_0000	Alternative U-Boot image
-	FE80_0000	Alternative HRCW
-	FEF0_0000	U-Boot image
-	FEFF_FFFF	End of flash
-
-	On the ITX, at the low boot address (LOWBOOT)
-
-	FE00_0000	HRCW and U-Boot image
-	FE04_0000	U-Boot environment variables
-	FE80_0000	Alternative HRCW and U-Boot image
-	FEFF_FFFF	End of flash
-
-	On the ITX-GP, the only option is LOWBOOT and there is only one chip
-
-	FE00_0000	HRCW and U-Boot image
-	FE04_0000	U-Boot environment variables
-	F7FF_FFFF	End of flash
-
-4. Definitions
-
-4.1 Explanation of NEW definitions in:
-
-	include/configs/MPC8349ITX.h
-
-	CONFIG_MPC83xx		MPC83xx family
-	CONFIG_MPC8349		MPC8349 specific
-	CONFIG_MPC8349ITX		MPC8349E-mITX
-	CONFIG_MPC8349ITXGP		MPC8349E-mITX-GP
-
-5. Compilation
-
-	Assuming you're using BASH shell:
-
-		export CROSS_COMPILE=your-cross-compile-prefix
-		cd u-boot
-		make distclean
-
-		make MPC8349ITX_config
-	or:
-		make MPC8349ITXGP_config
-	or:
-		make MPC8349ITX_LOWBOOT_config
-
-		make
-
-6. Downloading and Flashing Images
-
-6.1 Download via tftp:
-
-	tftp $loadaddr <uboot>
-
-	where "<uboot>" is the path and filename, on the TFTP server, of
-	the U-Boot image.
-
-6.1 Reflash U-Boot Image using U-Boot
-
-	setenv uboot <uboot>
-	run tftpflash
-
-	where "<uboot>" is the path and filename, on the TFTP server, of
-	the U-Boot image.
-
-6.2 Using the HRCW to switch between two different U-Boot images on the ITX
-
-	Because the ITX has 16MB of flash, it is possible to keep two U-Boot
-	images in flash, and use the HRCW to specify which one is to be used
-	when the board boots.  This trick is especially effective with a
-	hardware debugger that can override the HRCW, such as the BDI-2000.
-
-	When the BMS bit in the HRCW is 0, the ITX will boot the U-Boot image
-	at address FE000000.  When the BMS bit is 1, the ITX will boot the
-	image at address FEF00000.
-
-	Therefore, just put a U-Boot image at both FE000000 and FEF00000 and
-	change the BMS bit whenever you want to boot the other image.
-
-	Step-by-step instructions:
-
-	1) Build an ITX image to be loaded at FEF00000
-
-		make distclean
-		make MPC8349ITX_config
-		make
-
-	2) Take the u-boot.bin image and flash it at FEF00000.
-
-		tftp $loadaddr u-boot.bin
-		protect off all
-		erase FEF00000 +$filesize
-		cp.b $loadaddr FEF00000 $filesize
-
-	3) Build an ITX image to be loaded at FE000000
-
-		make distclean
-		make MPC8349ITX_LOWBOOT_config
-		make
-
-	4) Take the u-boot.bin image and flash it at FE000000.
-
-		tftp $loadaddr u-boot.bin
-		protect off FE000000 +$filesize
-		erase FE000000 +$filesize
-		cp.b $loadaddr FE000000 $filesize
-
-	The HRCW in flash is currently set to boot the image at FE000000.
-
-	If you have a hardware debugger, configure it to set the HRCW to
-	B460A000 04040000 if you want to boot the image at FEF00000, or set
-	it to B060A000 04040000 if you want to boot the image at FE000000.
-
-	To change the HRCW in flash to boot the image at FEF00000, use these
-	U-Boot commands:
-
-		cp.b FE000000 1000 10000	; copy 1st flash sector to 1000
-		mw.b 1020 b4 8			; modify BMS bit
-		protect off FE000000 +10000
-		erase FE000000 +10000
-		cp.b 1000 FE000000 10000
-
-7. Notes
-	1) The console baudrate for MPC8349EITX is 115200bps.

board/freescale/mpc8349itx/mpc8349itx.c deleted +0 -390

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@@ -1,390 +0,0 @@
-/*
- * Copyright (C) Freescale Semiconductor, Inc. 2006.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc83xx.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <vsc7385.h>
-#ifdef CONFIG_PCI
-#include <asm/mpc8349_pci.h>
-#include <pci.h>
-#endif
-#include <spd_sdram.h>
-#include <asm/mmu.h>
-#if defined(CONFIG_OF_LIBFDT)
-#include <libfdt.h>
-#endif
-
-#ifndef CONFIG_SPD_EEPROM
-/*************************************************************************
- *  fixed sdram init -- doesn't use serial presence detect.
- ************************************************************************/
-int fixed_sdram(void)
-{
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	/* The size of RAM, in bytes */
-	u32 ddr_size = CONFIG_SYS_DDR_SIZE << 20;
-	u32 ddr_size_log2 = __ilog2(ddr_size);
-
-	im->sysconf.ddrlaw[0].ar =
-	    LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
-	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
-
-#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
-#warning Chip select bounds is only configurable in 16MB increments
-#endif
-	im->ddr.csbnds[0].csbnds =
-		((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
-		(((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
-				CSBNDS_EA_SHIFT) & CSBNDS_EA);
-	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
-
-	/* Only one CS for DDR */
-	im->ddr.cs_config[1] = 0;
-	im->ddr.cs_config[2] = 0;
-	im->ddr.cs_config[3] = 0;
-
-	debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds);
-	debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]);
-
-	debug("DDR:bar=0x%08x\n", im->sysconf.ddrlaw[0].bar);
-	debug("DDR:ar=0x%08x\n", im->sysconf.ddrlaw[0].ar);
-
-	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
-	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */
-	im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR1;
-	im->ddr.sdram_mode =
-	    (0x0000 << SDRAM_MODE_ESD_SHIFT) | (0x0032 << SDRAM_MODE_SD_SHIFT);
-	im->ddr.sdram_interval =
-	    (0x0410 << SDRAM_INTERVAL_REFINT_SHIFT) | (0x0100 <<
-						       SDRAM_INTERVAL_BSTOPRE_SHIFT);
-	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
-
-	udelay(200);
-
-	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
-
-	debug("DDR:timing_cfg_1=0x%08x\n", im->ddr.timing_cfg_1);
-	debug("DDR:timing_cfg_2=0x%08x\n", im->ddr.timing_cfg_2);
-	debug("DDR:sdram_mode=0x%08x\n", im->ddr.sdram_mode);
-	debug("DDR:sdram_interval=0x%08x\n", im->ddr.sdram_interval);
-	debug("DDR:sdram_cfg=0x%08x\n", im->ddr.sdram_cfg);
-
-	return CONFIG_SYS_DDR_SIZE;
-}
-#endif
-
-#ifdef CONFIG_PCI
-/*
- * Initialize PCI Devices, report devices found
- */
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_mpc83xxmitx_config_table[] = {
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