ATSAMA5D big endian work

The ATSAMA5D devices are based on Cortex-A5 which should work in big endian configuration. Add ARCH_SUPPORTS_BIG_ENDIAN if these SoCs are configured so we can run the system big endian.

Signed-off-by Ben Dooks <[email protected]>

--
CC: Linux ARM Kernel <[email protected]>
CC: Andrew Victor <[email protected]>
CC: Nicolas Ferre <[email protected]>
CC: Jean-Christophe Plagniol-Villard

CC Russell King <[email protected]>

---
 arch/arm/mach-at91/Kconfig | 1 +
 1 file changed, 1 insertion(+)

arch/arm/mach-at91/Kconfig +0 -0

index c74a443..05212fb 100644

Add support for using this driver on ARMv7 devices configured for big endian.

Signed-off-by Ben Dooks <[email protected]>

--
CC: Nicolas Ferre <[email protected]>
CC: Greg Kroah-Hartman <[email protected]>
CC: Jiri Slaby <[email protected]>
CC: linux-serial at vger.kernel.org
CC: Linux ARM Kernel <[email protected]>

---
 drivers/tty/serial/atmel_serial.c | 62 ++++++++++++++++++++++-----------------
 1 file changed, 35 insertions(+), 27 deletions(-)

Fix the use of __raw IO accessor with the readl/writel_relaxed versions to allow the code to be used on a system running in big endian.

Signed-off-by Ben Dooks <[email protected]>

--
CC: Daniel Lezcano <[email protected]>
CC: Thomas Gleixner <[email protected]>
CC: Linux Kernel <[email protected]>
CC: Linux ARM Kernel <[email protected]>
CC: Andrew Victor <[email protected]>
CC: Nicolas Ferre <[email protected]>

CC Jean-Christophe Plagniol-Villard <[email protected]>

---
 drivers/clocksource/timer-atmel-pit.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

drivers/clocksource/timer-atmel-pit.c +2 -2

index b5b4d45..c0304ff 100644
@@ -61,12 +61,12 @@ static inline struct pit_data *clkevt_to_pit_data(struct clock_event_device *clk
 
 static inline unsigned int pit_read(void __iomem *base, unsigned int reg_offset)
 {
-	return __raw_readl(base + reg_offset);
+	return readl_relaxed(base + reg_offset);
 }
 
 static inline void pit_write(void __iomem *base, unsigned int reg_offset, unsigned long value)
 {
-	__raw_writel(value, base + reg_offset);
+	writel_relaxed(value, base + reg_offset);
 }
 
 /*

Le 18/03/2015 16:53, Ben Dooks a ?crit :

Quoted 11 lines

Fix the use of __raw IO accessor with the readl/writel_relaxed versions to allow the code to be used on a system running in big endian.

Signed-off-by Ben Dooks <[email protected]>

--
CC: Daniel Lezcano <[email protected]>
CC: Thomas Gleixner <[email protected]>
CC: Linux Kernel <[email protected]>
CC: Linux ARM Kernel <[email protected]>
CC: Andrew Victor <[email protected]>
CC: Nicolas Ferre <[email protected]>

Yes:

Acked-by Nicolas Ferre <[email protected]>

Daniel, do you want to take it?

Quoted 25 lines

CC Jean-Christophe Plagniol-Villard <[email protected]>

---
  drivers/clocksource/timer-atmel-pit.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

drivers/clocksource/timer-atmel-pit.c +2 -2

index b5b4d45..c0304ff 100644
@@ -61,12 +61,12 @@ static inline struct pit_data *clkevt_to_pit_data(struct clock_event_device *clk
 
  static inline unsigned int pit_read(void __iomem *base, unsigned int reg_offset)
  {
-	return __raw_readl(base + reg_offset);
+	return readl_relaxed(base + reg_offset);
  }
 
  static inline void pit_write(void __iomem *base, unsigned int reg_offset, unsigned long value)
  {
-	__raw_writel(value, base + reg_offset);
+	writel_relaxed(value, base + reg_offset);
  }
 
  /*

Change the __raw read and write to use readl/writel_relaxed to make the code endian agnostic.

Signed-off-by Ben Dooks <[email protected]>

--
CC: Daniel Lezcano <[email protected]>
CC: Thomas Gleixner <[email protected]>
CC: Linux Kernel <[email protected]>
CC: Linux ARM Kernel <[email protected]>
CC: Andrew Victor <[email protected]>
CC: Nicolas Ferre <[email protected]>
CC: Jean-Christophe Plagniol-Villard <[email protected]>

---
  drivers/clocksource/tcb_clksrc.c | 66 ++++++++++++++++++++++------------------
  1 file changed, 37 insertions(+), 29 deletions(-)

drivers/clocksource/tcb_clksrc.c +37 -29

index 8bdbc45..0f819dd3 100644
@@ -41,6 +41,14 @@
 
  static void __iomem *tcaddr;
 
+#ifdef CONFIG_AVR32
+#define tcb_readl	__raw_readl
+#define tcb_writel	__raw_writel
+#else
+#define tcb_readl	readl_relaxed
+#define tcb_writel	writel_relaxed
+#endif
+
  static cycle_t tc_get_cycles(struct clocksource *cs)
  {
  	unsigned long	flags;

@@ -48,9 +56,9 @@ static cycle_t tc_get_cycles(struct clocksource *cs)
 
  	raw_local_irq_save(flags);
  	do {
-		upper = __raw_readl(tcaddr + ATMEL_TC_REG(1, CV));
-		lower = __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));
-	} while (upper != __raw_readl(tcaddr + ATMEL_TC_REG(1, CV)));
+		upper = tcb_readl(tcaddr + ATMEL_TC_REG(1, CV));
+		lower = tcb_readl(tcaddr + ATMEL_TC_REG(0, CV));
+	} while (upper != tcb_readl(tcaddr + ATMEL_TC_REG(1, CV)));
 
  	raw_local_irq_restore(flags);
  	return (upper << 16) | lower;

@@ -58,7 +66,7 @@ static cycle_t tc_get_cycles(struct clocksource *cs)
 
  static cycle_t tc_get_cycles32(struct clocksource *cs)
  {
-	return __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));
+	return tcb_readl(tcaddr + ATMEL_TC_REG(0, CV));
  }
 
  static struct clocksource clksrc = {

@@ -98,8 +106,8 @@ static void tc_mode(enum clock_event_mode m, struct clock_event_device *d)
 
  	if (tcd->clkevt.mode == CLOCK_EVT_MODE_PERIODIC
  			|| tcd->clkevt.mode == CLOCK_EVT_MODE_ONESHOT) {
-		__raw_writel(0xff, regs + ATMEL_TC_REG(2, IDR));
-		__raw_writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));
+		tcb_writel(0xff, regs + ATMEL_TC_REG(2, IDR));
+		tcb_writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));
  		clk_disable(tcd->clk);
  	}
 

@@ -112,16 +120,16 @@ static void tc_mode(enum clock_event_mode m, struct clock_event_device *d)
  		clk_enable(tcd->clk);
 
  		/* slow clock, count up to RC, then irq and restart */
-		__raw_writel(timer_clock
+		tcb_writel(timer_clock
  				| ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
  				regs + ATMEL_TC_REG(2, CMR));
-		__raw_writel((32768 + HZ/2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));
+		tcb_writel((32768 + HZ/2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));
 
  		/* Enable clock and interrupts on RC compare */
-		__raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
+		tcb_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
 
  		/* go go gadget! */
-		__raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
+		tcb_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
  				regs + ATMEL_TC_REG(2, CCR));
  		break;
 

@@ -129,10 +137,10 @@ static void tc_mode(enum clock_event_mode m, struct clock_event_device *d)
  		clk_enable(tcd->clk);
 
  		/* slow clock, count up to RC, then irq and stop */
-		__raw_writel(timer_clock | ATMEL_TC_CPCSTOP
+		tcb_writel(timer_clock | ATMEL_TC_CPCSTOP
  				| ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
  				regs + ATMEL_TC_REG(2, CMR));
-		__raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
+		tcb_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
 
  		/* set_next_event() configures and starts the timer */
  		break;

@@ -144,10 +152,10 @@ static void tc_mode(enum clock_event_mode m, struct clock_event_device *d)
 
  static int tc_next_event(unsigned long delta, struct clock_event_device *d)
  {
-	__raw_writel(delta, tcaddr + ATMEL_TC_REG(2, RC));
+	tcb_writel(delta, tcaddr + ATMEL_TC_REG(2, RC));
 
  	/* go go gadget! */
-	__raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
+	tcb_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
  			tcaddr + ATMEL_TC_REG(2, CCR));
  	return 0;
  }

@@ -169,7 +177,7 @@ static irqreturn_t ch2_irq(int irq, void *handle)
  	struct tc_clkevt_device	*dev = handle;
  	unsigned int		sr;
 
-	sr = __raw_readl(dev->regs + ATMEL_TC_REG(2, SR));
+	sr = tcb_readl(dev->regs + ATMEL_TC_REG(2, SR));
  	if (sr & ATMEL_TC_CPCS) {
  		dev->clkevt.event_handler(&dev->clkevt);
  		return IRQ_HANDLED;

@@ -221,43 +229,43 @@ static int __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
  static void __init tcb_setup_dual_chan(struct atmel_tc *tc, int mck_divisor_idx)
  {
  	/* channel 0:  waveform mode, input mclk/8, clock TIOA0 on overflow */
-	__raw_writel(mck_divisor_idx			/* likely divide-by-8 */
+	tcb_writel(mck_divisor_idx			/* likely divide-by-8 */
  			| ATMEL_TC_WAVE
  			| ATMEL_TC_WAVESEL_UP		/* free-run */
  			| ATMEL_TC_ACPA_SET		/* TIOA0 rises at 0 */
  			| ATMEL_TC_ACPC_CLEAR,		/* (duty cycle 50%) */
  			tcaddr + ATMEL_TC_REG(0, CMR));
-	__raw_writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA));
-	__raw_writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC));
-	__raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));	/* no irqs */
-	__raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
+	tcb_writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA));
+	tcb_writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC));
+	tcb_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));	/* no irqs */
+	tcb_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
 
  	/* channel 1:  waveform mode, input TIOA0 */
-	__raw_writel(ATMEL_TC_XC1			/* input: TIOA0 */
+	tcb_writel(ATMEL_TC_XC1			/* input: TIOA0 */
  			| ATMEL_TC_WAVE
  			| ATMEL_TC_WAVESEL_UP,		/* free-run */
  			tcaddr + ATMEL_TC_REG(1, CMR));
-	__raw_writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR));	/* no irqs */
-	__raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR));
+	tcb_writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR));	/* no irqs */
+	tcb_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR));
 
  	/* chain channel 0 to channel 1*/
-	__raw_writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR);
+	tcb_writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR);
  	/* then reset all the timers */
-	__raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
+	tcb_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
  }
 
  static void __init tcb_setup_single_chan(struct atmel_tc *tc, int mck_divisor_idx)
  {
  	/* channel 0:  waveform mode, input mclk/8 */
-	__raw_writel(mck_divisor_idx			/* likely divide-by-8 */
+	tcb_writel(mck_divisor_idx			/* likely divide-by-8 */
  			| ATMEL_TC_WAVE
  			| ATMEL_TC_WAVESEL_UP,		/* free-run */
  			tcaddr + ATMEL_TC_REG(0, CMR));
-	__raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));	/* no irqs */
-	__raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
+	tcb_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));	/* no irqs */
+	tcb_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
 
  	/* then reset all the timers */
-	__raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
+	tcb_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
  }
 
  static int __init tcb_clksrc_init(void)

Quoted 4 lines

Change the __raw read and write to use readl/writel_relaxed to make the code endian agnostic.

Signed-off-by Ben Dooks <[email protected]>

Nicolas,

what about this one ? Do you ack it ?

Quoted 179 lines

--
CC: Daniel Lezcano <[email protected]>
CC: Thomas Gleixner <[email protected]>
CC: Linux Kernel <[email protected]>
CC: Linux ARM Kernel <[email protected]>
CC: Andrew Victor <[email protected]>
CC: Nicolas Ferre <[email protected]>
CC: Jean-Christophe Plagniol-Villard <[email protected]>

---
  drivers/clocksource/tcb_clksrc.c | 66 ++++++++++++++++++++++------------------
  1 file changed, 37 insertions(+), 29 deletions(-)

drivers/clocksource/tcb_clksrc.c +37 -29

index 8bdbc45..0f819dd3 100644
@@ -41,6 +41,14 @@
 
  static void __iomem *tcaddr;
 
+#ifdef CONFIG_AVR32
+#define tcb_readl	__raw_readl
+#define tcb_writel	__raw_writel
+#else
+#define tcb_readl	readl_relaxed
+#define tcb_writel	writel_relaxed
+#endif
+
  static cycle_t tc_get_cycles(struct clocksource *cs)
  {
  	unsigned long	flags;

@@ -48,9 +56,9 @@ static cycle_t tc_get_cycles(struct clocksource *cs)
 
  	raw_local_irq_save(flags);
  	do {
-		upper = __raw_readl(tcaddr + ATMEL_TC_REG(1, CV));
-		lower = __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));
-	} while (upper != __raw_readl(tcaddr + ATMEL_TC_REG(1, CV)));
+		upper = tcb_readl(tcaddr + ATMEL_TC_REG(1, CV));
+		lower = tcb_readl(tcaddr + ATMEL_TC_REG(0, CV));
+	} while (upper != tcb_readl(tcaddr + ATMEL_TC_REG(1, CV)));
 
  	raw_local_irq_restore(flags);
  	return (upper << 16) | lower;

@@ -58,7 +66,7 @@ static cycle_t tc_get_cycles(struct clocksource *cs)
 
  static cycle_t tc_get_cycles32(struct clocksource *cs)
  {
-	return __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));
+	return tcb_readl(tcaddr + ATMEL_TC_REG(0, CV));
  }
 
  static struct clocksource clksrc = {

@@ -98,8 +106,8 @@ static void tc_mode(enum clock_event_mode m, struct clock_event_device *d)
 
  	if (tcd->clkevt.mode == CLOCK_EVT_MODE_PERIODIC
  			|| tcd->clkevt.mode == CLOCK_EVT_MODE_ONESHOT) {
-		__raw_writel(0xff, regs + ATMEL_TC_REG(2, IDR));
-		__raw_writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));
+		tcb_writel(0xff, regs + ATMEL_TC_REG(2, IDR));
+		tcb_writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));
  		clk_disable(tcd->clk);
  	}
 

@@ -112,16 +120,16 @@ static void tc_mode(enum clock_event_mode m, struct clock_event_device *d)
  		clk_enable(tcd->clk);
 
  		/* slow clock, count up to RC, then irq and restart */
-		__raw_writel(timer_clock
+		tcb_writel(timer_clock
  				| ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
  				regs + ATMEL_TC_REG(2, CMR));
-		__raw_writel((32768 + HZ/2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));
+		tcb_writel((32768 + HZ/2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));
 
  		/* Enable clock and interrupts on RC compare */
-		__raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
+		tcb_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
 
  		/* go go gadget! */
-		__raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
+		tcb_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
  				regs + ATMEL_TC_REG(2, CCR));
  		break;
 

@@ -129,10 +137,10 @@ static void tc_mode(enum clock_event_mode m, struct clock_event_device *d)
  		clk_enable(tcd->clk);
 
  		/* slow clock, count up to RC, then irq and stop */
-		__raw_writel(timer_clock | ATMEL_TC_CPCSTOP
+		tcb_writel(timer_clock | ATMEL_TC_CPCSTOP
  				| ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
  				regs + ATMEL_TC_REG(2, CMR));
-		__raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
+		tcb_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
 
  		/* set_next_event() configures and starts the timer */
  		break;

@@ -144,10 +152,10 @@ static void tc_mode(enum clock_event_mode m, struct clock_event_device *d)
 
  static int tc_next_event(unsigned long delta, struct clock_event_device *d)
  {
-	__raw_writel(delta, tcaddr + ATMEL_TC_REG(2, RC));
+	tcb_writel(delta, tcaddr + ATMEL_TC_REG(2, RC));
 
  	/* go go gadget! */
-	__raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
+	tcb_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
  			tcaddr + ATMEL_TC_REG(2, CCR));
  	return 0;
  }

@@ -169,7 +177,7 @@ static irqreturn_t ch2_irq(int irq, void *handle)
  	struct tc_clkevt_device	*dev = handle;
  	unsigned int		sr;
 
-	sr = __raw_readl(dev->regs + ATMEL_TC_REG(2, SR));
+	sr = tcb_readl(dev->regs + ATMEL_TC_REG(2, SR));
  	if (sr & ATMEL_TC_CPCS) {
  		dev->clkevt.event_handler(&dev->clkevt);
  		return IRQ_HANDLED;

@@ -221,43 +229,43 @@ static int __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
  static void __init tcb_setup_dual_chan(struct atmel_tc *tc, int mck_divisor_idx)
  {
  	/* channel 0:  waveform mode, input mclk/8, clock TIOA0 on overflow */
-	__raw_writel(mck_divisor_idx			/* likely divide-by-8 */
+	tcb_writel(mck_divisor_idx			/* likely divide-by-8 */
  			| ATMEL_TC_WAVE
  			| ATMEL_TC_WAVESEL_UP		/* free-run */
  			| ATMEL_TC_ACPA_SET		/* TIOA0 rises at 0 */
  			| ATMEL_TC_ACPC_CLEAR,		/* (duty cycle 50%) */
  			tcaddr + ATMEL_TC_REG(0, CMR));
-	__raw_writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA));
-	__raw_writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC));
-	__raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));	/* no irqs */
-	__raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
+	tcb_writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA));
+	tcb_writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC));
+	tcb_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));	/* no irqs */
+	tcb_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
 
  	/* channel 1:  waveform mode, input TIOA0 */
-	__raw_writel(ATMEL_TC_XC1			/* input: TIOA0 */
+	tcb_writel(ATMEL_TC_XC1			/* input: TIOA0 */
  			| ATMEL_TC_WAVE
  			| ATMEL_TC_WAVESEL_UP,		/* free-run */
  			tcaddr + ATMEL_TC_REG(1, CMR));
-	__raw_writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR));	/* no irqs */
-	__raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR));
+	tcb_writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR));	/* no irqs */
+	tcb_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR));
 
  	/* chain channel 0 to channel 1*/
-	__raw_writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR);
+	tcb_writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR);
  	/* then reset all the timers */
-	__raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
+	tcb_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
  }
 
  static void __init tcb_setup_single_chan(struct atmel_tc *tc, int mck_divisor_idx)
  {
  	/* channel 0:  waveform mode, input mclk/8 */
-	__raw_writel(mck_divisor_idx			/* likely divide-by-8 */
+	tcb_writel(mck_divisor_idx			/* likely divide-by-8 */
  			| ATMEL_TC_WAVE
  			| ATMEL_TC_WAVESEL_UP,		/* free-run */
  			tcaddr + ATMEL_TC_REG(0, CMR));
-	__raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));	/* no irqs */
-	__raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
+	tcb_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));	/* no irqs */
+	tcb_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
 
  	/* then reset all the timers */
-	__raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
+	tcb_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
  }
 
  static int __init tcb_clksrc_init(void)

Le 26/03/2015 10:55, Daniel Lezcano a ?crit :

Quoted 9 lines · Ben Dooks

Quoted 4 lines

Change the __raw read and write to use readl/writel_relaxed to make the code endian agnostic.

Signed-off-by Ben Dooks <[email protected]>

Nicolas,

what about this one ? Do you ack it ?

Yes:

Acked-by Nicolas Ferre <[email protected]>

We were discussing about having a common macro for this... But we will think more about it later.

So, let's go for it.

Change the __raw IO calls to readl/write_relaxed which makes the driver endian agnostic to run properly on big endian systems.

Signed-off-by Ben Dooks <[email protected]>

--
CC: Alessandro Zummo <[email protected]>
CC: rtc-linux at googlegroups.com
CC: linux-arm-kernel at lists.infradead.org
CC: Andrew Victor <[email protected]>
CC: Nicolas Ferre <[email protected]>
CC: Jean-Christophe Plagniol-Villard <[email protected]>

---
 drivers/rtc/rtc-at91rm9200.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

drivers/rtc/rtc-at91rm9200.c +0 -0

index b4f7744..4106abc 100644

drivers/rtc/rtc-at91rm9200.c +0 -0

 #define AT91_RTC_EPOCH		1900UL	/* just like arch/arm/common/rtctime.c */
 

Signature · 12 lines

2.1.4

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Quoted 22 lines · Ben Dooks

Change the __raw IO calls to readl/write_relaxed which makes the driver endian agnostic to run properly on big endian systems.

Signed-off-by Ben Dooks <[email protected]>

--
CC: Alessandro Zummo <[email protected]>
CC: rtc-linux at googlegroups.com
CC: linux-arm-kernel at lists.infradead.org
CC: Andrew Victor <[email protected]>
CC: Nicolas Ferre <[email protected]>
CC: Jean-Christophe Plagniol-Villard <[email protected]>

---
 drivers/rtc/rtc-at91rm9200.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

drivers/rtc/rtc-at91rm9200.c +0 -0

index b4f7744..4106abc 100644
@@ -37,9 +37,9 @@
 #include "rtc-at91rm9200.h"
 

drivers/rtc/rtc-at91rm9200.c line 42

Quoted 6 lines

drivers/rtc/rtc-at91rm9200.c +2 -2

 #define at91_rtc_read(field) \
-	__raw_readl(at91_rtc_regs + field)
+	readl_relaxed(at91_rtc_regs + field)
 #define at91_rtc_write(field, val) \
-	__raw_writel((val), at91_rtc_regs + field)
+	writel_relaxed((val), at91_rtc_regs + field)

I'm not against it but the SoC using it are Little only

Change the __raw IO calls to readl/write_relaxed which makes the driver endian agnostic to run properly on big endian systems.

Signed-off-by Ben Dooks <[email protected]>

--
CC: Alessandro Zummo <[email protected]>
CC: rtc-linux at googlegroups.com
CC: linux-arm-kernel at lists.infradead.org
CC: Andrew Victor <[email protected]>
CC: Nicolas Ferre <[email protected]>

CC Jean-Christophe Plagniol-Villard <[email protected]>

---
 drivers/rtc/rtc-at91rm9200.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

drivers/rtc/rtc-at91rm9200.c +2 -2

index b4f7744..4106abc 100644
@@ -37,9 +37,9 @@
 #include "rtc-at91rm9200.h"
 
 #define at91_rtc_read(field) \
-	__raw_readl(at91_rtc_regs + field)
+	readl_relaxed(at91_rtc_regs + field)
 #define at91_rtc_write(field, val) \
-	__raw_writel((val), at91_rtc_regs + field)
+	writel_relaxed((val), at91_rtc_regs + field)
 
 #define AT91_RTC_EPOCH		1900UL	/* just like arch/arm/common/rtctime.c */
 

Use the endian agnositc IO functions instead of the __raw ones for when the driver is in use on big-endian systems.

Signed-off-by Ben Dooks <[email protected]>

Use the endian agnositc IO functions instead of the __raw ones for when the driver is in use on big-endian systems.

Signed-off-by Ben Dooks <[email protected]>

--
CC: Nicolas Ferre <[email protected]> (supporter:ATMEL SPI DRIVER)
CC: Mark Brown <[email protected]> (maintainer:SPI SUBSYSTEM)
CC: linux-spi at vger.kernel.org (open list:SPI SUBSYSTEM)

---
 drivers/spi/spi-atmel.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

drivers/spi/spi-atmel.c +7 -1

index 06de340..a2f40b1 100644
@@ -180,11 +180,17 @@
 	  | SPI_BF(name, value))
 
 /* Register access macros */
+#ifdef CONFIG_AVR32
 #define spi_readl(port, reg) \
 	__raw_readl((port)->regs + SPI_##reg)
 #define spi_writel(port, reg, value) \
 	__raw_writel((value), (port)->regs + SPI_##reg)
-
+#else
+#define spi_readl(port, reg) \
+	readl_relaxed((port)->regs + SPI_##reg)
+#define spi_writel(port, reg, value) \
+	writel_relaxed((value), (port)->regs + SPI_##reg)
+#endif
 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
  * cache operations; better heuristics consider wordsize and bitrate.
  */

Use the endian agnositc IO functions instead of the __raw ones for when the driver is in use on big-endian systems.

Signed-off-by Ben Dooks <[email protected]>

--
CC: Nicolas Ferre <[email protected]> (supporter:ATMEL SPI DRIVER)
CC: Mark Brown <[email protected]> (maintainer:SPI SUBSYSTEM)
CC: linux-spi at vger.kernel.org (open list:SPI SUBSYSTEM)

Change from using the __raw IO accesors to the endian agnostic versions of readl/writel_relaxed when not on AVR32. This fixes issues with running big endian on ARMv7.

Signed-off-by Ben Dooks <[email protected]>

--
CC: Nicolas Ferre <[email protected]>

CC Felipe Balbi <[email protected]>

CC Greg Kroah-Hartman <[email protected]>

CC linux-usb at vger.kernel.org

---
 drivers/usb/gadget/udc/atmel_usba_udc.c |  4 ++--
 drivers/usb/gadget/udc/atmel_usba_udc.h | 22 ++++++++++++++++------
 2 files changed, 18 insertions(+), 8 deletions(-)

drivers/usb/gadget/udc/atmel_usba_udc.c +2 -2

index d79cb35..be2f503 100644
@@ -152,7 +152,7 @@ static int regs_dbg_open(struct inode *inode, struct file *file)
 
 	spin_lock_irq(&udc->lock);
 	for (i = 0; i < inode->i_size / 4; i++)
-		data[i] = __raw_readl(udc->regs + i * 4);
+		data[i] = usba_io_readl(udc->regs + i * 4);
 	spin_unlock_irq(&udc->lock);
 
 	file->private_data = data;

@@ -1249,7 +1249,7 @@ static int handle_ep0_setup(struct usba_udc *udc, struct usba_ep *ep,
 		if (crq->wLength != cpu_to_le16(sizeof(status)))
 			goto stall;
 		ep->state = DATA_STAGE_IN;
-		__raw_writew(status, ep->fifo);
+		usba_io_writew(status, ep->fifo);
 		usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
 		break;
 	}

drivers/usb/gadget/udc/atmel_usba_udc.h +16 -6

index 497cd18..92bd486 100644
@@ -191,18 +191,28 @@
 	 | USBA_BF(name, value))
 
 /* Register access macros */
+#ifdef CONFIG_AVR32
+#define usba_io_readl	__raw_readl
+#define usba_io_writel	__raw_writel
+#define usba_io_writew	__raw_writew
+#else
+#define usba_io_readl	readl_relaxed
+#define usba_io_writel	writel_relaxed
+#define usba_io_writew	writew_relaxed
+#endif
+
 #define usba_readl(udc, reg)					\
-	__raw_readl((udc)->regs + USBA_##reg)
+	usba_io_readl((udc)->regs + USBA_##reg)
 #define usba_writel(udc, reg, value)				\
-	__raw_writel((value), (udc)->regs + USBA_##reg)
+	usba_io_writel((value), (udc)->regs + USBA_##reg)
 #define usba_ep_readl(ep, reg)					\
-	__raw_readl((ep)->ep_regs + USBA_EPT_##reg)
+	usba_io_readl((ep)->ep_regs + USBA_EPT_##reg)
 #define usba_ep_writel(ep, reg, value)				\
-	__raw_writel((value), (ep)->ep_regs + USBA_EPT_##reg)
+	usba_io_writel((value), (ep)->ep_regs + USBA_EPT_##reg)
 #define usba_dma_readl(ep, reg)					\
-	__raw_readl((ep)->dma_regs + USBA_DMA_##reg)
+	usba_io_readl((ep)->dma_regs + USBA_DMA_##reg)
 #define usba_dma_writel(ep, reg, value)				\
-	__raw_writel((value), (ep)->dma_regs + USBA_DMA_##reg)
+	usba_io_writel((value), (ep)->dma_regs + USBA_DMA_##reg)
 
 /* Calculate base address for a given endpoint or DMA controller */
 #define USBA_EPT_BASE(x)	(0x100 + (x) * 0x20)

Le 18/03/2015 16:53, Ben Dooks a ?crit :

Quoted 7 lines

Change from using the __raw IO accesors to the endian agnostic versions of readl/writel_relaxed when not on AVR32. This fixes issues with running big endian on ARMv7.

Signed-off-by Ben Dooks <[email protected]>

--
CC: Nicolas Ferre <[email protected]>

Felipe, for the record:

Acked-by Nicolas Ferre <[email protected]>

Change __raw accesors to endian agnostic versions to allow the driver to work properly on big endian systems.

Signed-off-by Ben Dooks <[email protected]>

--
CC: Wolfgang Grandegger <[email protected]>
CC: Marc Kleine-Budde <[email protected]>
CC: linux-can at vger.kernel.org
CC: netdev at vger.kernel.org
CC: Nicolas Ferre <[email protected]>

---
 drivers/net/can/at91_can.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

drivers/net/can/at91_can.c +2 -2

index eeb4b8b..f4e40aa 100644
@@ -291,13 +291,13 @@ static inline unsigned int get_tx_echo_mb(const struct at91_priv *priv)
 
 static inline u32 at91_read(const struct at91_priv *priv, enum at91_reg reg)
 {
-	return __raw_readl(priv->reg_base + reg);
+	return readl_relaxed(priv->reg_base + reg);
 }
 
 static inline void at91_write(const struct at91_priv *priv, enum at91_reg reg,
 		u32 value)
 {
-	__raw_writel(value, priv->reg_base + reg);
+	writel_relaxed(value, priv->reg_base + reg);
 }
 
 static inline void set_mb_mode_prio(const struct at91_priv *priv,

Change __raw accesors to endian agnostic versions to allow the driver to work properly on big endian systems.

Signed-off-by Ben Dooks <[email protected]>

Change the __raw IO functions to endian agnostic relaxed ones to allow the driver to function on big endian ARM systems.

Signed-off-by Ben Dooks <[email protected]>

--
CC: Ludovic Desroches <[email protected]>
CC: Chris Ball <[email protected]>
CC: Ulf Hansson <[email protected]>
CC: linux-mmc at vger.kernel.org

---
 drivers/mmc/host/atmel-mci-regs.h | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

drivers/mmc/host/atmel-mci-regs.h +1 -1

index c97001e..711bb53 100644
@@ -135,10 +135,17 @@
 #define ATMCI_REGS_SIZE		0x100
 
 /* Register access macros */
-#define atmci_readl(port,reg)				\
+#ifdef CONFIG_AVR32

drivers/mmc/host/atmel-mci-regs.h +0 -0

 /* On AVR chips the Peripheral DMA Controller is not connected to MCI. */
 #ifdef CONFIG_AVR32

Quoted 23 lines · Ben Dooks

Change the __raw IO functions to endian agnostic relaxed ones to allow the driver to function on big endian ARM systems.

Signed-off-by Ben Dooks <[email protected]>

--
CC: Ludovic Desroches <[email protected]>
CC: Chris Ball <[email protected]>
CC: Ulf Hansson <[email protected]>
CC: linux-mmc at vger.kernel.org

---
 drivers/mmc/host/atmel-mci-regs.h | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

drivers/mmc/host/atmel-mci-regs.h +1 -1

index c97001e..711bb53 100644
@@ -135,10 +135,17 @@
 #define ATMCI_REGS_SIZE		0x100
 
 /* Register access macros */
-#define atmci_readl(port,reg)				\
+#ifdef CONFIG_AVR32

drivers/mmc/host/atmel-mci-regs.h line 148

Quoted 10 lines

drivers/mmc/host/atmel-mci-regs.h +7 -0

+#define atmci_readl(port,reg)			\
 	__raw_readl((port)->regs + reg)
 #define atmci_writel(port,reg,value)			\
 	__raw_writel((value), (port)->regs + reg)
+#else
+#define atmci_readl(port,reg)			\
+	readl_relaxed((port)->regs + reg)
+#define atmci_writel(port,reg,value)			\
+	writel_relaxed((value), (port)->regs + reg)
+#endif

This pattern is repeated in a lot of drivers; is it worth defining atmel_{read,write}l_relaxed() in a common header?

#ifdef CONFIG_AVR32

/* CPU and peripherals are both big-endian, so don't byte-swap */
#define atmel_readl_relaxed(addr) __raw_readl(addr)
#define atmel_writel_relaxed(value, addr) __raw_writel(value, addr)

#else

/* Peripherals are little-endian, so byte-swap if CPU isn't */
#define atmel_readl_relaxed(addr) readl_relaxed(addr)
#define atmel_writel_relaxed(value, addr) writel_relaxed(value, addr)

#endif

Ben.

Quoted 46 lines · Ben Hutchings

Quoted 23 lines · Ben Dooks

Change the __raw IO functions to endian agnostic relaxed ones to allow the driver to function on big endian ARM systems.

Signed-off-by Ben Dooks <[email protected]>

--
CC: Ludovic Desroches <[email protected]>
CC: Chris Ball <[email protected]>
CC: Ulf Hansson <[email protected]>
CC: linux-mmc at vger.kernel.org

---
 drivers/mmc/host/atmel-mci-regs.h | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

drivers/mmc/host/atmel-mci-regs.h +1 -1

index c97001e..711bb53 100644
@@ -135,10 +135,17 @@
 #define ATMCI_REGS_SIZE		0x100
 
 /* Register access macros */
-#define atmci_readl(port,reg)				\
+#ifdef CONFIG_AVR32

drivers/mmc/host/atmel-mci-regs.h line 148

Quoted 10 lines

drivers/mmc/host/atmel-mci-regs.h +7 -0

+#define atmci_readl(port,reg)			\
 	__raw_readl((port)->regs + reg)
 #define atmci_writel(port,reg,value)			\
 	__raw_writel((value), (port)->regs + reg)
+#else
+#define atmci_readl(port,reg)			\
+	readl_relaxed((port)->regs + reg)
+#define atmci_writel(port,reg,value)			\
+	writel_relaxed((value), (port)->regs + reg)
+#endif

This pattern is repeated in a lot of drivers; is it worth defining atmel_{read,write}l_relaxed() in a common header?

#ifdef CONFIG_AVR32

/* CPU and peripherals are both big-endian, so don't byte-swap */
#define atmel_readl_relaxed(addr) __raw_readl(addr)
#define atmel_writel_relaxed(value, addr) __raw_writel(value, addr)

#else

Quoted 7 lines

/* Peripherals are little-endian, so byte-swap if CPU isn't */
#define atmel_readl_relaxed(addr) readl_relaxed(addr)
#define atmel_writel_relaxed(value, addr) writel_relaxed(value, addr)

#endif

Ben.

Hi, I think it will probably be a good idea to have an avr32/at91 read/write functions however I will put this forward as a separate series as it will require both avr32 and at91 maintainers as well as driver updates.

how about:

	atmel_readl_onchip{b,w,l}
	atmel_writel_onchip{b,w,l}

Change the __raw IO functions to endian agnostic relaxed ones to allow the driver to function on big endian ARM systems.

Signed-off-by Ben Dooks <[email protected]>

--
CC: Ludovic Desroches <[email protected]>
CC: Chris Ball <[email protected]>
CC: Ulf Hansson <[email protected]>
CC: linux-mmc at vger.kernel.org

---
 drivers/mmc/host/atmel-mci-regs.h | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

drivers/mmc/host/atmel-mci-regs.h +8 -1

index c97001e..711bb53 100644
@@ -135,10 +135,17 @@
 #define ATMCI_REGS_SIZE		0x100
 
 /* Register access macros */
-#define atmci_readl(port,reg)				\
+#ifdef CONFIG_AVR32
+#define atmci_readl(port,reg)			\
 	__raw_readl((port)->regs + reg)
 #define atmci_writel(port,reg,value)			\
 	__raw_writel((value), (port)->regs + reg)
+#else
+#define atmci_readl(port,reg)			\
+	readl_relaxed((port)->regs + reg)
+#define atmci_writel(port,reg,value)			\
+	writel_relaxed((value), (port)->regs + reg)
+#endif
 
 /* On AVR chips the Peripheral DMA Controller is not connected to MCI. */
 #ifdef CONFIG_AVR32

Signature · 1 line

2.1.4

Change the __raw IO functions to endian agnostic relaxed ones to allow the driver to function on big endian ARM systems.

Signed-off-by Ben Dooks <[email protected]>

--
CC: Ludovic Desroches <[email protected]>
CC: Chris Ball <[email protected]>
CC: Ulf Hansson <[email protected]>
CC: linux-mmc at vger.kernel.org

---
 drivers/mmc/host/atmel-mci-regs.h | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

drivers/mmc/host/atmel-mci-regs.h +8 -2

index c97001e..711bb53 100644
@@ -135,10 +135,17 @@
 #define ATMCI_REGS_SIZE                0x100
 
 /* Register access macros */
-#define atmci_readl(port,reg)                          \
+#ifdef CONFIG_AVR32
+#define atmci_readl(port,reg)                  \
        __raw_readl((port)->regs + reg)
 #define atmci_writel(port,reg,value)                   \
        __raw_writel((value), (port)->regs + reg)
+#else
+#define atmci_readl(port,reg)                  \
+       readl_relaxed((port)->regs + reg)
+#define atmci_writel(port,reg,value)                   \
+       writel_relaxed((value), (port)->regs + reg)
+#endif
 
 /* On AVR chips the Peripheral DMA Controller is not connected to MCI. */
 #ifdef CONFIG_AVR32
--

2.1.4

I have been testing the ATSAMA5D36 xplained board with big endian and the following are the fixes to get the system working.

Hi,

Quoted 3 lines · Ben Dooks

I have been testing the ATSAMA5D36 xplained board with big endian and the following are the fixes to get the system working.

The series looks good to me, we will drop patches 3 and 4 as the files doesn't exist anymore.

Quoted 3 lines · Alexandre Belloni

Hi,

On 18/03/2015 at 15:52:59 +0000, Ben Dooks wrote :

Quoted 6 lines

Quoted 3 lines

I have been testing the ATSAMA5D36 xplained board with big endian and the following are the fixes to get the system working.

The series looks good to me, we will drop patches 3 and 4 as the files doesn't exist anymore.

Where can I find a repository with these changes in?

Quoted 11 lines · Ben Dooks

Quoted 9 lines · Alexandre Belloni

Hi,

Quoted 3 lines · Ben Dooks

I have been testing the ATSAMA5D36 xplained board with big endian and the following are the fixes to get the system working.

The series looks good to me, we will drop patches 3 and 4 as the files doesn't exist anymore.

Quoted 2 lines

Where can I find a repository with these changes in?

You can use this branch until Nicolas merges my patches:

https://github.com/alexandrebelloni/linux/tree/at91_4.1_04_cleanup2

The remaining __raw_writel and __raw_readl are in pm.h

Quoted 5 lines

You can use this branch until Nicolas merges my patches:

https://github.com/alexandrebelloni/linux/tree/at91_4.1_04_cleanup2

The remaining __raw_writel and __raw_readl are in pm.h

Ok, should I submit my next series for inclusion in to your tree?

Hi,

Quoted 4 lines · Ben Dooks

Quoted 4 lines

You can use this branch until Nicolas merges my patches:

https://github.com/alexandrebelloni/linux/tree/at91_4.1_04_cleanup2

Quoted 4 lines

Quoted 1 line

The remaining __raw_writel and __raw_readl are in pm.h

Ok, should I submit my next series for inclusion in to your tree?

I've sent all my series and Nicolas is supposed to take them soon so I think the best would be to wait a bit. IF you want, I'll ping you when everything is in.

Quoted 9 lines

Hi,

Quoted 6 lines · Ben Dooks

Quoted 5 lines

You can use this branch until Nicolas merges my patches:

https://github.com/alexandrebelloni/linux/tree/at91_4.1_04_cleanup2

The remaining __raw_writel and __raw_readl are in pm.h

Quoted 6 lines

Quoted 2 lines

Ok, should I submit my next series for inclusion in to your tree?

I've sent all my series and Nicolas is supposed to take them soon so I think the best would be to wait a bit. IF you want, I'll ping you when everything is in.

Ok, I'll try and re-base on and test with your series in prep.

I have been testing the ATSAMA5D36 xplained board with big endian and the following are the fixes to get the system working.