Amlogic Meson8b pinctrl driver support

PATCH Superseded Carlo Caione 3 participants 11 messages Mar 19, 2015 – Apr 7, 2015

Subsystems (4)

Device tree bindings GPIO Arm/Amlogic Meson SoC support Pin control

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Carlo Caione

author

2015-03-19 21:34 UTC #0 lore raw

v3 cover Amlogic Meson8b pinctrl driver support

From: Carlo Caione <[email protected]>

This patchset extends the pinctrl driver to support AmLogic Meson8b. The driver for Meson8 has been revised to make it shorter.

Changelog:

v3: * shorten the meson8/meson8b support files
* document GPIO banks for meson8b
v2: * fix holes in GPIOs numbering
v1: * initial version

Carlo Caione (3):
pinctrl: Cleanup Meson8 driver
documentation: Extend pinctrl docs for Meson8b
pinctrl: Add support for Meson8b

 .../devicetree/bindings/pinctrl/meson,pinctrl.txt  |    2 +-
 drivers/pinctrl/meson/Makefile                     |    2 +-
 drivers/pinctrl/meson/pinctrl-meson.c              |    9 +-
 drivers/pinctrl/meson/pinctrl-meson.h              |    9 +-
 drivers/pinctrl/meson/pinctrl-meson8.c             | 1050 +++++++++-----------
 drivers/pinctrl/meson/pinctrl-meson8b.c            |  900 +++++++++++++++++
 include/dt-bindings/gpio/meson8b-gpio.h            |   32 +
 7 files changed, 1403 insertions(+), 601 deletions(-)
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson8b.c
 create mode 100644 include/dt-bindings/gpio/meson8b-gpio.h

Signature · 1 line

1.9.1

Carlo Caione

author

2015-03-19 21:34 UTC #1 lore raw

PATCH v3 1/3 pinctrl: Cleanup Meson8 driver

From: Carlo Caione <[email protected]>

This patch introduces a new PIN macro and few small modifications to simplify and shorten the Meson pinctrl drivers and cleanup the support file for the AmLogic Meson8 SoC.

Signed-off-by Carlo Caione <[email protected]>

---
 drivers/pinctrl/meson/pinctrl-meson.h  |    8 +-
 drivers/pinctrl/meson/pinctrl-meson8.c | 1050 ++++++++++++++------------------
 2 files changed, 461 insertions(+), 597 deletions(-)

drivers/pinctrl/meson/pinctrl-meson.h +5 -3

index bfea8ad..bc48c78 100644
@@ -155,6 +155,8 @@ struct meson_pinctrl {
 	struct meson_domain *domains;
 };
 
+#define PIN(x, b)	(b + x)
+
 #define GROUP(grp, r, b)						\
 	{								\
 		.name = #grp,						\

@@ -165,10 +167,10 @@ struct meson_pinctrl {
 		.domain = 0,						\
 	 }
 
-#define GPIO_GROUP(gpio)						\
+#define GPIO_GROUP(gpio, b)						\
 	{								\
 		.name = #gpio,						\
-		.pins = (const unsigned int[]){ PIN_ ## gpio},		\
+		.pins = (const unsigned int[]){ PIN(gpio, b) },		\
 		.num_pins = 1,						\
 		.is_gpio = true,					\
 	 }

@@ -204,6 +206,6 @@ struct meson_pinctrl {
 		},							\
 	 }
 
-#define MESON_PIN(x) PINCTRL_PIN(PIN_ ## x, #x)
+#define MESON_PIN(x, b) PINCTRL_PIN(PIN(x, b), #x)
 
 extern struct meson_pinctrl_data meson8_pinctrl_data;

drivers/pinctrl/meson/pinctrl-meson8.c +456 ~~-594~~

1,095 lines not on this page · raw message

Signature · 1 line

1.9.1

Beniamino Galvani

2015-03-28 09:47 UTC #2 lore raw

PATCH v3 1/3 pinctrl: Cleanup Meson8 driver

Quoted 5 lines · Carlo Caione

From: Carlo Caione <[email protected]>
This patch introduces a new PIN macro and few small modifications to simplify and shorten the Meson pinctrl drivers and cleanup the support file for the AmLogic Meson8 SoC.

Hi Carlo,

nice cleanup.

Acked-by Beniamino Galvani <[email protected]>

Linus Walleij

2015-04-07 09:42 UTC #3 lore raw

PATCH v3 1/3 pinctrl: Cleanup Meson8 driver

In reply to Carlo Caione

Quoted 7 lines · Carlo Caione

From: Carlo Caione <[email protected]>
This patch introduces a new PIN macro and few small modifications to simplify and shorten the Meson pinctrl drivers and cleanup the support file for the AmLogic Meson8 SoC.
Signed-off-by Carlo Caione <[email protected]>

Patch applied with Beniamino's ACK.

Yours,
Linus Walleij

Carlo Caione

author

2015-03-19 21:34 UTC #4 lore raw

PATCH v3 2/3 documentation: Extend pinctrl docs for Meson8b

In reply to Carlo Caione

From: Carlo Caione <[email protected]>

Add the compatible string for Meson8b in Meson pinctrl documentation and add new information for Meson8b in source code comments.

Signed-off-by Carlo Caione <[email protected]>

---
 Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt | 2 +-
 drivers/pinctrl/meson/pinctrl-meson.c                       | 5 +++--
 2 files changed, 4 insertions(+), 3 deletions(-)

Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt +1 -1

index 17e7240..3f6a524 100644
@@ -1,7 +1,7 @@
 == Amlogic Meson pinmux controller ==
 
 Required properties for the root node:
- - compatible: "amlogic,meson8-pinctrl"
+ - compatible: "amlogic,meson8-pinctrl" or "amlogic,meson8b-pinctrl"
  - reg: address and size of registers controlling irq functionality
 
 === GPIO sub-nodes ===

drivers/pinctrl/meson/pinctrl-meson.c +3 -2

index a2bf49c..e0195c1 100644
@@ -13,8 +13,9 @@
 
 /*
  * The available pins are organized in banks (A,B,C,D,E,X,Y,Z,AO,
- * BOOT,CARD for meson6 and X,Y,DV,H,Z,AO,BOOT,CARD for meson8) and
- * each bank has a variable number of pins.
+ * BOOT,CARD for meson6, X,Y,DV,H,Z,AO,BOOT,CARD for meson8 and
+ * X,Y,DV,H,AO,BOOT,CARD,DIF for meson8b) and each bank has a
+ * variable number of pins.
  *
  * The AO bank is special because it belongs to the Always-On power
  * domain which can't be powered off; the bank also uses a set of

Signature · 1 line

1.9.1

Beniamino Galvani

2015-03-28 09:49 UTC #5 lore raw

PATCH v3 2/3 documentation: Extend pinctrl docs for Meson8b

Quoted 4 lines · Carlo Caione

From: Carlo Caione <[email protected]>
Add the compatible string for Meson8b in Meson pinctrl documentation and add new information for Meson8b in source code comments.

Acked-by Beniamino Galvani <[email protected]>

Linus Walleij

2015-04-07 09:43 UTC #6 lore raw

PATCH v3 2/3 documentation: Extend pinctrl docs for Meson8b

In reply to Carlo Caione

Quoted 6 lines · Carlo Caione

From: Carlo Caione <[email protected]>
Add the compatible string for Meson8b in Meson pinctrl documentation and add new information for Meson8b in source code comments.
Signed-off-by Carlo Caione <[email protected]>

Patch applied with Beniamino's ACK.

Yours,
Linus Walleij

Carlo Caione

author

2015-03-19 21:34 UTC #7 lore raw

PATCH v3 3/3 pinctrl: Add support for Meson8b

In reply to Carlo Caione

From: Carlo Caione <[email protected]>

This patch adds support for the AmLogic Meson8b SoC.

Signed-off-by Carlo Caione <[email protected]>

---
 drivers/pinctrl/meson/Makefile          |   2 +-
 drivers/pinctrl/meson/pinctrl-meson.c   |   4 +
 drivers/pinctrl/meson/pinctrl-meson.h   |   1 +
 drivers/pinctrl/meson/pinctrl-meson8b.c | 900 ++++++++++++++++++++++++++++++++
 include/dt-bindings/gpio/meson8b-gpio.h |  32 ++
 5 files changed, 938 insertions(+), 1 deletion(-)
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson8b.c
 create mode 100644 include/dt-bindings/gpio/meson8b-gpio.h

drivers/pinctrl/meson/Makefile +1 -1

index eafc216..c751d22 100644
@@ -1,2 +1,2 @@
-obj-y	+= pinctrl-meson8.o
+obj-y	+= pinctrl-meson8.o pinctrl-meson8b.o
 obj-y	+= pinctrl-meson.o

drivers/pinctrl/meson/pinctrl-meson.c +4 -0

index e0195c1..edcd140 100644
@@ -545,6 +545,10 @@ static const struct of_device_id meson_pinctrl_dt_match[] = {
 		.compatible = "amlogic,meson8-pinctrl",
 		.data = &meson8_pinctrl_data,
 	},
+	{
+		.compatible = "amlogic,meson8b-pinctrl",
+		.data = &meson8b_pinctrl_data,
+	},
 	{ },
 };
 MODULE_DEVICE_TABLE(of, meson_pinctrl_dt_match);

drivers/pinctrl/meson/pinctrl-meson.h +1 -0

index bc48c78..0fe7d53 100644
@@ -209,3 +209,4 @@ struct meson_pinctrl {
 #define MESON_PIN(x, b) PINCTRL_PIN(PIN(x, b), #x)
 
 extern struct meson_pinctrl_data meson8_pinctrl_data;
+extern struct meson_pinctrl_data meson8b_pinctrl_data;

drivers/pinctrl/meson/pinctrl-meson8b.c new file +900 -0

900 lines not on this page · raw message

include/dt-bindings/gpio/meson8b-gpio.h new file +32 -0

new file mode 100644
index 0000000..8e02a05
@@ -0,0 +1,32 @@
+/*
+ * GPIO definitions for Amlogic Meson8b SoCs
+ *
+ * Copyright (C) 2015 Endless Mobile, Inc.
+ * Author: Carlo Caione <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _DT_BINDINGS_MESON8B_GPIO_H
+#define _DT_BINDINGS_MESON8B_GPIO_H
+
+#include <dt-bindings/gpio/meson8-gpio.h>
+
+/* GPIO Bank DIF */
+#define DIF_0_P		0
+#define DIF_0_N		1
+#define DIF_1_P		2
+#define DIF_1_N		3
+#define DIF_2_P		4
+#define DIF_2_N		5
+#define DIF_3_P		6
+#define DIF_3_N		7
+#define DIF_4_P		8
+#define DIF_4_N		9
+
+#endif /* _DT_BINDINGS_MESON8B_GPIO_H */

Signature · 1 line

1.9.1

Beniamino Galvani

2015-03-28 10:06 UTC #8 lore raw

PATCH v3 3/3 pinctrl: Add support for Meson8b

Quoted 17 lines · Carlo Caione

From: Carlo Caione <[email protected]>

This patch adds support for the AmLogic Meson8b SoC.

Signed-off-by Carlo Caione <[email protected]>

---
 drivers/pinctrl/meson/Makefile          |   2 +-
 drivers/pinctrl/meson/pinctrl-meson.c   |   4 +
 drivers/pinctrl/meson/pinctrl-meson.h   |   1 +
 drivers/pinctrl/meson/pinctrl-meson8b.c | 900 ++++++++++++++++++++++++++++++++
 include/dt-bindings/gpio/meson8b-gpio.h |  32 ++
 5 files changed, 938 insertions(+), 1 deletion(-)
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson8b.c
 create mode 100644 include/dt-bindings/gpio/meson8b-gpio.h

[...]

drivers/pinctrl/meson/pinctrl-meson8b.c line 867

Quoted 10 lines

drivers/pinctrl/meson/pinctrl-meson8b.c new file +10 -0

+static struct meson_bank meson8b_banks[] = {
+	/*   name    first                      last                   pullen  pull    dir     out     in  */
+	BANK("X",    PIN(GPIOX_0, 0),		PIN(GPIOX_21, 0),      4,  0,  4,  0,  0,  0,  1,  0,  2,  0),
+	BANK("Y",    PIN(GPIOY_0, 0),		PIN(GPIOY_14, 0),      3,  0,  3,  0,  3,  0,  4,  0,  5,  0),
+	BANK("DV",   PIN(GPIODV_9, 0),		PIN(GPIODV_29, 0),     0,  0,  0,  0,  7,  0,  8,  0,  9,  0),
+	BANK("H",    PIN(GPIOH_0, 0),		PIN(GPIOH_9, 0),       1, 16,  1, 16,  9, 19, 10, 19, 11, 19),
+	BANK("CARD", PIN(CARD_0, 0),		PIN(CARD_6, 0),        2, 20,  2, 20,  0, 22,  1, 22,  2, 22),
+	BANK("BOOT", PIN(BOOT_0, 0),		PIN(BOOT_18, 0),       2,  0,  2,  0,  9,  0, 10,  0, 11,  0),
+	BANK("DIF",  PIN(DIF_0_P, DIF_OFF),	PIN(DIF_4_N, DIF_OFF), 5,  8,  5,  8, 12, 12, 13, 12, 14, 12),
+};

So DIF pins belong to the standard domain and this is ok since they use the same range of registers of other non-AO pins, but see below...

Quoted 21 lines

drivers/pinctrl/meson/pinctrl-meson8b.c new file +6 -0

+
+static struct meson_bank meson8b_ao_banks[] = {
+	/*   name    first                  last                      pullen  pull    dir     out     in  */
+	BANK("AO",   PIN(GPIOAO_0, AO_OFF), PIN(GPIO_TEST_N, AO_OFF), 0,  0,  0, 16,  0,  0,  0, 16,  1,  0),
+};
+
 
[...]

include/dt-bindings/gpio/meson8b-gpio.h new file +9 -0

@@ -0,0 +1,32 @@
+
+#ifndef _DT_BINDINGS_MESON8B_GPIO_H
+#define _DT_BINDINGS_MESON8B_GPIO_H
+
+#include <dt-bindings/gpio/meson8-gpio.h>
+
+/* GPIO Bank DIF */
+#define DIF_0_P		0
+#define DIF_0_N		1

include/dt-bindings/gpio/meson8b-gpio.h line 19

Quoted 10 lines

include/dt-bindings/gpio/meson8b-gpio.h new file +10 -0

+#define DIF_1_P		2
+#define DIF_1_N		3
+#define DIF_2_P		4
+#define DIF_2_N		5
+#define DIF_3_P		6
+#define DIF_3_N		7
+#define DIF_4_P		8
+#define DIF_4_N		9
+
+#endif /* _DT_BINDINGS_MESON8B_GPIO_H */

... however these definitions start from 0 and thus overlap with the definitions in meson8-gpio.h.

This means that the following GPIO specifier in a DTS:

gpios = <&gpio DIF_0_P GPIO_ACTIVE_HIGH>

has the same effect as

gpios = <&gpio GPIOX_0 GPIO_ACTIVE_HIGH>

I think that DIF_* pins should have a different numbering, for example starting just after the end of the last non-AO pin. AO pin should also be shifted accordingly.

Beniamino

Carlo Caione

author

2015-03-28 10:24 UTC #9 lore raw

PATCH v3 3/3 pinctrl: Add support for Meson8b

Quoted 71 lines · Beniamino Galvani

Quoted 17 lines · Carlo Caione

From: Carlo Caione <[email protected]>

This patch adds support for the AmLogic Meson8b SoC.

Signed-off-by Carlo Caione <[email protected]>

---
 drivers/pinctrl/meson/Makefile          |   2 +-
 drivers/pinctrl/meson/pinctrl-meson.c   |   4 +
 drivers/pinctrl/meson/pinctrl-meson.h   |   1 +
 drivers/pinctrl/meson/pinctrl-meson8b.c | 900 ++++++++++++++++++++++++++++++++
 include/dt-bindings/gpio/meson8b-gpio.h |  32 ++
 5 files changed, 938 insertions(+), 1 deletion(-)
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson8b.c
 create mode 100644 include/dt-bindings/gpio/meson8b-gpio.h

[...]

drivers/pinctrl/meson/pinctrl-meson8b.c line 867

Quoted 10 lines

drivers/pinctrl/meson/pinctrl-meson8b.c new file +10 -0

+static struct meson_bank meson8b_banks[] = {
+     /*   name    first                      last                   pullen  pull    dir     out     in  */
+     BANK("X",    PIN(GPIOX_0, 0),           PIN(GPIOX_21, 0),      4,  0,  4,  0,  0,  0,  1,  0,  2,  0),
+     BANK("Y",    PIN(GPIOY_0, 0),           PIN(GPIOY_14, 0),      3,  0,  3,  0,  3,  0,  4,  0,  5,  0),
+     BANK("DV",   PIN(GPIODV_9, 0),          PIN(GPIODV_29, 0),     0,  0,  0,  0,  7,  0,  8,  0,  9,  0),
+     BANK("H",    PIN(GPIOH_0, 0),           PIN(GPIOH_9, 0),       1, 16,  1, 16,  9, 19, 10, 19, 11, 19),
+     BANK("CARD", PIN(CARD_0, 0),            PIN(CARD_6, 0),        2, 20,  2, 20,  0, 22,  1, 22,  2, 22),
+     BANK("BOOT", PIN(BOOT_0, 0),            PIN(BOOT_18, 0),       2,  0,  2,  0,  9,  0, 10,  0, 11,  0),
+     BANK("DIF",  PIN(DIF_0_P, DIF_OFF),     PIN(DIF_4_N, DIF_OFF), 5,  8,  5,  8, 12, 12, 13, 12, 14, 12),
+};

So DIF pins belong to the standard domain and this is ok since they use the same range of registers of other non-AO pins, but see below...

Quoted 21 lines

drivers/pinctrl/meson/pinctrl-meson8b.c new file +6 -0

+
+static struct meson_bank meson8b_ao_banks[] = {
+     /*   name    first                  last                      pullen  pull    dir     out     in  */
+     BANK("AO",   PIN(GPIOAO_0, AO_OFF), PIN(GPIO_TEST_N, AO_OFF), 0,  0,  0, 16,  0,  0,  0, 16,  1,  0),
+};
+
 
[...]

include/dt-bindings/gpio/meson8b-gpio.h new file +9 -0

@@ -0,0 +1,32 @@
+
+#ifndef _DT_BINDINGS_MESON8B_GPIO_H
+#define _DT_BINDINGS_MESON8B_GPIO_H
+
+#include <dt-bindings/gpio/meson8-gpio.h>
+
+/* GPIO Bank DIF */
+#define DIF_0_P              0
+#define DIF_0_N              1

include/dt-bindings/gpio/meson8b-gpio.h line 19

Quoted 10 lines

include/dt-bindings/gpio/meson8b-gpio.h new file +10 -0

+#define DIF_1_P              2
+#define DIF_1_N              3
+#define DIF_2_P              4
+#define DIF_2_N              5
+#define DIF_3_P              6
+#define DIF_3_N              7
+#define DIF_4_P              8
+#define DIF_4_N              9
+
+#endif /* _DT_BINDINGS_MESON8B_GPIO_H */

... however these definitions start from 0 and thus overlap with the definitions in meson8-gpio.h.

This means that the following GPIO specifier in a DTS:

gpios = <&gpio DIF_0_P GPIO_ACTIVE_HIGH>

Quoted 7 lines

has the same effect as
gpios = <&gpio GPIOX_0 GPIO_ACTIVE_HIGH>
I think that DIF_* pins should have a different numbering, for example starting just after the end of the last non-AO pin. AO pin should also be shifted accordingly.

Right. Fix in v4.

Thanks for the review.

Signature · 1 line

Carlo Caione

Linus Walleij

2015-03-27 09:02 UTC #10 lore raw

v3 cover Amlogic Meson8b pinctrl driver support

In reply to Carlo Caione

Quoted 11 lines · Carlo Caione

From: Carlo Caione <[email protected]>
This patchset extends the pinctrl driver to support AmLogic Meson8b. The driver for Meson8 has been revised to make it shorter.
Changelog:
v3: * shorten the meson8/meson8b support files
* document GPIO banks for meson8b
v2: * fix holes in GPIOs numbering
v1: * initial version

Beniamino, can you look at this patch set? I want your ACK before applying.

Yours,
Linus Walleij