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clk: sunxi: Add muxable AHB clock to fix hstimer issues

PATCH Superseded Chen-Yu Tsai 2 participants 9 messages Mar 24, 2015 – Mar 30, 2015

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Device tree bindings Common clk Arm/Allwinner sunXi SoC support Arm/Allwinner SoC Clock Support
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Chen-Yu Tsai

author
#0 lore raw

v2 cover clk: sunxi: Add muxable AHB clock to fix hstimer issues

Hi everyone,

This is v2 of the sun5i muxable AHB clock series.

Changes since v1:

- Dropped patches 1~3 that are merged
- Extend comments to clarify what the "base factor clock" refers to, and what the divs clocks outputs should be.

This series adds support for the muxable ahb clock on sun5/7i. The mux has inputs such as the axi clock, the cpu clock on sun5i, and pll6 with various dividers. The goal is to have ahb muxed to pll6, which should be a fixed rate albeit configurable clock. This fixes issues with cpufreq changing the cpu frequency, which would affect the hstimer clocked from ahb.

Patch 1 makes divs clocks explicitly specify in the driver which output is the base factor clock, instead of always putting it in last. This is done to ensure DT bindings compatibility when we add outputs.

Patch 2 adds the new pll6/4 output, which is used on sun7i as an input to ahb mux.

Patch 3 updates the dtsi files with the new drivers.

The series is also available at

https://github.com/wens/linux/commits/sun5i-ahb-v2

Regards
ChenYu

Chen-Yu Tsai (3):
clk: sunxi: Make divs clocks specify which output is the base factor
clock
clk: sunxi: Add pll6 / 4 clock output to sun4i-a10-pll6
ARM: dts: sunxi: Update ahb clocks for sun5i and sun7i

 arch/arm/boot/dts/sun5i.dtsi     | 10 ++++++++--
 arch/arm/boot/dts/sun7i-a20.dtsi | 13 ++++++++++---
 drivers/clk/sunxi/clk-sunxi.c    | 38 ++++++++++++++++++++++++++------------
 3 files changed, 44 insertions(+), 17 deletions(-)
Signature · 1 line
2.1.4
author
#1 lore raw

PATCH v2 1/3 clk: sunxi: Make divs clocks specify which output is the base factor clock

The current sunxi clock driver has the base factor clock of divs clocks as the last clock output of the clock node. This makes it rather difficult to add new outputs, such as fixed dividers, which were previously unknown.

This patch makes the divs clocks data structure specify which output is the factor clock, and updates all current divs clocks accordingly.

We can then add new outputs after the factor clocks, at least not breaking backward compatibility with regards to the devicetree bindings.

Also replace kzalloc with kcalloc in sunxi_divs_clk_setup().

Signed-off-by Chen-Yu Tsai <[email protected]>
---
 drivers/clk/sunxi/clk-sunxi.c | 37 +++++++++++++++++++++++++------------
 1 file changed, 25 insertions(+), 12 deletions(-)
drivers/clk/sunxi/clk-sunxi.c +25 -12
index d92e30371d8a..9f31314a9cd7 100644
@@ -1046,13 +1046,20 @@ static void __init sunxi_gates_clk_setup(struct device_node *node,
  * sunxi_divs_clk_setup() helper data
  */
 
-#define SUNXI_DIVS_MAX_QTY	2
+#define SUNXI_DIVS_MAX_QTY	4
 #define SUNXI_DIVISOR_WIDTH	2
 
 struct divs_data {
 	const struct factors_data *factors; /* data for the factor clock */
-	int ndivs; /* number of children */
+	int ndivs; /* number of outputs */
+	/*
+	 * List of outputs. Refer to the diagram for sunxi_divs_clk_setup():
+	 * self or base factor clock refers to the output from the pll
+	 * itself. The remaining refer to fixed or configurable divider
+	 * outputs.
+	 */
 	struct {
+		u8 self; /* is it the base factor clock? (only one) */
 		u8 fixed; /* is it a fixed divisor? if not... */
 		struct clk_div_table *table; /* is it a table based divisor? */
 		u8 shift; /* otherwise it's a normal divisor with this shift */

@@ -1075,23 +1082,26 @@ static const struct divs_data pll5_divs_data __initconst = {
 	.div = {
 		{ .shift = 0, .pow = 0, }, /* M, DDR */
 		{ .shift = 16, .pow = 1, }, /* P, other */
+		/* No output for the base factor clock */
 	}
 };
 
 static const struct divs_data pll6_divs_data __initconst = {
 	.factors = &sun4i_pll6_data,
-	.ndivs = 2,
+	.ndivs = 3,
 	.div = {
 		{ .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */
 		{ .fixed = 2 }, /* P, other */
+		{ .self = 1 }, /* base factor clock, 2x */
 	}
 };
 
 static const struct divs_data sun6i_a31_pll6_divs_data __initconst = {
 	.factors = &sun6i_a31_pll6_data,
-	.ndivs = 1,
+	.ndivs = 2,
 	.div = {
 		{ .fixed = 2 }, /* normal output */
+		{ .self = 1 }, /* base factor clock, 2x */
 	}
 };
 

@@ -1122,6 +1132,10 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
 	int ndivs = SUNXI_DIVS_MAX_QTY, i = 0;
 	int flags, clkflags;
 
+	/* if number of children known, use it */
+	if (data->ndivs)
+		ndivs = data->ndivs;
+
 	/* Set up factor clock that we will be dividing */
 	pclk = sunxi_factors_clk_setup(node, data->factors);
 	parent = __clk_get_name(pclk);

@@ -1132,7 +1146,7 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
 	if (!clk_data)
 		return;
 
-	clks = kzalloc((SUNXI_DIVS_MAX_QTY+1) * sizeof(*clks), GFP_KERNEL);
+	clks = kcalloc(ndivs, sizeof(*clks), GFP_KERNEL);
 	if (!clks)
 		goto free_clkdata;
 

@@ -1142,15 +1156,17 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
 	 * our RAM clock! */
 	clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT;
 
-	/* if number of children known, use it */
-	if (data->ndivs)
-		ndivs = data->ndivs;
-
 	for (i = 0; i < ndivs; i++) {
 		if (of_property_read_string_index(node, "clock-output-names",
 						  i, &clk_name) != 0)
 			break;
 
+		/* If this is the base factor clock, only update clks */
+		if (data->div[i].self) {
+			clk_data->clks[i] = pclk;
+			continue;
+		}
+
 		gate_hw = NULL;
 		rate_hw = NULL;
 		rate_ops = NULL;

@@ -1209,9 +1225,6 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
 		clk_register_clkdev(clks[i], clk_name, NULL);
 	}
 
-	/* The last clock available on the getter is the parent */
-	clks[i++] = pclk;
-
 	/* Adjust to the real max */
 	clk_data->clk_num = i;
Signature · 1 line
2.1.4
author
#2 lore raw

PATCH v2 2/3 clk: sunxi: Add pll6 / 4 clock output to sun4i-a10-pll6

In reply to Chen-Yu Tsai

The pll6 has a /4 output that is used as an input to the ahb mux clock.

Signed-off-by Chen-Yu Tsai <[email protected]>
---
 drivers/clk/sunxi/clk-sunxi.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)
drivers/clk/sunxi/clk-sunxi.c +2 -1
index 9f31314a9cd7..7e1e2bd189b6 100644
@@ -1088,11 +1088,12 @@ static const struct divs_data pll5_divs_data __initconst = {
 
 static const struct divs_data pll6_divs_data __initconst = {
 	.factors = &sun4i_pll6_data,
-	.ndivs = 3,
+	.ndivs = 4,
 	.div = {
 		{ .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */
 		{ .fixed = 2 }, /* P, other */
 		{ .self = 1 }, /* base factor clock, 2x */
+		{ .fixed = 4 }, /* pll6 / 4, used as ahb input */
 	}
 };
Signature · 1 line
2.1.4
author
#3 lore raw

PATCH v2 3/3 ARM: dts: sunxi: Update ahb clocks for sun5i and sun7i

In reply to Chen-Yu Tsai

The clock driver now supports a muxable ahb clock. Update the dtsi with the proper compatible and add the new parent clocks.

This also adds the new pll6/4 output for pll6 on sun7i-a20. The output is not used on sun4/5i.

Also use assigned-clocks to reparent ahb to pll6. We want ahb to have a stable, non-changing clock rate. cpu/axi clock rate changes as a result of newly added cpufreq support.

Signed-off-by Chen-Yu Tsai <[email protected]>
---
 arch/arm/boot/dts/sun5i.dtsi     | 10 ++++++++--
 arch/arm/boot/dts/sun7i-a20.dtsi | 13 ++++++++++---
 2 files changed, 18 insertions(+), 5 deletions(-)
arch/arm/boot/dts/sun5i.dtsi +8 -2
index e42cbb03620f..df79b4c75b34 100644
@@ -150,10 +150,16 @@
 
 		ahb: ahb at 01c20054 {
 			#clock-cells = <0>;
-			compatible = "allwinner,sun4i-a10-ahb-clk";
+			compatible = "allwinner,sun5i-a13-ahb-clk";
 			reg = <0x01c20054 0x4>;
-			clocks = <&axi>;
+			clocks = <&axi>, <&cpu>, <&pll6 1>;
 			clock-output-names = "ahb";
+			/*
+			 * Use PLL6 as parent, instead of CPU/AXI
+			 * which has rate changes due to cpufreq
+			 */
+			assigned-clocks = <&ahb>;
+			assigned-clock-parents = <&pll6 1>;
 		};
 
 		apb0: apb0 at 01c20054 {
arch/arm/boot/dts/sun7i-a20.dtsi +10 -3
index 3a8530b79f1c..52538beb969a 100644
@@ -225,7 +225,8 @@
 			compatible = "allwinner,sun4i-a10-pll6-clk";
 			reg = <0x01c20028 0x4>;
 			clocks = <&osc24M>;
-			clock-output-names = "pll6_sata", "pll6_other", "pll6";
+			clock-output-names = "pll6_sata", "pll6_other", "pll6",
+					     "pll6_div_4";
 		};
 
 		pll8: clk at 01c20040 {

@@ -254,10 +255,16 @@
 
 		ahb: ahb at 01c20054 {
 			#clock-cells = <0>;
-			compatible = "allwinner,sun4i-a10-ahb-clk";
+			compatible = "allwinner,sun5i-a13-ahb-clk";
 			reg = <0x01c20054 0x4>;
-			clocks = <&axi>;
+			clocks = <&axi>, <&pll6 3>, <&pll6 1>;
 			clock-output-names = "ahb";
+			/*
+			 * Use PLL6 as parent, instead of CPU/AXI
+			 * which has rate changes due to cpufreq
+			 */
+			assigned-clocks = <&ahb>;
+			assigned-clock-parents = <&pll6 3>;
 		};
 
 		ahb_gates: clk at 01c20060 {
Signature · 1 line
2.1.4
Applied
#4 lore raw

v2 cover clk: sunxi: Add muxable AHB clock to fix hstimer issues

In reply to Chen-Yu Tsai
Quoted 22 lines · Chen-Yu Tsai

Hi everyone,

This is v2 of the sun5i muxable AHB clock series.

Changes since v1:

- Dropped patches 1~3 that are merged
- Extend comments to clarify what the "base factor clock" refers to, and what the divs clocks outputs should be.

This series adds support for the muxable ahb clock on sun5/7i. The mux has inputs such as the axi clock, the cpu clock on sun5i, and pll6 with various dividers. The goal is to have ahb muxed to pll6, which should be a fixed rate albeit configurable clock. This fixes issues with cpufreq changing the cpu frequency, which would affect the hstimer clocked from ahb.

Patch 1 makes divs clocks explicitly specify in the driver which output is the base factor clock, instead of always putting it in last. This is done to ensure DT bindings compatibility when we add outputs.

Quoted 8 lines

Patch 2 adds the new pll6/4 output, which is used on sun7i as an input to ahb mux.

Patch 3 updates the dtsi files with the new drivers.

The series is also available at

https://github.com/wens/linux/commits/sun5i-ahb-v2

Applied all three. I think it would be great to convert the later SoCs to that too, just to make sure we have the same policy on all SoCs.

Thanks!
Maxime

Signature · 10 lines
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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author
#5 lore raw

v2 cover clk: sunxi: Add muxable AHB clock to fix hstimer issues

Quoted 26 lines · Maxime Ripard
Quoted 25 lines · Chen-Yu Tsai

Hi everyone,

This is v2 of the sun5i muxable AHB clock series.

Changes since v1:

- Dropped patches 1~3 that are merged
- Extend comments to clarify what the "base factor clock" refers to, and what the divs clocks outputs should be.

This series adds support for the muxable ahb clock on sun5/7i. The mux has inputs such as the axi clock, the cpu clock on sun5i, and pll6 with various dividers. The goal is to have ahb muxed to pll6, which should be a fixed rate albeit configurable clock. This fixes issues with cpufreq changing the cpu frequency, which would affect the hstimer clocked from ahb.

Patch 1 makes divs clocks explicitly specify in the driver which output is the base factor clock, instead of always putting it in last. This is done to ensure DT bindings compatibility when we add outputs.

Patch 2 adds the new pll6/4 output, which is used on sun7i as an input to ahb mux.

Quoted 8 lines
Quoted 5 lines

Patch 3 updates the dtsi files with the new drivers.

The series is also available at

https://github.com/wens/linux/commits/sun5i-ahb-v2

Applied all three. I think it would be great to convert the later SoCs to that too, just to make sure we have the same policy on all SoCs.

For sun6i this is already doable. We just move the assignment from the dmaengine node to the clock node.

For sun8i the default divider results in 300 MHz for AHB, which might be too fast. And we can't do clock rate assignment yet. The clock drivers need to be split out.

For sun9i it is already the default.

ChenYu

#6 lore raw

v2 cover clk: sunxi: Add muxable AHB clock to fix hstimer issues

Quoted 32 lines · Chen-Yu Tsai
Quoted 30 lines · Maxime Ripard
Quoted 29 lines · Chen-Yu Tsai

Hi everyone,

This is v2 of the sun5i muxable AHB clock series.

Changes since v1:

- Dropped patches 1~3 that are merged
- Extend comments to clarify what the "base factor clock" refers to, and what the divs clocks outputs should be.

This series adds support for the muxable ahb clock on sun5/7i. The mux has inputs such as the axi clock, the cpu clock on sun5i, and pll6 with various dividers. The goal is to have ahb muxed to pll6, which should be a fixed rate albeit configurable clock. This fixes issues with cpufreq changing the cpu frequency, which would affect the hstimer clocked from ahb.

Patch 1 makes divs clocks explicitly specify in the driver which output is the base factor clock, instead of always putting it in last. This is done to ensure DT bindings compatibility when we add outputs.

Patch 2 adds the new pll6/4 output, which is used on sun7i as an input to ahb mux.

Patch 3 updates the dtsi files with the new drivers.

The series is also available at

Quoted 7 lines
Quoted 4 lines
Quoted 1 line

https://github.com/wens/linux/commits/sun5i-ahb-v2

Applied all three. I think it would be great to convert the later SoCs to that too, just to make sure we have the same policy on all SoCs.

For sun6i this is already doable. We just move the assignment from the dmaengine node to the clock node.

Yep.

Quoted 2 lines

For sun8i the default divider results in 300 MHz for AHB, which might be too fast.

I guess you're talking about AHB1? APB2 should be muxed to PLL6 as well.

Quoted 2 lines

And we can't do clock rate assignment yet. The clock drivers need to be split out.

Why?

Quoted 1 line

For sun9i it is already the default.

Perfect.

Maxime

Signature · 10 lines
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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author
#7 lore raw

v2 cover clk: sunxi: Add muxable AHB clock to fix hstimer issues

Quoted 35 lines · Maxime Ripard
Quoted 34 lines · Chen-Yu Tsai
Quoted 32 lines · Maxime Ripard
Quoted 30 lines · Chen-Yu Tsai

Hi everyone,

This is v2 of the sun5i muxable AHB clock series.

Changes since v1:

- Dropped patches 1~3 that are merged
- Extend comments to clarify what the "base factor clock" refers to, and what the divs clocks outputs should be.

This series adds support for the muxable ahb clock on sun5/7i. The mux has inputs such as the axi clock, the cpu clock on sun5i, and pll6 with various dividers. The goal is to have ahb muxed to pll6, which should be a fixed rate albeit configurable clock. This fixes issues with cpufreq changing the cpu frequency, which would affect the hstimer clocked from ahb.

Patch 1 makes divs clocks explicitly specify in the driver which output is the base factor clock, instead of always putting it in last. This is done to ensure DT bindings compatibility when we add outputs.

Patch 2 adds the new pll6/4 output, which is used on sun7i as an input to ahb mux.

Patch 3 updates the dtsi files with the new drivers.

The series is also available at

https://github.com/wens/linux/commits/sun5i-ahb-v2

Quoted 7 lines
Quoted 5 lines
Quoted 2 lines

Applied all three. I think it would be great to convert the later SoCs to that too, just to make sure we have the same policy on all SoCs.

For sun6i this is already doable. We just move the assignment from the dmaengine node to the clock node.

Yep.

Sent out a patch as part of the sun6i cpufreq series.

Quoted 5 lines
Quoted 2 lines

For sun8i the default divider results in 300 MHz for AHB, which might be too fast.

I guess you're talking about AHB1? APB2 should be muxed to PLL6 as well.

Ah, AHB1 yes. Is APB2 muxed from OSC 24MHz too slow?

Quoted 4 lines
Quoted 2 lines

And we can't do clock rate assignment yet. The clock drivers need to be split out.

Why?

The clock rate is propagated down the tree from the root OSC 24M clock. Unfortunately it is registered after all the A23 clocks, due to the way the sunxi clock driver works. So at the time the AHB1 clock is registered, the parent clocks all have rate=0, as there is no proper reference value for all the factor clocks to calculate their rates.

ChenYu

Quoted 10 lines
Quoted 1 line

For sun9i it is already the default.

Perfect.

Maxime

--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

#8 lore raw

v2 cover clk: sunxi: Add muxable AHB clock to fix hstimer issues

Quoted 7 lines
Quoted 5 lines
Quoted 2 lines

For sun8i the default divider results in 300 MHz for AHB, which might be too fast.

I guess you're talking about AHB1? APB2 should be muxed to PLL6 as well.

Ah, AHB1 yes. Is APB2 muxed from OSC 24MHz too slow?

If it's clocked from the HOSC by default, I guess we're fine.

Quoted 11 lines
Quoted 4 lines
Quoted 2 lines

And we can't do clock rate assignment yet. The clock drivers need to be split out.

Why?

The clock rate is propagated down the tree from the root OSC 24M clock. Unfortunately it is registered after all the A23 clocks, due to the way the sunxi clock driver works. So at the time the AHB1 clock is registered, the parent clocks all have rate=0, as there is no proper reference value for all the factor clocks to calculate their rates.

Too bad. I guess we will be able to switch to this when we will have converted all the clocks.

Thanks,
Maxime

Signature · 10 lines
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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