ARM64: Update support for FSL's LS2085A SoC

index a5462b6..29b53a7 100644
@@ -132,3 +132,11 @@ LS2085A ARMv8 based Simulator model
 Required root node properties:
     - compatible = "fsl,ls2085a-simu", "fsl,ls2085a";
 
+LS2085A ARMv8 based QDS Board
+Required root node properties:
+    - compatible = "fsl,ls2085a-qds", "fsl,ls2085a";
+
+LS2085A ARMv8 based RDB Board
+Required root node properties:
+    - compatible = "fsl,ls2085a-rdb", "fsl,ls2085a";
+

index 6286f04..0654809 100644
@@ -4,7 +4,8 @@ This PCIe host controller is based on the Synopsis Designware PCIe IP
 and thus inherits all the common properties defined in designware-pcie.txt.
 
 Required properties:
-- compatible: should contain the platform identifier such as "fsl,ls1021a-pcie"
+- compatible: should contain the platform identifier such as "fsl,ls1021a-pcie",
+  "fsl,ls2085a-pcie".
 - reg: base addresses and lengths of the PCIe controller
 - interrupts: A list of interrupt outputs of the controller. Must contain an
   entry for each entry in the interrupt-names property.

index df4a259..60d758e 100644
@@ -14,6 +14,7 @@ Chassis Version		Example Chips
 ---------------		-------------
 1.0			p4080, p5020, p5040
 2.0			t4240, b4860, t1040
+3.0			ls2085a
 
 1. Clock Block Binding
 

@@ -30,9 +31,11 @@ Required properties:
 	* "fsl,b4420-clockgen"
 	* "fsl,b4860-clockgen"
 	* "fsl,ls1021a-clockgen"
+	* "fsl,ls2085a-clockgen"
 	Chassis clock strings include:
 	* "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks
 	* "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks
+	* "fsl,qoriq-clockgen-3.0": for chassis 3.0 clocks
 - reg: Describes the address of the device's resources within the
 	address space defined by its parent bus, and resource zero
 	represents the clock register set

@@ -57,18 +60,23 @@ Required properties:
 - compatible : Should include one of the following:
 	* "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0)
 	* "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0)
+	* "fsl,qoriq-core-pll-3.0" for core PLL clocks (v3.0)
 	* "fsl,qoriq-core-mux-1.0" for core mux clocks (v1.0)
 	* "fsl,qoriq-core-mux-2.0" for core mux clocks (v2.0)
+	* "fsl,qoriq-core-mux-3.0" for core mux clocks (v3.0)
 	* "fsl,qoriq-sysclk-1.0": for input system clock (v1.0).
 		It takes parent's clock-frequency as its clock.
 	* "fsl,qoriq-sysclk-2.0": for input system clock (v2.0).
 		It takes parent's clock-frequency as its clock.
+	* "fsl,qoriq-sysclk-3.0": for input system clock (v3.0).
+		It takes parent's clock-frequency as its clock.
 	* "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0)
 	* "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0)
+	* "fsl,qoriq-platform-pll-3.0" for the platform PLL clock (v3.0)
 - #clock-cells: From common clock binding. The number of cells in a
-	clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0"
-	clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks.
-	For "fsl,qoriq-core-pll-[1,2].0" clocks, the single
+	clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2,3].0"
+	clocks, or <1> for "fsl,qoriq-core-pll-[1,2,3].0" clocks.
+	For "fsl,qoriq-core-pll-[1,2,3].0" clocks, the single
 	clock-specifier cell may take the following values:
 	* 0 - equal to the PLL frequency
 	* 1 - equal to the PLL frequency divided by 2

index aa8c402..a372ed7 100644
@@ -2,12 +2,18 @@ Freescale FlexTimer Module (FTM) Timer
 
 Required properties:
 
-- compatible : should be "fsl,ftm-timer"
+- compatible : should be "fsl,ftm-timer" & "fsl,ftm-alarm".
+  (a) "fsl,ftm-timer", for FlexTimer compatible as normal timer.
+  (b) "fsl,ftm-alarm", for FlexTimer compatible when FTM0 as an ALARM timer.
+
 - reg : Specifies base physical address and size of the register sets for the
   clock event device and clock source device.
+
 - interrupts : Should be the clock event device interrupt.
+
 - clocks : The clocks provided by the SoC to drive the timer, must contain an
   entry for each entry in clock-names.
+
 - clock-names : Must include the following entries:
   o "ftm-evt"
   o "ftm-src"

@@ -16,16 +22,28 @@ Required properties:
 - big-endian: One boolean property, the big endian mode will be in use if it is
   present, or the little endian mode will be in use for all the device registers.
 
-Example:
-ftm: ftm at 400b8000 {
-	compatible = "fsl,ftm-timer";
-	reg = <0x400b8000 0x1000 0x400b9000 0x1000>;
-	interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
-	clock-names = "ftm-evt", "ftm-src",
-		"ftm-evt-counter-en", "ftm-src-counter-en";
-	clocks = <&clks VF610_CLK_FTM2>,
-		<&clks VF610_CLK_FTM3>,
-		<&clks VF610_CLK_FTM2_EXT_FIX_EN>,
-		<&clks VF610_CLK_FTM3_EXT_FIX_EN>;
-	big-endian;
-};
+Example 1: In this example, The FlexTimer module (FTM) is a two-to-eight,
+	   channel timer that supports input capture, output compare, and
+	   the generation of PWM signals to control electric motor and power
+	   management applications.
+
+	ftm: ftm at 400b8000 {
+		compatible = "fsl,ftm-timer";
+		reg = <0x400b8000 0x1000 0x400b9000 0x1000>;
+		interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "ftm-evt", "ftm-src",
+			"ftm-evt-counter-en", "ftm-src-counter-en";
+		clocks = <&clks VF610_CLK_FTM2>,
+			<&clks VF610_CLK_FTM3>,
+			<&clks VF610_CLK_FTM2_EXT_FIX_EN>,
+			<&clks VF610_CLK_FTM3_EXT_FIX_EN>;
+		big-endian;
+	};
+
+Example 2: In this example, FTM0 only be used as an alarm timer.
+
+	ftm0: ftm0 at 2800000 {
+		compatible = "fsl,ftm-alarm";
+		reg = <0x0 0x2800000 0x0 0x10000>;
+		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+	};