Add SPL support for SoCFPGA
Subsystems (3)
v3 cover Add SPL support for SoCFPGA
From: Dinh Nguyen <[email protected]>
Hello,
This is v3 of the patchset that adds all the SPL code that is necessary to support the SoCFPGA platform. For v3, here are the changes:
- Remove gdata
- Remove s_init
- Remove socfpga lowlevel_init.S
- Use common u-boot-spl.lds
- Properly use CONFIG_SPL_TEXT_BASE so we don't have to add an .sram section
I have pushed a branch to git://git.rocketboards.org/u-boot-socfpga-next.gitsocfpga_for_next_spl_v3 for testing and reviewing.
Rebased to 2015.04-rc4.
Thanks,
Dinh Nguyen (17):
arm: socfpga: spl: Add main sdram code
arm: socfpga: spl: Add CONFIG_SPL_MAX_SIZE to be 64KB
arm: socfpga: add functions to bring sdram, timer, and uart out of
reset
arm: socfpga: spl: enable sdram, timer and uart
arm: socfpga: spl: Add call to timer_init
arm: socfpga: spl: allow bootrom to enable IOs after warm reset
arm: socfpga: spl: add sdram init and calibration
arm: socfpga: spl: printout sdram size
arm: socfpga: spl: Use common lowlevel_init
arm: socfpga: spl: Add s_init stub
arm: socfpga: spl: add CONFIG_SPL_STACK to socfpga_common.h
arm: socfpga: spl: Adjust the SYS_INIT_RAM_SIZE to have room for the
spl malloc
arm: socfpga: spl: add board_init_f to SPL
arm: socfpga: spl: Add SDRAM check
arm: socfpga: spl: update pll_config for dev kit
arm: socfpga: remove the need to map sdram in arch_early_init
arm: socfpga: fix uart0 pin mux configuration
Makefile | 1 + arch/arm/cpu/armv7/Makefile | 2 +- arch/arm/cpu/armv7/socfpga/Makefile | 1 - arch/arm/cpu/armv7/socfpga/lowlevel_init.S | 45 - arch/arm/cpu/armv7/socfpga/misc.c | 3 - arch/arm/cpu/armv7/socfpga/reset_manager.c | 24 + arch/arm/cpu/armv7/socfpga/spl.c | 62 + arch/arm/cpu/armv7/socfpga/system_manager.c | 9 + arch/arm/include/asm/arch-socfpga/reset_manager.h | 6 + arch/arm/include/asm/arch-socfpga/sdram.h | 434 +++ arch/arm/include/asm/arch-socfpga/sdram_config.h | 100 + arch/arm/include/asm/arch-socfpga/system_manager.h | 1 + board/altera/socfpga/pinmux_config.c | 4 +- board/altera/socfpga/pll_config.h | 4 +- board/altera/socfpga/socfpga.c | 2 + drivers/ddr/altera/Makefile | 12 + drivers/ddr/altera/sdram.c | 1307 +++++++ drivers/ddr/altera/sequencer.c | 3970 ++++++++++++++++++++ drivers/ddr/altera/sequencer.h | 359 ++ drivers/ddr/altera/sequencer_auto.h | 216 ++ drivers/ddr/altera/sequencer_auto_ac_init.c | 85 + drivers/ddr/altera/sequencer_auto_inst_init.c | 270 ++ drivers/ddr/altera/sequencer_defines.h | 121 + include/configs/socfpga_common.h | 8 +- include/configs/socfpga_cyclone5.h | 1 + scripts/Makefile.spl | 1 + 26 files changed, 6993 insertions(+), 55 deletions(-) delete mode 100644 arch/arm/cpu/armv7/socfpga/lowlevel_init.S create mode 100644 arch/arm/include/asm/arch-socfpga/sdram.h create mode 100644 arch/arm/include/asm/arch-socfpga/sdram_config.h create mode 100644 drivers/ddr/altera/Makefile create mode 100644 drivers/ddr/altera/sdram.c create mode 100644 drivers/ddr/altera/sequencer.c create mode 100644 drivers/ddr/altera/sequencer.h create mode 100644 drivers/ddr/altera/sequencer_auto.h create mode 100644 drivers/ddr/altera/sequencer_auto_ac_init.c create mode 100644 drivers/ddr/altera/sequencer_auto_inst_init.c create mode 100644 drivers/ddr/altera/sequencer_defines.h
Signature · 1 line
2.2.1
PATCH v3 1/17 arm: socfpga: spl: Add main sdram code
From: Dinh Nguyen <[email protected]>
This adds the code to configure the SDRAM controller that is found in the SoCFGPA Cyclone5 and Arria5 platforms.
---
v2: moved to drivers/ddr/altera/
only supports DDR3 at FULLRATE
--- Makefile | 1 + arch/arm/include/asm/arch-socfpga/sdram.h | 434 +++ arch/arm/include/asm/arch-socfpga/sdram_config.h | 100 + drivers/ddr/altera/Makefile | 12 + drivers/ddr/altera/sdram.c | 1307 +++++++ drivers/ddr/altera/sequencer.c | 3970 ++++++++++++++++++++++ drivers/ddr/altera/sequencer.h | 359 ++ drivers/ddr/altera/sequencer_auto.h | 216 ++ drivers/ddr/altera/sequencer_auto_ac_init.c | 85 + drivers/ddr/altera/sequencer_auto_inst_init.c | 270 ++ drivers/ddr/altera/sequencer_defines.h | 121 + include/configs/socfpga_cyclone5.h | 1 + scripts/Makefile.spl | 1 + 13 files changed, 6877 insertions(+) create mode 100644 arch/arm/include/asm/arch-socfpga/sdram.h create mode 100644 arch/arm/include/asm/arch-socfpga/sdram_config.h create mode 100644 drivers/ddr/altera/Makefile create mode 100644 drivers/ddr/altera/sdram.c create mode 100644 drivers/ddr/altera/sequencer.c create mode 100644 drivers/ddr/altera/sequencer.h create mode 100644 drivers/ddr/altera/sequencer_auto.h create mode 100644 drivers/ddr/altera/sequencer_auto_ac_init.c create mode 100644 drivers/ddr/altera/sequencer_auto_inst_init.c create mode 100644 drivers/ddr/altera/sequencer_defines.h
Makefile +1 -0
@@ -636,6 +636,7 @@ libs-y += drivers/power/ \ libs-y += drivers/spi/ libs-$(CONFIG_FMAN_ENET) += drivers/net/fm/ libs-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/ +libs-$(CONFIG_ALTERA_SDRAM) += drivers/ddr/altera/ libs-y += drivers/serial/ libs-y += drivers/usb/eth/ libs-y += drivers/usb/gadget/
arch/arm/include/asm/arch-socfpga/sdram.h new file +434 -0
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arch/arm/include/asm/arch-socfpga/sdram_config.h new file +100 -0
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drivers/ddr/altera/Makefile new file +12 -0
@@ -0,0 +1,12 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd at denx.de. +# +# (C) Copyright 2010, Thomas Chou <[email protected]> +# Copyright (C) 2014 Altera Corporation <www.altera.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_ALTERA_SDRAM) += sdram.o sequencer.o sequencer_auto_ac_init.o \ + sequencer_auto_inst_init.o
drivers/ddr/altera/sdram.c new file +1307 -0
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drivers/ddr/altera/sequencer.c new file +3970 -0
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drivers/ddr/altera/sequencer.h new file +359 -0
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drivers/ddr/altera/sequencer_auto.h new file +216 -0
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drivers/ddr/altera/sequencer_auto_ac_init.c new file +85 -0
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drivers/ddr/altera/sequencer_auto_inst_init.c new file +270 -0
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drivers/ddr/altera/sequencer_defines.h new file +121 -0
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Signature · 1 line
2.2.1
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PATCH v3 1/17 arm: socfpga: spl: Add main sdram code
Dear dinguyen at opensource.altera.com,
Quoted 1 line · In message <[email protected]>…
...
Quoted 6 lines
arch/arm/include/asm/arch-socfpga/sdram.h new file +6
-0+/* Register: sdr.ctrlgrp.ctrlcfg */ +#define SDR_CTRLGRP_CTRLCFG_ADDRESS 0x5000 +/* Register: sdr.ctrlgrp.dramtiming1 */ +#define SDR_CTRLGRP_DRAMTIMING1_ADDRESS 0x5004 +/* Register: sdr.ctrlgrp.dramtiming2 */ +#define SDR_CTRLGRP_DRAMTIMING2_ADDRESS 0x5008
arch/arm/include/asm/arch-socfpga/sdram.h line 45
Quoted 10 lines
arch/arm/include/asm/arch-socfpga/sdram.h new file +10
-0+/* Register: sdr.ctrlgrp.dramtiming3 */ +#define SDR_CTRLGRP_DRAMTIMING3_ADDRESS 0x500c +/* Register: sdr.ctrlgrp.dramtiming4 */ +#define SDR_CTRLGRP_DRAMTIMING4_ADDRESS 0x5010 +/* Register: sdr.ctrlgrp.lowpwrtiming */ +#define SDR_CTRLGRP_LOWPWRTIMING_ADDRESS 0x5014 +/* Register: sdr.ctrlgrp.dramodt */ +#define SDR_CTRLGRP_DRAMODT_ADDRESS 0x5018 +/* Register: sdr.ctrlgrp.dramaddrw */ +#define SDR_CTRLGRP_DRAMADDRW_ADDRESS 0x502c
...
First, this whole block of registers should probably made a C struct. Also, the comments are pretty much redundant - they do not add any new information that is not already included in the #define, so they could be omitted to make the code easier to read.
Quoted 6 lines
arch/arm/include/asm/arch-socfpga/sdram.h new file +6
-0+#define SDR_CTRLGRP_PHYCTRL_ADDRESS 0x5150 +/* Register: sdr.ctrlgrp.phyctrl.phyctrl_0 */ +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDRESS 0x5150 +/* Register: sdr.ctrlgrp.phyctrl.phyctrl_1 */ +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_ADDRESS 0x5154 +/* Register: sdr.ctrlgrp.phyctrl.phyctrl_2 */
arch/arm/include/asm/arch-socfpga/sdram.h line 142
Quoted 10 lines
arch/arm/include/asm/arch-socfpga/sdram.h new file +10
-0+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_ADDRESS 0x5158 +/* Register instance: sdr::ctrlgrp::phyctrl.phyctrl_0 */ +/* Register template referenced: sdr::ctrlgrp::phyctrl::phyctrl_0 */ +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_OFFSET 0x150 +/* Register instance: sdr::ctrlgrp::phyctrl.phyctrl_1 */ +/* Register template referenced: sdr::ctrlgrp::phyctrl::phyctrl_1 */ +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_OFFSET 0x154 +/* Register instance: sdr::ctrlgrp::phyctrl.phyctrl_2 */ +/* Register template referenced: sdr::ctrlgrp::phyctrl::phyctrl_2 */ +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_OFFSET 0x158
Is it not redundant to define both the address and the offset? Decide for one. And again, this should probably be rather a C struct.
Quoted 77 lines
arch/arm/include/asm/arch-socfpga/sdram.h new file +77
-0+/* Register template: sdr::ctrlgrp::ctrlcfg */ +#define SDR_CTRLGRP_CTRLCFG_OUTPUTREG_LSB 26 +#define SDR_CTRLGRP_CTRLCFG_OUTPUTREG_MASK 0x04000000 +#define SDR_CTRLGRP_CTRLCFG_BURSTTERMEN_LSB 25 +#define SDR_CTRLGRP_CTRLCFG_BURSTTERMEN_MASK 0x02000000 +#define SDR_CTRLGRP_CTRLCFG_BURSTINTREN_LSB 24 +#define SDR_CTRLGRP_CTRLCFG_BURSTINTREN_MASK 0x01000000 +#define SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB 23 +#define SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK 0x00800000 +#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB 22 +#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK 0x00400000 +#define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB 16 +#define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_MASK 0x003f0000 +#define SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB 15 +#define SDR_CTRLGRP_CTRLCFG_REORDEREN_MASK 0x00008000 +#define SDR_CTRLGRP_CTRLCFG_GENDBE_LSB 14 +#define SDR_CTRLGRP_CTRLCFG_GENDBE_MASK 0x00004000 +#define SDR_CTRLGRP_CTRLCFG_GENSBE_LSB 13 +#define SDR_CTRLGRP_CTRLCFG_GENSBE_MASK 0x00002000 +#define SDR_CTRLGRP_CTRLCFG_CFG_ENABLE_ECC_CODE_OVERWRITES_LSB 12 +#define SDR_CTRLGRP_CTRLCFG_CFG_ENABLE_ECC_CODE_OVERWRITES_MASK 0x00001000 +#define SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB 11 +#define SDR_CTRLGRP_CTRLCFG_ECCCORREN_MASK 0x00000800 +#define SDR_CTRLGRP_CTRLCFG_ECCEN_LSB 10 +#define SDR_CTRLGRP_CTRLCFG_ECCEN_MASK 0x00000400 +#define SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB 8 +#define SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK 0x00000300 +#define SDR_CTRLGRP_CTRLCFG_MEMBL_LSB 3 +#define SDR_CTRLGRP_CTRLCFG_MEMBL_MASK 0x000000f8 +#define SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB 0 +#define SDR_CTRLGRP_CTRLCFG_MEMTYPE_MASK 0x00000007 +/* Register template: sdr::ctrlgrp::dramtiming1 */ +#define SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB 24 +#define SDR_CTRLGRP_DRAMTIMING1_TRFC_MASK 0xff000000 +#define SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB 18 +#define SDR_CTRLGRP_DRAMTIMING1_TFAW_MASK 0x00fc0000 +#define SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB 14 +#define SDR_CTRLGRP_DRAMTIMING1_TRRD_MASK 0x0003c000 +#define SDR_CTRLGRP_DRAMTIMING1_TCL_LSB 9 +#define SDR_CTRLGRP_DRAMTIMING1_TCL_MASK 0x00003e00 +#define SDR_CTRLGRP_DRAMTIMING1_TAL_LSB 4 +#define SDR_CTRLGRP_DRAMTIMING1_TAL_MASK 0x000001f0 +#define SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB 0 +#define SDR_CTRLGRP_DRAMTIMING1_TCWL_MASK 0x0000000f +/* Register template: sdr::ctrlgrp::dramtiming2 */ +#define SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB 25 +#define SDR_CTRLGRP_DRAMTIMING2_TWTR_MASK 0x1e000000 +#define SDR_CTRLGRP_DRAMTIMING2_TWR_LSB 21 +#define SDR_CTRLGRP_DRAMTIMING2_TWR_MASK 0x01e00000 +#define SDR_CTRLGRP_DRAMTIMING2_TRP_LSB 17 +#define SDR_CTRLGRP_DRAMTIMING2_TRP_MASK 0x001e0000 +#define SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB 13 +#define SDR_CTRLGRP_DRAMTIMING2_TRCD_MASK 0x0001e000 +#define SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB 0 +#define SDR_CTRLGRP_DRAMTIMING2_TREFI_MASK 0x00001fff +/* Register template: sdr::ctrlgrp::dramtiming3 */ +#define SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB 19 +#define SDR_CTRLGRP_DRAMTIMING3_TCCD_MASK 0x00780000 +#define SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB 15 +#define SDR_CTRLGRP_DRAMTIMING3_TMRD_MASK 0x00078000 +#define SDR_CTRLGRP_DRAMTIMING3_TRC_LSB 9 +#define SDR_CTRLGRP_DRAMTIMING3_TRC_MASK 0x00007e00 +#define SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB 4 +#define SDR_CTRLGRP_DRAMTIMING3_TRAS_MASK 0x000001f0 +#define SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB 0 +#define SDR_CTRLGRP_DRAMTIMING3_TRTP_MASK 0x0000000f +/* Register template: sdr::ctrlgrp::dramtiming4 */ +#define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_LSB 20 +#define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_MASK 0x00f00000 +#define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB 10 +#define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_MASK 0x000ffc00 +#define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB 0 +#define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_MASK 0x000003ff +/* Register template: sdr::ctrlgrp::lowpwrtiming */ +#define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB 16 +#define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_MASK 0x000f0000 +#define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB 0
arch/arm/include/asm/arch-socfpga/sdram.h line 230
Quoted 10 lines
arch/arm/include/asm/arch-socfpga/sdram.h new file +10
-0+#define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_MASK 0x0000ffff +/* Register template: sdr::ctrlgrp::dramaddrw */ +#define SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB 13 +#define SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK 0x0000e000 +#define SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB 10 +#define SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK 0x00001c00 +#define SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB 5 +#define SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK 0x000003e0 +#define SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB 0 +#define SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK 0x0000001f
...
Are all these #defines actually used in the code? Maybe we can remove some that will never play a role here?
arch/arm/include/asm/arch-socfpga/sdram_config.h line 16
Quoted 7 lines
arch/arm/include/asm/arch-socfpga/sdram_config.h new file +7
-0+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE (2) +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL (8) +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER (0) +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN (1) +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN (1) +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN (1) +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT (10)
...
Please remove parens from all such simple definitions. Please fix globally.
drivers/ddr/altera/sdram.c line 20
Quoted 4 lines
drivers/ddr/altera/sdram.c new file +4
-0+#define ADDRORDER2_INFO \ + "INFO: Changing address order to 2 (row, chip, bank, column)\n" +#define ADDRORDER0_INFO \ + "INFO: Changing address order to 0 (chip, row, bank, column)\n"
Please insert the strings where they are used, this makes the code much easier to read.
drivers/ddr/altera/sdram.c line 93
Quoted 12 lines
drivers/ddr/altera/sdram.c new file +12
-0+typedef struct _sdram_prot_rule { +uint32_t rule;/* SDRAM protection rule number: 0-19 */ +uint64_t sdram_start;/* SDRAM start address */ +uint64_t sdram_end;/* SDRAM end address */ +int valid;/* Rule valid or not? 1 - valid, 0 not*/ + +uint32_t security; +uint32_t portmask; +uint32_t result; +uint32_t lo_prot_id; +uint32_t hi_prot_id; +}sdram_prot_rule , *psdram_prot_rule ;
Would it make sense to move the "uint32_t rule" after the uint64_t entries to avoid a gap in the struct?
drivers/ddr/altera/sdram.c line 106
Quoted 3 lines
drivers/ddr/altera/sdram.c new file +3
-0+/* Select the rule */ + regoffs =SDR_CTRLGRP_PROTRULERDWR_ADDRESS ; +writel (ruleno, (SOCFPGA_SDR_ADDRESS + regoffs));
NAK. We do not allow such syntax. Please use a C struct. Please fix globally.
drivers/ddr/altera/sdram.c line 253
Quoted 8 lines
drivers/ddr/altera/sdram.c new file +8
-0+/* Function to update the field within variable */ +static unsigned sdram_write_register_field (unsigned masked_value, +unsigned data,unsigned shift,unsigned mask) +{ + masked_value &= ~(mask); + masked_value |= (data << shift) & mask; +return masked_value; +}
Is this really needed? I guess you could use standard I/O accessors like clrsetbits-*() instead?
Quoted 22 lines
drivers/ddr/altera/sdram.c new file +22
-0+#if defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS ) && \ +defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS ) && \ +defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS ) && \ +defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS ) && \ +defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS ) + +int cs =CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS ; +int width =8 ; +int rows =CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS ; +int banks =CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS ; +int cols =CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS ; +unsigned long long workaround_memsize =MEMSIZE_4G ; + +writel (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS , + &sysmgr_regs->iswgrp_handoff[4 ]); +#endif + +/***** CTRLCFG *****/ +#if defined(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE) || \ +defined(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL) || \ +defined(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER) || \ +defined(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN) || \
drivers/ddr/altera/sdram.c line 321
Quoted 10 lines
drivers/ddr/altera/sdram.c new file +10
-0+defined (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN ) || \ +defined (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN ) || \ +defined (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT ) || \ +defined (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN ) || \ +defined(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS) +debug ("\nConfiguring CTRLCFG\n" ); + register_offset =SDR_CTRLGRP_CTRLCFG_ADDRESS ; +/* Read original register value */ + reg_value =readl (SOCFPGA_SDR_ADDRESS + register_offset); +#ifdef CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE
This is an unreadable #ifdef mess. Can we somehow clean up this code, please?
Quoted 26 lines
drivers/ddr/altera/sdram.c new file +26
-0+#ifdef CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN + reg_value =sdram_write_register_field (reg_value, +CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN , +SDR_CTRLGRP_CTRLCFG_ECCEN_LSB , +SDR_CTRLGRP_CTRLCFG_ECCEN_MASK ); +#endif +#ifdef CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN + reg_value =sdram_write_register_field (reg_value, +CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN , +SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB , +SDR_CTRLGRP_CTRLCFG_ECCCORREN_MASK ); +#endif +#ifdef CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN + reg_value =sdram_write_register_field (reg_value, +CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN , +SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB , +SDR_CTRLGRP_CTRLCFG_REORDEREN_MASK ); +#endif +#ifdef CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT + reg_value =sdram_write_register_field (reg_value, +CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT , +SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB , +SDR_CTRLGRP_CTRLCFG_STARVELIMIT_MASK ); +#endif +#ifdef CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN + reg_value = sdram_write_register_field(reg_value,
drivers/ddr/altera/sdram.c line 398
Quoted 10 lines
drivers/ddr/altera/sdram.c new file +10
-0+CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN , +SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB , + SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK); +#endif +#ifdef CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS + reg_value =sdram_write_register_field (reg_value, +CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS , +SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB , +SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK ); +#endif
You would get much simpler code if you did not define shift and mask, but the direct hex value instead - this just became one big |.
drivers/ddr/altera/sequencer.c line 78
Quoted 5 lines
drivers/ddr/altera/sequencer.c new file +5
-0+/* +* space around comma is required for varargs macro to remove comma if args +* is empty +*/ +#define BFM_GBL_SET (field, value)
where do we have a varargs macro here?
Quoted 1 line
+#define
DYNAMIC_CALIB_STEPS(dyn_calib_steps)
The following code uses a mix of DYNAMIC_CALIB_STEPS and dyn_calib_steps. Please drop DYNAMIC_CALIB_STEPS and use dyn_calib_steps consistently.
Review
Quoted 2 lines
(quoted diff) +2
-0+static int sdr_ops(u32 *base, u32 offset, u32 data, bool write) +{
Is this needed? It appears we could use standard I/O accessors instead?
Quoted 98 lines
drivers/ddr/altera/sequencer.c new file +98
-0+static inline void scc_mgr_set_dqs_bypass (uint32_t write_group,uint32_t bypass) +{ +/* Load the setting in the SCC manager */ +WRITE_SCC_DQS_BYPASS (write_group, bypass); +} + +inline void scc_mgr_set_dq_out1_delay (uint32_t write_group, +uint32_t dq_in_group,uint32_t delay) +{ +/* Load the setting in the SCC manager */ +sdr_ops ((u32 *)SCC_MGR_IO_OUT1_DELAY , dq_in_group <<2 , delay,SDR_WRITE ); +} + +inline void scc_mgr_set_dq_out2_delay (uint32_t write_group, +uint32_t dq_in_group,uint32_t delay) +{ +/* Load the setting in the SCC manager */ +WRITE_SCC_DQ_OUT2_DELAY (dq_in_group, delay); +} + +inline void scc_mgr_set_dq_in_delay (uint32_t write_group, +uint32_t dq_in_group,uint32_t delay) +{ +/* Load the setting in the SCC manager */ +sdr_ops ((u32 *)SCC_MGR_IO_IN_DELAY , dq_in_group <<2 , delay,SDR_WRITE ); +} + +static inline void scc_mgr_set_dq_bypass (uint32_t write_group, +uint32_t dq_in_group,uint32_t bypass) +{ +/* Load the setting in the SCC manager */ +WRITE_SCC_DQ_BYPASS (dq_in_group, bypass); +} + +static inline void scc_mgr_set_rfifo_mode (uint32_t write_group, +uint32_t dq_in_group,uint32_t mode) +{ +/* Load the setting in the SCC manager */ +WRITE_SCC_RFIFO_MODE (dq_in_group, mode); +} + +static inline void scc_mgr_set_hhp_extras (void ) +{ +/* +* Load the fixed setting in the SCC manager +* bits: 0:0 = 1'b1 - dqs bypass +* bits: 1:1 = 1'b1 - dq bypass +* bits: 4:2 = 3'b001 - rfifo_mode +* bits: 6:5 = 2'b01 - rfifo clock_select +* bits: 7:7 = 1'b0 - separate gating from ungating setting +* bits: 8:8 = 1'b0 - separate OE from Output delay setting +*/ +uint32_t value = (0 <<8 ) | (0 <<7 ) | (1 <<5 ) | (1 <<2 ) | (1 <<1 ) | (1 <<0 ); +sdr_ops ((u32 *)SCC_MGR_HHP_GLOBALS ,SCC_MGR_HHP_EXTRAS_OFFSET , + value,SDR_WRITE ); +} + +static inline void scc_mgr_set_hhp_dqse_map (void ) +{ +/* Load the fixed setting in the SCC manager */ +sdr_ops ((u32 *)SCC_MGR_HHP_GLOBALS ,SCC_MGR_HHP_DQSE_MAP_OFFSET ,0 , +SDR_WRITE ); +} + +static inline void scc_mgr_set_dqs_out1_delay (uint32_t write_group, +uint32_t delay) +{ +/* Load the setting in the SCC manager */ +sdr_ops ((u32 *)SCC_MGR_IO_OUT1_DELAY ,RW_MGR_MEM_DQ_PER_WRITE_DQS <<2 , + delay,SDR_WRITE ); +} + +static inline void scc_mgr_set_dqs_out2_delay (uint32_t write_group, +uint32_t delay) +{ +/* Load the setting in the SCC manager */ +WRITE_SCC_DQS_IO_OUT2_DELAY (delay); +} + +static inline void scc_mgr_set_dm_out1_delay (uint32_t write_group, +uint32_t dm,uint32_t delay) +{ +/* Load the setting in the SCC manager */ +sdr_ops ((u32 *)SCC_MGR_IO_OUT1_DELAY , + (RW_MGR_MEM_DQ_PER_WRITE_DQS +1 + dm) <<2 , delay,SDR_WRITE ); +} + +static inline void scc_mgr_set_dm_out2_delay (uint32_t write_group,uint32_t dm, +uint32_t delay) +{ +/* Load the setting in the SCC manager */ +WRITE_SCC_DM_IO_OUT2_DELAY (dm, delay); +} + +static inline void scc_mgr_set_dm_in_delay (uint32_t write_group, +uint32_t dm,uint32_t delay) +{ +/* Load the setting in the SCC manager */
drivers/ddr/altera/sequencer.c line 624
Quoted 10 lines
drivers/ddr/altera/sequencer.c new file +10
-0+sdr_ops ((u32 *)SCC_MGR_IO_IN_DELAY , + (RW_MGR_MEM_DQ_PER_WRITE_DQS +1 + dm) <<2 , delay,SDR_WRITE ); +} + +static inline void scc_mgr_set_dm_bypass (uint32_t write_group,uint32_t dm, +uint32_t bypass) +{ +/* Load the setting in the SCC manager */ +WRITE_SCC_DM_BYPASS (dm, bypass); +}
All these one-line functions should probably rather be inlined?
...
drivers/ddr/altera/sdram.c is 1,300+ lines; and drivers/ddr/altera/sequencer.c is nearly 4,000 lines. Have you considered splitting this off into smaller units? Eventually this might help to reduce the #ifdef mess, too ?
drivers/ddr/altera/sequencer.h line 249
Quoted 6 lines
drivers/ddr/altera/sequencer.h new file +6
-0+#define SCC_MGR_DQS_ENA (BASE_SCC_MGR + 0x0E00) +#define SCC_MGR_DQS_IO_ENA (BASE_SCC_MGR + 0x0E04) +#define SCC_MGR_DQ_ENA (BASE_SCC_MGR + 0x0E08) +#define SCC_MGR_DM_ENA (BASE_SCC_MGR + 0x0E0C) +#define SCC_MGR_UPD (BASE_SCC_MGR + 0x0E20) +#define SCC_MGR_ACTIVE_RANK (BASE_SCC_MGR + 0x0E40)
Guess this should be a C struct?
drivers/ddr/altera/sequencer_auto.h line 2
Quoted 8 lines
drivers/ddr/altera/sequencer_auto.h new file +2
-0@@ -0,0 +1,216 @@ +/* +* Copyright Altera Corporation (C) 2012-2014. All rights reserved
Can we please get rid of the non-sense "All rights reserved" clause here (and in the other fiels)? Thanks!
drivers/ddr/altera/sequencer_auto.h line 10
Quoted 7 lines
drivers/ddr/altera/sequencer_auto.h new file +7
-0+* SPDX-License-Identifier: BSD-3-Clause +*/ + +#define __RW_MGR_ac_mrs1 0x04 +#define __RW_MGR_ac_mrs3 0x06 +#define __RW_MGR_ac_write_bank_0_col_0_nodata_wl_1 0x1C +#define __RW_MGR_ac_act_1 0x11
Macro names must be all caps. Please fix globally.
Also, please be aware of the special meaning of a __ prefix for C macros. I think your usage here might be incorrect.
Best regards,
Wolfgang Denk
Signature · 4 lines
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de "If anything can go wrong, it will." - Edsel Murphy
PATCH v3 1/17 arm: socfpga: spl: Add main sdram code
Quoted 27 lines · Wolfgang Denk
Dear dinguyen at opensource.altera.com,
In message <[email protected]> you wrote:
...
Quoted 16 lines
(quoted diff) +8
-0+/* Register: sdr.ctrlgrp.ctrlcfg */ +#define SDR_CTRLGRP_CTRLCFG_ADDRESS 0x5000 +/* Register: sdr.ctrlgrp.dramtiming1 */ +#define SDR_CTRLGRP_DRAMTIMING1_ADDRESS 0x5004 +/* Register: sdr.ctrlgrp.dramtiming2 */ +#define SDR_CTRLGRP_DRAMTIMING2_ADDRESS 0x5008 +/* Register: sdr.ctrlgrp.dramtiming3 */ +#define SDR_CTRLGRP_DRAMTIMING3_ADDRESS 0x500c +/* Register: sdr.ctrlgrp.dramtiming4 */ +#define SDR_CTRLGRP_DRAMTIMING4_ADDRESS 0x5010 +/* Register: sdr.ctrlgrp.lowpwrtiming */ +#define SDR_CTRLGRP_LOWPWRTIMING_ADDRESS 0x5014 +/* Register: sdr.ctrlgrp.dramodt */ +#define SDR_CTRLGRP_DRAMODT_ADDRESS 0x5018 +/* Register: sdr.ctrlgrp.dramaddrw */ +#define SDR_CTRLGRP_DRAMADDRW_ADDRESS 0x502c...
Quoted 4 lines
First, this whole block of registers should probably made a C struct. Also, the comments are pretty much redundant - they do not add any new information that is not already included in the #define, so they could be omitted to make the code easier to read.
Hi!
Sculpting this file into shape would be the most difficult part. I guess Wolfgang already pointed out the largest issues. I also picked up most of the series to make your life easier.
Is there any way I can help you with getting this patch in shape ?
Thanks a lot for working on these!
Best regards,
Marek Vasut
PATCH v3 1/17 arm: socfpga: spl: Add main sdram code
Hi Marek,
Quoted 33 lines · Marek Vasut
Quoted 27 lines · Wolfgang Denk
Dear dinguyen at opensource.altera.com,
In message <[email protected]> you wrote:
...
Quoted 16 lines
(quoted diff) +8
-0+/* Register: sdr.ctrlgrp.ctrlcfg */ +#define SDR_CTRLGRP_CTRLCFG_ADDRESS 0x5000 +/* Register: sdr.ctrlgrp.dramtiming1 */ +#define SDR_CTRLGRP_DRAMTIMING1_ADDRESS 0x5004 +/* Register: sdr.ctrlgrp.dramtiming2 */ +#define SDR_CTRLGRP_DRAMTIMING2_ADDRESS 0x5008 +/* Register: sdr.ctrlgrp.dramtiming3 */ +#define SDR_CTRLGRP_DRAMTIMING3_ADDRESS 0x500c +/* Register: sdr.ctrlgrp.dramtiming4 */ +#define SDR_CTRLGRP_DRAMTIMING4_ADDRESS 0x5010 +/* Register: sdr.ctrlgrp.lowpwrtiming */ +#define SDR_CTRLGRP_LOWPWRTIMING_ADDRESS 0x5014 +/* Register: sdr.ctrlgrp.dramodt */ +#define SDR_CTRLGRP_DRAMODT_ADDRESS 0x5018 +/* Register: sdr.ctrlgrp.dramaddrw */ +#define SDR_CTRLGRP_DRAMADDRW_ADDRESS 0x502c...
Quoted 4 lines
First, this whole block of registers should probably made a C struct. Also, the comments are pretty much redundant - they do not add any new information that is not already included in the #define, so they could be omitted to make the code easier to read.
Quoted 8 lines
Hi!
Sculpting this file into shape would be the most difficult part. I guess Wolfgang already pointed out the largest issues. I also picked up most of the series to make your life easier.
Is there any way I can help you with getting this patch in shape ?
Thanks for picking up the other patches for the SPL. That helps out ALOT! I can focus on getting the SDRAM driver in better shape. Give me a week or 2 for an updated patch.
Dinh
PATCH v3 1/17 arm: socfpga: spl: Add main sdram code
Quoted 1 line · Dinh Nguyen
Hi Marek,
Hi Dinh,
Quoted 55 lines · Marek Vasut
Quoted 54 lines · Wolfgang Denk
Quoted 38 lines
Dear dinguyen at opensource.altera.com,
In message <[email protected]> you wrote:
...
Quoted 30 lines
(quoted diff) +8
-0+/* Register: sdr.ctrlgrp.ctrlcfg */ +#define SDR_CTRLGRP_CTRLCFG_ADDRESS 0x5000 +/* Register: sdr.ctrlgrp.dramtiming1 */ +#define SDR_CTRLGRP_DRAMTIMING1_ADDRESS 0x5004 +/* Register: sdr.ctrlgrp.dramtiming2 */ +#define SDR_CTRLGRP_DRAMTIMING2_ADDRESS 0x5008 +/* Register: sdr.ctrlgrp.dramtiming3 */ +#define SDR_CTRLGRP_DRAMTIMING3_ADDRESS 0x500c +/* Register: sdr.ctrlgrp.dramtiming4 */ +#define SDR_CTRLGRP_DRAMTIMING4_ADDRESS 0x5010 +/* Register: sdr.ctrlgrp.lowpwrtiming */ +#define SDR_CTRLGRP_LOWPWRTIMING_ADDRESS 0x5014 +/* Register: sdr.ctrlgrp.dramodt */ +#define SDR_CTRLGRP_DRAMODT_ADDRESS 0x5018 +/* Register: sdr.ctrlgrp.dramaddrwQuoted 8 lines
Quoted 1 line
*/ +#define
SDR_CTRLGRP_DRAMADDRW_ADDRESS0x502c...
First, this whole block of registers should probably made a C struct. Also, the comments are pretty much redundant - they do not add any new information that is not already included in the #define, so they could be omitted to make the code easier to read.
Hi!
Sculpting this file into shape would be the most difficult part. I guess Wolfgang already pointed out the largest issues. I also picked up most of the series to make your life easier.
Quoted 5 lines
Quoted 1 line
Is there any way I can help you with getting this patch in shape ?
Thanks for picking up the other patches for the SPL. That helps out ALOT! I can focus on getting the SDRAM driver in better shape. Give me a week or 2 for an updated patch.
Roger that, thank you! If I can help with anything, please let me know.
Best regards,
Marek Vasut
PATCH v3 2/17 arm: socfpga: spl: Add CONFIG_SPL_MAX_SIZE to be 64KB
In reply to dinguyen at opensource.altera.comFrom: Dinh Nguyen <[email protected]>
The Cyclone5 SoCFPGA has 64KB of OCRAM for SPL use.
--- include/configs/socfpga_common.h | 1 + 1 file changed, 1 insertion(+)
include/configs/socfpga_common.h +1 -0
@@ -293,6 +293,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void);#define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR#define CONFIG_SYS_SPL_MALLOC_START CONFIG_SYS_INIT_SP_ADDR#define CONFIG_SYS_SPL_MALLOC_SIZE (5 * 1024) +#define CONFIG_SPL_MAX_SIZE (64 * 1024)#define CHUNKSZ_CRC32 (1 * 1024)/* FIXME: ewww */ #define CONFIG_CRC32_VERIFY
Signature · 1 line
2.2.1
PATCH v3 2/17 arm: socfpga: spl: Add CONFIG_SPL_MAX_SIZE to be 64KB
Quoted 5 lines · dinguyen at opensource.altera.com
From: Dinh Nguyen <[email protected]>
The Cyclone5 SoCFPGA has 64KB of OCRAM for SPL use.
Signed-off-by Dinh Nguyen <[email protected]>
Applied to u-boot-socfpga/next . Thanks!
Best regards,
Marek Vasut
PATCH v3 3/17 arm: socfpga: add functions to bring sdram, timer, and uart out of reset
In reply to dinguyen at opensource.altera.comFrom: Dinh Nguyen <[email protected]>
These functions will be needed for use by the SPL for enabling the console and sdram initialization.
--- arch/arm/cpu/armv7/socfpga/reset_manager.c | 24 +++++++++++++++++++++++ arch/arm/include/asm/arch-socfpga/reset_manager.h | 6 ++++++ 2 files changed, 30 insertions(+)
arch/arm/cpu/armv7/socfpga/reset_manager.c +24 -0
@@ -113,3 +113,27 @@ void socfpga_spim_enable(void)clrbits_le32 (reset, (1 <<RSTMGR_PERMODRST_SPIM0_LSB ) | (1 <<RSTMGR_PERMODRST_SPIM1_LSB )); } + +/* Bring UART0 out of reset. */ +void socfpga_uart0_enable (void ) +{ +const void *reset = &reset_manager_base->per_mod_reset; + +clrbits_le32 (reset,1 <<RSTMGR_PERMODRST_UART0_LSB ); +} + +/* Bring SDRAM controller out of reset. */ +void socfpga_sdram_enable (void ) +{ +const void *reset = &reset_manager_base->per_mod_reset; + +clrbits_le32 (reset,1 <<RSTMGR_PERMODRST_SDR_LSB ); +} + +/* Bring OSC1 timer out of reset. */ +void socfpga_osc1timer_enable (void ) +{ +const void *reset = &reset_manager_base->per_mod_reset; + +clrbits_le32 (reset,1 <<RSTMGR_PERMODRST_OSC1TIMER0_LSB ); +}
arch/arm/include/asm/arch-socfpga/reset_manager.h +6 -0
@@ -15,6 +15,9 @@ void socfpga_bridges_reset(int enable);void socfpga_emac_reset (int enable);void socfpga_watchdog_reset (void );void socfpga_spim_enable (void ); +void socfpga_uart0_enable (void ); +void socfpga_sdram_enable (void ); +void socfpga_osc1timer_enable (void );struct socfpga_reset_manager {u32 status;
@@ -36,7 +39,10 @@ struct socfpga_reset_manager {#define RSTMGR_PERMODRST_EMAC0_LSB 0#define RSTMGR_PERMODRST_EMAC1_LSB 1#define RSTMGR_PERMODRST_L4WD0_LSB 6 +#define RSTMGR_PERMODRST_OSC1TIMER0_LSB 8 +#define RSTMGR_PERMODRST_UART0_LSB 16#define RSTMGR_PERMODRST_SPIM0_LSB 18#define RSTMGR_PERMODRST_SPIM1_LSB 19 +#define RSTMGR_PERMODRST_SDR_LSB 29#endif /* _RESET_MANAGER_H_ */
Signature · 1 line
2.2.1
PATCH v3 3/17 arm: socfpga: add functions to bring sdram, timer, and uart out of reset
Quoted 8 lines · dinguyen at opensource.altera.com
From: Dinh Nguyen <[email protected]>
These functions will be needed for use by the SPL for enabling the console and sdram initialization.
Signed-off-by Dinh Nguyen <[email protected]>Acked-by Marek Vasut <[email protected]>Acked-by Pavel Machek <[email protected]>
Applied to u-boot-socfpga/next , thanks!
Best regards,
Marek Vasut
PATCH v3 4/17 arm: socfpga: spl: enable sdram, timer and uart
In reply to dinguyen at opensource.altera.comFrom: Dinh Nguyen <[email protected]>
Add the calls in the spl_board_init to enable SDRAM, timer, and UART.
--- arch/arm/cpu/armv7/socfpga/spl.c | 4 ++++ 1 file changed, 4 insertions(+)
arch/arm/cpu/armv7/socfpga/spl.c +4 -0
@@ -144,6 +144,10 @@ void spl_board_init(void)/* freeze all IO banks */ sys_mgr_frzctrl_freeze_req (); +socfpga_sdram_enable (); +socfpga_uart0_enable (); +socfpga_osc1timer_enable (); +debug ("Reconfigure Clock Manager\n" );/* reconfigure the PLLs */ cm_basic_init (&cm_default_cfg);
Signature · 1 line
2.2.1
PATCH v3 4/17 arm: socfpga: spl: enable sdram, timer and uart
Quoted 6 lines · dinguyen at opensource.altera.com
From: Dinh Nguyen <[email protected]>
Add the calls in the
spl_board_initto enable SDRAM, timer, and UART.Signed-off-by Dinh Nguyen <[email protected]>Acked-by Marek Vasut <[email protected]>
Applied to u-boot-socfpga/next , thanks!
Best regards,
Marek Vasut
PATCH v3 5/17 arm: socfpga: spl: Add call to timer_init
In reply to dinguyen at opensource.altera.comFrom: Dinh Nguyen <[email protected]>
--- arch/arm/cpu/armv7/socfpga/spl.c | 2 ++ 1 file changed, 2 insertions(+)
arch/arm/cpu/armv7/socfpga/spl.c +2 -0
@@ -148,6 +148,8 @@ void spl_board_init(void)socfpga_uart0_enable ();socfpga_osc1timer_enable (); +timer_init (); +debug ("Reconfigure Clock Manager\n" );/* reconfigure the PLLs */ cm_basic_init (&cm_default_cfg);
Signature · 1 line
2.2.1
PATCH v3 5/17 arm: socfpga: spl: Add call to timer_init
Quoted 3 lines · dinguyen at opensource.altera.com
From: Dinh Nguyen <[email protected]>
Signed-off-by Dinh Nguyen <[email protected]>
Applied to u-boot-socfpga/next , thanks!
Best regards,
Marek Vasut
PATCH v3 6/17 arm: socfpga: spl: allow bootrom to enable IOs after warm reset
In reply to dinguyen at opensource.altera.comFrom: Dinh Nguyen <[email protected]>
--- arch/arm/cpu/armv7/socfpga/spl.c | 3 +++ arch/arm/cpu/armv7/socfpga/system_manager.c | 9 +++++++++ arch/arm/include/asm/arch-socfpga/system_manager.h | 1 + 3 files changed, 13 insertions(+)
arch/arm/cpu/armv7/socfpga/spl.c +3 -0
@@ -154,6 +154,9 @@ void spl_board_init(void)/* reconfigure the PLLs */ cm_basic_init (&cm_default_cfg); +/* Enable bootrom to configure IOs. */ +sysmgr_enable_warmrstcfgio (); +/* configure the IOCSR / IO buffer settings */ if (scan_mgr_configure_iocsr ())hang ();
arch/arm/cpu/armv7/socfpga/system_manager.c +9 -0
@@ -66,3 +66,12 @@ void sysmgr_pinmux_init(void)populate_sysmgr_fpgaintf_module (); } + +/* +* This bit allows the bootrom to configure the IOs after a warm reset. +*/ +void sysmgr_enable_warmrstcfgio (void ) +{ +setbits_le32 (&sysmgr_regs->romcodegrp_ctrl, +SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO ); +}
arch/arm/include/asm/arch-socfpga/system_manager.h +1 -0
@@ -10,6 +10,7 @@#ifndef __ASSEMBLY__void sysmgr_pinmux_init (void ); +void sysmgr_enable_warmrstcfgio (void );/* declaration for handoff table type */ extern unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM ];
Signature · 1 line
2.2.1
PATCH v3 6/17 arm: socfpga: spl: allow bootrom to enable IOs after warm reset
Quoted 4 lines · dinguyen at opensource.altera.com
From: Dinh Nguyen <[email protected]>
Signed-off-by Dinh Nguyen <[email protected]>Acked-by Marek Vasut <[email protected]>
Applied to u-boot-socfpga/next , thanks!
Best regards,
Marek Vasut
PATCH v3 7/17 arm: socfpga: spl: add sdram init and calibration
In reply to dinguyen at opensource.altera.comFrom: Dinh Nguyen <[email protected]>
Add a call to checkboard along with sdram intilialization and calibration.
---
v3: Use debug instead of puts and add a newline for visual separation
v2: Add a fail message
--- arch/arm/cpu/armv7/socfpga/spl.c | 13 +++++++++++++ 1 file changed, 13 insertions(+)
arch/arm/cpu/armv7/socfpga/spl.c +13 -0
@@ -15,6 +15,7 @@#include <asm/arch/freeze_controller.h> #include <asm/arch/clock_manager.h> #include <asm/arch/scan_manager.h> +#include <asm/arch/sdram.h> DECLARE_GLOBAL_DATA_PTR ;
@@ -174,4 +175,16 @@ void spl_board_init(void)/* enable console uart printing */ preloader_console_init (); + +if (sdram_mmr_init_full (0xffffffff ) !=0 ) { +puts ("SDRAM init failed\n" ); +hang (); + } + +debug ("SDRAM: Calibrating PHY\n" ); +/* SDRAM calibration */ +if (sdram_calibration_full () ==0 ) { +puts ("SDRAM calibration failed!\n" ); +hang (); + } }
Signature · 1 line
2.2.1
PATCH v3 7/17 arm: socfpga: spl: add sdram init and calibration
Quoted 25 lines · dinguyen at opensource.altera.com
From: Dinh Nguyen <[email protected]>
Add a call to checkboard along with sdram intilialization and calibration.
Signed-off-by Dinh Nguyen <[email protected]>---
v3: Use debug instead of puts and add a newline for visual separation
v2: Add a fail message--- arch/arm/cpu/armv7/socfpga/spl.c | 13 +++++++++++++ 1 file changed, 13 insertions(+)arch/arm/cpu/armv7/socfpga/spl.c +1
-0@@ -15,6 +15,7 @@#include <asm/arch/freeze_controller.h> #include <asm/arch/clock_manager.h> #include <asm/arch/scan_manager.h> +#include <asm/arch/sdram.h> DECLARE_GLOBAL_DATA_PTR ;
arch/arm/cpu/armv7/socfpga/spl.c void spl_board_init(void) · line 181
Quoted 7 lines
arch/arm/cpu/armv7/socfpga/spl.c +4
-0@@ -174,4 +175,16 @@ void spl_board_init(void)/* enable console uart printing */ preloader_console_init (); + +if (sdram_mmr_init_full (0xffffffff ) !=0 ) { +puts ("SDRAM init failed\n" ); +hang ();
For consistency, you may want to add "." at end of message.
arch/arm/cpu/armv7/socfpga/spl.c void spl_board_init(void) · line 188
Quoted 7 lines
arch/arm/cpu/armv7/socfpga/spl.c +7
-0+ } + +debug ("SDRAM: Calibrating PHY\n" ); +/* SDRAM calibration */ +if (sdram_calibration_full () ==0 ) { +puts ("SDRAM calibration failed!\n" ); +hang ();
I'd change ! to . here, but...
Pavel
Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
PATCH v3 7/17 arm: socfpga: spl: add sdram init and calibration
Quoted 10 lines · Pavel Machek
Quoted 9 lines · dinguyen at opensource.altera.com
From: Dinh Nguyen <[email protected]>
Add a call to checkboard along with sdram intilialization and calibration.
Signed-off-by Dinh Nguyen <[email protected]>---
v3: Use debug instead of puts and add a newline for visual separation
v2: Add a fail message
Applied with changes suggested by Pavel. Thanks!
Best regards,
Marek Vasut
PATCH v3 8/17 arm: socfpga: spl: printout sdram size
In reply to dinguyen at opensource.altera.comFrom: Dinh Nguyen <[email protected]>
---
v3: remove extra brackets
v2: Add a debug print
--- arch/arm/cpu/armv7/socfpga/spl.c | 4 ++++ 1 file changed, 4 insertions(+)
arch/arm/cpu/armv7/socfpga/spl.c +4 -0
@@ -54,6 +54,7 @@ u32 spl_boot_device(void)*/ void spl_board_init (void ) { +unsigned long sdram_size;#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET cm_config_t cm_default_cfg = { /* main group */
@@ -187,4 +188,7 @@ void spl_board_init(void)puts ("SDRAM calibration failed!\n" );hang (); } + + sdram_size =sdram_calculate_size (); +debug ("SDRAM: %ld MiB\n" , sdram_size >>20 ); }
Signature · 1 line
2.2.1
PATCH v3 8/17 arm: socfpga: spl: printout sdram size
Quoted 4 lines · dinguyen at opensource.altera.com
From: Dinh Nguyen <[email protected]>
Signed-off-by Dinh Nguyen <[email protected]>Reviewed-by Marek Vasut <[email protected]>
Applied to u-boot-socfpga/next , thanks!
Best regards,
Marek Vasut
PATCH v3 9/17 arm: socfpga: spl: Use common lowlevel_init
In reply to dinguyen at opensource.altera.comFrom: Dinh Nguyen <[email protected]>
For SoCFGPA, use the common ARMv7 lowlevel_init. Thus, we can delete the SoCFPGA lowlevel_init.S file.
---
v3: Delete SoCFPGA's lowlevel_init.S file
--- arch/arm/cpu/armv7/Makefile | 2 +- arch/arm/cpu/armv7/socfpga/Makefile | 1 - arch/arm/cpu/armv7/socfpga/lowlevel_init.S | 45 ------------------------------ 3 files changed, 1 insertion(+), 47 deletions(-) delete mode 100644 arch/arm/cpu/armv7/socfpga/lowlevel_init.S
arch/arm/cpu/armv7/Makefile +1 -1
@@ -12,7 +12,7 @@ obj-y += cache_v7.o obj-y += cpu.o cp15.o obj-y += syslib.o -ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI),) +ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI)$(CONFIG_SOCFPGA),) ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y) obj-y += lowlevel_init.o endif
arch/arm/cpu/armv7/socfpga/Makefile +0 -1
@@ -7,7 +7,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y := lowlevel_init.o obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \ fpga_manager.o obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o scan_manager.o
arch/arm/cpu/armv7/socfpga/lowlevel_init.S deleted +0 -45
45 lines not on this page · raw message
Signature · 1 line
2.2.1
PATCH v3 9/17 arm: socfpga: spl: Use common lowlevel_init
Quoted 6 lines · dinguyen at opensource.altera.com
From: Dinh Nguyen <[email protected]>
For SoCFGPA, use the common ARMv7
lowlevel_init. Thus, we can delete the SoCFPGAlowlevel_init.Sfile.Signed-off-by Dinh Nguyen <[email protected]>
This patch I like :)
Applied to u-boot-socfpga/next , thanks!
Best regards,
Marek Vasut
PATCH v3 10/17 arm: socfpga: spl: Add s_init stub
In reply to dinguyen at opensource.altera.comFrom: Dinh Nguyen <[email protected]>
Add a stub s_init function in the board file.
---
v3: move the contents of s_init into board_init_f
v2: remove redundant code that is already in arch_early_init_r
--- board/altera/socfpga/socfpga.c | 2 ++ 1 file changed, 2 insertions(+)
board/altera/socfpga/socfpga.c +2 -0
@@ -18,6 +18,8 @@DECLARE_GLOBAL_DATA_PTR ; +void s_init (void ) {} +/* * Miscellaneous platform dependent initialisations */
Signature · 1 line
2.2.1
PATCH v3 10/17 arm: socfpga: spl: Add s_init stub
Quoted 3 lines · dinguyen at opensource.altera.com
From: Dinh Nguyen <[email protected]>
Add a stub
s_initfunction in the board file.
Why do you add this stub function ? The commit message should clarify why the patch is needed.
Quoted 1 line
Signed-off-by Dinh Nguyen <[email protected]>
[...]
Best regards,
Marek Vasut
PATCH v3 10/17 arm: socfpga: spl: Add s_init stub
Quoted 8 lines · Marek Vasut
Quoted 3 lines · dinguyen at opensource.altera.com
From: Dinh Nguyen <[email protected]>
Add a stub
s_initfunction in the board file.Why do you add this stub function ? The commit message should clarify why the patch is needed.
I get this error without this patch:
make: *** [spl/u-boot-spl] Error 2arch/arm/cpu/armv7/built-in.o: In function `lowlevel_init':/home/dinguyen/linux_dev/uboot-socfpga/arch/arm/cpu/armv7/lowlevel_init.S:57: undefined reference to `s_init'
I got the idea that I needed to add this function from this commit "24a6bc010 arm: Reduce the scope of lowlevel_init()".
Commit "e755d543 spl_atmel.c: Switch s_init to board_init_f" is alluding that lowlevel_init is morphing into s_init(), so for now, a stub s_init is needed?
BR,
Dinh
PATCH v3 10/17 arm: socfpga: spl: Add s_init stub
Quoted 2 lines · Dinh Nguyen
Quoted 1 line · Marek Vasut
On Tuesday, March 31, 2015 at 12:01:11 AM, dinguyen at opensource.altera.com
Quoted 14 lines · wrote:
Quoted 6 lines
Quoted 3 lines
From: Dinh Nguyen <[email protected]>
Add a stub
s_initfunction in the board file.Why do you add this stub function ? The commit message should clarify why the patch is needed.
I get this error without this patch:
make: *** [spl/u-boot-spl] Error 2
arch/arm/cpu/armv7/built-in.o: In function `lowlevel_init':/home/dinguyen/linux_dev/uboot-socfpga/arch/arm/cpu/armv7/lowlevel_init.S:57: undefined reference to `s_init'
Quoted 6 lines
I got the idea that I needed to add this function from this commit "
24a6bc010arm: Reduce the scope oflowlevel_init()".Commit "
e755d543spl_atmel.c: Switchs_inittoboard_init_f" is alluding thatlowlevel_initis morphing intos_init(), so for now, a stubs_initis needed?
Ah right. Sorry for the noise.
Best regards,
Marek Vasut
PATCH v3 10/17 arm: socfpga: spl: Add s_init stub
Quoted 18 lines · Marek Vasut
Quoted 2 lines · Dinh Nguyen
Quoted 1 line · Marek Vasut
On Tuesday, March 31, 2015 at 12:01:11 AM, dinguyen at opensource.altera.com
Quoted 14 lines · wrote:
Quoted 6 lines
Quoted 3 lines
From: Dinh Nguyen <[email protected]>
Add a stub
s_initfunction in the board file.Why do you add this stub function ? The commit message should clarify why the patch is needed.
I get this error without this patch:
make: *** [spl/u-boot-spl] Error 2
arch/arm/cpu/armv7/built-in.o: In function `lowlevel_init':/home/dinguyen/linux_dev/uboot-socfpga/arch/arm/cpu/armv7/lowlevel_init.S:57: undefined reference to `s_init'
Quoted 8 lines
Quoted 6 lines
I got the idea that I needed to add this function from this commit "
24a6bc010arm: Reduce the scope oflowlevel_init()".Commit "
e755d543spl_atmel.c: Switchs_inittoboard_init_f" is alluding thatlowlevel_initis morphing intos_init(), so for now, a stubs_initis needed?Ah right. Sorry for the noise.
No worries, I should have been more descriptive in my commit message. Will try to be in future revisions.
Dinh
PATCH v3 10/17 arm: socfpga: spl: Add s_init stub
Quoted 24 lines · Dinh Nguyen
Quoted 23 lines · Marek Vasut
Quoted 3 lines · Dinh Nguyen
Quoted 2 lines · Marek Vasut
On Tuesday, March 31, 2015 at 12:01:11 AM,
dinguyen at opensource.altera.comQuoted 17 lines · wrote:
Quoted 6 lines
Quoted 3 lines
From: Dinh Nguyen <[email protected]>
Add a stub
s_initfunction in the board file.Why do you add this stub function ? The commit message should clarify why the patch is needed.
I get this error without this patch:
make: *** [spl/u-boot-spl] Error 2
arch/arm/cpu/armv7/built-in.o: In function `lowlevel_init':/home/dinguyen/linux_dev/uboot-socfpga/arch/arm/cpu/armv7/lowlevel_init. S:5 7: undefined reference to `s_init'I got the idea that I needed to add this function from this commit "
24a6bc010arm: Reduce the scope oflowlevel_init()".
Quoted 8 lines
Quoted 5 lines
Quoted 3 lines
Commit "
e755d543spl_atmel.c: Switchs_inittoboard_init_f" is alluding thatlowlevel_initis morphing intos_init(), so for now, a stubs_initis needed?Ah right. Sorry for the noise.
No worries, I should have been more descriptive in my commit message. Will try to be in future revisions.
Roger that, thanks!
Best regards,
Marek Vasut
PATCH v3 11/17 arm: socfpga: spl: add CONFIG_SPL_STACK to socfpga_common.h
In reply to dinguyen at opensource.altera.comFrom: Dinh Nguyen <[email protected]>
--- include/configs/socfpga_common.h | 5 +++++ 1 file changed, 5 insertions(+)
include/configs/socfpga_common.h +5 -0
@@ -306,6 +306,11 @@ unsigned int cm_get_qspi_controller_clk_hz(void);#define CONFIG_SPL_WATCHDOG_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT +/* +* Stack setup +*/ +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR +#ifdef CONFIG_SPL_BUILD #undef CONFIG_PARTITIONS#endif
Signature · 1 line
2.2.1
PATCH v3 11/17 arm: socfpga: spl: add CONFIG_SPL_STACK to socfpga_common.h
Quoted 3 lines · dinguyen at opensource.altera.com
From: Dinh Nguyen <[email protected]>
Signed-off-by Dinh Nguyen <[email protected]>
You know, you should really put more effort into writing those commit messages ;-)
Applied to u-boot-socfpga/next , thanks!
Best regards,
Marek Vasut
PATCH v3 12/17 arm: socfpga: spl: Adjust the SYS_INIT_RAM_SIZE to have room for the spl malloc
In reply to dinguyen at opensource.altera.comFrom: Dinh Nguyen <[email protected]>
We need to adjust the SYS_INIT_RAM_SIZE to have room for the SPL_MALLOC_SIZE.
--- include/configs/socfpga_common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
include/configs/socfpga_common.h +1 -1
@@ -40,7 +40,7 @@#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 -#define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100) +#define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - CONFIG_SYS_SPL_MALLOC_SIZE)#define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE)
Signature · 1 line
2.2.1
PATCH v3 12/17 arm: socfpga: spl: Adjust the SYS_INIT_RAM_SIZE to have room for the spl malloc
Quoted 6 lines · dinguyen at opensource.altera.com
From: Dinh Nguyen <[email protected]>
We need to adjust the
SYS_INIT_RAM_SIZEto have room for theSPL_MALLOC_SIZE.Signed-off-by Dinh Nguyen <[email protected]>
Applied to u-boot-socfpga/next , thanks!
Best regards,
Marek Vasut
PATCH v3 13/17 arm: socfpga: spl: add board_init_f to SPL
In reply to dinguyen at opensource.altera.comFrom: Dinh Nguyen <[email protected]>
Remap SDRAM to 0x0, and clear OCRAM's ECC in board_init_f().
---
v3: Move the code from s_init to board_init_f
--- arch/arm/cpu/armv7/socfpga/spl.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+)
arch/arm/cpu/armv7/socfpga/spl.c +30 -0
@@ -6,6 +6,7 @@#include <common.h> #include <asm/io.h> +#include <asm/pl310.h> #include <asm/u-boot.h> #include <asm/utils.h> #include <image.h>
@@ -19,6 +20,9 @@DECLARE_GLOBAL_DATA_PTR ; +static struct pl310_regs *const pl310 = + (struct pl310_regs *)CONFIG_SYS_PL310_BASE ; +#define MAIN_VCO_BASE ( \ (CONFIG_HPS_MAINPLLGRP_VCO_DENOM << \ CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) | \
@@ -44,6 +48,32 @@ DECLARE_GLOBAL_DATA_PTR; CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) \ ) +void board_init_f (ulong dummy) +{ +#ifdef CONFIG_SPL_BUILD +struct socfpga_system_manager *sysmgr_regs = + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS ; +unsigned long reg; +/* +* First C code to run. Clear fake OCRAM ECC first as SBE +* and DBE might triggered during power on +*/ + reg =readl (&sysmgr_regs->eccgrp_ocram); +if (reg &SYSMGR_ECC_OCRAM_SERR ) +writel (SYSMGR_ECC_OCRAM_SERR |SYSMGR_ECC_OCRAM_EN , + &sysmgr_regs->eccgrp_ocram); +if (reg &SYSMGR_ECC_OCRAM_DERR ) +writel (SYSMGR_ECC_OCRAM_DERR |SYSMGR_ECC_OCRAM_EN , + &sysmgr_regs->eccgrp_ocram); +#endif /* CONFIG_SPL_BUILD */ + +memset (__bss_start,0 , __bss_end - __bss_start); + +writel (0x1 , &pl310->pl310_addr_filter_start); + +board_init_r (NULL ,0 ); +} +u32 spl_boot_device (void ) {return BOOT_DEVICE_RAM ;
Signature · 1 line
2.2.1
PATCH v3 13/17 arm: socfpga: spl: add board_init_f to SPL
Hi!
Quoted 35 lines · dinguyen at opensource.altera.com
From: Dinh Nguyen <[email protected]>
Remap SDRAM to
0x0, and clear OCRAM's ECC inboard_init_f().Signed-off-by Dinh Nguyen <[email protected]>Reviewed-by Marek Vasut <[email protected]>---
v3: Move the code froms_inittoboard_init_f--- arch/arm/cpu/armv7/socfpga/spl.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+)arch/arm/cpu/armv7/socfpga/spl.c +4
-0@@ -6,6 +6,7 @@#include <common.h> #include <asm/io.h> +#include <asm/pl310.h> #include <asm/u-boot.h> #include <asm/utils.h> #include <image.h> @@ -19,6 +20,9 @@DECLARE_GLOBAL_DATA_PTR ; +static struct pl310_regs *const pl310 = + (struct pl310_regs *)CONFIG_SYS_PL310_BASE ; +#define MAIN_VCO_BASE ( \ (CONFIG_HPS_MAINPLLGRP_VCO_DENOM << \ CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) | \
arch/arm/cpu/armv7/socfpga/spl.c DECLARE_GLOBAL_DATA_PTR; · line 53
Quoted 6 lines
arch/arm/cpu/armv7/socfpga/spl.c +3
-0@@ -44,6 +48,32 @@ DECLARE_GLOBAL_DATA_PTR; CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) \ ) +void board_init_f (ulong dummy) +{ +#ifdef CONFIG_SPL_BUILD
I don't get it. File is called spl.c, still it has ifdefs for CONFIG_SPL_BUILD?
Quoted 7 lines
arch/arm/cpu/armv7/socfpga/spl.c +7
-0+struct socfpga_system_manager *sysmgr_regs = + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS ; +unsigned long reg; +/* +* First C code to run. Clear fake OCRAM ECC first as SBE +* and DBE might triggered during power on +*/
arch/arm/cpu/armv7/socfpga/spl.c DECLARE_GLOBAL_DATA_PTR; · line 70
Quoted 10 lines
arch/arm/cpu/armv7/socfpga/spl.c +10
-0+ reg =readl (&sysmgr_regs->eccgrp_ocram); +if (reg &SYSMGR_ECC_OCRAM_SERR ) +writel (SYSMGR_ECC_OCRAM_SERR |SYSMGR_ECC_OCRAM_EN , + &sysmgr_regs->eccgrp_ocram); +if (reg &SYSMGR_ECC_OCRAM_DERR ) +writel (SYSMGR_ECC_OCRAM_DERR |SYSMGR_ECC_OCRAM_EN , + &sysmgr_regs->eccgrp_ocram); +#endif /* CONFIG_SPL_BUILD */ + +memset (__bss_start,0 , __bss_end - __bss_start);
Add a comment below?
/* Remap SDRAM to 0x0 */
Quoted 3 lines
arch/arm/cpu/armv7/socfpga/spl.c +3
-0+ +writel (0x1 , &pl310->pl310_addr_filter_start); +
Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
PATCH v3 13/17 arm: socfpga: spl: add board_init_f to SPL
Quoted 49 lines · Pavel Machek
Hi!
Quoted 46 lines · dinguyen at opensource.altera.com
From: Dinh Nguyen <[email protected]>
Remap SDRAM to
0x0, and clear OCRAM's ECC inboard_init_f().Signed-off-by Dinh Nguyen <[email protected]>Reviewed-by Marek Vasut <[email protected]>---
v3: Move the code froms_inittoboard_init_f
---arch/arm/cpu/armv7/socfpga/spl.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+)(quoted diff) +0
-0
b/arch/arm/cpu/armv7/socfpga/spl.cindex a008eac..f2d3f79 100644arch/arm/cpu/armv7/socfpga/spl.c +1
-0@@ -6,6 +6,7 @@#include <common.h> #include <asm/io.h> +#include <asm/pl310.h> #include <asm/u-boot.h> #include <
asm/utils.h>
#include <image.h>arch/arm/cpu/armv7/socfpga/spl.c +3
-0@@ -19,6 +20,9 @@DECLARE_GLOBAL_DATA_PTR ; +static struct pl310_regs *const pl310 = + (struct pl310_regs *)CONFIG_SYS_PL310_BASE ; +#define MAIN_VCO_BASE ( \arch/arm/cpu/armv7/socfpga/spl.c +0
-0(CONFIG_HPS_MAINPLLGRP_VCO_DENOM << \ CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) | \@@ -44,6 +48,32 @@ DECLARE_GLOBAL_DATA_PTR; CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) \
Quoted 8 lines
arch/arm/cpu/armv7/socfpga/spl.c DECLARE_GLOBAL_DATA_PTR; · line 53
Quoted 5 lines
arch/arm/cpu/armv7/socfpga/spl.c +3
-0) +void board_init_f (ulong dummy) +{ +#ifdef CONFIG_SPL_BUILD I don't get it. File is called
spl.c, still it has ifdefs forCONFIG_SPL_BUILD?
Yeah, this shouldn't be here. In case spl.c would be compiled into regular u-boot build, this board_init_f symbol would colide with the board_init_f implemented by common/board_f.c
Quoted 25 lines
Quoted 7 lines
arch/arm/cpu/armv7/socfpga/spl.c +7
-0+struct socfpga_system_manager *sysmgr_regs = + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS ; +unsigned long reg; +/* +* First C code to run. Clear fake OCRAM ECC first as SBE +* and DBE might triggered during power on +*/ arch/arm/cpu/armv7/socfpga/spl.c DECLARE_GLOBAL_DATA_PTR; · line 70
Quoted 10 lines
arch/arm/cpu/armv7/socfpga/spl.c +10
-0+ reg =readl (&sysmgr_regs->eccgrp_ocram); +if (reg &SYSMGR_ECC_OCRAM_SERR ) +writel (SYSMGR_ECC_OCRAM_SERR |SYSMGR_ECC_OCRAM_EN , + &sysmgr_regs->eccgrp_ocram); +if (reg &SYSMGR_ECC_OCRAM_DERR ) +writel (SYSMGR_ECC_OCRAM_DERR |SYSMGR_ECC_OCRAM_EN , + &sysmgr_regs->eccgrp_ocram); +#endif /* CONFIG_SPL_BUILD */ + +memset (__bss_start,0 , __bss_end - __bss_start);Add a comment below?
/* Remap SDRAM to
0x0*/Quoted 3 lines
arch/arm/cpu/armv7/socfpga/spl.c +3
-0+ +writel (0x1 , &pl310->pl310_addr_filter_start); +
PATCH v3 13/17 arm: socfpga: spl: add board_init_f to SPL
Quoted 59 lines · Marek Vasut
Quoted 49 lines · Pavel Machek
Hi!
Quoted 46 lines · dinguyen at opensource.altera.com
From: Dinh Nguyen <[email protected]>
Remap SDRAM to
0x0, and clear OCRAM's ECC inboard_init_f().Signed-off-by Dinh Nguyen <[email protected]>Reviewed-by Marek Vasut <[email protected]>---
v3: Move the code froms_inittoboard_init_f
---arch/arm/cpu/armv7/socfpga/spl.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+)(quoted diff) +0
-0
b/arch/arm/cpu/armv7/socfpga/spl.cindex a008eac..f2d3f79 100644arch/arm/cpu/armv7/socfpga/spl.c +1
-0@@ -6,6 +6,7 @@#include <common.h> #include <asm/io.h> +#include <asm/pl310.h> #include <asm/u-boot.h> #include <
asm/utils.h>
#include <image.h>arch/arm/cpu/armv7/socfpga/spl.c +3
-0@@ -19,6 +20,9 @@DECLARE_GLOBAL_DATA_PTR ; +static struct pl310_regs *const pl310 = + (struct pl310_regs *)CONFIG_SYS_PL310_BASE ; +#define MAIN_VCO_BASE ( \arch/arm/cpu/armv7/socfpga/spl.c +0
-0(CONFIG_HPS_MAINPLLGRP_VCO_DENOM << \ CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) | \@@ -44,6 +48,32 @@ DECLARE_GLOBAL_DATA_PTR; CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) \Quoted 8 lines
arch/arm/cpu/armv7/socfpga/spl.c DECLARE_GLOBAL_DATA_PTR; · line 53
Quoted 5 lines
arch/arm/cpu/armv7/socfpga/spl.c +3
-0) +void board_init_f (ulong dummy) +{ +#ifdef CONFIG_SPL_BUILD I don't get it. File is called
spl.c, still it has ifdefs forCONFIG_SPL_BUILD?
Quoted 4 lines
Yeah, this shouldn't be here. In case
spl.cwould be compiled into regular u-boot build, thisboard_init_fsymbol would colide with theboard_init_fimplemented bycommon/board_f.c
Will fix in V4.
Quoted 20 lines
Quoted 20 lines
Quoted 7 lines
arch/arm/cpu/armv7/socfpga/spl.c +7
-0+struct socfpga_system_manager *sysmgr_regs = + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS ; +unsigned long reg; +/* +* First C code to run. Clear fake OCRAM ECC first as SBE +* and DBE might triggered during power on +*/ arch/arm/cpu/armv7/socfpga/spl.c DECLARE_GLOBAL_DATA_PTR; · line 70
Quoted 10 lines
arch/arm/cpu/armv7/socfpga/spl.c +10
-0+ reg =readl (&sysmgr_regs->eccgrp_ocram); +if (reg &SYSMGR_ECC_OCRAM_SERR ) +writel (SYSMGR_ECC_OCRAM_SERR |SYSMGR_ECC_OCRAM_EN , + &sysmgr_regs->eccgrp_ocram); +if (reg &SYSMGR_ECC_OCRAM_DERR ) +writel (SYSMGR_ECC_OCRAM_DERR |SYSMGR_ECC_OCRAM_EN , + &sysmgr_regs->eccgrp_ocram); +#endif /* CONFIG_SPL_BUILD */ + +memset (__bss_start,0 , __bss_end - __bss_start);Add a comment below?
Quoted 2 lines
Quoted 2 lines
/* Remap SDRAM to
0x0*/
I'll add to V4.
BR,
Dinh
PATCH v3 13/17 arm: socfpga: spl: add board_init_f to SPL
Quoted 86 lines · Dinh Nguyen
Quoted 59 lines · Marek Vasut
Quoted 49 lines · Pavel Machek
Hi!
Quoted 46 lines · dinguyen at opensource.altera.com
From: Dinh Nguyen <[email protected]>
Remap SDRAM to
0x0, and clear OCRAM's ECC inboard_init_f().Signed-off-by Dinh Nguyen <[email protected]>Reviewed-by Marek Vasut <[email protected]>---
v3: Move the code froms_inittoboard_init_f
---arch/arm/cpu/armv7/socfpga/spl.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+)(quoted diff) +0
-0
b/arch/arm/cpu/armv7/socfpga/spl.cindex a008eac..f2d3f79 100644arch/arm/cpu/armv7/socfpga/spl.c +1
-0@@ -6,6 +6,7 @@#include <common.h> #include <asm/io.h> +#include <asm/pl310.h> #include <asm/u-boot.h> #include <
asm/utils.h>
#include <image.h>arch/arm/cpu/armv7/socfpga/spl.c +3
-0@@ -19,6 +20,9 @@DECLARE_GLOBAL_DATA_PTR ; +static struct pl310_regs *const pl310 = + (struct pl310_regs *)CONFIG_SYS_PL310_BASE ; +#define MAIN_VCO_BASE ( \arch/arm/cpu/armv7/socfpga/spl.c +0
-0(CONFIG_HPS_MAINPLLGRP_VCO_DENOM << \ CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) | \@@ -44,6 +48,32 @@ DECLARE_GLOBAL_DATA_PTR; CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) \Quoted 8 lines
arch/arm/cpu/armv7/socfpga/spl.c DECLARE_GLOBAL_DATA_PTR; · line 53
Quoted 5 lines
arch/arm/cpu/armv7/socfpga/spl.c +3
-0) +void board_init_f (ulong dummy) +{ +#ifdef CONFIG_SPL_BUILD I don't get it. File is called
spl.c, still it has ifdefs forCONFIG_SPL_BUILD?Quoted 3 lines
Yeah, this shouldn't be here. In case
spl.cwould be compiled into regular u-boot build, thisboard_init_fsymbol would colide with theboard_init_fimplemented bycommon/board_f.cWill fix in V4.
Quoted 20 lines
Quoted 20 lines
Quoted 7 lines
arch/arm/cpu/armv7/socfpga/spl.c +7
-0+struct socfpga_system_manager *sysmgr_regs = + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS ; +unsigned long reg; +/* +* First C code to run. Clear fake OCRAM ECC first as SBE +* and DBE might triggered during power on +*/ arch/arm/cpu/armv7/socfpga/spl.c DECLARE_GLOBAL_DATA_PTR; · line 70
Quoted 10 lines
arch/arm/cpu/armv7/socfpga/spl.c +10
-0+ reg =readl (&sysmgr_regs->eccgrp_ocram); +if (reg &SYSMGR_ECC_OCRAM_SERR ) +writel (SYSMGR_ECC_OCRAM_SERR |SYSMGR_ECC_OCRAM_EN , + &sysmgr_regs->eccgrp_ocram); +if (reg &SYSMGR_ECC_OCRAM_DERR ) +writel (SYSMGR_ECC_OCRAM_DERR |SYSMGR_ECC_OCRAM_EN , + &sysmgr_regs->eccgrp_ocram); +#endif /* CONFIG_SPL_BUILD */ + +memset (__bss_start,0 , __bss_end - __bss_start);Add a comment below?
Quoted 3 lines
Quoted 1 line
Quoted 1 line
/* Remap SDRAM to
0x0*/I'll add to V4.
Thanks!
PATCH v3 14/17 arm: socfpga: spl: Add SDRAM check
In reply to dinguyen at opensource.altera.comFrom: Dinh Nguyen <[email protected]>
---
v3: Only report the failure
v2: Be a bit more verbose about the fail message
--- arch/arm/cpu/armv7/socfpga/spl.c | 6 ++++++ 1 file changed, 6 insertions(+)
arch/arm/cpu/armv7/socfpga/spl.c +6 -0
@@ -221,4 +221,10 @@ void spl_board_init(void) sdram_size =sdram_calculate_size ();debug ("SDRAM: %ld MiB\n" , sdram_size >>20 ); + +/* Sanity check ensure correct SDRAM size specified */ +if (get_ram_size (0 , sdram_size) != sdram_size) { +puts ("SDRAM size check failed!\n" ); +hang (); + } }
Signature · 1 line
2.2.1
PATCH v3 14/17 arm: socfpga: spl: Add SDRAM check
Quoted 15 lines · dinguyen at opensource.altera.com
From: Dinh Nguyen <[email protected]>
Signed-off-by Dinh Nguyen <[email protected]>---
v3: Only report the failure
v2: Be a bit more verbose about the fail message--- arch/arm/cpu/armv7/socfpga/spl.c | 6 ++++++ 1 file changed, 6 insertions(+)arch/arm/cpu/armv7/socfpga/spl.c +0
-0
arch/arm/cpu/armv7/socfpga/spl.c void spl_board_init(void) · line 225
Quoted 5 lines
arch/arm/cpu/armv7/socfpga/spl.c +2
-0@@ -221,4 +221,10 @@ void spl_board_init(void) sdram_size =sdram_calculate_size ();debug ("SDRAM: %ld MiB\n" , sdram_size >>20 ); + +/* Sanity check ensure correct SDRAM size specified */
There's extra space before /*. Plus.. maybe you want to merge this to previous patch adding the sdram_size calculation? There's no need to split 4 line patch to two 2 liners...
Pavel
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PATCH v3 14/17 arm: socfpga: spl: Add SDRAM check
Quoted 21 lines · Pavel Machek
Quoted 20 lines · dinguyen at opensource.altera.com
From: Dinh Nguyen <[email protected]>
Signed-off-by Dinh Nguyen <[email protected]>---
v3: Only report the failure
v2: Be a bit more verbose about the fail message
---arch/arm/cpu/armv7/socfpga/spl.c | 6 ++++++ 1 file changed, 6 insertions(+)(quoted diff) +0
-0
b/arch/arm/cpu/armv7/socfpga/spl.cindex f2d3f79..dd4d882 100644arch/arm/cpu/armv7/socfpga/spl.c +0
-0@@ -221,4 +221,10 @@ void spl_board_init(void) sdram_size =sdram_calculate_size ();debug ("SDRAM: %ld MiB\n" , sdram_size >>20 );
Quoted 6 lines
arch/arm/cpu/armv7/socfpga/spl.c void spl_board_init(void) · line 225
Quoted 2 lines
arch/arm/cpu/armv7/socfpga/spl.c +2
-0+ +/* Sanity check ensure correct SDRAM size specified */ There's extra space before /*. Plus.. maybe you want to merge this to previous patch adding the
sdram_sizecalculation? There's no need to split 4 line patch to two 2 liners...
Fixed the extra space (nice catch) and applied, thanks!
Best regards,
Marek Vasut
PATCH v3 15/17 arm: socfpga: spl: update pll_config for dev kit
In reply to dinguyen at opensource.altera.comFrom: Dinh Nguyen <[email protected]>
This sets the CPU clocks to 925MHz and DDR to 400MHz, and the correct CONFIG_HPS_MAINPLLGRP_VCO_NUMER should be 79.
--- board/altera/socfpga/pll_config.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
board/altera/socfpga/pll_config.h +2 -2
@@ -12,7 +12,7 @@/* PLL configuration data */ /* Main PLL */ #define CONFIG_HPS_MAINPLLGRP_VCO_DENOM (0) -#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER (63) +#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER (73)#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT (0)#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT (0)#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT (0)
@@ -36,7 +36,7 @@/* Peripheral PLL */ #define CONFIG_HPS_PERPLLGRP_VCO_DENOM (1) -#define CONFIG_HPS_PERPLLGRP_VCO_NUMER (39) +#define CONFIG_HPS_PERPLLGRP_VCO_NUMER (79)/* * To tell where is the VCOs source: * 0 = EOSC1
Signature · 1 line
2.2.1
PATCH v3 15/17 arm: socfpga: spl: update pll_config for dev kit
Quoted 4 lines · dinguyen at opensource.altera.com
From: Dinh Nguyen <[email protected]>
This sets the CPU clocks to 925MHz and DDR to 400MHz, and the correct
CONFIG_HPS_MAINPLLGRP_VCO_NUMERshould be 79.
Didn't various CV SX run at 800MHz only ? I think only some of them ran at 925MHz, not all of them.
Quoted 2 lines
Signed-off-by Dinh Nguyen <[email protected]>Reviewed-by Marek Vasut <[email protected]>
[...]
Best regards,
Marek Vasut
PATCH v3 15/17 arm: socfpga: spl: update pll_config for dev kit
Quoted 9 lines · Marek Vasut
Quoted 4 lines · dinguyen at opensource.altera.com
From: Dinh Nguyen <[email protected]>
This sets the CPU clocks to 925MHz and DDR to 400MHz, and the correct
CONFIG_HPS_MAINPLLGRP_VCO_NUMERshould be 79.Didn't various CV SX run at 800MHz only ? I think only some of them ran at 925MHz, not all of them.
Ah yes, I think I'm lucky to have a 925MHz devkit on my desk. But I think CONFIG_HPS_MAINPLLGRP_VCO_NUMER should be 79, as I cannot get a correct baudrate without it.
Dinh
PATCH v3 15/17 arm: socfpga: spl: update pll_config for dev kit
Quoted 2 lines · Dinh Nguyen
Quoted 1 line · Marek Vasut
On Tuesday, March 31, 2015 at 12:01:16 AM, dinguyen at opensource.altera.com
Quoted 11 lines · wrote:
Quoted 7 lines
Quoted 4 lines
From: Dinh Nguyen <[email protected]>
This sets the CPU clocks to 925MHz and DDR to 400MHz, and the correct
CONFIG_HPS_MAINPLLGRP_VCO_NUMERshould be 79.Didn't various CV SX run at 800MHz only ? I think only some of them ran at 925MHz, not all of them.
Ah yes, I think I'm lucky to have a 925MHz devkit on my desk. But I think
CONFIG_HPS_MAINPLLGRP_VCO_NUMERshould be 79, as I cannot get a correct baudrate without it.
Yep, you and me are both lucky. The AV is also 925MHz part.
I have some SoCrates and MCV SoMs which are 800 MHz parts, so I'd like to keep those parts operational, but I think I'll just have to figure something out on a per-board basis.
I'll check the subsequent patch and see if I can pick it up now. Thanks!
Best regards,
Marek Vasut
PATCH v3 16/17 arm: socfpga: remove the need to map sdram in arch_early_init
In reply to dinguyen at opensource.altera.comFrom: Dinh Nguyen <[email protected]>
Since we are already mapping sdram 0x0 in board_init_f, we can remove it here.
--- arch/arm/cpu/armv7/socfpga/misc.c | 3 --- 1 file changed, 3 deletions(-)
arch/arm/cpu/armv7/socfpga/misc.c +0 -3
@@ -205,9 +205,6 @@ int arch_early_init_r(void)/* Configure the L2 controller to make SDRAM start at 0 */ #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET writel (0x2 , &nic301_regs->remap); -#else -writel (0x1 , &nic301_regs->remap);/* remap.mpuzero */ -writel (0x1 , &pl310->pl310_addr_filter_start);#endif /* Add device descriptor to FPGA device table */
Signature · 1 line
2.2.1
PATCH v3 16/17 arm: socfpga: remove the need to map sdram in arch_early_init
Quoted 7 lines · dinguyen at opensource.altera.com
From: Dinh Nguyen <[email protected]>
Since we are already mapping sdram
0x0inboard_init_f, we can remove it here.Signed-off-by Dinh Nguyen <[email protected]>Reviewed-by Marek Vasut <[email protected]>
Yes, and you want to merge this to the patch that does that.
Also.. what about that "VIRTUAL_TARGET" ifdef? Should not the remap be done in the same place for both?
Quoted 18 lines
--- arch/arm/cpu/armv7/socfpga/misc.c | 3 --- 1 file changed, 3 deletions(-)arch/arm/cpu/armv7/socfpga/misc.c +0
-3@@ -205,9 +205,6 @@ int arch_early_init_r(void)/* Configure the L2 controller to make SDRAM start at 0 */ #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET writel (0x2 , &nic301_regs->remap); -#else -writel (0x1 , &nic301_regs->remap);/* remap.mpuzero */ -writel (0x1 , &pl310->pl310_addr_filter_start);#endif /* Add device descriptor to FPGA device table */
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PATCH v3 16/17 arm: socfpga: remove the need to map sdram in arch_early_init
In reply to dinguyen at opensource.altera.comQuoted 7 lines · dinguyen at opensource.altera.com
From: Dinh Nguyen <[email protected]>
Since we are already mapping sdram
0x0inboard_init_f, we can remove it here.Signed-off-by Dinh Nguyen <[email protected]>Reviewed-by Marek Vasut <[email protected]>
I'm kinda hesitant to apply this now, while we still don't have the SPL well in place. Is it OK to postpone this patch until we have the SPL well in place please ?
Best regards,
Marek Vasut
PATCH v3 17/17 arm: socfpga: fix uart0 pin mux configuration
In reply to dinguyen at opensource.altera.comFrom: Dinh Nguyen <[email protected]>
commit "07d30b6c3129 arm: socfpga: Sync Cyclone V DK pinmux configuration" incorrectly set the muxing for UART0 on the Cyclone V DK.
This fixes it up so UART0 is working again.
--- board/altera/socfpga/pinmux_config.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
board/altera/socfpga/pinmux_config.c +2 -2
@@ -54,8 +54,8 @@ unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM] = {2 ,/* GENERALIO14 */ 0 ,/* GENERALIO15 */ 0 ,/* GENERALIO16 */ -0 ,/* GENERALIO17 */ -0 ,/* GENERALIO18 */ +2 ,/* GENERALIO17 */ +2 ,/* GENERALIO18 */ 0 ,/* GENERALIO19 */ 0 ,/* GENERALIO20 */ 0, /* GENERALIO21 */
Signature · 1 line
2.2.1
PATCH v3 17/17 arm: socfpga: fix uart0 pin mux configuration
Quoted 8 lines · dinguyen at opensource.altera.com
From: Dinh Nguyen <[email protected]>
commit "
07d30b6c3129arm: socfpga: Sync Cyclone V DK pinmux configuration" incorrectly set the muxing for UART0 on the Cyclone V DK.This fixes it up so UART0 is working again.
Signed-off-by Dinh Nguyen <[email protected]>
But I guess this one should be merged ahead of the rest of series...?
Pavel
Quoted 19 lines
--- board/altera/socfpga/pinmux_config.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)board/altera/socfpga/pinmux_config.c +2
-2@@ -54,8 +54,8 @@ unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM] = {2 ,/* GENERALIO14 */ 0 ,/* GENERALIO15 */ 0 ,/* GENERALIO16 */ -0 ,/* GENERALIO17 */ -0 ,/* GENERALIO18 */ +2 ,/* GENERALIO17 */ +2 ,/* GENERALIO18 */ 0 ,/* GENERALIO19 */ 0 ,/* GENERALIO20 */ 0, /* GENERALIO21 */
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PATCH v3 17/17 arm: socfpga: fix uart0 pin mux configuration
Quoted 8 lines · Pavel Machek
Quoted 7 lines · dinguyen at opensource.altera.com
From: Dinh Nguyen <[email protected]>
commit "
07d30b6c3129arm: socfpga: Sync Cyclone V DK pinmux configuration" incorrectly set the muxing for UART0 on the Cyclone V DK.This fixes it up so UART0 is working again.
Quoted 7 lines
Quoted 1 line
Signed-off-by Dinh Nguyen <[email protected]>Acked-by Pavel Machek <[email protected]>But I guess this one should be merged ahead of the rest of series...?
Pavel
Yes, this patch should get merged without the SPL.
Dinh
PATCH v3 17/17 arm: socfpga: fix uart0 pin mux configuration
Quoted 11 lines · Dinh Nguyen
Quoted 8 lines · Pavel Machek
Quoted 7 lines · dinguyen at opensource.altera.com
From: Dinh Nguyen <[email protected]>
commit "
07d30b6c3129arm: socfpga: Sync Cyclone V DK pinmux configuration" incorrectly set the muxing for UART0 on the Cyclone V DK.This fixes it up so UART0 is working again.
Quoted 7 lines
Quoted 6 lines
Quoted 1 line
Signed-off-by Dinh Nguyen <[email protected]>Acked-by Pavel Machek <[email protected]>But I guess this one should be merged ahead of the rest of series...?
Yes, this patch should get merged without the SPL.
I suggest to send it separately, or make it part 1/ of the series.
Thanks,
Pavel
Signature · 2 lines
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PATCH v3 17/17 arm: socfpga: fix uart0 pin mux configuration
Quoted 13 lines · Pavel Machek
Quoted 12 lines · Dinh Nguyen
Quoted 11 lines · Pavel Machek
Quoted 9 lines · dinguyen at opensource.altera.com
From: Dinh Nguyen <[email protected]>
commit "
07d30b6c3129arm: socfpga: Sync Cyclone V DK pinmux configuration" incorrectly set the muxing for UART0 on the Cyclone V DK.This fixes it up so UART0 is working again.
Signed-off-by Dinh Nguyen <[email protected]>
Quoted 7 lines
Quoted 5 lines
Quoted 3 lines
Acked-by Pavel Machek <[email protected]>But I guess this one should be merged ahead of the rest of series...?
Yes, this patch should get merged without the SPL.
I suggest to send it separately, or make it part 1/ of the series.
Yeah, sending unrelated patches separately so they can go in ASAP would really help. Even breaking a series into smaller chunks could help.
I applied whatever was reasonable to u-boot-socfpga/next, so you don't have to re-send the entire bulk of patches again.
Best regards,
Marek Vasut
PATCH v3 17/17 arm: socfpga: fix uart0 pin mux configuration
In reply to dinguyen at opensource.altera.comQuoted 9 lines · dinguyen at opensource.altera.com
From: Dinh Nguyen <[email protected]>
commit "
07d30b6c3129arm: socfpga: Sync Cyclone V DK pinmux configuration" incorrectly set the muxing for UART0 on the Cyclone V DK.This fixes it up so UART0 is working again.
Signed-off-by Dinh Nguyen <[email protected]>---
Applied to u-boot-socfpga/next , thanks!
Best regards,
Marek Vasut
v3 cover Add SPL support for SoCFPGA
In reply to dinguyen at opensource.altera.comHi!
Quoted 11 lines
This is v3 of the patchset that adds all the SPL code that is necessary to support the SoCFPGA platform. For v3, here are the changes:
- Remove gdata
- Removes_init
- Remove socfpgalowlevel_init.S
- Use commonu-boot-spl.lds
- Properly useCONFIG_SPL_TEXT_BASEso we don't have to add an .sram sectionI have pushed a branch to
git://git.rocketboards.org/u-boot-socfpga-next.gitsocfpga_for_next_spl_v3for testing and reviewing.
For 2,4,5,6,8,9,10,11,12,15 of the series, you can add
Thanks,
Pavel
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[U-Boot] printf("%d") breaks u-boot 2015.01+
In reply to dinguyen at opensource.altera.comHi!
In u-boot 2015.04-rc, as soon as execution hits printf("%d"), it hangs. (Usually, that's after "DRAM: " message).
Now, I have to admit I'm chainloading u-boot from
U-Boot 2013.01.01 (Mar 25 2015 - 15:57:21)
tftp 0x01000040 .../u-boot.bin
Waiting for PHY auto negotiation to complete.. done ENET Speed is 100 Mbps - FULL duplex connection Using mii0 device
TFTP from server 10.0.0.6; our IP address is 10.0.0.99
...
Bytes transferred = 325004 (4f58c hex)
# go 0x01000040
...but that worked well for 2014.10, (and is nearly mandatory in my config).
I'm using cross-compiler from eldk-5.6, but eldk-5.4 crosscompiler produces same behaviour, and both seem to work for 2014.10.
Any ideas?
Thanks,
Pavel
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[U-Boot] printf("%d") breaks u-boot 2015.01+
Quoted 4 lines · Pavel Machek
Hi!
In u-boot 2015.04-rc, as soon as execution hits
printf("%d"), it hangs. (Usually, that's after "DRAM: " message).
printf("%d") expects an argument, so could it be that it touches random piece of memory and thus hangs?
Best regards,
Marek Vasut
[U-Boot] printf("%d") breaks u-boot 2015.01+
Quoted 8 lines · Marek Vasut
Quoted 4 lines · Pavel Machek
Hi!
In u-boot 2015.04-rc, as soon as execution hits
printf("%d"), it hangs. (Usually, that's after "DRAM: " message).
printf("%d")expects an argument, so could it be that it touches random piece of memory and thus hangs?
It had an argument, sorry for confusion. I was actually doing this:
the test with %s works, the one with %d kills it.
I suspect too small stack...?
Pavel
int dram_init(void)
{
printf("dram init: print size\n");
- // printf("printf test: %x\n", 0x12345678);
- // printf("dram_init... %x\n", PHYS_SDRAM_1_SIZE);
- gd->ram_size = PHYS_SDRAM_1_SIZE /2; //get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+ printf("printf test: %x\n", 0x12345678);
+ printf("dram_init... %x\n", PHYS_SDRAM_1_SIZE);
+ gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
printf("dram init: ram size set\n");
return 0;
}
@@ -108,6 +108,9 @@ int cpu_mmc_init(bd_t *bis)
int print_cpuinfo(void)
{
puts("CPU: Altera SoCFPGA Platform\n");
+ printf("printf test string: %s\n", "ahoj");
+ printf("printf test: %d\n", 1234567);
+ printf("printf test: %x\n", 0x12345678); return 0;
}
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[U-Boot] printf("%d") breaks u-boot 2015.01+
Quoted 7 lines · Pavel Machek
Quoted 6 lines · Marek Vasut
Quoted 4 lines · Pavel Machek
Hi!
In u-boot 2015.04-rc, as soon as execution hits
printf("%d"), it hangs. (Usually, that's after "DRAM: " message).
Quoted 7 lines
Quoted 2 lines
printf("%d")expects an argument, so could it be that it touches random piece of memory and thus hangs?It had an argument, sorry for confusion. I was actually doing this:
the test with %s works, the one with %d kills it.I suspect too small stack...?
Does this happen in the SPL ? You can check the stack placement and utilization with BDI to verigy your hypothesis.
Best regards,
Marek Vasut
[U-Boot] printf("%d") breaks u-boot 2015.01+
Quoted 11 lines · Marek Vasut
Quoted 10 lines · Pavel Machek
Quoted 8 lines · Marek Vasut
Quoted 4 lines · Pavel Machek
Hi!
In u-boot 2015.04-rc, as soon as execution hits
printf("%d"), it hangs. (Usually, that's after "DRAM: " message).
printf("%d")expects an argument, so could it be that it touches random piece of memory and thus hangs?
Quoted 7 lines
Quoted 4 lines
It had an argument, sorry for confusion. I was actually doing this:
the test with %s works, the one with %d kills it.I suspect too small stack...?
Does this happen in the SPL ? You can check the stack placement and utilization with BDI to verigy your hypothesis.
No, this is u-boot proper, and I'm chainloading it (see first mail) -- so unsupported configuration.
I'm preparing to flash the u-boot into the NOR, that should tell us if it is chainloading problem or not.
Best regards,
Pavel
Signature · 2 lines
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[U-Boot] printf("%d") breaks u-boot 2015.01+
Quoted 17 lines · Pavel Machek
Quoted 16 lines · Marek Vasut
Quoted 14 lines · Pavel Machek
Quoted 8 lines · Marek Vasut
Quoted 4 lines · Pavel Machek
Hi!
In u-boot 2015.04-rc, as soon as execution hits
printf("%d"), it hangs. (Usually, that's after "DRAM: " message).
printf("%d")expects an argument, so could it be that it touches random piece of memory and thus hangs?It had an argument, sorry for confusion. I was actually doing this:
the test with %s works, the one with %d kills it.I suspect too small stack...?
Quoted 8 lines
Quoted 2 lines
Does this happen in the SPL ? You can check the stack placement and utilization with BDI to verigy your hypothesis.
No, this is u-boot proper, and I'm chainloading it (see first mail) -- so unsupported configuration.
I'm preparing to flash the u-boot into the NOR, that should tell us if it is chainloading problem or not.
OK, since this email was in-reply-to SPL patch series, I got confused. Is it in any way related to this patchset then or not ?
Best regards,
Marek Vasut
[U-Boot] printf("%d") breaks u-boot 2015.01+
Quoted 21 lines · Marek Vasut
Quoted 20 lines · Pavel Machek
Quoted 18 lines · Marek Vasut
Quoted 7 lines · Pavel Machek
Quoted 6 lines · Marek Vasut
Quoted 4 lines · Pavel Machek
Hi!
In u-boot 2015.04-rc, as soon as execution hits
printf("%d"), it hangs. (Usually, that's after "DRAM: " message).Quoted 7 lines
Quoted 2 lines
printf("%d")expects an argument, so could it be that it touches random piece of memory and thus hangs?It had an argument, sorry for confusion. I was actually doing this:
the test with %s works, the one with %d kills it.I suspect too small stack...?
Does this happen in the SPL ? You can check the stack placement and utilization with BDI to verigy your hypothesis.
Quoted 8 lines
Quoted 5 lines
No, this is u-boot proper, and I'm chainloading it (see first mail) -- so unsupported configuration.
I'm preparing to flash the u-boot into the NOR, that should tell us if it is chainloading problem or not.
OK, since this email was in-reply-to SPL patch series, I got confused. Is it in any way related to this patchset then or not ?
No, it is not related to SPL series. Sorry for confusion.
Pavel
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[U-Boot] u-boot 2015.04 on socfpga was Re: printf("%d") breaks u-boot 2015.01+
In reply to Marek VasutHi!
Quoted 2 lines
Quoted 2 lines
In u-boot 2015.04-rc, as soon as execution hits
printf("%d"), it hangs. (Usually, that's after "DRAM: " message).
I tried on different board, and same hang. Does u-boot 2015.01+ work for you on socfpga? Do I need some kind of special configuration?
Thanks, Pavel
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[U-Boot] printf("%d") breaks u-boot 2015.01+
In reply to Pavel MachekHello Pavel,
Am 06.04.2015 16:40, schrieb Pavel Machek:
Quoted 18 lines
Hi!
In u-boot 2015.04-rc, as soon as execution hits
printf("%d"), it hangs. (Usually, that's after "DRAM: " message).Now, I have to admit I'm chainloading u-boot from
U-Boot 2013.01.01 (Mar 25 2015 - 15:57:21)
tftp
0x01000040.../u-boot.bin
Waiting for PHY auto negotiation to complete.. done ENET Speed is 100 Mbps - FULL duplex connection Using mii0 device
TFTP from server 10.0.0.6; our IP address is 10.0.0.99
...
Bytes transferred = 325004 (4f58c hex)# go 0x01000040
Quoted 7 lines
...but that worked well for 2014.10, (and is nearly mandatory in my config).
I'm using cross-compiler from eldk-5.6, but eldk-5.4 crosscompiler produces same behaviour, and both seem to work for 2014.10.
Any ideas?
Do you have caches on?
Try to disable "dcache off" before "go ..." ...
or ...
common/cmd_boot.c +1 -0
@@ -19,6 +19,7 @@ __attribute__((weak))unsigned long do_go_exec (ulong (*entry)(int ,char *const []),int argc,char *const argv[]) { +cleanup_before_linux ();return entry (argc, argv); }
maybe this helps? I just stepped into same problem on an am335x, but had not yet time to look deeper in it ...
bye,
Heiko
Signature · 2 lines
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
[U-Boot] printf("%d") breaks u-boot 2015.01+
Hi!
Quoted 19 lines
Quoted 19 lines
In u-boot 2015.04-rc, as soon as execution hits
printf("%d"), it hangs. (Usually, that's after "DRAM: " message).Now, I have to admit I'm chainloading u-boot from
U-Boot 2013.01.01 (Mar 25 2015 - 15:57:21)
tftp
0x01000040.../u-boot.bin
Waiting for PHY auto negotiation to complete.. done ENET Speed is 100 Mbps - FULL duplex connection Using mii0 device
TFTP from server 10.0.0.6; our IP address is 10.0.0.99
...
Bytes transferred = 325004 (4f58c hex)# go 0x01000040...but that worked well for 2014.10, (and is nearly mandatory in my config).
Quoted 7 lines
Quoted 4 lines
I'm using cross-compiler from eldk-5.6, but eldk-5.4 crosscompiler produces same behaviour, and both seem to work for 2014.10.
Any ideas?
Do you have caches on?
Try to disable "dcache off" before "go ..." ...
I tried, and did not get any change. I also tried to flash 2015.04-rc4 directly into NOR to be loaded from SPL (not chainloaded), and it fails the same way.
Quoted 2 lines
maybe this helps? I just stepped into same problem on an am335x, but had not yet time to look deeper in it ...
I did not try the cleanup_before_linux(), but "dcache off" should have same effect, right?
Thanks and best regards,
Pavel
Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
[U-Boot] printf("%d") breaks u-boot 2015.01+
Hello Pavel,
Am 07.04.2015 09:56, schrieb Pavel Machek:
Quoted 24 lines
Hi!
Quoted 22 lines
Quoted 22 lines
In u-boot 2015.04-rc, as soon as execution hits
printf("%d"), it hangs. (Usually, that's after "DRAM: " message).Now, I have to admit I'm chainloading u-boot from
U-Boot 2013.01.01 (Mar 25 2015 - 15:57:21)
tftp
0x01000040.../u-boot.bin
Waiting for PHY auto negotiation to complete.. done ENET Speed is 100 Mbps - FULL duplex connection Using mii0 device
TFTP from server 10.0.0.6; our IP address is 10.0.0.99
...
Bytes transferred = 325004 (4f58c hex)# go 0x01000040...but that worked well for 2014.10, (and is nearly mandatory in my config).
I'm using cross-compiler from eldk-5.6, but eldk-5.4 crosscompiler produces same behaviour, and both seem to work for 2014.10.
Quoted 8 lines
Quoted 4 lines
Quoted 1 line
Any ideas?
Do you have caches on?
Try to disable "dcache off" before "go ..." ...I tried, and did not get any change. I also tried to flash 2015.04-rc4 directly into NOR to be loaded from SPL (not chainloaded), and it fails the same way.
Ok.
Quoted 5 lines
Quoted 2 lines
maybe this helps? I just stepped into same problem on an am335x, but had not yet time to look deeper in it ...
I did not try the
cleanup_before_linux(), but "dcache off" should have same effect, right?
Hmm.. not exactly... cleanup_before_linux() does also disable the mmu.
bye,
Heiko
Signature · 2 lines
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
[U-Boot] printf("%d") breaks u-boot 2015.01+
Hi!
Quoted 7 lines
Quoted 5 lines
Quoted 2 lines
maybe this helps? I just stepped into same problem on an am335x, but had not yet time to look deeper in it ...
I did not try the
cleanup_before_linux(), but "dcache off" should have same effect, right?Hmm.. not exactly...
cleanup_before_linux()does also disable the mmu.
Seems like I found the reason. CONFIG_THUMB_BUILD was set, and that causes problems in put_dec_trunc() function (and elsewhere).
commit 1602a502985d42bafb58cc6862b469ac03a7d634
Author: Pavel <[email protected]> Date: Wed Apr 8 14:08:18 2015 +0200
Disable thumb build; it breaks put_dec_trunc() function on toolchain from eldk-5.6 and eldk-5.4, and some other place, too.
include/configs/socfpga_common.h +1 -1
@@ -11,7 +11,7 @@/* Virtual target or real hardware */ #undef CONFIG_SOCFPGA_VIRTUAL_TARGET -#define CONFIG_SYS_THUMB_BUILD +#undef CONFIG_SYS_THUMB_BUILD#define CONFIG_SOCFPGA
Signature · 2 lines
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[U-Boot] printf("%d") breaks u-boot 2015.01+
Quoted 27 lines · Pavel Machek
Hi!
Quoted 7 lines
Quoted 5 lines
Quoted 2 lines
maybe this helps? I just stepped into same problem on an am335x, but had not yet time to look deeper in it ...
I did not try the
cleanup_before_linux(), but "dcache off" should have same effect, right?Hmm.. not exactly...
cleanup_before_linux()does also disable the mmu.Seems like I found the reason.
CONFIG_THUMB_BUILDwas set, and that causes problems input_dec_trunc()function (and elsewhere).commit
1602a502985d42bafb58cc6862b469ac03a7d634Author: Pavel <[email protected]> Date: Wed Apr 8 14:08:18 2015 +0200Disable thumb build; it breaks
put_dec_trunc()function on toolchain from eldk-5.6 and eldk-5.4, and some other place, too.Signed-off-by Pavel Machek <[email protected]>(quoted diff) +0
-0
b/include/configs/socfpga_common.hindex 6d93472..6608d7d 100644
include/configs/socfpga_common.h line 16
Quoted 7 lines
include/configs/socfpga_common.h +1
-1@@ -11,7 +11,7 @@/* Virtual target or real hardware */ #undef CONFIG_SOCFPGA_VIRTUAL_TARGET -#define CONFIG_SYS_THUMB_BUILD +#undef CONFIG_SYS_THUMB_BUILD#define CONFIG_SOCFPGA
Disabling thumb build to paper over the problem is certainly not a solution, right? What is the root cause for those problems and how can we fix it in the right place ?
Best regards,
Marek Vasut
[U-Boot] printf("%d") breaks u-boot 2015.01+
Quoted 31 lines · Marek Vasut
Quoted 30 lines · Pavel Machek
Hi!
Quoted 7 lines
Quoted 5 lines
Quoted 2 lines
maybe this helps? I just stepped into same problem on an am335x, but had not yet time to look deeper in it ...
I did not try the
cleanup_before_linux(), but "dcache off" should have same effect, right?Hmm.. not exactly...
cleanup_before_linux()does also disable the mmu.Seems like I found the reason.
CONFIG_THUMB_BUILDwas set, and that causes problems input_dec_trunc()function (and elsewhere).commit
1602a502985d42bafb58cc6862b469ac03a7d634Author: Pavel <[email protected]> Date: Wed Apr 8 14:08:18 2015 +0200Disable thumb build; it breaks
put_dec_trunc()function on toolchain from eldk-5.6 and eldk-5.4, and some other place, too.Signed-off-by Pavel Machek <[email protected]>(quoted diff) +0
-0
b/include/configs/socfpga_common.hindex 6d93472..6608d7d 100644include/configs/socfpga_common.h +0
-0@@ -11,7 +11,7 @@/* Virtual target or real hardware */ #undef CONFIG_SOCFPGA_VIRTUAL_TARGET
Quoted 7 lines
include/configs/socfpga_common.h line 16
Quoted 4 lines
include/configs/socfpga_common.h +1
-1-#define CONFIG_SYS_THUMB_BUILD +#undef CONFIG_SYS_THUMB_BUILD#define CONFIG_SOCFPGA Disabling thumb build to paper over the problem is certainly not a solution, right?
Well. First questions first: does it work for you? What version and what compiler?
Quoted 2 lines
What is the root cause for those problems and
how can we fix it in the right place ?
If I knew what is the root cause, do you think I'd do this?
Pavel
Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
[U-Boot] "socfpga sdram_applycfg" in mainline u-boot
In reply to Marek VasutHi!
Is there equivalent of "socfpga sdram_applycfg" in mainline u-boot? If not, does anyone have a patch porting functionality forward? If not would it be ok to create "socfpga" command with sdram_applycfg subcommand, or would different interface be preffered?
Best regards,
Pavel
Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
[U-Boot] "socfpga sdram_applycfg" in mainline u-boot
Quoted 6 lines · Pavel Machek
Hi!
Is there equivalent of "socfpga
sdram_applycfg" in mainline u-boot? If not, does anyone have a patch porting functionality forward? If not would it be ok to create "socfpga" command withsdram_applycfgsubcommand, or would different interface be preffered?
Doesn't "bridge enable" do something along those lines ?
btw please DO FIX YOUR MAILER . It's the second time the email is in-reply-to some completely unrelated thread. This is really annoying.
Best regards,
Marek Vasut
[U-Boot] "socfpga sdram_applycfg" in mainline u-boot
Quoted 9 lines · Marek Vasut
Quoted 6 lines · Pavel Machek
Hi!
Is there equivalent of "socfpga
sdram_applycfg" in mainline u-boot? If not, does anyone have a patch porting functionality forward? If not would it be ok to create "socfpga" command withsdram_applycfgsubcommand, or would different interface be preffered?Doesn't "bridge enable" do something along those lines ?
Yes, "bridge enable" does replace this quite ugly jump into some U-boot code from the earlier U-Boot versions. It does work for me quite good.
Thanks,
Stefan
[U-Boot] printf("%d") breaks u-boot 2015.01+
In reply to Pavel MachekQuoted 27 lines · Pavel Machek
Hi!
Quoted 7 lines
Quoted 5 lines
Quoted 2 lines
maybe this helps? I just stepped into same problem on an am335x, but had not yet time to look deeper in it ...
I did not try the
cleanup_before_linux(), but "dcache off" should have same effect, right?Hmm.. not exactly...
cleanup_before_linux()does also disable the mmu.Seems like I found the reason.
CONFIG_THUMB_BUILDwas set, and that causes problems input_dec_trunc()function (and elsewhere).commit
1602a502985d42bafb58cc6862b469ac03a7d634Author: Pavel <[email protected]> Date: Wed Apr 8 14:08:18 2015 +0200Disable thumb build; it breaks
put_dec_trunc()function on toolchain from eldk-5.6 and eldk-5.4, and some other place, too.Signed-off-by Pavel Machek <[email protected]>include/configs/socfpga_common.h +0
-0
include/configs/socfpga_common.h line 16
Quoted 7 lines
include/configs/socfpga_common.h +1
-1@@ -11,7 +11,7 @@/* Virtual target or real hardware */ #undef CONFIG_SOCFPGA_VIRTUAL_TARGET -#define CONFIG_SYS_THUMB_BUILD +#undef CONFIG_SYS_THUMB_BUILD#define CONFIG_SOCFPGA
OK, this is kind of scary. What is wrong with those toolchains OR how we're telling them to build things as no, we should be able to use thumb mode just fine and need to for size reasons in various cases. If this is a generic problem then for example, omap4_panda + ELDK 5.4/5.6 just shouldn't work either and we _must_ use thumb there for at least SPL.
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[U-Boot] printf("%d") breaks u-boot 2015.01+
Quoted 31 lines · Tom Rini
Quoted 30 lines · Pavel Machek
Hi!
Quoted 7 lines
Quoted 5 lines
Quoted 2 lines
maybe this helps? I just stepped into same problem on an am335x, but had not yet time to look deeper in it ...
I did not try the
cleanup_before_linux(), but "dcache off" should have same effect, right?Hmm.. not exactly...
cleanup_before_linux()does also disable the mmu.Seems like I found the reason.
CONFIG_THUMB_BUILDwas set, and that causes problems input_dec_trunc()function (and elsewhere).commit
1602a502985d42bafb58cc6862b469ac03a7d634Author: Pavel <[email protected]> Date: Wed Apr 8 14:08:18 2015 +0200Disable thumb build; it breaks
put_dec_trunc()function on toolchain from eldk-5.6 and eldk-5.4, and some other place, too.Signed-off-by Pavel Machek <[email protected]>include/configs/socfpga_common.h +0
-0@@ -11,7 +11,7 @@/* Virtual target or real hardware */ #undef CONFIG_SOCFPGA_VIRTUAL_TARGET
Quoted 8 lines
include/configs/socfpga_common.h line 16
Quoted 4 lines
include/configs/socfpga_common.h +1
-1-#define CONFIG_SYS_THUMB_BUILD +#undef CONFIG_SYS_THUMB_BUILD#define CONFIG_SOCFPGA OK, this is kind of scary. What is wrong with those toolchains OR how we're telling them to build things as no, we should be able to use thumb mode just fine and need to for size reasons in various cases.
Well.. it is scary, as put_dec_trunc() is very straightforward function. It works in 2014.10, even with thumb on.
Quoted 3 lines
If this
is a generic problem then for example,omap4_panda+ ELDK 5.4/5.6 just shouldn't work either and we _must_ use thumb there for at least SPL.
I don't know enough about thumb in u-boot. And yes, I'd like people to confirm if u-boot works for them on socfpga...
Pavel
Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
[U-Boot] printf("%d") breaks u-boot 2015.01+
Quoted 44 lines · Pavel Machek
Quoted 31 lines · Tom Rini
Quoted 30 lines · Pavel Machek
Hi!
Quoted 7 lines
Quoted 5 lines
Quoted 2 lines
maybe this helps? I just stepped into same problem on an am335x, but had not yet time to look deeper in it ...
I did not try the
cleanup_before_linux(), but "dcache off" should have same effect, right?Hmm.. not exactly...
cleanup_before_linux()does also disable the mmu.Seems like I found the reason.
CONFIG_THUMB_BUILDwas set, and that causes problems input_dec_trunc()function (and elsewhere).commit
1602a502985d42bafb58cc6862b469ac03a7d634Author: Pavel <[email protected]> Date: Wed Apr 8 14:08:18 2015 +0200Disable thumb build; it breaks
put_dec_trunc()function on toolchain from eldk-5.6 and eldk-5.4, and some other place, too.Signed-off-by Pavel Machek <[email protected]>include/configs/socfpga_common.h +0
-0@@ -11,7 +11,7 @@/* Virtual target or real hardware */ #undef CONFIG_SOCFPGA_VIRTUAL_TARGETQuoted 8 lines
include/configs/socfpga_common.h line 16
Quoted 4 lines
include/configs/socfpga_common.h +1
-1-#define CONFIG_SYS_THUMB_BUILD +#undef CONFIG_SYS_THUMB_BUILD#define CONFIG_SOCFPGA OK, this is kind of scary. What is wrong with those toolchains OR how we're telling them to build things as no, we should be able to use thumb mode just fine and need to for size reasons in various cases.
Well.. it is scary, as
put_dec_trunc()is very straightforward function. It works in 2014.10, even with thumb on.
Quoted 6 lines
Quoted 3 lines
If this
is a generic problem then for example,omap4_panda+ ELDK 5.4/5.6 just shouldn't work either and we _must_ use thumb there for at least SPL.I don't know enough about thumb in u-boot. And yes, I'd like people to confirm if u-boot works for them on socfpga...
I'll fire up ELDK 5.4 + Pandaboard later today (which uses thumb) but I think you need to bisect down to when exactly things break since my gut is telling me it's not toolchain / thumb but something else that broke things.
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[U-Boot] printf("%d") breaks u-boot 2015.01+
Quoted 49 lines · Tom Rini
Quoted 48 lines · Pavel Machek
Quoted 31 lines · Tom Rini
Quoted 30 lines · Pavel Machek
Hi!
Quoted 7 lines
Quoted 5 lines
Quoted 2 lines
maybe this helps? I just stepped into same problem on an am335x, but had not yet time to look deeper in it ...
I did not try the
cleanup_before_linux(), but "dcache off" should have same effect, right?Hmm.. not exactly...
cleanup_before_linux()does also disable the mmu.Seems like I found the reason.
CONFIG_THUMB_BUILDwas set, and that causes problems input_dec_trunc()function (and elsewhere).commit
1602a502985d42bafb58cc6862b469ac03a7d634Author: Pavel <[email protected]> Date: Wed Apr 8 14:08:18 2015 +0200Disable thumb build; it breaks
put_dec_trunc()function on toolchain from eldk-5.6 and eldk-5.4, and some other place, too.Signed-off-by Pavel Machek <[email protected]>include/configs/socfpga_common.h +0
-0@@ -11,7 +11,7 @@/* Virtual target or real hardware */ #undef CONFIG_SOCFPGA_VIRTUAL_TARGETQuoted 8 lines
include/configs/socfpga_common.h line 16
Quoted 4 lines
include/configs/socfpga_common.h +1
-1-#define CONFIG_SYS_THUMB_BUILD +#undef CONFIG_SYS_THUMB_BUILD#define CONFIG_SOCFPGA OK, this is kind of scary. What is wrong with those toolchains OR how we're telling them to build things as no, we should be able to use thumb mode just fine and need to for size reasons in various cases.
Well.. it is scary, as
put_dec_trunc()is very straightforward function. It works in 2014.10, even with thumb on.Quoted 3 lines
If this
is a generic problem then for example,omap4_panda+ ELDK 5.4/5.6 just shouldn't work either and we _must_ use thumb there for at least SPL.
Quoted 7 lines
Quoted 2 lines
I don't know enough about thumb in u-boot. And yes, I'd like people to confirm if u-boot works for them on socfpga...
I'll fire up ELDK 5.4 + Pandaboard later today (which uses thumb) but I think you need to bisect down to when exactly things break since my gut is telling me it's not toolchain / thumb but something else that broke things.
Thanks.
Well, it broke between 2014.10 and 2015.01, so I think it should be toolchain (because broken socfpga for >4 months... someone would notice, no?).
Marek told me I should mention... I'm using USE_PRIVATE_LIBGCC because compilation does not work without that.
Best regards,
Pavel
Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
[U-Boot] printf("%d") breaks u-boot 2015.01+
Quoted 58 lines · Pavel Machek
Quoted 49 lines · Tom Rini
Quoted 48 lines · Pavel Machek
Quoted 31 lines · Tom Rini
Quoted 30 lines · Pavel Machek
Hi!
Quoted 7 lines
Quoted 5 lines
Quoted 2 lines
maybe this helps? I just stepped into same problem on an am335x, but had not yet time to look deeper in it ...
I did not try the
cleanup_before_linux(), but "dcache off" should have same effect, right?Hmm.. not exactly...
cleanup_before_linux()does also disable the mmu.Seems like I found the reason.
CONFIG_THUMB_BUILDwas set, and that causes problems input_dec_trunc()function (and elsewhere).commit
1602a502985d42bafb58cc6862b469ac03a7d634Author: Pavel <[email protected]> Date: Wed Apr 8 14:08:18 2015 +0200Disable thumb build; it breaks
put_dec_trunc()function on toolchain from eldk-5.6 and eldk-5.4, and some other place, too.Signed-off-by Pavel Machek <[email protected]>include/configs/socfpga_common.h +0
-0@@ -11,7 +11,7 @@/* Virtual target or real hardware */ #undef CONFIG_SOCFPGA_VIRTUAL_TARGETQuoted 8 lines
include/configs/socfpga_common.h line 16
Quoted 4 lines
include/configs/socfpga_common.h +1
-1-#define CONFIG_SYS_THUMB_BUILD +#undef CONFIG_SYS_THUMB_BUILD#define CONFIG_SOCFPGA OK, this is kind of scary. What is wrong with those toolchains OR how we're telling them to build things as no, we should be able to use thumb mode just fine and need to for size reasons in various cases.
Well.. it is scary, as
put_dec_trunc()is very straightforward function. It works in 2014.10, even with thumb on.Quoted 3 lines
If this
is a generic problem then for example,omap4_panda+ ELDK 5.4/5.6 just shouldn't work either and we _must_ use thumb there for at least SPL.Quoted 7 lines
Quoted 2 lines
I don't know enough about thumb in u-boot. And yes, I'd like people to confirm if u-boot works for them on socfpga...
I'll fire up ELDK 5.4 + Pandaboard later today (which uses thumb) but I think you need to bisect down to when exactly things break since my gut is telling me it's not toolchain / thumb but something else that broke things.
Quoted 8 lines
Thanks.
Well, it broke between 2014.10 and 2015.01, so I think it should be toolchain (because broken socfpga for >4 months... someone would notice, no?).
Marek told me I should mention... I'm using
USE_PRIVATE_LIBGCCbecause compilation does not work without that.
I think the answer is that it's bisect time.
Signature · 8 lines
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[U-Boot] printf("%d") breaks u-boot 2015.01+
In reply to Tom RiniQuoted 49 lines · Tom Rini
Quoted 48 lines · Pavel Machek
Quoted 31 lines · Tom Rini
Quoted 30 lines · Pavel Machek
Hi!
Quoted 7 lines
Quoted 5 lines
Quoted 2 lines
maybe this helps? I just stepped into same problem on an am335x, but had not yet time to look deeper in it ...
I did not try the
cleanup_before_linux(), but "dcache off" should have same effect, right?Hmm.. not exactly...
cleanup_before_linux()does also disable the mmu.Seems like I found the reason.
CONFIG_THUMB_BUILDwas set, and that causes problems input_dec_trunc()function (and elsewhere).commit
1602a502985d42bafb58cc6862b469ac03a7d634Author: Pavel <[email protected]> Date: Wed Apr 8 14:08:18 2015 +0200Disable thumb build; it breaks
put_dec_trunc()function on toolchain from eldk-5.6 and eldk-5.4, and some other place, too.Signed-off-by Pavel Machek <[email protected]>include/configs/socfpga_common.h +0
-0@@ -11,7 +11,7 @@/* Virtual target or real hardware */ #undef CONFIG_SOCFPGA_VIRTUAL_TARGETQuoted 8 lines
include/configs/socfpga_common.h line 16
Quoted 4 lines
include/configs/socfpga_common.h +1
-1-#define CONFIG_SYS_THUMB_BUILD +#undef CONFIG_SYS_THUMB_BUILD#define CONFIG_SOCFPGA OK, this is kind of scary. What is wrong with those toolchains OR how we're telling them to build things as no, we should be able to use thumb mode just fine and need to for size reasons in various cases.
Well.. it is scary, as
put_dec_trunc()is very straightforward function. It works in 2014.10, even with thumb on.Quoted 3 lines
If this
is a generic problem then for example,omap4_panda+ ELDK 5.4/5.6 just shouldn't work either and we _must_ use thumb there for at least SPL.
Quoted 7 lines
Quoted 2 lines
I don't know enough about thumb in u-boot. And yes, I'd like people to confirm if u-boot works for them on socfpga...
I'll fire up ELDK 5.4 + Pandaboard later today (which uses thumb) but I think you need to bisect down to when exactly things break since my gut is telling me it's not toolchain / thumb but something else that broke things.
Panda + ELDK 5.4, which sets CONFIG_SYS_THUMB_BUILD for both SPL and U-Boot boots up fine on top of tree, cold boot tested even.
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[U-Boot] printf("%d") breaks u-boot 2015.01+
Hi!
Quoted 7 lines
Quoted 4 lines
I'll fire up ELDK 5.4 + Pandaboard later today (which uses thumb) but I think you need to bisect down to when exactly things break since my gut is telling me it's not toolchain / thumb but something else that broke things.
Panda + ELDK 5.4, which sets
CONFIG_SYS_THUMB_BUILDfor both SPL and U-Boot boots up fine on top of tree, cold boot tested even.
Can you try with
CONFIG_USE_PRIVATE_LIBGCC=y
? Because it works for me, as long as I keepCONFIG_USE_PRIVATE_LIBGCC unset.
Unfortunately, I need CONFIG_USE_PRIVATE_LIBGCC for my development machine, otherwise I get compile failure.
It seems to me our private "library" would need special version for thumb mode, in similar way memcpy.S needs it, no?
I think fix needs to be something along these lines, but this does not work for me.
Pavel
arch/arm/lib/_ashldi3.S +5 -0
@@ -12,6 +12,11 @@ #define ah r1 #endif +#ifdef CONFIG_SYS_THUMB_BUILD + .thumb + .thumb_func +#endif + .globl __ashldi3 .globl __aeabi_llsl __ashldi3:
arch/arm/lib/_ashrdi3.S +5 -0
@@ -12,6 +12,11 @@ #define ah r1 #endif +#ifdef CONFIG_SYS_THUMB_BUILD + .thumb + .thumb_func +#endif + .globl __ashrdi3 .globl __aeabi_lasr __ashrdi3:
arch/arm/lib/_divsi3.S +4 -0
@@ -1,5 +1,9 @@ .macro ARM_DIV_BODY dividend, divisor, result, curbit +#ifdef CONFIG_SYS_THUMB_BUILD + .thumb + .thumb_func +#endif #if __LINUX_ARM_ARCH__ >= 5 clz \curbit, \divisor
arch/arm/lib/_lshrdi3.S +5 -0
@@ -12,6 +12,11 @@ #define ah r1 #endif +#ifdef CONFIG_SYS_THUMB_BUILD + .thumb + .thumb_func +#endif + .globl __lshrdi3 .globl __aeabi_llsr __lshrdi3:
arch/arm/lib/_modsi3.S +4 -0
@@ -1,4 +1,8 @@ .macro ARM_MOD_BODY dividend, divisor, order, spare +#ifdef CONFIG_SYS_THUMB_BUILD + .thumb + .thumb_func +#endif #if __LINUX_ARM_ARCH__ >= 5
arch/arm/lib/_umodsi3.S +4 -0
@@ -1,6 +1,10 @@ /* # 1 "libgcc1.S" */ @ libgcc1 routines for ARM cpu. @ Division routines, written by Richard Earnshaw, (rearnsha at armltd.co.uk) +#ifdef CONFIG_SYS_THUMB_BUILD + .thumb + .thumb_func +#endif /* # 145 "libgcc1.S" */ dividend .req r0 divisor .req r1
mkit +1 -0
@@ -12,3 +12,4 @@ nice make -j 3 u-boot.img u-boot-dtb.bin && \ # git diff 742de9076e8a8f44b77794b43e6175d86b897996 -- arch board common drivers include > ../wagabuibui.patch # scp ../wagabuibui.patch pavel at pollux.denx.de:~/wagabuibui/eldk/meta-eldk/recipes-bsp/uboot/u-boot/wagabuibui.patch +# scp pavel at pollux.denx.de:~/wagabuibui/u-boot/u-boot-dtb.bin /srv/tftp/wagabuibui/u-boot.bin
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(english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
PATCH 1/1 break build if it would produce broken binary
In reply to Tom RiniAdd an error in known-bad case so that we don't produce broken and hard to debug binaries.
arch/arm/include/asm/u-boot.h +4 -0
@@ -49,4 +49,8 @@ typedef struct bd_info {#define IH_ARCH_DEFAULT IH_ARCH_ARM64#endif +#if defined(CONFIG_USE_PRIVATE_LIBGCC ) && defined(CONFIG_SYS_THUMB_BUILD ) +#error Thumb build does not work with private libgcc. +#endif +#endif /* _U_BOOT_H_ */
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(english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
PATCH 1/1 break build if it would produce broken binary
Quoted 10 lines · Pavel Machek
Add an error in known-bad case so that we don't produce broken and hard to debug binaries.
Signed-off-by Pavel Machek <[email protected]>arch/arm/include/asm/u-boot.h +0
-0
arch/arm/include/asm/u-boot.h typedef struct bd_info { · line 56
Quoted 8 lines
arch/arm/include/asm/u-boot.h +4
-0@@ -49,4 +49,8 @@ typedef struct bd_info {#define IH_ARCH_DEFAULT IH_ARCH_ARM64#endif +#if defined(CONFIG_USE_PRIVATE_LIBGCC ) && defined(CONFIG_SYS_THUMB_BUILD ) +#error Thumb build does not work with private libgcc. +#endif +#endif /* _U_BOOT_H_ */
I'm agreeable to taking this for the release if you'll go and debug what's wrong with our private libgcc code for the next release.
Signature · 8 lines
Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 836 bytes Desc: Digital signature URL: <http://lists.denx.de/pipermail/u-boot/attachments/20150413/4217b71d/attachment.sig>
PATCH 1/1 break build if it would produce broken binary
Quoted 15 lines · Tom Rini
Quoted 13 lines · Pavel Machek
Add an error in known-bad case so that we don't produce broken and hard to debug binaries.
Signed-off-by Pavel Machek <[email protected]>arch/arm/include/asm/u-boot.h +0
-0@@ -49,4 +49,8 @@ typedef struct bd_info {#define IH_ARCH_DEFAULT IH_ARCH_ARM64#endif
Quoted 8 lines
arch/arm/include/asm/u-boot.h typedef struct bd_info { · line 56
Quoted 5 lines
arch/arm/include/asm/u-boot.h +4
-0+#if defined(CONFIG_USE_PRIVATE_LIBGCC ) && defined(CONFIG_SYS_THUMB_BUILD ) +#error Thumb build does not work with private libgcc. +#endif +#endif /* _U_BOOT_H_ */ I'm agreeable to taking this for the release if you'll go and debug what's wrong with our private libgcc code for the next release.
If you are willing to ship u-boot with known and nasty to debug problem, it is your choice.
Either the patch is good or it is bad, my future plans should have nothing to do with it. Notice that this patch does not help _me_ in any way, as I know about the issue and am unlikely to hit it again, and that original problem still breaks the build on my system.
Help from someone knowing ARM assembly would be nice. Now that we know what the problem is, it should not be too bad.
Best regards,
Pavel
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PATCH 1/1 break build if it would produce broken binary
Hi,
Quoted 29 lines · Pavel Machek
Quoted 15 lines · Tom Rini
Quoted 13 lines · Pavel Machek
Add an error in known-bad case so that we don't produce broken and hard to debug binaries.
Signed-off-by Pavel Machek <[email protected]>arch/arm/include/asm/u-boot.h +0
-0@@ -49,4 +49,8 @@ typedef struct bd_info {#define IH_ARCH_DEFAULT IH_ARCH_ARM64#endif Quoted 8 lines
arch/arm/include/asm/u-boot.h typedef struct bd_info { · line 56
Quoted 5 lines
arch/arm/include/asm/u-boot.h +4
-0+#if defined(CONFIG_USE_PRIVATE_LIBGCC ) && defined(CONFIG_SYS_THUMB_BUILD ) +#error Thumb build does not work with private libgcc. +#endif +#endif /* _U_BOOT_H_ */ I'm agreeable to taking this for the release if you'll go and debug what's wrong with our private libgcc code for the next release.
If you are willing to ship u-boot with known and nasty to debug problem, it is your choice.
Quoted 7 lines
Either the patch is good or it is bad, my future plans should have nothing to do with it. Notice that this patch does not help _me_ in any way, as I know about the issue and am unlikely to hit it again, and that original problem still breaks the build on my system.
Help from someone knowing ARM assembly would be nice. Now that we know what the problem is, it should not be too bad.
I hit this also and I think it has to do with missing ENTRY/ENDPROC macros. I sent a patch.
Pavel, your email seemed to me as a little sharp for the mailing list.
Quoted 3 lines
Best regards,
Pavel
Regards,
Simon
PATCH 1/1 break build if it would produce broken binary
Quoted 25 lines · Simon Glass
Hi,
Quoted 23 lines
Quoted 7 lines
Quoted 7 lines
index 43cc494..ae4c21b 100644
arch/arm/include/asm/u-boot.h +0
-0@@ -49,4 +49,8 @@ typedef struct bd_info {#define IH_ARCH_DEFAULT IH_ARCH_ARM64#endif Quoted 8 lines
arch/arm/include/asm/u-boot.h typedef struct bd_info { · line 56
Quoted 5 lines
arch/arm/include/asm/u-boot.h +4
-0+#if defined(CONFIG_USE_PRIVATE_LIBGCC ) && defined(CONFIG_SYS_THUMB_BUILD ) +#error Thumb build does not work with private libgcc. +#endif +#endif /* _U_BOOT_H_ */ I'm agreeable to taking this for the release if you'll go and debug what's wrong with our private libgcc code for the next release.
If you are willing to ship u-boot with known and nasty to debug problem, it is your choice.
Either the patch is good or it is bad, my future plans should have nothing to do with it. Notice that this patch does not help _me_ in any way, as I know about the issue and am unlikely to hit it again, and that original problem still breaks the build on my system.
...
Quoted 1 line
Pavel, your email seemed to me as a little sharp for the mailing list.
Well, I have to survive on the lkml, so I write sharp emails sometimes.
Sorry about that.
Pavel#
(not a typo)
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(english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
PATCH 1/1 break build if it would produce broken binary
Quoted 30 lines · Pavel Machek
Quoted 28 lines · Simon Glass
Hi,
Quoted 26 lines
Quoted 14 lines
Quoted 14 lines
index 43cc494..ae4c21b 100644
arch/arm/include/asm/u-boot.h +1
-0@@ -49,4 +49,8 @@ typedef struct bd_info {#define IH_ARCH_DEFAULT IH_ARCH_ARM64#endif +#if defined(CONFIG_USE_PRIVATE_LIBGCC) &&
defined(CONFIG_SYS_THUMB_BUILD)+#error Thumb build does not work with private libgcc.arch/arm/include/asm/u-boot.h +2
-0+#endif +Quoted 4 lines
Quoted 1 line
#endif /* _U_BOOT_H_ */
I'm agreeable to taking this for the release if you'll go and debug what's wrong with our private libgcc code for the next release.
If you are willing to ship u-boot with known and nasty to debug problem, it is your choice.
Either the patch is good or it is bad, my future plans should have nothing to do with it. Notice that this patch does not help _me_ in any way, as I know about the issue and am unlikely to hit it again, and that original problem still breaks the build on my system.
Quoted 5 lines
...
Quoted 1 line
Pavel, your email seemed to me as a little sharp for the mailing list.
Well, I have to survive on the lkml, so I write sharp emails sometimes.
Well, this is not LKML.
Best regards,
Marek Vasut