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Makefile: remove extra ifdef/endif of top Makefile

PATCH New Masahiro Yamada 3 participants 3 messages Apr 7, 2015 Kbuild

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#0 lore raw

PATCH v2 1/1 Makefile: remove extra ifdef/endif of top Makefile

The GNU make's origin function know undefined variable well, so the outer ifdef/endif conditional checking is unneeded.

From info make documentation, origin will return

`undefined'
if VARIABLE was never defined.
`command line'
if VARIABLE was defined on the command line.
...

Therefore, $(origin V) will get a value anyway, killing ifdef/endif is viable and safe.

Furthermore, I've checked the minimal requirements from the top Makefile is GNU make 3.81, and that version of GNU make has support of origin function well already, so now it's safe to kill the outer conditional checking, without upgrading the minimal requirements.

[ Commit description is borrowed from Linux Kernel
(commit b8b0618cf6fa) and adjusted for Buildroot ]

---

Changes in v2:
- Add more detailed explanation

 Makefile | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)
Makefile +2 -4
index d6426b3..9db52a8 100644
@@ -184,10 +184,8 @@ endif
 
 # To put more focus on warnings, be less verbose as default
 # Use 'make V=1' to see the full commands
-ifdef V
-  ifeq ("$(origin V)", "command line")
-    KBUILD_VERBOSE = $(V)
-  endif
+ifeq ("$(origin V)", "command line")
+  KBUILD_VERBOSE = $(V)
 endif
 ifndef KBUILD_VERBOSE
   KBUILD_VERBOSE = 0
Signature · 1 line
1.9.1
#1 lore raw

PATCH v2 1/1 Makefile: remove extra ifdef/endif of top Makefile

Masahiro, All,

On 2015-04-07 14:09 +0900, Masahiro Yamada spake thusly:

Quoted 19 lines

The GNU make's origin function know undefined variable well, so the outer ifdef/endif conditional checking is unneeded.

From info make documentation, origin will return

`undefined'
if VARIABLE was never defined.
`command line'
if VARIABLE was defined on the command line.
...

Therefore, $(origin V) will get a value anyway, killing ifdef/endif is viable and safe.

Furthermore, I've checked the minimal requirements from the top Makefile is GNU make 3.81, and that version of GNU make has support of origin function well already, so now it's safe to kill the outer conditional checking, without upgrading the minimal requirements.

Quoted 5 lines

[ Commit description is borrowed from Linux Kernel
(commit b8b0618cf6fa) and adjusted for Buildroot ]

Regards,
Yann E. MORIN.

Quoted 32 lines

---

Changes in v2:
- Add more detailed explanation

 Makefile | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)
Makefile +2 -4
index d6426b3..9db52a8 100644
@@ -184,10 +184,8 @@ endif
 
 # To put more focus on warnings, be less verbose as default
 # Use 'make V=1' to see the full commands
-ifdef V
-  ifeq ("$(origin V)", "command line")
-    KBUILD_VERBOSE = $(V)
-  endif
+ifeq ("$(origin V)", "command line")
+  KBUILD_VERBOSE = $(V)
 endif
 ifndef KBUILD_VERBOSE
   KBUILD_VERBOSE = 0
Signature · 6 lines
1.9.1

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#2 lore raw

PATCH v2 1/1 Makefile: remove extra ifdef/endif of top Makefile

In reply to Masahiro Yamada

Dear Masahiro Yamada,

Quoted 19 lines · Masahiro Yamada

The GNU make's origin function know undefined variable well, so the outer ifdef/endif conditional checking is unneeded.

From info make documentation, origin will return

`undefined'
if VARIABLE was never defined.
`command line'
if VARIABLE was defined on the command line.
...

Therefore, $(origin V) will get a value anyway, killing ifdef/endif is viable and safe.

Furthermore, I've checked the minimal requirements from the top Makefile is GNU make 3.81, and that version of GNU make has support of origin function well already, so now it's safe to kill the outer conditional checking, without upgrading the minimal requirements.

Quoted 5 lines

[ Commit description is borrowed from Linux Kernel
(commit b8b0618cf6fa) and adjusted for Buildroot ]

Applied, thanks!

Thomas

Signature · 3 lines
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com