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ARM: cpu: Add ARMv7 barrier operations support

PATCH New Vladimir Barinov 3 participants 4 messages Mar 20, 2015 – Aug 20, 2015 Arm (32-bit)

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Vladimir Barinov

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#0 lore raw

PATCH 1/1 ARM: cpu: Add ARMv7 barrier operations support

From: Valentine Barshak <[email protected]>

This enables ARMv7 barrier operations support when march=armv7-a is enabled.

Using CP15 barriers causes U-Boot bootm command crash when transferring control to the loaded image on Renesas R8A7794 Cortex A7 CPU. Using ARMv7 barrier operations instead of the deprecated CP15 barriers helps to avoid these issues.

Signed-off-by Valentine Barshak <[email protected]>
Signed-off-by Vladimir Barinov <[email protected]>
Reviewed-by Tom Rini <[email protected]>
---
 arch/arm/cpu/armv7/cache_v7.c | 14 +++++++-------
 arch/arm/include/asm/armv7.h  | 10 ++++++++++
 2 files changed, 17 insertions(+), 7 deletions(-)
arch/arm/cpu/armv7/cache_v7.c +7 -7
index 0f9d837..e8ee875 100644
@@ -68,7 +68,7 @@ static void v7_inval_dcache_level_setway(u32 level, u32 num_sets,
 		}
 	}
 	/* DSB to make sure the operation is complete */
-	CP15DSB;
+	DSB;
 }
 
 static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets,

@@ -96,7 +96,7 @@ static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets,
 		}
 	}
 	/* DSB to make sure the operation is complete */
-	CP15DSB;
+	DSB;
 }
 
 static void v7_maint_dcache_level_setway(u32 level, u32 operation)

@@ -215,7 +215,7 @@ static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op)
 	}
 
 	/* DSB to make sure the operation is complete */
-	CP15DSB;
+	DSB;
 }
 
 /* Invalidate TLB */

@@ -228,9 +228,9 @@ static void v7_inval_tlb(void)
 	/* Invalidate entire instruction TLB */
 	asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0));
 	/* Full system DSB - make sure that the invalidation is complete */
-	CP15DSB;
+	DSB;
 	/* Full system ISB - make sure the instruction stream sees it */
-	CP15ISB;
+	ISB;
 }
 
 void invalidate_dcache_all(void)

@@ -343,10 +343,10 @@ void invalidate_icache_all(void)
 	asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
 
 	/* Full system DSB - make sure that the invalidation is complete */
-	CP15DSB;
+	DSB;
 
 	/* ISB - make sure the instruction stream sees it */
-	CP15ISB;
+	ISB;
 }
 #else
 void invalidate_icache_all(void)
arch/arm/include/asm/armv7.h +10 -0
index a13da23..189f3f0 100644
@@ -70,6 +70,16 @@
 #define CP15DSB	asm volatile ("mcr     p15, 0, %0, c7, c10, 4" : : "r" (0))
 #define CP15DMB	asm volatile ("mcr     p15, 0, %0, c7, c10, 5" : : "r" (0))
 
+#ifdef __ARM_ARCH_7A__
+#define ISB	asm volatile ("isb" : : : "memory")
+#define DSB	asm volatile ("dsb" : : : "memory")
+#define DMB	asm volatile ("dmb" : : : "memory")
+#else
+#define ISB	CP15ISB
+#define DSB	CP15DSB
+#define DMB	CP15DMB
+#endif
+
 /*
  * Workaround for ARM errata # 798870
  * Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been
Signature · 1 line
1.9.3
#1 lore raw

PATCH 1/1 ARM: cpu: Add ARMv7 barrier operations support

Hi,

2015-03-21 0:16 GMT+09:00 Vladimir Barinov
<[email protected]>:

Quoted 5 lines

From: Valentine Barshak <[email protected]>

This enables ARMv7 barrier operations support when march=armv7-a is enabled.

Quoted 8 lines

Using CP15 barriers causes U-Boot bootm command crash when transferring control to the loaded image on Renesas R8A7794 Cortex A7 CPU. Using ARMv7 barrier operations instead of the deprecated CP15 barriers helps to avoid these issues.

Signed-off-by Valentine Barshak <[email protected]>
Signed-off-by Vladimir Barinov <[email protected]>
Reviewed-by Tom Rini <[email protected]>
Reviewed-by Nobuhiro Iwamatsu <[email protected]>

Best regards,
Nobuhiro

Quoted 89 lines
---
 arch/arm/cpu/armv7/cache_v7.c | 14 +++++++-------
 arch/arm/include/asm/armv7.h  | 10 ++++++++++
 2 files changed, 17 insertions(+), 7 deletions(-)
arch/arm/cpu/armv7/cache_v7.c +7 -7
index 0f9d837..e8ee875 100644
@@ -68,7 +68,7 @@ static void v7_inval_dcache_level_setway(u32 level, u32 num_sets,
                }
        }
        /* DSB to make sure the operation is complete */
-       CP15DSB;
+       DSB;
 }
 
 static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets,

@@ -96,7 +96,7 @@ static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets,
                }
        }
        /* DSB to make sure the operation is complete */
-       CP15DSB;
+       DSB;
 }
 
 static void v7_maint_dcache_level_setway(u32 level, u32 operation)

@@ -215,7 +215,7 @@ static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op)
        }
 
        /* DSB to make sure the operation is complete */
-       CP15DSB;
+       DSB;
 }
 
 /* Invalidate TLB */

@@ -228,9 +228,9 @@ static void v7_inval_tlb(void)
        /* Invalidate entire instruction TLB */
        asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0));
        /* Full system DSB - make sure that the invalidation is complete */
-       CP15DSB;
+       DSB;
        /* Full system ISB - make sure the instruction stream sees it */
-       CP15ISB;
+       ISB;
 }
 
 void invalidate_dcache_all(void)

@@ -343,10 +343,10 @@ void invalidate_icache_all(void)
        asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
 
        /* Full system DSB - make sure that the invalidation is complete */
-       CP15DSB;
+       DSB;
 
        /* ISB - make sure the instruction stream sees it */
-       CP15ISB;
+       ISB;
 }
 #else
 void invalidate_icache_all(void)
arch/arm/include/asm/armv7.h +10 -1
index a13da23..189f3f0 100644
@@ -70,6 +70,16 @@
 #define CP15DSB        asm volatile ("mcr     p15, 0, %0, c7, c10, 4" : : "r" (0))
 #define CP15DMB        asm volatile ("mcr     p15, 0, %0, c7, c10, 5" : : "r" (0))
 
+#ifdef __ARM_ARCH_7A__
+#define ISB    asm volatile ("isb" : : : "memory")
+#define DSB    asm volatile ("dsb" : : : "memory")
+#define DMB    asm volatile ("dmb" : : : "memory")
+#else
+#define ISB    CP15ISB
+#define DSB    CP15DSB
+#define DMB    CP15DMB
+#endif
+
 /*
  * Workaround for ARM errata # 798870
  * Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been
--

1.9.3

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Signature · 1 line
Nobuhiro Iwamatsu
#2 lore raw

PATCH 1/1 ARM: cpu: Add ARMv7 barrier operations support

In reply to Vladimir Barinov

Hello Vladimir,

Quoted 98 lines · Vladimir Barinov

From: Valentine Barshak <[email protected]>

This enables ARMv7 barrier operations support when march=armv7-a is enabled.

Using CP15 barriers causes U-Boot bootm command crash when transferring control to the loaded image on Renesas R8A7794 Cortex A7 CPU. Using ARMv7 barrier operations instead of the deprecated CP15 barriers helps to avoid these issues.

Signed-off-by Valentine Barshak <[email protected]>
Signed-off-by Vladimir Barinov <[email protected]>
Reviewed-by Tom Rini <[email protected]>
---
 arch/arm/cpu/armv7/cache_v7.c | 14 +++++++-------
 arch/arm/include/asm/armv7.h  | 10 ++++++++++
 2 files changed, 17 insertions(+), 7 deletions(-)
arch/arm/cpu/armv7/cache_v7.c +7 -7
index 0f9d837..e8ee875 100644
@@ -68,7 +68,7 @@ static void v7_inval_dcache_level_setway(u32 level, u32 num_sets,
 		}
 	}
 	/* DSB to make sure the operation is complete */
-	CP15DSB;
+	DSB;
 }
 
 static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets,

@@ -96,7 +96,7 @@ static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets,
 		}
 	}
 	/* DSB to make sure the operation is complete */
-	CP15DSB;
+	DSB;
 }
 
 static void v7_maint_dcache_level_setway(u32 level, u32 operation)

@@ -215,7 +215,7 @@ static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op)
 	}
 
 	/* DSB to make sure the operation is complete */
-	CP15DSB;
+	DSB;
 }
 
 /* Invalidate TLB */

@@ -228,9 +228,9 @@ static void v7_inval_tlb(void)
 	/* Invalidate entire instruction TLB */
 	asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0));
 	/* Full system DSB - make sure that the invalidation is complete */
-	CP15DSB;
+	DSB;
 	/* Full system ISB - make sure the instruction stream sees it */
-	CP15ISB;
+	ISB;
 }
 
 void invalidate_dcache_all(void)

@@ -343,10 +343,10 @@ void invalidate_icache_all(void)
 	asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
 
 	/* Full system DSB - make sure that the invalidation is complete */
-	CP15DSB;
+	DSB;
 
 	/* ISB - make sure the instruction stream sees it */
-	CP15ISB;
+	ISB;
 }
 #else
 void invalidate_icache_all(void)
arch/arm/include/asm/armv7.h +10 -0
index a13da23..189f3f0 100644
@@ -70,6 +70,16 @@
 #define CP15DSB	asm volatile ("mcr     p15, 0, %0, c7, c10, 4" : : "r" (0))
 #define CP15DMB	asm volatile ("mcr     p15, 0, %0, c7, c10, 5" : : "r" (0))
 
+#ifdef __ARM_ARCH_7A__
+#define ISB	asm volatile ("isb" : : : "memory")
+#define DSB	asm volatile ("dsb" : : : "memory")
+#define DMB	asm volatile ("dmb" : : : "memory")
+#else
+#define ISB	CP15ISB
+#define DSB	CP15DSB
+#define DMB	CP15DMB
+#endif
+
 /*
  * Workaround for ARM errata # 798870
  * Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been
Signature · 1 line
1.9.3

Applied to u-boot-arm/master, thanks!

Amicalement,

Signature · 1 line
Albert.
author
#3 lore raw

PATCH 1/1 ARM: cpu: Add ARMv7 barrier operations support

In reply to Vladimir Barinov

Hello Albert,

Could you provide any response on this patch.

TIA,
Vladimir

Quoted 95 lines · Vladimir Barinov

From: Valentine Barshak <[email protected]>

This enables ARMv7 barrier operations support when march=armv7-a is enabled.

Using CP15 barriers causes U-Boot bootm command crash when transferring control to the loaded image on Renesas R8A7794 Cortex A7 CPU. Using ARMv7 barrier operations instead of the deprecated CP15 barriers helps to avoid these issues.

Signed-off-by Valentine Barshak <[email protected]>
Signed-off-by Vladimir Barinov <[email protected]>
Reviewed-by Tom Rini <[email protected]>
---
  arch/arm/cpu/armv7/cache_v7.c | 14 +++++++-------
  arch/arm/include/asm/armv7.h  | 10 ++++++++++
  2 files changed, 17 insertions(+), 7 deletions(-)
arch/arm/cpu/armv7/cache_v7.c +7 -7
index 0f9d837..e8ee875 100644
@@ -68,7 +68,7 @@ static void v7_inval_dcache_level_setway(u32 level, u32 num_sets,
  		}
  	}
  	/* DSB to make sure the operation is complete */
-	CP15DSB;
+	DSB;
  }
 
  static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets,

@@ -96,7 +96,7 @@ static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets,
  		}
  	}
  	/* DSB to make sure the operation is complete */
-	CP15DSB;
+	DSB;
  }
 
  static void v7_maint_dcache_level_setway(u32 level, u32 operation)

@@ -215,7 +215,7 @@ static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op)
  	}
 
  	/* DSB to make sure the operation is complete */
-	CP15DSB;
+	DSB;
  }
 
  /* Invalidate TLB */

@@ -228,9 +228,9 @@ static void v7_inval_tlb(void)
  	/* Invalidate entire instruction TLB */
  	asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0));
  	/* Full system DSB - make sure that the invalidation is complete */
-	CP15DSB;
+	DSB;
  	/* Full system ISB - make sure the instruction stream sees it */
-	CP15ISB;
+	ISB;
  }
 
  void invalidate_dcache_all(void)

@@ -343,10 +343,10 @@ void invalidate_icache_all(void)
  	asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
 
  	/* Full system DSB - make sure that the invalidation is complete */
-	CP15DSB;
+	DSB;
 
  	/* ISB - make sure the instruction stream sees it */
-	CP15ISB;
+	ISB;
  }
  #else
  void invalidate_icache_all(void)
arch/arm/include/asm/armv7.h +10 -0
index a13da23..189f3f0 100644
@@ -70,6 +70,16 @@
  #define CP15DSB	asm volatile ("mcr     p15, 0, %0, c7, c10, 4" : : "r" (0))
  #define CP15DMB	asm volatile ("mcr     p15, 0, %0, c7, c10, 5" : : "r" (0))
 
+#ifdef __ARM_ARCH_7A__
+#define ISB	asm volatile ("isb" : : : "memory")
+#define DSB	asm volatile ("dsb" : : : "memory")
+#define DMB	asm volatile ("dmb" : : : "memory")
+#else
+#define ISB	CP15ISB
+#define DSB	CP15DSB
+#define DMB	CP15DMB
+#endif
+
  /*
   * Workaround for ARM errata # 798870
   * Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been