Add ARMv7M STM32F1 and STM3210E-EVAL board support

This series adds support for the STM32F1 SoC family and the STM3210E-EVAL board on top of the STM32F4 SoC family support [1].

Since this board has no DRAM the first patch fixes the build when CONFIG_NR_DRAM_BANKS is not set. A patch is also required to force the processor to stay in Thumb mode when 'go'ing to an application.

As the STM32F1 differs greatly from STM32F4 in flash and clock layout, there's a separate subdirectory for the STM32F1 family. The gpio and serial drivers are shared as these peripherals are mostly similar with only the pinmux bits being significantly different in the gpio driver.

The STM3210E-EVAL board is supported with 1MiB Flash and 96KiB of SRAM on the STM32F103ZGT6, USART1 for console, and four user LEDs.

[1] http://lists.denx.de/pipermail/u-boot/2015-March/206640.html

Matt Porter (6):
image: fix build when CONFIG_NR_DRAM_BANKS is disabled on ARM common/cmd_boot: keep ARM v7M in thumb mode during do_go_exec()
ARMv7M: add STM32F1 support
gpio: stm32: add stm32f1 support
serial: stm32: add stm32f1 support
board: add stm3210e-eval board support

 arch/arm/Kconfig                          |   5 +
 arch/arm/cpu/armv7m/Makefile              |   1 +
 arch/arm/cpu/armv7m/stm32f1/Makefile      |  13 ++
 arch/arm/cpu/armv7m/stm32f1/clock.c       | 195 ++++++++++++++++++++++++++++++
 arch/arm/cpu/armv7m/stm32f1/flash.c       | 179 +++++++++++++++++++++++++++
 arch/arm/cpu/armv7m/stm32f1/soc.c         |  35 ++++++
 arch/arm/cpu/armv7m/stm32f1/timer.c       | 120 ++++++++++++++++++
 arch/arm/include/asm/arch-stm32f1/gpio.h  | 117 ++++++++++++++++++
 arch/arm/include/asm/arch-stm32f1/stm32.h | 115 ++++++++++++++++++
 board/st/stm3210e-eval/Kconfig            |  19 +++
 board/st/stm3210e-eval/MAINTAINERS        |   5 +
 board/st/stm3210e-eval/Makefile           |  13 ++
 board/st/stm3210e-eval/stm3210e-eval.c    |  85 +++++++++++++
 common/cmd_boot.c                         |   4 +
 common/image.c                            |   2 +-
 configs/stm3210e-eval_defconfig           |   3 +
 drivers/gpio/stm32_gpio.c                 | 103 +++++++++++++++-
 drivers/serial/serial_stm32.c             |   7 ++
 include/configs/stm3210e-eval.h           | 117 ++++++++++++++++++
 include/flash.h                           |   1 +
 20 files changed, 1137 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/cpu/armv7m/stm32f1/Makefile
 create mode 100644 arch/arm/cpu/armv7m/stm32f1/clock.c
 create mode 100644 arch/arm/cpu/armv7m/stm32f1/flash.c
 create mode 100644 arch/arm/cpu/armv7m/stm32f1/soc.c
 create mode 100644 arch/arm/cpu/armv7m/stm32f1/timer.c
 create mode 100644 arch/arm/include/asm/arch-stm32f1/gpio.h
 create mode 100644 arch/arm/include/asm/arch-stm32f1/stm32.h
 create mode 100644 board/st/stm3210e-eval/Kconfig
 create mode 100644 board/st/stm3210e-eval/MAINTAINERS
 create mode 100644 board/st/stm3210e-eval/Makefile
 create mode 100644 board/st/stm3210e-eval/stm3210e-eval.c
 create mode 100644 configs/stm3210e-eval_defconfig
 create mode 100644 include/configs/stm3210e-eval.h

2.1.0

common/image.c currently implicitly depends on CONFIG_NR_DRAM_BANKS when CONFIG_ARM is enabled. Make this requirement explicit.

---
 common/image.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

index 162b682..73c24f5 100644
@@ -461,7 +461,7 @@ phys_size_t getenv_bootm_size(void)
 		tmp = 0;
 
 
-#if defined(CONFIG_ARM)
+#if defined(CONFIG_ARM) && defined(CONFIG_NR_DRAM_BANKS)
 	return gd->bd->bi_dram[0].size - tmp;
 #else
 	return gd->bd->bi_memsize - tmp;

2.1.0

Hello Matt,

I am not entirely fond of a symbol's existence conditioning some code which does not actually use the symbol. I do understand the dependency here -- that bi_dram[0] is meaningful only if CONFIG_NR_DRAM_BANKS is 1 or more -- but then, why does this code not depend on the value of the symbol? Makes me think the patch is not complete and the code should be fixed to depend on the value of CONFIG_NR_DRAM_BANKS.

Amicalement,

Albert.

The problem is that CONFIG_NR_DRAM_BANKS means both "I have DRAM" and "I have X number of DRAM banks". In turn include/asm-generic/u-boot.h will only say we have gd->bd->bi_dram if CONFIG_NR_DRAM_BANKS is set so we can only reference that field when it's also set. Otherwise we get a compile error about no such member.

There's a further argument (as I read and re-read getenv_bootm_size()) that getenv_bootm_clsize() should be cleaned-up / re-worked as it defaults to too large of a value (which is why stuff gets relocated "high" and then Linux doesn't see it and then people do initrd_high=0xffffffff and fdt_high=0xffffffff) but that's unrelated to this patch I think.

Tom
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On ARM v7M, the processor will return to ARM mode when executing a blx instruction with bit 0 of the address == 0. Always set it to 1 to stay in thumb mode.

---
 common/cmd_boot.c | 4 ++++
 1 file changed, 4 insertions(+)

index 8f2e070..20ce652 100644
@@ -38,6 +38,10 @@ static int do_go(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	 * pass address parameter as argv[0] (aka command name),
 	 * and all remaining args
 	 */
+#ifdef CONFIG_CPU_V7M
+	/* For ARM V7M, set bit zero to stay in Thumb mode */
+	addr++;
+#endif
 	rc = do_go_exec ((void *)addr, argc - 1, argv + 1);
 	if (rc != 0) rcode = 1;
 

2.1.0

2015-04-14 20:07 GMT+02:00 Matt Porter <[email protected]>:

I think addr |= 1 would be better - there is always a possibility that kernel image has the zero bit already set (this is the case in my own Buildroot build setup I am using for STM32F4 builds). Anyways - keeping this bit set should be the responsibility of kernel image build process so such machine specific quirk can be kept out of the common code.

/Kamil

I'd agree about |='ing in 1. But it's not a machine quirk, it's a requirement of the Cortex-M family that you not exit Thumb-mode (since it's Thumb-only) and given how we end up trying to jump to the address (here or in 'go' which Matt didn't post the patch for, but same logic) we can / will have problems if we don't do this. You can work around it for images we throw a header into but 'go' is where this gets really annoying.

Tom
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"|1" is indeed much better, I will update it for that implementation. Just to be clear, this patch *is* for the go command which is what I use to load my RTOS. Kamil's comment implies the bootm path which I don't touch at all since I don't even support it in this config (we're running full U-Boot from SRAM and the CMD_BOOTM support is quite large and not necessary for my application).

I understand the concern about cluttering up common code with this. An alternative is to force this knowledge on the user such that they need to "go 080203a9" to run a Thumb-2 application located at 0x080203a8. It's ugly, but could be documented. I'd rather see an address fixup function or similar approach if we want to avoid cluttering the common path with ifdefry.

-Matt
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Hello Matt,

This should be done for all targets which build with Thumb instruction set, not only ARMv7M, should it not?

Amicalement,

Albert.

No, because it's not a problem on CPUs where we can do Thumb or non-Thumb instructions, only on CPUs where we can _only_ do Thumb instructions (or the special subset of "other" instructions the core allows). On ARM v7M trying to do the blx in ARM mode isn't allowed and causes an abort (or some other exception, I forget which) to happen upon execution.

Tom
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Add ARMv7M STM32F1 support including clocks, timer, gpio, and flash.

---
 arch/arm/cpu/armv7m/Makefile              |   1 +
 arch/arm/cpu/armv7m/stm32f1/Makefile      |  13 ++
 arch/arm/cpu/armv7m/stm32f1/clock.c       | 195 ++++++++++++++++++++++++++++++
 arch/arm/cpu/armv7m/stm32f1/flash.c       | 179 +++++++++++++++++++++++++++
 arch/arm/cpu/armv7m/stm32f1/soc.c         |  35 ++++++
 arch/arm/cpu/armv7m/stm32f1/timer.c       | 120 ++++++++++++++++++
 arch/arm/include/asm/arch-stm32f1/gpio.h  | 117 ++++++++++++++++++
 arch/arm/include/asm/arch-stm32f1/stm32.h | 115 ++++++++++++++++++
 include/flash.h                           |   1 +
 9 files changed, 776 insertions(+)
 create mode 100644 arch/arm/cpu/armv7m/stm32f1/Makefile
 create mode 100644 arch/arm/cpu/armv7m/stm32f1/clock.c
 create mode 100644 arch/arm/cpu/armv7m/stm32f1/flash.c
 create mode 100644 arch/arm/cpu/armv7m/stm32f1/soc.c
 create mode 100644 arch/arm/cpu/armv7m/stm32f1/timer.c
 create mode 100644 arch/arm/include/asm/arch-stm32f1/gpio.h
 create mode 100644 arch/arm/include/asm/arch-stm32f1/stm32.h

index b662e03..93a1956 100644
@@ -8,4 +8,5 @@
 extra-y := start.o
 obj-y += cpu.o
 
+obj-$(CONFIG_STM32F1) += stm32f1/
 obj-$(CONFIG_STM32F4) += stm32f4/

new file mode 100644
index 0000000..7b43761
@@ -0,0 +1,13 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# (C) Copyright 2015
+# Kamil Lulko, <[email protected]>
+#
+# Copyright 2015 Konsulko Group, Matt Porter <[email protected]>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += soc.o clock.o timer.o flash.o

new file mode 100644
index 0000000..ecb1269
@@ -0,0 +1,35 @@
+/*
+ * (C) Copyright 2015
+ * Kamil Lulko, <[email protected]>
+ *
+ * Copyright 2015 Konsulko Group, Matt Porter <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/armv7m.h>
+#include <asm/arch/stm32.h>
+
+u32 get_cpu_rev(void)
+{
+	return 0;
+}
+
+int arch_cpu_init(void)
+{
+	configure_clocks();
+
+	/*
+	 * Configure the memory protection unit (MPU) to allow full access to
+	 * the whole 4GB address space.
+	 */
+	writel(0, &V7M_MPU->rnr);
+	writel(0, &V7M_MPU->rbar);
+	writel((V7M_MPU_RASR_AP_RW_RW | V7M_MPU_RASR_SIZE_4GB
+		| V7M_MPU_RASR_EN), &V7M_MPU->rasr);
+	writel(V7M_MPU_CTRL_ENABLE | V7M_MPU_CTRL_HFNMIENA, &V7M_MPU->ctrl);
+
+	return 0;
+}

index 48aa3a5..5754cf9 100644
@@ -460,6 +460,7 @@ extern flash_info_t *flash_get_info(ulong base);
 #define FLASH_S29GL128N 0x00F1		/* Spansion S29GL128N			*/
 
 #define FLASH_STM32F4	0x00F2		/* STM32F4 Embedded Flash */
+#define FLASH_STM32F1	0x00F3		/* STM32F1 Embedded Flash */
 
 #define FLASH_UNKNOWN	0xFFFF		/* unknown flash type			*/
 

2.1.0

Add support for the STM32F1 family to the STM32 gpio driver.

---
 drivers/gpio/stm32_gpio.c | 103 +++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 102 insertions(+), 1 deletion(-)

index d3497e9..9174414 100644
@@ -5,6 +5,8 @@
  * (C) Copyright 2015
  * Kamil Lulko, <[email protected]>
  *
+ * Copyright 2015 Konsulko Group, Matt Porter <[email protected]>
+ *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 

@@ -16,6 +18,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef STM32_F4
 #define STM32_GPIOA_BASE	(STM32_AHB1PERIPH_BASE + 0x0000)
 #define STM32_GPIOB_BASE	(STM32_AHB1PERIPH_BASE + 0x0400)
 #define STM32_GPIOC_BASE	(STM32_AHB1PERIPH_BASE + 0x0800)

@@ -90,6 +93,90 @@ int stm32_gpio_config(const struct stm32_gpio_dsc *dsc,
 out:
 	return rv;
 }
+#else
+#define STM32_GPIOA_BASE	(STM32_APB2PERIPH_BASE + 0x0800)
+#define STM32_GPIOB_BASE	(STM32_APB2PERIPH_BASE + 0x0C00)
+#define STM32_GPIOC_BASE	(STM32_APB2PERIPH_BASE + 0x1000)
+#define STM32_GPIOD_BASE	(STM32_APB2PERIPH_BASE + 0x1400)
+#define STM32_GPIOE_BASE	(STM32_APB2PERIPH_BASE + 0x1800)
+#define STM32_GPIOF_BASE	(STM32_APB2PERIPH_BASE + 0x1C00)
+#define STM32_GPIOG_BASE	(STM32_APB2PERIPH_BASE + 0x2000)
+
+static const unsigned long io_base[] = {
+	STM32_GPIOA_BASE, STM32_GPIOB_BASE, STM32_GPIOC_BASE,
+	STM32_GPIOD_BASE, STM32_GPIOE_BASE, STM32_GPIOF_BASE,
+	STM32_GPIOG_BASE
+};
+
+#define STM32_GPIO_CR_MODE_MASK		0x3
+#define STM32_GPIO_CR_MODE_SHIFT(p)	(p * 4)
+#define STM32_GPIO_CR_CNF_MASK		0x3
+#define STM32_GPIO_CR_CNF_SHIFT(p)	(p * 4 + 2)
+
+struct stm32_gpio_regs {
+	u32 crl;	/* GPIO port configuration low */
+	u32 crh;	/* GPIO port configuration high */
+	u32 idr;	/* GPIO port input data */
+	u32 odr;	/* GPIO port output data */
+	u32 bsrr;	/* GPIO port bit set/reset */
+	u32 brr;	/* GPIO port bit reset */
+	u32 lckr;	/* GPIO port configuration lock */
+};
+
+#define CHECK_DSC(x)	(!x || x->port > 6 || x->pin > 15)
+#define CHECK_CTL(x)	(!x || x->mode > 3 || x->icnf > 3 || x->ocnf > 3 || \
+			 x->pupd > 1)
+
+int stm32_gpio_config(const struct stm32_gpio_dsc *dsc,
+		const struct stm32_gpio_ctl *ctl)
+{
+	struct stm32_gpio_regs *gpio_regs;
+	u32 *cr;
+	int p, crp;
+	int rv;
+
+	if (CHECK_DSC(dsc)) {
+		rv = -EINVAL;
+		goto out;
+	}
+	if (CHECK_CTL(ctl)) {
+		rv = -EINVAL;
+		goto out;
+	}
+
+	p = dsc->pin;
+
+	gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port];
+
+	/* Enable clock for GPIO port */
+	setbits_le32(&STM32_RCC->apb2enr, 0x04 << dsc->port);
+
+	if (p < 8) {
+		cr = &gpio_regs->crl;
+		crp = p;
+	} else {
+		cr = &gpio_regs->crh;
+		crp = p - 8;
+	}
+
+	clrbits_le32(cr, 0x3 << STM32_GPIO_CR_MODE_SHIFT(crp));
+	setbits_le32(cr, ctl->mode << STM32_GPIO_CR_MODE_SHIFT(crp));
+
+	clrbits_le32(cr, 0x3 << STM32_GPIO_CR_CNF_SHIFT(crp));
+	/* Inputs set the optional pull up / pull down */
+	if (ctl->mode == STM32_GPIO_MODE_IN) {
+		setbits_le32(cr, ctl->icnf << STM32_GPIO_CR_CNF_SHIFT(crp));
+		clrbits_le32(&gpio_regs->odr, 0x1 << p);
+		setbits_le32(&gpio_regs->odr, ctl->pupd << p);
+	} else {
+		setbits_le32(cr, ctl->ocnf << STM32_GPIO_CR_CNF_SHIFT(crp));
+	}
+
+	rv = 0;
+out:
+	return rv;
+}
+#endif
 
 int stm32_gpout_set(const struct stm32_gpio_dsc *dsc, int state)
 {

@@ -148,10 +235,18 @@ int gpio_direction_input(unsigned gpio)
 
 	dsc.port = stm32_gpio_to_port(gpio);
 	dsc.pin = stm32_gpio_to_pin(gpio);
+#ifdef STM32_F4
 	ctl.af = STM32_GPIO_AF0;
 	ctl.mode = STM32_GPIO_MODE_IN;
+	ctl.otype = STM32_GPIO_OTYPE_PP;
 	ctl.pupd = STM32_GPIO_PUPD_NO;
 	ctl.speed = STM32_GPIO_SPEED_50M;
+#else
+	ctl.mode = STM32_GPIO_MODE_IN;
+	ctl.icnf = STM32_GPIO_ICNF_IN_FLT;
+	ctl.ocnf = STM32_GPIO_OCNF_GP_PP;	/* ignored for input */
+	ctl.pupd = STM32_GPIO_PUPD_UP;		/* ignored for floating */
+#endif
 
 	return stm32_gpio_config(&dsc, &ctl);
 }

@@ -164,11 +259,17 @@ int gpio_direction_output(unsigned gpio, int value)
 
 	dsc.port = stm32_gpio_to_port(gpio);
 	dsc.pin = stm32_gpio_to_pin(gpio);
+#ifdef STM32_F4
 	ctl.af = STM32_GPIO_AF0;
 	ctl.mode = STM32_GPIO_MODE_OUT;
-	ctl.otype = STM32_GPIO_OTYPE_PP;
 	ctl.pupd = STM32_GPIO_PUPD_NO;
 	ctl.speed = STM32_GPIO_SPEED_50M;
+#else
+	ctl.mode = STM32_GPIO_MODE_OUT_50M;
+	ctl.ocnf = STM32_GPIO_OCNF_GP_PP;
+	ctl.icnf = STM32_GPIO_ICNF_IN_FLT;	/* ignored for output */
+	ctl.pupd = STM32_GPIO_PUPD_UP;		/* ignored for output */
+#endif
 
 	res = stm32_gpio_config(&dsc, &ctl);
 	if (res < 0)

2.1.0

Add support for the STM32F1 famly to the STM32 serial driver.

---
 drivers/serial/serial_stm32.c | 7 +++++++
 1 file changed, 7 insertions(+)

index 3c80096..a0397e1 100644
@@ -2,6 +2,8 @@
  * (C) Copyright 2015
  * Kamil Lulko, <[email protected]>
  *
+ * Copyright 2015 Konsulko Group, Matt Porter <[email protected]>
+ *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 

@@ -10,8 +12,13 @@
 #include <serial.h>
 #include <asm/arch/stm32.h>
 
+#ifdef CONFIG_STM32F4
 #define STM32_USART1_BASE	(STM32_APB2PERIPH_BASE + 0x1000)
 #define RCC_APB2ENR_USART1EN	(1 << 4)
+#else
+#define STM32_USART1_BASE	(STM32_APB2PERIPH_BASE + 0x3800)
+#define RCC_APB2ENR_USART1EN	(1 << 14)
+#endif
 
 #define USART_BASE		STM32_USART1_BASE
 #define RCC_USART_ENABLE	RCC_APB2ENR_USART1EN

2.1.0

Add support for the STM32F1-based stm3210e-eval boards from ST. UART, Flash, GPIO, and LEDs are supported.

---
 arch/arm/Kconfig                       |   5 ++
 board/st/stm3210e-eval/Kconfig         |  19 ++++++
 board/st/stm3210e-eval/MAINTAINERS     |   5 ++
 board/st/stm3210e-eval/Makefile        |  13 ++++
 board/st/stm3210e-eval/stm3210e-eval.c |  85 ++++++++++++++++++++++++
 configs/stm3210e-eval_defconfig        |   3 +
 include/configs/stm3210e-eval.h        | 117 +++++++++++++++++++++++++++++++++
 7 files changed, 247 insertions(+)
 create mode 100644 board/st/stm3210e-eval/Kconfig
 create mode 100644 board/st/stm3210e-eval/MAINTAINERS
 create mode 100644 board/st/stm3210e-eval/Makefile
 create mode 100644 board/st/stm3210e-eval/stm3210e-eval.c
 create mode 100644 configs/stm3210e-eval_defconfig
 create mode 100644 include/configs/stm3210e-eval.h

index 4eb047c..bcf4e46 100644
@@ -731,6 +731,10 @@ config ARCH_UNIPHIER
 	select SPL
 	select OF_CONTROL
 
+config TARGET_STM3210E_EVAL
+	bool "Support STM3210E-EVAL board"
+	select CPU_V7M
+
 config TARGET_STM32F429_DISCOVERY
 	bool "Support STM32F429 Discovery"
 	select CPU_V7M

@@ -872,6 +876,7 @@ source "board/spear/spear600/Kconfig"
 source "board/spear/x600/Kconfig"
 source "board/st-ericsson/snowball/Kconfig"
 source "board/st-ericsson/u8500/Kconfig"
+source "board/st/stm3210e-eval/Kconfig"
 source "board/st/stm32f429-discovery/Kconfig"
 source "board/st/stv0991/Kconfig"
 source "board/sunxi/Kconfig"

new file mode 100644
index 0000000..49bc770
@@ -0,0 +1,19 @@
+if TARGET_STM3210E_EVAL
+
+config SYS_BOARD
+	string
+	default "stm3210e-eval"
+
+config SYS_VENDOR
+	string
+	default "st"
+
+config SYS_SOC
+	string
+	default "stm32f1"
+
+config SYS_CONFIG_NAME
+	string
+	default "stm3210e-eval"
+
+endif

new file mode 100644
index 0000000..0f9f31b
@@ -0,0 +1,5 @@
+M:	Matt Porter <[email protected]>
+S:	Maintained
+F:	board/st/stm3210e-eval/
+F:	include/configs/stm3210e-eval.h
+F:	configs/stm3210e-eval_defconfig

new file mode 100644
index 0000000..b018e08
@@ -0,0 +1,13 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# (C) Copyright 2015
+# Kamil Lulko, <[email protected]>
+#
+# Copyright 2015 Konsulko Group, Matt Porter <[email protected]>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= stm3210e-eval.o

new file mode 100644
index 0000000..ac3cad3
@@ -0,0 +1,3 @@
+CONFIG_ARM=y
+CONFIG_TARGET_STM3210E_EVAL=y
+CONFIG_CMD_BOOTM=n

2.1.0