Add Freescale i.mx7d support
Subsystems (9)
v2 cover Add Freescale i.mx7d support
From: Frank Li <[email protected]>
add basic support for chip imx7d.
- MSL
- Clock support. All clock enabled.
- pinctrl support
- SD Card support
Change from V1 to V2:
- split patch1 to three small one to avoid 100k maillist limitation.
- fix imx7d.dtsi code style problem
Anson Huang (1):
ARM: imx: add msl support for imx7d
Frank Li (8):
ARM: dts: add pinfunc include file to support imx7d
ARM: dts: add clock include file to support imx7d
ARM: dts: add imx7d soc dtsi file
pinctrl: add imx7d support
ARM: imx: add gpt system timer support for imx7d
ARM: imx: add imx7d clk tree support
arm: dts: add imx7d-sdb support
ARM: config: imx_v6_v7_defconfig add imx7d support
arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/imx7d-pinfunc.h | 1153 +++++++++++++++++++++++++++++ arch/arm/boot/dts/imx7d-sdb.dts | 723 ++++++++++++++++++ arch/arm/boot/dts/imx7d.dtsi | 1091 +++++++++++++++++++++++++++ arch/arm/configs/imx_v6_v7_defconfig | 1 + arch/arm/mach-imx/Kconfig | 11 + arch/arm/mach-imx/Makefile | 1 + arch/arm/mach-imx/anatop.c | 33 +- arch/arm/mach-imx/clk-imx7d.c | 885 ++++++++++++++++++++++ arch/arm/mach-imx/clk-pllv3.c | 17 +- arch/arm/mach-imx/clk.h | 8 + arch/arm/mach-imx/common.h | 1 + arch/arm/mach-imx/cpu.c | 10 + arch/arm/mach-imx/hardware.h | 7 +- arch/arm/mach-imx/mach-imx7d.c | 53 ++ arch/arm/mach-imx/mx7.h | 38 + arch/arm/mach-imx/mxc.h | 15 +- arch/arm/mach-imx/platsmp.c | 24 +- arch/arm/mach-imx/time.c | 3 +- drivers/pinctrl/freescale/Kconfig | 7 + drivers/pinctrl/freescale/Makefile | 1 + drivers/pinctrl/freescale/pinctrl-imx.c | 3 +- drivers/pinctrl/freescale/pinctrl-imx.h | 1 + drivers/pinctrl/freescale/pinctrl-imx7d.c | 411 ++++++++++ include/dt-bindings/clock/imx7d-clock.h | 450 +++++++++++ 25 files changed, 4941 insertions(+), 8 deletions(-) create mode 100644 arch/arm/boot/dts/imx7d-pinfunc.h create mode 100644 arch/arm/boot/dts/imx7d-sdb.dts create mode 100644 arch/arm/boot/dts/imx7d.dtsi create mode 100644 arch/arm/mach-imx/clk-imx7d.c create mode 100644 arch/arm/mach-imx/mach-imx7d.c create mode 100644 arch/arm/mach-imx/mx7.h create mode 100644 drivers/pinctrl/freescale/pinctrl-imx7d.c create mode 100644 include/dt-bindings/clock/imx7d-clock.h
Signature · 1 line
1.9.1
PATCH v2 2/9 ARM: dts: add clock include file to support imx7d
From: Frank Li <[email protected]>
Add i.MX7D support:
clock define part.
Signed-off-by Frank Li <[email protected]>
--- include/dt-bindings/clock/imx7d-clock.h | 450 ++++++++++++++++++++++++++++++++ 1 file changed, 450 insertions(+) create mode 100644 include/dt-bindings/clock/imx7d-clock.h
include/dt-bindings/clock/imx7d-clock.h new file +450 -0
@@ -0,0 +1,450 @@ +/* +* Copyright (C) 2014-2015 Freescale Semiconductor, Inc. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +*/ + +#ifndef __DT_BINDINGS_CLOCK_IMX7D_H +#define __DT_BINDINGS_CLOCK_IMX7D_H + +#define IMX7D_OSC_24M_CLK 0 +#define IMX7D_PLL_ARM_MAIN 1 +#define IMX7D_PLL_ARM_MAIN_CLK 2 +#define IMX7D_PLL_ARM_MAIN_SRC 3 +#define IMX7D_PLL_ARM_MAIN_BYPASS 4 +#define IMX7D_PLL_SYS_MAIN 5 +#define IMX7D_PLL_SYS_MAIN_CLK 6 +#define IMX7D_PLL_SYS_MAIN_SRC 7 +#define IMX7D_PLL_SYS_MAIN_BYPASS 8 +#define IMX7D_PLL_SYS_MAIN_480M 9 +#define IMX7D_PLL_SYS_MAIN_240M 10 +#define IMX7D_PLL_SYS_MAIN_120M 11 +#define IMX7D_PLL_SYS_MAIN_480M_CLK 12 +#define IMX7D_PLL_SYS_MAIN_240M_CLK 13 +#define IMX7D_PLL_SYS_MAIN_120M_CLK 14 +#define IMX7D_PLL_SYS_PFD0_392M_CLK 15 +#define IMX7D_PLL_SYS_PFD0_196M 16 +#define IMX7D_PLL_SYS_PFD0_196M_CLK 17 +#define IMX7D_PLL_SYS_PFD1_332M_CLK 18 +#define IMX7D_PLL_SYS_PFD1_166M 19 +#define IMX7D_PLL_SYS_PFD1_166M_CLK 20 +#define IMX7D_PLL_SYS_PFD2_270M_CLK 21 +#define IMX7D_PLL_SYS_PFD2_135M 22 +#define IMX7D_PLL_SYS_PFD2_135M_CLK 23 +#define IMX7D_PLL_SYS_PFD3_CLK 24 +#define IMX7D_PLL_SYS_PFD4_CLK 25 +#define IMX7D_PLL_SYS_PFD5_CLK 26 +#define IMX7D_PLL_SYS_PFD6_CLK 27 +#define IMX7D_PLL_SYS_PFD7_CLK 28 +#define IMX7D_PLL_ENET_MAIN 29 +#define IMX7D_PLL_ENET_MAIN_CLK 30 +#define IMX7D_PLL_ENET_MAIN_SRC 31 +#define IMX7D_PLL_ENET_MAIN_BYPASS 32 +#define IMX7D_PLL_ENET_MAIN_500M 33 +#define IMX7D_PLL_ENET_MAIN_250M 34 +#define IMX7D_PLL_ENET_MAIN_125M 35 +#define IMX7D_PLL_ENET_MAIN_100M 36 +#define IMX7D_PLL_ENET_MAIN_50M 37 +#define IMX7D_PLL_ENET_MAIN_40M 38 +#define IMX7D_PLL_ENET_MAIN_25M 39 +#define IMX7D_PLL_ENET_MAIN_500M_CLK 40 +#define IMX7D_PLL_ENET_MAIN_250M_CLK 41 +#define IMX7D_PLL_ENET_MAIN_125M_CLK 42 +#define IMX7D_PLL_ENET_MAIN_100M_CLK 43 +#define IMX7D_PLL_ENET_MAIN_50M_CLK 44 +#define IMX7D_PLL_ENET_MAIN_40M_CLK 45 +#define IMX7D_PLL_ENET_MAIN_25M_CLK 46 +#define IMX7D_PLL_DRAM_MAIN 47 +#define IMX7D_PLL_DRAM_MAIN_CLK 48 +#define IMX7D_PLL_DRAM_MAIN_SRC 49 +#define IMX7D_PLL_DRAM_MAIN_BYPASS 50 +#define IMX7D_PLL_DRAM_MAIN_533M 51 +#define IMX7D_PLL_DRAM_MAIN_533M_CLK 52 +#define IMX7D_PLL_AUDIO_MAIN 53 +#define IMX7D_PLL_AUDIO_MAIN_CLK 54 +#define IMX7D_PLL_AUDIO_MAIN_SRC 55 +#define IMX7D_PLL_AUDIO_MAIN_BYPASS 56 +#define IMX7D_PLL_VIDEO_MAIN_CLK 57 +#define IMX7D_PLL_VIDEO_MAIN 58 +#define IMX7D_PLL_VIDEO_MAIN_SRC 59 +#define IMX7D_PLL_VIDEO_MAIN_BYPASS 60 +#define IMX7D_USB_MAIN_480M_CLK 61 +#define IMX7D_ARM_A7_ROOT_CLK 62 +#define IMX7D_ARM_A7_ROOT_SRC 63 +#define IMX7D_ARM_A7_ROOT_CG 64 +#define IMX7D_ARM_A7_ROOT_DIV 65 +#define IMX7D_ARM_M4_ROOT_CLK 66 +#define IMX7D_ARM_M4_ROOT_SRC 67 +#define IMX7D_ARM_M4_ROOT_CG 68 +#define IMX7D_ARM_M4_ROOT_DIV 69 +#define IMX7D_ARM_M0_ROOT_CLK 70 +#define IMX7D_ARM_M0_ROOT_SRC 71 +#define IMX7D_ARM_M0_ROOT_CG 72 +#define IMX7D_ARM_M0_ROOT_DIV 73 +#define IMX7D_MAIN_AXI_ROOT_CLK 74 +#define IMX7D_MAIN_AXI_ROOT_SRC 75 +#define IMX7D_MAIN_AXI_ROOT_CG 76 +#define IMX7D_MAIN_AXI_ROOT_DIV 77 +#define IMX7D_DISP_AXI_ROOT_CLK 78 +#define IMX7D_DISP_AXI_ROOT_SRC 79 +#define IMX7D_DISP_AXI_ROOT_CG 80 +#define IMX7D_DISP_AXI_ROOT_DIV 81 +#define IMX7D_ENET_AXI_ROOT_CLK 82 +#define IMX7D_ENET_AXI_ROOT_SRC 83 +#define IMX7D_ENET_AXI_ROOT_CG 84 +#define IMX7D_ENET_AXI_ROOT_DIV 85 +#define IMX7D_NAND_USDHC_BUS_ROOT_CLK 86 +#define IMX7D_NAND_USDHC_BUS_ROOT_SRC 87 +#define IMX7D_NAND_USDHC_BUS_ROOT_CG 88 +#define IMX7D_NAND_USDHC_BUS_ROOT_DIV 89 +#define IMX7D_AHB_CHANNEL_ROOT_CLK 90 +#define IMX7D_AHB_CHANNEL_ROOT_SRC 91 +#define IMX7D_AHB_CHANNEL_ROOT_CG 92 +#define IMX7D_AHB_CHANNEL_ROOT_DIV 93 +#define IMX7D_DRAM_PHYM_ROOT_CLK 94 +#define IMX7D_DRAM_PHYM_ROOT_SRC 95 +#define IMX7D_DRAM_PHYM_ROOT_CG 96 +#define IMX7D_DRAM_PHYM_ROOT_DIV 97 +#define IMX7D_DRAM_ROOT_CLK 98 +#define IMX7D_DRAM_ROOT_SRC 99 +#define IMX7D_DRAM_ROOT_CG 100 +#define IMX7D_DRAM_ROOT_DIV 101 +#define IMX7D_DRAM_PHYM_ALT_ROOT_CLK 102 +#define IMX7D_DRAM_PHYM_ALT_ROOT_SRC 103 +#define IMX7D_DRAM_PHYM_ALT_ROOT_CG 104 +#define IMX7D_DRAM_PHYM_ALT_ROOT_DIV 105 +#define IMX7D_DRAM_ALT_ROOT_CLK 106 +#define IMX7D_DRAM_ALT_ROOT_SRC 107 +#define IMX7D_DRAM_ALT_ROOT_CG 108 +#define IMX7D_DRAM_ALT_ROOT_DIV 109 +#define IMX7D_USB_HSIC_ROOT_CLK 110 +#define IMX7D_USB_HSIC_ROOT_SRC 111 +#define IMX7D_USB_HSIC_ROOT_CG 112 +#define IMX7D_USB_HSIC_ROOT_DIV 113 +#define IMX7D_PCIE_CTRL_ROOT_CLK 114 +#define IMX7D_PCIE_CTRL_ROOT_SRC 115 +#define IMX7D_PCIE_CTRL_ROOT_CG 116 +#define IMX7D_PCIE_CTRL_ROOT_DIV 117 +#define IMX7D_PCIE_PHY_ROOT_CLK 118 +#define IMX7D_PCIE_PHY_ROOT_SRC 119 +#define IMX7D_PCIE_PHY_ROOT_CG 120 +#define IMX7D_PCIE_PHY_ROOT_DIV 121 +#define IMX7D_EPDC_PIXEL_ROOT_CLK 122 +#define IMX7D_EPDC_PIXEL_ROOT_SRC 123 +#define IMX7D_EPDC_PIXEL_ROOT_CG 124 +#define IMX7D_EPDC_PIXEL_ROOT_DIV 125 +#define IMX7D_LCDIF_PIXEL_ROOT_CLK 126 +#define IMX7D_LCDIF_PIXEL_ROOT_SRC 127 +#define IMX7D_LCDIF_PIXEL_ROOT_CG 128 +#define IMX7D_LCDIF_PIXEL_ROOT_DIV 129 +#define IMX7D_MIPI_DSI_ROOT_CLK 130 +#define IMX7D_MIPI_DSI_ROOT_SRC 131 +#define IMX7D_MIPI_DSI_ROOT_CG 132 +#define IMX7D_MIPI_DSI_ROOT_DIV 133 +#define IMX7D_MIPI_CSI_ROOT_CLK 134 +#define IMX7D_MIPI_CSI_ROOT_SRC 135 +#define IMX7D_MIPI_CSI_ROOT_CG 136 +#define IMX7D_MIPI_CSI_ROOT_DIV 137 +#define IMX7D_MIPI_DPHY_ROOT_CLK 138 +#define IMX7D_MIPI_DPHY_ROOT_SRC 139 +#define IMX7D_MIPI_DPHY_ROOT_CG 140 +#define IMX7D_MIPI_DPHY_ROOT_DIV 141 +#define IMX7D_SAI1_ROOT_CLK 142 +#define IMX7D_SAI1_ROOT_SRC 143 +#define IMX7D_SAI1_ROOT_CG 144 +#define IMX7D_SAI1_ROOT_DIV 145 +#define IMX7D_SAI2_ROOT_CLK 146 +#define IMX7D_SAI2_ROOT_SRC 147 +#define IMX7D_SAI2_ROOT_CG 148 +#define IMX7D_SAI2_ROOT_DIV 149 +#define IMX7D_SAI3_ROOT_CLK 150 +#define IMX7D_SAI3_ROOT_SRC 151 +#define IMX7D_SAI3_ROOT_CG 152 +#define IMX7D_SAI3_ROOT_DIV 153 +#define IMX7D_SPDIF_ROOT_CLK 154 +#define IMX7D_SPDIF_ROOT_SRC 155 +#define IMX7D_SPDIF_ROOT_CG 156 +#define IMX7D_SPDIF_ROOT_DIV 157 +#define IMX7D_ENET1_REF_ROOT_CLK 158 +#define IMX7D_ENET1_REF_ROOT_SRC 159 +#define IMX7D_ENET1_REF_ROOT_CG 160 +#define IMX7D_ENET1_REF_ROOT_DIV 161 +#define IMX7D_ENET1_TIME_ROOT_CLK 162 +#define IMX7D_ENET1_TIME_ROOT_SRC 163 +#define IMX7D_ENET1_TIME_ROOT_CG 164 +#define IMX7D_ENET1_TIME_ROOT_DIV 165 +#define IMX7D_ENET2_REF_ROOT_CLK 166 +#define IMX7D_ENET2_REF_ROOT_SRC 167 +#define IMX7D_ENET2_REF_ROOT_CG 168 +#define IMX7D_ENET2_REF_ROOT_DIV 169 +#define IMX7D_ENET2_TIME_ROOT_CLK 170 +#define IMX7D_ENET2_TIME_ROOT_SRC 171 +#define IMX7D_ENET2_TIME_ROOT_CG 172 +#define IMX7D_ENET2_TIME_ROOT_DIV 173 +#define IMX7D_ENET_PHY_REF_ROOT_CLK 174 +#define IMX7D_ENET_PHY_REF_ROOT_SRC 175 +#define IMX7D_ENET_PHY_REF_ROOT_CG 176 +#define IMX7D_ENET_PHY_REF_ROOT_DIV 177 +#define IMX7D_EIM_ROOT_CLK 178 +#define IMX7D_EIM_ROOT_SRC 179 +#define IMX7D_EIM_ROOT_CG 180 +#define IMX7D_EIM_ROOT_DIV 181 +#define IMX7D_NAND_ROOT_CLK 182 +#define IMX7D_NAND_ROOT_SRC 183 +#define IMX7D_NAND_ROOT_CG 184 +#define IMX7D_NAND_ROOT_DIV 185 +#define IMX7D_QSPI_ROOT_CLK 186 +#define IMX7D_QSPI_ROOT_SRC 187 +#define IMX7D_QSPI_ROOT_CG 188 +#define IMX7D_QSPI_ROOT_DIV 189 +#define IMX7D_USDHC1_ROOT_CLK 190 +#define IMX7D_USDHC1_ROOT_SRC 191 +#define IMX7D_USDHC1_ROOT_CG 192 +#define IMX7D_USDHC1_ROOT_DIV 193 +#define IMX7D_USDHC2_ROOT_CLK 194 +#define IMX7D_USDHC2_ROOT_SRC 195 +#define IMX7D_USDHC2_ROOT_CG 196 +#define IMX7D_USDHC2_ROOT_DIV 197 +#define IMX7D_USDHC3_ROOT_CLK 198 +#define IMX7D_USDHC3_ROOT_SRC 199 +#define IMX7D_USDHC3_ROOT_CG 200 +#define IMX7D_USDHC3_ROOT_DIV 201 +#define IMX7D_CAN1_ROOT_CLK 202 +#define IMX7D_CAN1_ROOT_SRC 203 +#define IMX7D_CAN1_ROOT_CG 204 +#define IMX7D_CAN1_ROOT_DIV 205 +#define IMX7D_CAN2_ROOT_CLK 206 +#define IMX7D_CAN2_ROOT_SRC 207 +#define IMX7D_CAN2_ROOT_CG 208 +#define IMX7D_CAN2_ROOT_DIV 209 +#define IMX7D_I2C1_ROOT_CLK 210 +#define IMX7D_I2C1_ROOT_SRC 211 +#define IMX7D_I2C1_ROOT_CG 212 +#define IMX7D_I2C1_ROOT_DIV 213 +#define IMX7D_I2C2_ROOT_CLK 214 +#define IMX7D_I2C2_ROOT_SRC 215 +#define IMX7D_I2C2_ROOT_CG 216 +#define IMX7D_I2C2_ROOT_DIV 217 +#define IMX7D_I2C3_ROOT_CLK 218 +#define IMX7D_I2C3_ROOT_SRC 219 +#define IMX7D_I2C3_ROOT_CG 220 +#define IMX7D_I2C3_ROOT_DIV 221 +#define IMX7D_I2C4_ROOT_CLK 222 +#define IMX7D_I2C4_ROOT_SRC 223 +#define IMX7D_I2C4_ROOT_CG 224 +#define IMX7D_I2C4_ROOT_DIV 225 +#define IMX7D_UART1_ROOT_CLK 226 +#define IMX7D_UART1_ROOT_SRC 227 +#define IMX7D_UART1_ROOT_CG 228 +#define IMX7D_UART1_ROOT_DIV 229 +#define IMX7D_UART2_ROOT_CLK 230 +#define IMX7D_UART2_ROOT_SRC 231 +#define IMX7D_UART2_ROOT_CG 232 +#define IMX7D_UART2_ROOT_DIV 233 +#define IMX7D_UART3_ROOT_CLK 234 +#define IMX7D_UART3_ROOT_SRC 235 +#define IMX7D_UART3_ROOT_CG 236 +#define IMX7D_UART3_ROOT_DIV 237 +#define IMX7D_UART4_ROOT_CLK 238 +#define IMX7D_UART4_ROOT_SRC 239 +#define IMX7D_UART4_ROOT_CG 240 +#define IMX7D_UART4_ROOT_DIV 241 +#define IMX7D_UART5_ROOT_CLK 242 +#define IMX7D_UART5_ROOT_SRC 243 +#define IMX7D_UART5_ROOT_CG 244 +#define IMX7D_UART5_ROOT_DIV 245 +#define IMX7D_UART6_ROOT_CLK 246 +#define IMX7D_UART6_ROOT_SRC 247 +#define IMX7D_UART6_ROOT_CG 248 +#define IMX7D_UART6_ROOT_DIV 249 +#define IMX7D_UART7_ROOT_CLK 250 +#define IMX7D_UART7_ROOT_SRC 251 +#define IMX7D_UART7_ROOT_CG 252 +#define IMX7D_UART7_ROOT_DIV 253 +#define IMX7D_ECSPI1_ROOT_CLK 254 +#define IMX7D_ECSPI1_ROOT_SRC 255 +#define IMX7D_ECSPI1_ROOT_CG 256 +#define IMX7D_ECSPI1_ROOT_DIV 257 +#define IMX7D_ECSPI2_ROOT_CLK 258 +#define IMX7D_ECSPI2_ROOT_SRC 259 +#define IMX7D_ECSPI2_ROOT_CG 260 +#define IMX7D_ECSPI2_ROOT_DIV 261 +#define IMX7D_ECSPI3_ROOT_CLK 262 +#define IMX7D_ECSPI3_ROOT_SRC 263 +#define IMX7D_ECSPI3_ROOT_CG 264 +#define IMX7D_ECSPI3_ROOT_DIV 265 +#define IMX7D_ECSPI4_ROOT_CLK 266 +#define IMX7D_ECSPI4_ROOT_SRC 267 +#define IMX7D_ECSPI4_ROOT_CG 268 +#define IMX7D_ECSPI4_ROOT_DIV 269 +#define IMX7D_PWM1_ROOT_CLK 270 +#define IMX7D_PWM1_ROOT_SRC 271 +#define IMX7D_PWM1_ROOT_CG 272 +#define IMX7D_PWM1_ROOT_DIV 273 +#define IMX7D_PWM2_ROOT_CLK 274 +#define IMX7D_PWM2_ROOT_SRC 275 +#define IMX7D_PWM2_ROOT_CG 276 +#define IMX7D_PWM2_ROOT_DIV 277 +#define IMX7D_PWM3_ROOT_CLK 278 +#define IMX7D_PWM3_ROOT_SRC 279 +#define IMX7D_PWM3_ROOT_CG 280 +#define IMX7D_PWM3_ROOT_DIV 281 +#define IMX7D_PWM4_ROOT_CLK 282 +#define IMX7D_PWM4_ROOT_SRC 283 +#define IMX7D_PWM4_ROOT_CG 284 +#define IMX7D_PWM4_ROOT_DIV 285 +#define IMX7D_FLEXTIMER1_ROOT_CLK 286 +#define IMX7D_FLEXTIMER1_ROOT_SRC 287 +#define IMX7D_FLEXTIMER1_ROOT_CG 288 +#define IMX7D_FLEXTIMER1_ROOT_DIV 289 +#define IMX7D_FLEXTIMER2_ROOT_CLK 290 +#define IMX7D_FLEXTIMER2_ROOT_SRC 291 +#define IMX7D_FLEXTIMER2_ROOT_CG 292 +#define IMX7D_FLEXTIMER2_ROOT_DIV 293 +#define IMX7D_SIM1_ROOT_CLK 294 +#define IMX7D_SIM1_ROOT_SRC 295 +#define IMX7D_SIM1_ROOT_CG 296 +#define IMX7D_SIM1_ROOT_DIV 297 +#define IMX7D_SIM2_ROOT_CLK 298 +#define IMX7D_SIM2_ROOT_SRC 299 +#define IMX7D_SIM2_ROOT_CG 300 +#define IMX7D_SIM2_ROOT_DIV 301 +#define IMX7D_GPT1_ROOT_CLK 302 +#define IMX7D_GPT1_ROOT_SRC 303 +#define IMX7D_GPT1_ROOT_CG 304 +#define IMX7D_GPT1_ROOT_DIV 305 +#define IMX7D_GPT2_ROOT_CLK 306 +#define IMX7D_GPT2_ROOT_SRC 307 +#define IMX7D_GPT2_ROOT_CG 308 +#define IMX7D_GPT2_ROOT_DIV 309 +#define IMX7D_GPT3_ROOT_CLK 310 +#define IMX7D_GPT3_ROOT_SRC 311 +#define IMX7D_GPT3_ROOT_CG 312 +#define IMX7D_GPT3_ROOT_DIV 313 +#define IMX7D_GPT4_ROOT_CLK 314 +#define IMX7D_GPT4_ROOT_SRC 315 +#define IMX7D_GPT4_ROOT_CG 316 +#define IMX7D_GPT4_ROOT_DIV 317 +#define IMX7D_TRACE_ROOT_CLK 318 +#define IMX7D_TRACE_ROOT_SRC 319 +#define IMX7D_TRACE_ROOT_CG 320 +#define IMX7D_TRACE_ROOT_DIV 321 +#define IMX7D_WDOG1_ROOT_CLK 322 +#define IMX7D_WDOG_ROOT_SRC 323 +#define IMX7D_WDOG_ROOT_CG 324 +#define IMX7D_WDOG_ROOT_DIV 325 +#define IMX7D_CSI_MCLK_ROOT_CLK 326 +#define IMX7D_CSI_MCLK_ROOT_SRC 327 +#define IMX7D_CSI_MCLK_ROOT_CG 328 +#define IMX7D_CSI_MCLK_ROOT_DIV 329 +#define IMX7D_AUDIO_MCLK_ROOT_CLK 330 +#define IMX7D_AUDIO_MCLK_ROOT_SRC 331 +#define IMX7D_AUDIO_MCLK_ROOT_CG 332 +#define IMX7D_AUDIO_MCLK_ROOT_DIV 333 +#define IMX7D_WRCLK_ROOT_CLK 334 +#define IMX7D_WRCLK_ROOT_SRC 335 +#define IMX7D_WRCLK_ROOT_CG 336 +#define IMX7D_WRCLK_ROOT_DIV 337 +#define IMX7D_CLKO1_ROOT_SRC 338 +#define IMX7D_CLKO1_ROOT_CG 339 +#define IMX7D_CLKO1_ROOT_DIV 340 +#define IMX7D_CLKO2_ROOT_SRC 341 +#define IMX7D_CLKO2_ROOT_CG 342 +#define IMX7D_CLKO2_ROOT_DIV 343 +#define IMX7D_MAIN_AXI_ROOT_PRE_DIV 344 +#define IMX7D_DISP_AXI_ROOT_PRE_DIV 345 +#define IMX7D_ENET_AXI_ROOT_PRE_DIV 346 +#define IMX7D_NAND_USDHC_BUS_ROOT_PRE_DIV 347 +#define IMX7D_AHB_CHANNEL_ROOT_PRE_DIV 348 +#define IMX7D_USB_HSIC_ROOT_PRE_DIV 349 +#define IMX7D_PCIE_CTRL_ROOT_PRE_DIV 350 +#define IMX7D_PCIE_PHY_ROOT_PRE_DIV 351 +#define IMX7D_EPDC_PIXEL_ROOT_PRE_DIV 352 +#define IMX7D_LCDIF_PIXEL_ROOT_PRE_DIV 353 +#define IMX7D_MIPI_DSI_ROOT_PRE_DIV 354 +#define IMX7D_MIPI_CSI_ROOT_PRE_DIV 355 +#define IMX7D_MIPI_DPHY_ROOT_PRE_DIV 356 +#define IMX7D_SAI1_ROOT_PRE_DIV 357 +#define IMX7D_SAI2_ROOT_PRE_DIV 358 +#define IMX7D_SAI3_ROOT_PRE_DIV 359 +#define IMX7D_SPDIF_ROOT_PRE_DIV 360 +#define IMX7D_ENET1_REF_ROOT_PRE_DIV 361 +#define IMX7D_ENET1_TIME_ROOT_PRE_DIV 362 +#define IMX7D_ENET2_REF_ROOT_PRE_DIV 363 +#define IMX7D_ENET2_TIME_ROOT_PRE_DIV 364 +#define IMX7D_ENET_PHY_REF_ROOT_PRE_DIV 365 +#define IMX7D_EIM_ROOT_PRE_DIV 366 +#define IMX7D_NAND_ROOT_PRE_DIV 367 +#define IMX7D_QSPI_ROOT_PRE_DIV 368 +#define IMX7D_USDHC1_ROOT_PRE_DIV 369 +#define IMX7D_USDHC2_ROOT_PRE_DIV 370 +#define IMX7D_USDHC3_ROOT_PRE_DIV 371 +#define IMX7D_CAN1_ROOT_PRE_DIV 372 +#define IMX7D_CAN2_ROOT_PRE_DIV 373 +#define IMX7D_I2C1_ROOT_PRE_DIV 374 +#define IMX7D_I2C2_ROOT_PRE_DIV 375 +#define IMX7D_I2C3_ROOT_PRE_DIV 376 +#define IMX7D_I2C4_ROOT_PRE_DIV 377 +#define IMX7D_UART1_ROOT_PRE_DIV 378 +#define IMX7D_UART2_ROOT_PRE_DIV 379 +#define IMX7D_UART3_ROOT_PRE_DIV 380 +#define IMX7D_UART4_ROOT_PRE_DIV 381 +#define IMX7D_UART5_ROOT_PRE_DIV 382 +#define IMX7D_UART6_ROOT_PRE_DIV 383 +#define IMX7D_UART7_ROOT_PRE_DIV 384 +#define IMX7D_ECSPI1_ROOT_PRE_DIV 385 +#define IMX7D_ECSPI2_ROOT_PRE_DIV 386 +#define IMX7D_ECSPI3_ROOT_PRE_DIV 387 +#define IMX7D_ECSPI4_ROOT_PRE_DIV 388 +#define IMX7D_PWM1_ROOT_PRE_DIV 389 +#define IMX7D_PWM2_ROOT_PRE_DIV 390 +#define IMX7D_PWM3_ROOT_PRE_DIV 391 +#define IMX7D_PWM4_ROOT_PRE_DIV 392 +#define IMX7D_FLEXTIMER1_ROOT_PRE_DIV 393 +#define IMX7D_FLEXTIMER2_ROOT_PRE_DIV 394 +#define IMX7D_SIM1_ROOT_PRE_DIV 395 +#define IMX7D_SIM2_ROOT_PRE_DIV 396 +#define IMX7D_GPT1_ROOT_PRE_DIV 397 +#define IMX7D_GPT2_ROOT_PRE_DIV 398 +#define IMX7D_GPT3_ROOT_PRE_DIV 399 +#define IMX7D_GPT4_ROOT_PRE_DIV 400 +#define IMX7D_TRACE_ROOT_PRE_DIV 401 +#define IMX7D_WDOG_ROOT_PRE_DIV 402 +#define IMX7D_CSI_MCLK_ROOT_PRE_DIV 403 +#define IMX7D_AUDIO_MCLK_ROOT_PRE_DIV 404 +#define IMX7D_WRCLK_ROOT_PRE_DIV 405 +#define IMX7D_CLKO1_ROOT_PRE_DIV 406 +#define IMX7D_CLKO2_ROOT_PRE_DIV 407 +#define IMX7D_DRAM_PHYM_ALT_ROOT_PRE_DIV 408 +#define IMX7D_DRAM_ALT_ROOT_PRE_DIV 409 +#define IMX7D_LVDS1_IN_CLK 410 +#define IMX7D_LVDS1_OUT_SEL 411 +#define IMX7D_LVDS1_OUT_CLK 412 +#define IMX7D_CLK_DUMMY 413 +#define IMX7D_GPT_3M_CLK 414 +#define IMX7D_OCRAM_CLK 415 +#define IMX7D_OCRAM_S_CLK 416 +#define IMX7D_WDOG2_ROOT_CLK 417 +#define IMX7D_WDOG3_ROOT_CLK 418 +#define IMX7D_WDOG4_ROOT_CLK 419 +#define IMX7D_SDMA_CORE_CLK 420 +#define IMX7D_USB1_MAIN_480M_CLK 421 +#define IMX7D_USB_CTRL_CLK 422 +#define IMX7D_USB_PHY1_CLK 423 +#define IMX7D_USB_PHY2_CLK 424 +#define IMX7D_IPG_ROOT_CLK 425 +#define IMX7D_SAI1_IPG_CLK 426 +#define IMX7D_SAI2_IPG_CLK 427 +#define IMX7D_SAI3_IPG_CLK 428 +#define IMX7D_PLL_AUDIO_TEST_DIV 429 +#define IMX7D_PLL_AUDIO_POST_DIV 430 +#define IMX7D_PLL_VIDEO_TEST_DIV 431 +#define IMX7D_PLL_VIDEO_POST_DIV 432 +#define IMX7D_MU_ROOT_CLK 433 +#define IMX7D_SEMA4_HS_ROOT_CLK 434 +#define IMX7D_PLL_DRAM_TEST_DIV 435 +#define IMX7D_END_CLK 436 +#endif /* __DT_BINDINGS_CLOCK_IMX7D_H */
Signature · 1 line
1.9.1
PATCH v2 3/9 ARM: dts: add imx7d soc dtsi file
In reply to Frank.Li at freescale.comFrom: Frank Li <[email protected]>
Add i.mx7d support:
imx7d dtsi part
Signed-off-by Anson Huang <[email protected]>
Signed-off-by Frank Li <[email protected]>
--- arch/arm/boot/dts/imx7d.dtsi | 1091 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 1091 insertions(+) create mode 100644 arch/arm/boot/dts/imx7d.dtsi
arch/arm/boot/dts/imx7d.dtsi new file +1091 -0
@@ -0,0 +1,1091 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <dt-bindings/clock/imx7d-clock.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include "imx7d-pinfunc.h" +#include "skeleton.dtsi" + +/ { + aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + gpio5 = &gpio6; + gpio6 = &gpio7; + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + i2c3 = &i2c4; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + serial5 = &uart6; + serial6 = &uart7; + spi0 = &ecspi1; + spi1 = &ecspi2; + spi2 = &ecspi3; + spi3 = &ecspi4; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu at 0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + operating-points = < + /* KHz uV */ + 996000 1075000 + 792000 975000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clks IMX7D_ARM_A7_ROOT_CLK>, <&clks IMX7D_ARM_A7_ROOT_SRC>, + <&clks IMX7D_PLL_ARM_MAIN_CLK>, <&clks IMX7D_PLL_SYS_MAIN_CLK>; + clock-names = "arm", "arm_root_src", "pll_arm", "pll_sys_main"; + }; +/* + cpu1: cpu at 1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <1>; + }; +*/ + }; + + intc: interrupt-controller at 31001000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x31001000 0x1000>, + <0x31002000 0x100>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + ckil: clock at 0 { + compatible = "fixed-clock"; + reg = <0>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "ckil"; + }; + + osc: clock at 1 { + compatible = "fixed-clock"; + reg = <1>; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc"; + }; + + }; + + timer { + compatible = "arm,armv7-timer"; + arm,cpu-registers-not-fw-configured; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-parent = <&intc>; + clock-frequency = <8000000>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&intc>; + ranges; + + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + ocram: sram at 900000 { + compatible = "mmio-sram"; + reg = <0x00900000 0x20000>; + clocks = <&clks IMX7D_OCRAM_CLK>; + status = "disabled"; + }; + + ocrams: sram at 00180000 { + compatible = "fsl,lpm-sram"; + reg = <0x00180000 0x8000>; + clocks = <&clks IMX7D_OCRAM_S_CLK>; + status = "disabled"; + }; + + dma_apbh: dma-apbh at 33000000 { + compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; + reg = <0x33000000 0x2000>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; + #dma-cells = <1>; + dma-channels = <4>; + clocks = <&clks IMX7D_NAND_ROOT_CLK>; + }; + + gpmi: gpmi-nand at 33002000{ + compatible = "fsl,imx7d-gpmi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x33002000 0x2000>, <0x33004000 0x4000>; + reg-names = "gpmi-nand", "bch"; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "bch"; + clocks = <&clks IMX7D_NAND_ROOT_CLK>, + <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>; + clock-names = "gpmi_io", "gpmi_bch_apb"; + dmas = <&dma_apbh 0>; + dma-names = "rx-tx"; + status = "disabled"; + }; + + aips1: aips-bus at 30000000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x30000000 0x400000>; + ranges; + + gpio1: gpio at 30200000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30200000 0x10000>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */ + <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */ + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio at 30210000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30210000 0x10000>; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio at 30220000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30220000 0x10000>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio at 30230000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30230000 0x10000>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio5: gpio at 30240000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30240000 0x10000>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio6: gpio at 30250000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30250000 0x10000>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio7: gpio at 30260000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30260000 0x10000>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + wdog1: wdog at 30280000 { + compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; + reg = <0x30280000 0x10000>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_WDOG1_ROOT_CLK>; + }; + + wdog2: wdog at 30290000 { + compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; + reg = <0x30290000 0x10000>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_WDOG2_ROOT_CLK>; + status = "disabled"; + }; + + wdog3: wdog at 302a0000 { + compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; + reg = <0x302a0000 0x10000>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_WDOG3_ROOT_CLK>; + status = "disabled"; + }; + + wdog4: wdog at 302b0000 { + compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; + reg = <0x302b0000 0x10000>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_WDOG4_ROOT_CLK>; + status = "disabled"; + }; + + iomuxc_lpsr: iomuxc-lpsr at 302c0000 { + compatible = "fsl,imx7d-iomuxc-lpsr"; + reg = <0x302c0000 0x10000>; + }; + + gpt1: gpt at 302d0000 { + compatible = "fsl,imx7d-gpt", "fsl,imx31-gpt"; + reg = <0x302d0000 0x10000>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_GPT1_ROOT_CLK>; + clock-names = "ipg", "per"; + }; + + gpt2: gpt at 302e0000 { + compatible = "fsl,imx7d-gpt", "fsl,imx31-gpt"; + reg = <0x302e0000 0x10000>; + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_GPT2_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + gpt3: gpt at 302f0000 { + compatible = "fsl,imx7d-gpt", "fsl,imx31-gpt"; + reg = <0x302f0000 0x10000>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_GPT3_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + gpt4: gpt at 30300000 { + compatible = "fsl,imx7d-gpt", "fsl,imx31-gpt"; + reg = <0x30300000 0x10000>; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_GPT4_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + kpp: kpp at 30320000 { + compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp"; + reg = <0x30320000 0x10000>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_CLK_DUMMY>; + status = "disabled"; + }; + + iomuxc: iomuxc at 30330000 { + compatible = "fsl,imx7d-iomuxc"; + reg = <0x30330000 0x10000>; + }; + + gpr: iomuxc-gpr at 30340000 { + compatible = "fsl,imx7d-iomuxc-gpr", "syscon"; + reg = <0x30340000 0x10000>; + }; + + mqs: mqs { + compatible = "fsl,imx6sx-mqs"; + gpr = <&gpr>; + status = "disabled"; + }; + + ocotp: ocotp-ctrl at 30350000 { + compatible = "syscon"; + reg = <0x30350000 0x10000>; + clocks = <&clks IMX7D_CLK_DUMMY>; + status = "disabled"; + }; + + anatop: anatop at 30360000 { + compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop", + "syscon", "simple-bus"; + reg = <0x30360000 0x10000>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + + reg_1p0d: regulator-vdd1p0d at 210 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vdd1p0d"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1200000>; + anatop-reg-offset = <0x210>; + anatop-vol-bit-shift = <8>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <8>; + anatop-min-voltage = <800000>; + anatop-max-voltage = <1200000>; + anatop-enable-bit = <31>; + }; + }; + + snvs: snvs at 30370000 { + compatible = "fsl,sec-v4.0-mon", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x30370000 0x10000>; + + snvs-rtc-lp at 34 { + compatible = "fsl,sec-v4.0-mon-rtc-lp"; + reg = <0x34 0x58>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + snvs-pwrkey at 0x30370000 { + compatible = "fsl, imx7d-snvs-pwrkey", "fsl,imx6sx-snvs-pwrkey"; + reg = <0x30370000 0x10000>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + fsl,keycode = <116>; /* KEY_POWER */ + fsl,wakeup; + }; + + clks: ccm at 30380000 { + compatible = "fsl,imx7d-ccm"; + reg = <0x30380000 0x10000>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + #clock-cells = <1>; + clocks = <&ckil>, <&osc>; + clock-names = "ckil", "osc"; + }; + + src: src at 30390000 { + compatible = "fsl,imx7d-src", "fsl,imx51-src", "syscon"; + reg = <0x30390000 0x10000>; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + #reset-cells = <1>; + }; + + gpc: gpc at 303a0000 { + compatible = "fsl,imx7d-gpc"; + reg = <0x303a0000 0x10000>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + fsl,mf-mix-wakeup-irq = <0x4000000 0xc00 0x0 0x0>; + #power-domain-cells = <1>; + pcie-phy-supply = <®_1p0d>; + }; + }; + + aips2: aips-bus at 30400000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x30400000 0x400000>; + ranges; + + adc1: adc at 30610000 { + compatible = "fsl,imx7d-adc"; + reg = <0x30610000 0x10000>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_CLK_DUMMY>; + num-channels = <4>; + clock-names = "adc"; + status = "disabled"; + }; + + adc2: adc at 30620000 { + compatible = "fsl,imx7d-adc"; + reg = <0x30620000 0x10000>; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_CLK_DUMMY>; + num-channels = <4>; + clock-names = "adc"; + status = "disabled"; + }; + + ecspi4: ecspi at 30630000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-ecspi", "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; + reg = <0x30630000 0x10000>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>, + <&clks IMX7D_ECSPI4_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + flextimer1: flextimer at 30640000 { + compatible = "fsl,imx7d-flextimer"; + reg = <0x30640000 0x10000>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + flextimer2: flextimer at 30650000 { + compatible = "fsl,imx7d-flextimer"; + reg = <0x30650000 0x10000>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + pwm1: pwm at 30660000 { + compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; + reg = <0x30660000 0x10000>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_PWM1_ROOT_CLK>, + <&clks IMX7D_PWM1_ROOT_CLK>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm2: pwm at 30670000 { + compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; + reg = <0x30670000 0x10000>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_PWM2_ROOT_CLK>, + <&clks IMX7D_PWM2_ROOT_CLK>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm3: pwm at 30680000 { + compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; + reg = <0x30680000 0x10000>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_PWM3_ROOT_CLK>, + <&clks IMX7D_PWM3_ROOT_CLK>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm4: pwm at 30690000 { + compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; + reg = <0x30690000 0x10000>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_PWM4_ROOT_CLK>, + <&clks IMX7D_PWM4_ROOT_CLK>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + + system_counter_rd: system-counter-rd at 306a0000 { + compatible = "fsl,imx7d-system-counter-rd"; + reg = <0x306a0000 0x10000>; + status = "disabled"; + }; + + system_counter_cmp: system-counter-cmp at 306b0000 { + compatible = "fsl,imx7d-system-counter-cmp"; + reg = <0x306b0000 0x10000>; + status = "disabled"; + }; + + system_counter_ctrl: system-counter-ctrl at 306c0000 { + compatible = "fsl,imx7d-system-counter-ctrl"; + reg = <0x306c0000 0x10000>; + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + epdc: epdc at 306f0000 { + compatible = "fsl,imx7d-epdc"; + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x306f0000 0x10000>; + clocks = <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_EPDC_PIXEL_ROOT_CLK>; + clock-names = "epdc_axi", "epdc_pix"; + epdc-ram = <&gpr 0x4 30>; + status = "disabled"; + }; + + epxp: epxp at 30700000 { + compatible = "fsl,imx7d-pxp-dma"; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x30700000 0x10000>; + clocks = <&clks IMX7D_CLK_DUMMY>; + clock-names = "pxp-axi"; + status = "disabled"; + }; + + csi1: csi at 30710000 { + compatible = "fsl,imx7d-csi", "fsl,imx6s-csi"; + reg = <0x30710000 0x10000>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CSI_MCLK_ROOT_CLK>, + <&clks IMX7D_CLK_DUMMY>; + clock-names = "disp-axi", "csi_mclk", "disp_dcic"; + status = "disabled"; + }; + + lcdif: lcdif at 30730000 { + compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif"; + reg = <0x30730000 0x10000>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>, + <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CLK_DUMMY>; + clock-names = "pix", "axi", "disp_axi"; + status = "disabled"; + }; + + mipi_csi: mipi-csi at 30750000 { + compatible = "fsl,imx7d-mipi-csi"; + reg = <0x30750000 0x10000>; + status = "disabled"; + }; + + mipi_dsi: mipi-dsi at 30760000 { + compatible = "fsl,imx7d-mipi-dsi"; + reg = <0x30760000 0x10000>; + status = "disabled"; + }; + + ddrc: ddrc at 307a0000 { + compatible = "fsl,imx7-ddrc"; + reg = <0x307a0000 0x10000>; + }; + }; + + aips3: aips-bus at 30800000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x30800000 0x400000>; + ranges; + + ecspi1: ecspi at 30820000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-ecspi", "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; + reg = <0x30820000 0x10000>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>, + <&clks IMX7D_ECSPI1_ROOT_CLK>; + clock-names = "ipg", "per"; + dmas = <&sdma 0 7 1>, <&sdma 1 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + ecspi2: ecspi at 30830000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-ecspi", "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; + reg = <0x30830000 0x10000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>, + <&clks IMX7D_ECSPI2_ROOT_CLK>; + clock-names = "ipg", "per"; + dmas = <&sdma 2 7 1>, <&sdma 3 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + ecspi3: ecspi at 30840000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-ecspi", "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; + reg = <0x30840000 0x10000>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>, + <&clks IMX7D_ECSPI3_ROOT_CLK>; + clock-names = "ipg", "per"; + dmas = <&sdma 4 7 1>, <&sdma 5 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart1: serial at 30860000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x30860000 0x10000>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_UART1_ROOT_CLK>, + <&clks IMX7D_UART1_ROOT_CLK>; + clock-names = "ipg", "per"; + dmas = <&sdma 22 4 0>, <&sdma 23 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart2: serial at 30870000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x30870000 0x10000>; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_UART2_ROOT_CLK>, + <&clks IMX7D_UART2_ROOT_CLK>; + clock-names = "ipg", "per"; + dmas = <&sdma 24 4 0>, <&sdma 25 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart3: serial at 30880000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x30880000 0x10000>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_UART3_ROOT_CLK>, + <&clks IMX7D_UART3_ROOT_CLK>; + clock-names = "ipg", "per"; + dmas = <&sdma 26 4 0>, <&sdma 27 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + sai1: sai at 308a0000 { + compatible = "fsl,imx7d-sai"; + reg = <0x308a0000 0x10000>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_SAI1_IPG_CLK>, + <&clks IMX7D_SAI1_ROOT_CLK>, + <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_CLK_DUMMY>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&sdma 8 25 0>, <&sdma 9 25 0>; + status = "disabled"; + }; + + sai2: sai at 308b0000 { + compatible = "fsl,imx7d-sai"; + reg = <0x308b0000 0x10000>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_SAI2_IPG_CLK>, + <&clks IMX7D_SAI2_ROOT_CLK>, + <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_CLK_DUMMY>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&sdma 10 25 0>, <&sdma 11 25 0>; + status = "disabled"; + }; + + sai3: sai at 308c0000 { + compatible = "fsl,imx7d-sai"; + reg = <0x308c0000 0x10000>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_SAI3_IPG_CLK>, + <&clks IMX7D_SAI3_ROOT_CLK>, + <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_CLK_DUMMY>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&sdma 12 25 0>, <&sdma 13 25 0>; + status = "disabled"; + }; + + flexcan1: can at 30a00000 { + compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; + reg = <0x30a00000 0x10000>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CAN1_ROOT_CLK>; + clock-names = "ipg", "per"; + stop-mode = <&gpr 0x10 1 0x10 17>; + status = "disabled"; + }; + + flexcan2: can at 30a10000 { + compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; + reg = <0x30a10000 0x10000>; + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CAN2_ROOT_CLK>; + clock-names = "ipg", "per"; + stop-mode = <&gpr 0x10 2 0x10 18>; + status = "disabled"; + }; + + i2c1: i2c at 30a20000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; + reg = <0x30a20000 0x10000>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_I2C1_ROOT_CLK>; + status = "disabled"; + }; + + i2c2: i2c at 30a30000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; + reg = <0x30a30000 0x10000>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_I2C2_ROOT_CLK>; + status = "disabled"; + }; + + i2c3: i2c at 30a40000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; + reg = <0x30a40000 0x10000>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_I2C3_ROOT_CLK>; + status = "disabled"; + }; + + i2c4: i2c at 30a50000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; + reg = <0x30a50000 0x10000>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_I2C4_ROOT_CLK>; + status = "disabled"; + }; + + uart4: serial at 30a60000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x30a60000 0x10000>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_UART4_ROOT_CLK>, + <&clks IMX7D_UART4_ROOT_CLK>; + clock-names = "ipg", "per"; + dmas = <&sdma 28 4 0>, <&sdma 29 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart5: serial at 30a70000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x30a70000 0x10000>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_UART5_ROOT_CLK>, + <&clks IMX7D_UART5_ROOT_CLK>; + clock-names = "ipg", "per"; + dmas = <&sdma 30 4 0>, <&sdma 31 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart6: serial at 30a80000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x30a80000 0x10000>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_UART6_ROOT_CLK>, + <&clks IMX7D_UART6_ROOT_CLK>; + clock-names = "ipg", "per"; + dmas = <&sdma 32 4 0>, <&sdma 33 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart7: serial at 30a90000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x30a90000 0x10000>; + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_UART7_ROOT_CLK>, + <&clks IMX7D_UART7_ROOT_CLK>; + clock-names = "ipg", "per"; + dmas = <&sdma 34 4 0>, <&sdma 35 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + mu: mu at 30aa0000 { + compatible = "fsl,imx7d-mu", "fsl,imx6sx-mu"; + reg = <0x30aa0000 0x10000>; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_MU_ROOT_CLK>; + clock-names = "mu"; + status = "okay"; + }; + + mcctest: mcctest{ + compatible = "fsl,imx6sx-mcc-test"; + status = "disabled"; + }; + + mcctty: mcctty{ + compatible = "fsl,imx6sx-mcc-tty"; + status = "disabled"; + }; + + sema4: sema4 at 30ac0000 { + compatible = "fsl,imx7d-sema4"; + reg = <0x30ac0000 0x10000>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_SEMA4_HS_ROOT_CLK>; + clock-names = "sema4"; + status = "okay"; + }; + + usbotg1: usb at 30b10000 { + compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; + reg = <0x30b10000 0x200>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_USB_CTRL_CLK>; + fsl,usbphy = <&usbphy_nop1>; + fsl,usbmisc = <&usbmisc1 0>; + status = "disabled"; + }; + + usbotg2: usb at 30b20000 { + compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; + reg = <0x30b20000 0x200>; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_USB_CTRL_CLK>; + fsl,usbphy = <&usbphy_nop2>; + fsl,usbmisc = <&usbmisc2 0>; + status = "disabled"; + }; + + usbh: usb at 30b30000 { + compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; + reg = <0x30b30000 0x200>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_USB_CTRL_CLK>; + fsl,usbphy = <&usbphy_nop3>; + fsl,usbmisc = <&usbmisc3 0>; + phy_type = "hsic"; + dr_mode = "host"; + status = "disabled"; + }; + + usbmisc1: usbmisc at 30b10200 { + #index-cells = <1>; + compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; + reg = <0x30b10200 0x200>; + }; + + usbmisc2: usbmisc at 30b20200 { + #index-cells = <1>; + compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; + reg = <0x30b20200 0x200>; + }; + + usbmisc3: usbmisc at 30b30200 { + #index-cells = <1>; + compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; + reg = <0x30b30200 0x200>; + }; + + usbphy_nop1: usbphy_nop1 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX7D_USB_PHY1_CLK>; + clock-names = "main_clk"; + }; + + usbphy_nop2: usbphy_nop2 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX7D_USB_PHY2_CLK>; + clock-names = "main_clk"; + }; + + usbphy_nop3: usbphy_nop3 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>; + clock-names = "main_clk"; + }; + + usdhc1: usdhc at 30b40000 { + compatible = "fsl,imx7d-usdhc", "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; + reg = <0x30b40000 0x10000>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_USDHC1_ROOT_CLK>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + usdhc2: usdhc at 30b50000 { + compatible = "fsl,imx7d-usdhc", "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; + reg = <0x30b50000 0x10000>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_USDHC2_ROOT_CLK>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + usdhc3: usdhc at 30b60000 { + compatible = "fsl,imx7d-usdhc", "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; + reg = <0x30b60000 0x10000>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_USDHC3_ROOT_CLK>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + sim1: sim at 30b90000 { + compatible = "fsl,imx7d-sim"; + reg = <0x30b90000 0x10000>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_SIM1_ROOT_CLK>; + clock-names = "sim"; + status = "disabled"; + }; + + sim2: sim at 30ba0000 { + compatible = "fsl,imx7d-sim"; + reg = <0x30ba0000 0x10000>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + qspi1: qspi at 30bb0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-qspi"; + reg = <0x30bb0000 0x10000>, <0x60000000 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_QSPI_ROOT_CLK>, + <&clks IMX7D_QSPI_ROOT_CLK>; + clock-names = "qspi_en", "qspi"; + status = "disabled"; + }; + + weim: weim at 30bc0000 { + compatible = "fsl,imx7d-weim", "fsl,imx6sx-weim", "fsl,imx6q-weim"; + reg = <0x30bc0000 0x10000>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_EIM_ROOT_CLK>; + status = "disabled"; + }; + + sdma: sdma at 30bd0000 { + compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma"; + reg = <0x30bd0000 0x10000>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_SDMA_CORE_CLK>, + <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + iram = <&ocram>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; + }; + + fec1: ethernet at 30be0000 { + compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec"; + reg = <0x30be0000 0x10000>; + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>, + <&clks IMX7D_ENET_AXI_ROOT_CLK>, + <&clks IMX7D_ENET1_TIME_ROOT_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, + <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; + clock-names = "ipg", "ahb", "ptp", + "enet_clk_ref", "enet_out"; + fsl,num-tx-queues=<3>; + fsl,num-rx-queues=<3>; + status = "disabled"; + }; + + fec2: ethernet at 30bf0000 { + compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec"; + reg = <0x30bf0000 0x10000>; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>, + <&clks IMX7D_ENET_AXI_ROOT_CLK>, + <&clks IMX7D_ENET2_TIME_ROOT_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, + <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; + clock-names = "ipg", "ahb", "ptp", + "enet_clk_ref", "enet_out"; + fsl,num-tx-queues=<3>; + fsl,num-rx-queues=<3>; + status = "disabled"; + }; + }; + + pcie: pcie at 0x33800000 { + compatible = "fsl,imx7d-pcie", "snps,dw-pcie"; + reg = <0x33800000 0x4000>, <0x4ff00000 0x80000>; + reg-names = "dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0 0x4ff80000 0 0x00010000 /* downstream I/O 64KB */ + 0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */ + num-lanes = <1>; + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>, + <&clks IMX7D_PCIE_PHY_ROOT_CLK>; + clock-names = "pcie", "pcie_bus", "pcie_phy"; + pcie-phy-supply = <®_1p0d>; + status = "disabled"; + }; + }; +};
Signature · 1 line
1.9.1
PATCH v2 3/9 ARM: dts: add imx7d soc dtsi file
arch/arm/boot/dts/imx7d.dtsi line 103
Quoted 3 lines · Frank.Li at freescale.com
arch/arm/boot/dts/imx7d.dtsi new file +3
-0+ timer { + compatible = "arm,armv7-timer"; + arm,cpu-registers-not-fw-configured;
Just checking -- do you definitely need this property? If so, the VDSO won't be able to service gettimeofday/clock_gettime.
PATCH v2 3/9 ARM: dts: add imx7d soc dtsi file
Quoted 1 line · Nathan Lynch
cpu-registers-not-fw-configured
So far, yes.
There are not firmware in our platform. virtual offset is random value when boot.
PATCH v2 4/9 pinctrl: add imx7d support
In reply to Frank.Li at freescale.comFrom: Frank Li <[email protected]>
Add i.MX7D pinctrl driver support
Signed-off-by Frank Li <[email protected]>
Signed-off-by Anson Huang <[email protected]>
--- drivers/pinctrl/freescale/Kconfig | 7 + drivers/pinctrl/freescale/Makefile | 1 + drivers/pinctrl/freescale/pinctrl-imx.c | 3 +- drivers/pinctrl/freescale/pinctrl-imx.h | 1 + drivers/pinctrl/freescale/pinctrl-imx7d.c | 411 ++++++++++++++++++++++++++++++ 5 files changed, 421 insertions(+), 2 deletions(-) create mode 100644 drivers/pinctrl/freescale/pinctrl-imx7d.c
drivers/pinctrl/freescale/Kconfig +7 -0
@@ -87,6 +87,13 @@ config PINCTRL_IMX6SX help Say Y here to enable the imx6sx pinctrl driver +config PINCTRL_IMX7D + bool "IMX7D pinctrl driver" + depends on SOC_IMX7D + select PINCTRL_IMX + help + Say Y here to enable the imx7d pinctrl driver + config PINCTRL_VF610 bool "Freescale Vybrid VF610 pinctrl driver" depends on SOC_VF610
drivers/pinctrl/freescale/Makefile +1 -0
@@ -12,6 +12,7 @@ obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6dl.o obj-$(CONFIG_PINCTRL_IMX6SL) += pinctrl-imx6sl.o obj-$(CONFIG_PINCTRL_IMX6SX) += pinctrl-imx6sx.o +obj-$(CONFIG_PINCTRL_IMX7D) += pinctrl-imx7d.o obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
drivers/pinctrl/freescale/pinctrl-imx.c +1 -2
@@ -580,7 +580,6 @@ static int imx_pinctrl_parse_functions(struct device_node *np,struct device_node *child;struct imx_pmx_func *func;struct imx_pin_group *grp; -static u32 grp_index;u32 i =0 ;dev_dbg (info->dev,"parse function(%d): %s\n" , index, np->name);
@@ -599,7 +598,7 @@ static int imx_pinctrl_parse_functions(struct device_node *np,for_each_child_of_node (np, child) { func->groups[i] = child->name; - grp = &info->groups[grp_index++]; + grp = &info->groups[info->grp_index++];imx_pinctrl_parse_groups (child, grp, info, i++); }
drivers/pinctrl/freescale/pinctrl-imx.h +1 -0
@@ -81,6 +81,7 @@ struct imx_pinctrl_soc_info {struct imx_pmx_func *functions;unsigned int nfunctions;unsigned int flags; +unsigned int grp_index; };#define SHARE_MUX_CONF_REG 0x1
drivers/pinctrl/freescale/pinctrl-imx7d.c new file +411 -0
411 lines not on this page · raw message
Signature · 1 line
1.9.1
Fabio Estevam
maintainerPATCH v2 4/9 pinctrl: add imx7d support
Quoted 6 lines · On Thu, Apr 16, 2015 at 4:17 PM, <[email protected]> wrote:
From: Frank Li <[email protected]>
Add i.MX7D pinctrl driver support
Signed-off-by Frank Li <[email protected]>Signed-off-by Anson Huang <[email protected]>
You should send this one to the pinctrl maintainer.
PATCH v2 5/9 ARM: imx: add msl support for imx7d
In reply to Frank.Li at freescale.comFrom: Anson Huang <[email protected]>
Add i.MX7D MSL support.
Signed-off-by Anson Huang <[email protected]>
Signed-off-by Frank Li <[email protected]>
--- arch/arm/mach-imx/Kconfig | 11 +++++++++ arch/arm/mach-imx/Makefile | 1 + arch/arm/mach-imx/anatop.c | 33 +++++++++++++++++++++++++- arch/arm/mach-imx/common.h | 1 + arch/arm/mach-imx/cpu.c | 10 ++++++++ arch/arm/mach-imx/hardware.h | 7 +++++- arch/arm/mach-imx/mach-imx7d.c | 53 ++++++++++++++++++++++++++++++++++++++++++ arch/arm/mach-imx/mx7.h | 38 ++++++++++++++++++++++++++++++ arch/arm/mach-imx/mxc.h | 15 +++++++++++- arch/arm/mach-imx/platsmp.c | 24 ++++++++++++++++++- 10 files changed, 189 insertions(+), 4 deletions(-) create mode 100644 arch/arm/mach-imx/mach-imx7d.c create mode 100644 arch/arm/mach-imx/mx7.h
arch/arm/mach-imx/Kconfig +11 -0
@@ -582,6 +582,17 @@ config SOC_IMX6SX help This enables support for Freescale i.MX6 SoloX processor. +config SOC_IMX7 + bool + select ARM_GIC + +config SOC_IMX7D + bool "i.MX7 Dual support" + select SOC_IMX7 + select PINCTRL_IMX7D + help + This enables support for Freescale i.MX7 Dual processor. + config SOC_VF610 bool "Vybrid Family VF610 support" select IRQ_DOMAIN_HIERARCHY
arch/arm/mach-imx/Makefile +1 -0
@@ -90,6 +90,7 @@ endif obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o mach-imx6sl.o obj-$(CONFIG_SOC_IMX6SX) += clk-imx6sx.o mach-imx6sx.o +obj-$(CONFIG_SOC_IMX7D) += clk-imx7d.o mach-imx7d.o ifeq ($(CONFIG_SUSPEND),y) AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a
arch/arm/mach-imx/anatop.c +32 -1
@@ -1,5 +1,5 @@/* -* Copyright (C) 2013 Freescale Semiconductor, Inc. +* Copyright (C) 2013-2015 Freescale Semiconductor, Inc. * * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License
@@ -21,6 +21,12 @@#define REG_SET 0x4#define REG_CLR 0x8 +#define ANADIG_ARM_PLL 0x60 +#define ANADIG_DDR_PLL 0x70 +#define ANADIG_SYS_PLL 0xb0 +#define ANADIG_ENET_PLL 0xe0 +#define ANADIG_AUDIO_PLL 0xf0 +#define ANADIG_VIDEO_PLL 0x130#define ANADIG_REG_2P5 0x130#define ANADIG_REG_CORE 0x140#define ANADIG_ANA_MISC0 0x150
@@ -28,6 +34,7 @@#define ANADIG_USB2_CHRG_DETECT 0x210#define ANADIG_DIGPROG 0x260#define ANADIG_DIGPROG_IMX6SL 0x280 +#define ANADIG_DIGPROG_IMX7D 0x800#define BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG 0x40000#define BM_ANADIG_REG_2P5_ENABLE_PULLDOWN 0x8
@@ -73,6 +80,17 @@ static inline void imx_anatop_disconnect_high_snvs(bool enable)void imx_anatop_pre_suspend (void ) { +if (cpu_is_imx7d ()) { +/* PLL overwrite set */ +regmap_write (anatop,ANADIG_ARM_PLL +REG_SET ,1 <<20 ); +regmap_write (anatop,ANADIG_DDR_PLL +REG_SET ,1 <<19 ); +regmap_write (anatop,ANADIG_SYS_PLL +REG_SET ,1 <<17 ); +regmap_write (anatop,ANADIG_ENET_PLL +REG_SET ,1 <<13 ); +regmap_write (anatop,ANADIG_AUDIO_PLL +REG_SET ,1 <<24 ); +regmap_write (anatop,ANADIG_VIDEO_PLL +REG_SET ,1 <<24 ); +return ; + } +if (imx_mmdc_get_ddr_type () ==IMX_DDR_TYPE_LPDDR2 )imx_anatop_enable_2p5_pulldown (true);else
@@ -86,6 +104,17 @@ void imx_anatop_pre_suspend(void)void imx_anatop_post_resume (void ) { +if (cpu_is_imx7d ()) { +/* PLL overwrite clear */ +regmap_write (anatop,ANADIG_ARM_PLL +REG_CLR ,1 <<20 ); +regmap_write (anatop,ANADIG_DDR_PLL +REG_CLR ,1 <<19 ); +regmap_write (anatop,ANADIG_SYS_PLL +REG_CLR ,1 <<17 ); +regmap_write (anatop,ANADIG_ENET_PLL +REG_CLR ,1 <<13 ); +regmap_write (anatop,ANADIG_AUDIO_PLL +REG_CLR ,1 <<24 ); +regmap_write (anatop,ANADIG_VIDEO_PLL +REG_CLR ,1 <<24 ); +return ; + } +if (imx_mmdc_get_ddr_type () ==IMX_DDR_TYPE_LPDDR2 )imx_anatop_enable_2p5_pulldown (false);else
@@ -121,6 +150,8 @@ void __init imx_init_revision_from_anatop(void)WARN_ON (!anatop_base);if (of_device_is_compatible (np,"fsl,imx6sl-anatop" )) offset =ANADIG_DIGPROG_IMX6SL ; +if (of_device_is_compatible (np,"fsl,imx7d-anatop" )) + offset =ANADIG_DIGPROG_IMX7D ; digprog =readl_relaxed (anatop_base + offset);iounmap (anatop_base);
arch/arm/mach-imx/common.h +1 -0
@@ -54,6 +54,7 @@ int mx31_clocks_init_dt(void);struct platform_device *mxc_register_gpio (char *name,int id,resource_size_t iobase,resource_size_t iosize,int irq,int irq_high);void mxc_set_cpu_type (unsigned int type); +void mxc_set_arch_type (unsigned int type);void mxc_restart (enum reboot_mode ,const char *);void mxc_arch_reset_init (void __iomem *);int mx51_revision (void );
arch/arm/mach-imx/cpu.c +10 -0
@@ -11,6 +11,8 @@unsigned int __mxc_cpu_type;EXPORT_SYMBOL (__mxc_cpu_type); +unsigned int __mxc_arch_type; +EXPORT_SYMBOL (__mxc_arch_type);static unsigned int imx_soc_revision;
@@ -19,6 +21,11 @@ void mxc_set_cpu_type(unsigned int type) __mxc_cpu_type = type; } +void mxc_set_arch_type (unsigned int type) +{ + __mxc_arch_type = type; +} +void imx_set_soc_revision (unsigned int rev) { imx_soc_revision = rev;
@@ -130,6 +137,9 @@ struct device * __init imx_soc_device_init(void)case MXC_CPU_IMX6Q : soc_id ="i.MX6Q" ;break ; +case MXC_CPU_IMX7D : + soc_id ="i.MX7D" ; +break ;default : soc_id ="Unknown" ; }
arch/arm/mach-imx/hardware.h +6 -1
@@ -1,5 +1,5 @@/* -* Copyright 2004-2007, 2014 Freescale Semiconductor, Inc. All Rights Reserved. +* Copyright 2004-2007, 2014-2015 Freescale Semiconductor, Inc. * Copyright 2008 Juergen Beisert, [email protected] * * This program is free software; you can redistribute it and/or
@@ -93,6 +93,10 @@* CCM 0x020c4000+0x004000 -> 0xf42c4000+0x004000 * ANATOP 0x020c8000+0x004000 -> 0xf42c8000+0x004000 * UART4 0x021f0000+0x004000 -> 0xf42f0000+0x004000 +* mx7d: +* CCM 0x30380000+0x010000 -> 0xf5380000+0x010000 +* ANATOP 0x30360000+0x010000 -> 0xf5360000+0x010000 +* UART1 0x30860000+0x010000 -> 0xf5860000+0x010000 */ #define IMX_IO_P2V (x) ( \ (((x) & 0x80000000) >> 7) | \
@@ -112,6 +116,7 @@#include "mx21.h" #include "mx27.h" #include "mx1.h" +#include "mx7.h" #define imx_map_entry (soc, name, _type) { \ .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \
arch/arm/mach-imx/mach-imx7d.c new file +53 -0
53 lines not on this page · raw message
arch/arm/mach-imx/mx7.h new file +38 -0
@@ -0,0 +1,38 @@ +/* +* Copyright (C) 2015 Freescale Semiconductor, Inc. All Rights Reserved. +*/ + +/* +* * This program is free software; you can redistribute it and/or modify +* * it under the terms of the GNU General Public License version 2 as +* * published by the Free Software Foundation. +* */ + +#ifndef __ASM_ARCH_MX7_IOMAP_H__ +#define __ASM_ARCH_MX7_IOMAP_H__ + +#define MX7D_IO_P2V (x) IMX_IO_P2V(x) +#define MX7D_IO_ADDRESS (x) IOMEM(MX7D_IO_P2V(x)) + +#define MX7D_CCM_BASE_ADDR 0x30380000 +#define MX7D_CCM_SIZE 0x10000 +#define MX7D_IOMUXC_BASE_ADDR 0x30330000 +#define MX7D_IOMUXC_SIZE 0x10000 +#define MX7D_ANATOP_BASE_ADDR 0x30360000 +#define MX7D_ANATOP_SIZE 0x10000 +#define MX7D_GPC_BASE_ADDR 0x303a0000 +#define MX7D_GPC_SIZE 0x10000 +#define MX7D_SRC_BASE_ADDR 0x30390000 +#define MX7D_SRC_SIZE 0x10000 +#define MX7D_DDRC_BASE_ADDR 0x307a0000 +#define MX7D_DDRC_SIZE 0x10000 +#define MX7D_AIPS1_BASE_ADDR 0x30000000 +#define MX7D_AIPS1_SIZE 0x400000 +#define MX7D_AIPS2_BASE_ADDR 0x30400000 +#define MX7D_AIPS2_SIZE 0x400000 +#define MX7D_AIPS3_BASE_ADDR 0x30900000 +#define MX7D_AIPS3_SIZE 0x300000 + +#define TT_ATTRIB_NON_CACHEABLE_1M 0x802 +#define MX7_IRAM_TLB_SIZE 0x4000 +#endif
arch/arm/mach-imx/mxc.h +14 -1
@@ -1,5 +1,5 @@/* -* Copyright 2004-2007, 2010 Freescale Semiconductor, Inc. All Rights Reserved. +* Copyright 2004-2007, 2010-2015 Freescale Semiconductor, Inc. * Copyright (C) 2008 Juergen Beisert (kernel at pengutronix.de) * * This program is free software; you can redistribute it and/or
@@ -38,6 +38,8 @@#define MXC_CPU_IMX6DL 0x61#define MXC_CPU_IMX6SX 0x62#define MXC_CPU_IMX6Q 0x63 +#define MXC_CPU_IMX7D 0x72 +#define MXC_ARCH_CA7 0xc07#define IMX_CHIP_REVISION_1_0 0x10#define IMX_CHIP_REVISION_1_1 0x11
@@ -59,6 +61,7 @@#ifndef __ASSEMBLY__extern unsigned int __mxc_cpu_type; +extern unsigned int __mxc_arch_type;#endif #ifdef CONFIG_SOC_IMX1
@@ -185,6 +188,16 @@ static inline bool cpu_is_imx6q(void)return __mxc_cpu_type ==MXC_CPU_IMX6Q ; } +static inline bool cpu_is_imx7d (void ) +{ +return __mxc_cpu_type ==MXC_CPU_IMX7D ; +} + +static inline bool arm_is_ca7 (void ) +{ +return __mxc_arch_type ==MXC_ARCH_CA7 ; +} +struct cpu_op {u32 cpu_rate; };
arch/arm/mach-imx/platsmp.c +23 -1
@@ -60,11 +60,33 @@ static int imx_boot_secondary(unsigned int cpu, struct task_struct *idle)static void __init imx_smp_init_cpus (void ) {int i, ncores; +unsigned long arch_type; - ncores =scu_get_core_count (scu_base); + asmvolatile ( +".align 4\n" +"mrc p15, 0, %0, c0, c0, 0\n" + :"=r" (arch_type) + ); + +/* MIDR[15:4] defines ARCH type */ +mxc_set_arch_type ((arch_type >>4 ) &0xfff ); + +if (arm_is_ca7 ()) { +unsigned long val; + +/* CA7 core number, [25:24] of CP15 L2CTLR */ + asmvolatile ("mrc p15, 1, %0, c9, c0, 2" :"=r" (val)); + ncores = ((val >>24 ) &0x3 ) +1 ; + }else { + ncores =scu_get_core_count (scu_base); + } + +if (setup_max_cpus < ncores) + ncores = (setup_max_cpus) ? setup_max_cpus :1 ;for (i = ncores; i <NR_CPUS ; i++)set_cpu_possible (i, false); + }void imx_smp_prepare (void )
Signature · 1 line
1.9.1
PATCH v2 5/9 ARM: imx: add msl support for imx7d
Quoted 6 lines · Frank.Li at freescale.com
From: Anson Huang <[email protected]>
Add i.MX7D MSL support.
Signed-off-by Anson Huang <[email protected]>Signed-off-by Frank Li <[email protected]>
I'm not happy with this.
Quoted 20 lines
void
imx_anatop_pre_suspend(void)
{arch/arm/mach-imx/anatop.c +11
-0+if (cpu_is_imx7d ()) { +/* PLL overwrite set */ +regmap_write (anatop,ANADIG_ARM_PLL +REG_SET ,1 <<20 ); +regmap_write (anatop,ANADIG_DDR_PLL +REG_SET ,1 <<19 ); +regmap_write (anatop,ANADIG_SYS_PLL +REG_SET ,1 <<17 ); +regmap_write (anatop,ANADIG_ENET_PLL +REG_SET ,1 <<13 ); +regmap_write (anatop,ANADIG_AUDIO_PLL +REG_SET ,1 <<24 ); +regmap_write (anatop,ANADIG_VIDEO_PLL +REG_SET ,1 <<24 ); +return ; + } +if (imx_mmdc_get_ddr_type () ==IMX_DDR_TYPE_LPDDR2 )imx_anatop_enable_2p5_pulldown (true);else @@ -86,6 +104,17 @@ void imx_anatop_pre_suspend(void)void imx_anatop_post_resume (void ) {
arch/arm/mach-imx/anatop.c void imx_anatop_pre_suspend(void) · line 116
Quoted 10 lines
arch/arm/mach-imx/anatop.c +10
-0+if (cpu_is_imx7d ()) { +/* PLL overwrite clear */ +regmap_write (anatop,ANADIG_ARM_PLL +REG_CLR ,1 <<20 ); +regmap_write (anatop,ANADIG_DDR_PLL +REG_CLR ,1 <<19 ); +regmap_write (anatop,ANADIG_SYS_PLL +REG_CLR ,1 <<17 ); +regmap_write (anatop,ANADIG_ENET_PLL +REG_CLR ,1 <<13 ); +regmap_write (anatop,ANADIG_AUDIO_PLL +REG_CLR ,1 <<24 ); +regmap_write (anatop,ANADIG_VIDEO_PLL +REG_CLR ,1 <<24 ); +return ; + }
Shouldn't both of these be determined by the compatible string rather than checking __mxc_cpu_type?
Quoted 14 lines
arch/arm/mach-imx/cpu.c +2
-0@@ -11,6 +11,8 @@unsigned int __mxc_cpu_type;EXPORT_SYMBOL (__mxc_cpu_type); +unsigned int __mxc_arch_type; +EXPORT_SYMBOL (__mxc_arch_type);static unsigned int imx_soc_revision;
arch/arm/mach-imx/cpu.c void mxc_set_cpu_type(unsigned int type) · line 27
Quoted 7 lines
arch/arm/mach-imx/cpu.c +4
-0@@ -19,6 +21,11 @@ void mxc_set_cpu_type(unsigned int type) __mxc_cpu_type = type; } +void mxc_set_arch_type (unsigned int type) +{ + __mxc_arch_type = type; +}
You're re-inventing the wheel here. Please get rid of __mxc_arch_type and mxc_set_arch_type() entirely.
arch/arm/mach-imx/cpu.c line 42
Quoted 6 lines
arch/arm/mach-imx/cpu.c +2
-0@@ -38,6 +38,8 @@#define MXC_CPU_IMX6DL 0x61#define MXC_CPU_IMX6SX 0x62#define MXC_CPU_IMX6Q 0x63 +#define MXC_CPU_IMX7D 0x72 +#define MXC_ARCH_CA7 0xc07
Get rid of MXC_ARCH_CA7.
arch/arm/mach-imx/cpu.c
Quoted 4 lines
arch/arm/mach-imx/cpu.c +4
-0+static inline bool arm_is_ca7 (void ) +{ +return __mxc_arch_type ==MXC_ARCH_CA7 ; +}
And this function.
Quoted 11 lines
arch/arm/mach-imx/platsmp.c +1
-1@@ -60,11 +60,33 @@ static int imx_boot_secondary(unsigned int cpu, struct task_struct *idle)static void __init imx_smp_init_cpus (void ) {int i, ncores; +unsigned long arch_type; - ncores =scu_get_core_count (scu_base);
arch/arm/mach-imx/platsmp.c static int imx_boot_secondary(unsigned int cpu, struct task_struct *idle) · line 74
Quoted 10 lines
arch/arm/mach-imx/platsmp.c +10
-0+ asmvolatile ( +".align 4\n" +"mrc p15, 0, %0, c0, c0, 0\n" + :"=r" (arch_type) + ); + +/* MIDR[15:4] defines ARCH type */ +mxc_set_arch_type ((arch_type >>4 ) &0xfff ); + +if (arm_is_ca7 ()) {
Rather than the above, use:
if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A7) {here.
Even better would be to _not_ re-use imx_smp_init_cpus(), but instead declare a separate smp_operations structure for the CA7 iMX7 which takes account of this difference by calling a seperate .smp_init_cpus function.
Thanks.
Signature · 2 lines
FTTC broadband for 0.8mile line: currently at 10.5Mbps down 400kbps up according to speedtest.net.
PATCH v2 5/9 ARM: imx: add msl support for imx7d
Quoted 10 lines · Russell King - ARM Linux
Quoted 6 lines · Frank.Li at freescale.com
From: Anson Huang <[email protected]>
Add i.MX7D MSL support.
Signed-off-by Anson Huang <[email protected]>Signed-off-by Frank Li <[email protected]>I'm not happy with this.
Sorry, what cause your unhappy?
Can you tell me detail?
best regards
Frank Li
Quoted 113 lines
Quoted 20 lines
void
imx_anatop_pre_suspend(void)
{arch/arm/mach-imx/anatop.c +11
-0+if (cpu_is_imx7d ()) { +/* PLL overwrite set */ +regmap_write (anatop,ANADIG_ARM_PLL +REG_SET ,1 <<20 ); +regmap_write (anatop,ANADIG_DDR_PLL +REG_SET ,1 <<19 ); +regmap_write (anatop,ANADIG_SYS_PLL +REG_SET ,1 <<17 ); +regmap_write (anatop,ANADIG_ENET_PLL +REG_SET ,1 <<13 ); +regmap_write (anatop,ANADIG_AUDIO_PLL +REG_SET ,1 <<24 ); +regmap_write (anatop,ANADIG_VIDEO_PLL +REG_SET ,1 <<24 ); +return ; + } +if (imx_mmdc_get_ddr_type () ==IMX_DDR_TYPE_LPDDR2 )imx_anatop_enable_2p5_pulldown (true);else @@ -86,6 +104,17 @@ void imx_anatop_pre_suspend(void)void imx_anatop_post_resume (void ) {arch/arm/mach-imx/anatop.c void imx_anatop_pre_suspend(void) · line 116
Quoted 10 lines
arch/arm/mach-imx/anatop.c +10
-0+if (cpu_is_imx7d ()) { +/* PLL overwrite clear */ +regmap_write (anatop,ANADIG_ARM_PLL +REG_CLR ,1 <<20 ); +regmap_write (anatop,ANADIG_DDR_PLL +REG_CLR ,1 <<19 ); +regmap_write (anatop,ANADIG_SYS_PLL +REG_CLR ,1 <<17 ); +regmap_write (anatop,ANADIG_ENET_PLL +REG_CLR ,1 <<13 ); +regmap_write (anatop,ANADIG_AUDIO_PLL +REG_CLR ,1 <<24 ); +regmap_write (anatop,ANADIG_VIDEO_PLL +REG_CLR ,1 <<24 ); +return ; + }Shouldn't both of these be determined by the compatible string rather than checking
__mxc_cpu_type?Quoted 14 lines
arch/arm/mach-imx/cpu.c +2
-0@@ -11,6 +11,8 @@unsigned int __mxc_cpu_type;EXPORT_SYMBOL (__mxc_cpu_type); +unsigned int __mxc_arch_type; +EXPORT_SYMBOL (__mxc_arch_type);static unsigned int imx_soc_revision;arch/arm/mach-imx/cpu.c void mxc_set_cpu_type(unsigned int type) · line 27
Quoted 7 lines
arch/arm/mach-imx/cpu.c +4
-0@@ -19,6 +21,11 @@ void mxc_set_cpu_type(unsigned int type) __mxc_cpu_type = type; } +void mxc_set_arch_type (unsigned int type) +{ + __mxc_arch_type = type; +}You're re-inventing the wheel here. Please get rid of
__mxc_arch_typeandmxc_set_arch_type()entirely.arch/arm/mach-imx/cpu.c line 42
Quoted 6 lines
arch/arm/mach-imx/cpu.c +2
-0@@ -38,6 +38,8 @@#define MXC_CPU_IMX6DL 0x61#define MXC_CPU_IMX6SX 0x62#define MXC_CPU_IMX6Q 0x63 +#define MXC_CPU_IMX7D 0x72 +#define MXC_ARCH_CA7 0xc07Get rid of
MXC_ARCH_CA7.arch/arm/mach-imx/cpu.c
Quoted 4 lines
arch/arm/mach-imx/cpu.c +4
-0+static inline bool arm_is_ca7 (void ) +{ +return __mxc_arch_type ==MXC_ARCH_CA7 ; +}And this function.
Quoted 11 lines
arch/arm/mach-imx/platsmp.c +1
-1@@ -60,11 +60,33 @@ static int imx_boot_secondary(unsigned int cpu, struct task_struct *idle)static void __init imx_smp_init_cpus (void ) {int i, ncores; +unsigned long arch_type; - ncores =scu_get_core_count (scu_base);arch/arm/mach-imx/platsmp.c static int imx_boot_secondary(unsigned int cpu, struct task_struct *idle) · line 74
Quoted 10 lines
arch/arm/mach-imx/platsmp.c +10
-0+ asmvolatile ( +".align 4\n" +"mrc p15, 0, %0, c0, c0, 0\n" + :"=r" (arch_type) + ); + +/* MIDR[15:4] defines ARCH type */ +mxc_set_arch_type ((arch_type >>4 ) &0xfff ); + +if (arm_is_ca7 ()) {Rather than the above, use:
if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A7) {here.
Even better would be to _not_ re-use
imx_smp_init_cpus(), but instead declare a separatesmp_operationsstructure for the CA7 iMX7 which takes account of this difference by calling a seperate .smp_init_cpus function.Thanks.
--
FTTC broadband for 0.8mile line: currently at 10.5Mbps down 400kbps up according to speedtest.net.
PATCH v2 5/9 ARM: imx: add msl support for imx7d
Quoted 7 lines · Zhi Li
Quoted 5 lines · Russell King - ARM Linux
Quoted 4 lines · Frank.Li at freescale.com
From: Anson Huang <[email protected]>
Add i.MX7D MSL support.
Quoted 8 lines
Quoted 5 lines
Quoted 2 lines
Signed-off-by Anson Huang <[email protected]>Signed-off-by Frank Li <[email protected]>I'm not happy with this.
Sorry, what cause your unhappy?
Can you tell me detail?
Please read the rest of Russell's mail and you'll find out.
rsc
Signature · 4 lines
Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
PATCH v2 5/9 ARM: imx: add msl support for imx7d
In reply to Zhi LiQuoted 7 lines · Zhi Li
Quoted 5 lines · Russell King - ARM Linux
Quoted 4 lines · Frank.Li at freescale.com
From: Anson Huang <[email protected]>
Add i.MX7D MSL support.
Quoted 8 lines
Quoted 5 lines
Quoted 2 lines
Signed-off-by Anson Huang <[email protected]>Signed-off-by Frank Li <[email protected]>I'm not happy with this.
Sorry, what cause your unhappy?
Can you tell me detail?
Please see comments in the rest of the email.
Quoted 113 lines
Quoted 113 lines
Quoted 20 lines
void
imx_anatop_pre_suspend(void)
{arch/arm/mach-imx/anatop.c +11
-0+if (cpu_is_imx7d ()) { +/* PLL overwrite set */ +regmap_write (anatop,ANADIG_ARM_PLL +REG_SET ,1 <<20 ); +regmap_write (anatop,ANADIG_DDR_PLL +REG_SET ,1 <<19 ); +regmap_write (anatop,ANADIG_SYS_PLL +REG_SET ,1 <<17 ); +regmap_write (anatop,ANADIG_ENET_PLL +REG_SET ,1 <<13 ); +regmap_write (anatop,ANADIG_AUDIO_PLL +REG_SET ,1 <<24 ); +regmap_write (anatop,ANADIG_VIDEO_PLL +REG_SET ,1 <<24 ); +return ; + } +if (imx_mmdc_get_ddr_type () ==IMX_DDR_TYPE_LPDDR2 )imx_anatop_enable_2p5_pulldown (true);else @@ -86,6 +104,17 @@ void imx_anatop_pre_suspend(void)void imx_anatop_post_resume (void ) {arch/arm/mach-imx/anatop.c void imx_anatop_pre_suspend(void) · line 116
Quoted 10 lines
arch/arm/mach-imx/anatop.c +10
-0+if (cpu_is_imx7d ()) { +/* PLL overwrite clear */ +regmap_write (anatop,ANADIG_ARM_PLL +REG_CLR ,1 <<20 ); +regmap_write (anatop,ANADIG_DDR_PLL +REG_CLR ,1 <<19 ); +regmap_write (anatop,ANADIG_SYS_PLL +REG_CLR ,1 <<17 ); +regmap_write (anatop,ANADIG_ENET_PLL +REG_CLR ,1 <<13 ); +regmap_write (anatop,ANADIG_AUDIO_PLL +REG_CLR ,1 <<24 ); +regmap_write (anatop,ANADIG_VIDEO_PLL +REG_CLR ,1 <<24 ); +return ; + }Shouldn't both of these be determined by the compatible string rather than checking
__mxc_cpu_type?Quoted 14 lines
arch/arm/mach-imx/cpu.c +2
-0@@ -11,6 +11,8 @@unsigned int __mxc_cpu_type;EXPORT_SYMBOL (__mxc_cpu_type); +unsigned int __mxc_arch_type; +EXPORT_SYMBOL (__mxc_arch_type);static unsigned int imx_soc_revision;arch/arm/mach-imx/cpu.c void mxc_set_cpu_type(unsigned int type) · line 27
Quoted 7 lines
arch/arm/mach-imx/cpu.c +4
-0@@ -19,6 +21,11 @@ void mxc_set_cpu_type(unsigned int type) __mxc_cpu_type = type; } +void mxc_set_arch_type (unsigned int type) +{ + __mxc_arch_type = type; +}You're re-inventing the wheel here. Please get rid of
__mxc_arch_typeandmxc_set_arch_type()entirely.arch/arm/mach-imx/cpu.c line 42
Quoted 6 lines
arch/arm/mach-imx/cpu.c +2
-0@@ -38,6 +38,8 @@#define MXC_CPU_IMX6DL 0x61#define MXC_CPU_IMX6SX 0x62#define MXC_CPU_IMX6Q 0x63 +#define MXC_CPU_IMX7D 0x72 +#define MXC_ARCH_CA7 0xc07Get rid of
MXC_ARCH_CA7.arch/arm/mach-imx/cpu.c
Quoted 4 lines
arch/arm/mach-imx/cpu.c +4
-0+static inline bool arm_is_ca7 (void ) +{ +return __mxc_arch_type ==MXC_ARCH_CA7 ; +}And this function.
Quoted 11 lines
arch/arm/mach-imx/platsmp.c +1
-1@@ -60,11 +60,33 @@ static int imx_boot_secondary(unsigned int cpu, struct task_struct *idle)static void __init imx_smp_init_cpus (void ) {int i, ncores; +unsigned long arch_type; - ncores =scu_get_core_count (scu_base);arch/arm/mach-imx/platsmp.c static int imx_boot_secondary(unsigned int cpu, struct task_struct *idle) · line 74
Quoted 10 lines
arch/arm/mach-imx/platsmp.c +10
-0+ asmvolatile ( +".align 4\n" +"mrc p15, 0, %0, c0, c0, 0\n" + :"=r" (arch_type) + ); + +/* MIDR[15:4] defines ARCH type */ +mxc_set_arch_type ((arch_type >>4 ) &0xfff ); + +if (arm_is_ca7 ()) {Rather than the above, use:
if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A7) {here.
Even better would be to _not_ re-use
imx_smp_init_cpus(), but instead declare a separatesmp_operationsstructure for the CA7 iMX7 which takes account of this difference by calling a seperate .smp_init_cpus function.Thanks.
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FTTC broadband for 0.8mile line: currently at 10.5Mbps down 400kbps up according to speedtest.net.
Signature · 2 lines
FTTC broadband for 0.8mile line: currently at 10.5Mbps down 400kbps up according to speedtest.net.
PATCH v2 6/9 ARM: imx: add gpt system timer support for imx7d
In reply to Frank.Li at freescale.comFrom: Frank Li <[email protected]>
Add GPT system timer support for i.MX7D, it has same hardware as i.MX6DL.
Signed-off-by Frank Li <[email protected]>
Signed-off-by Anson Huang <[email protected]>
--- arch/arm/mach-imx/time.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
arch/arm/mach-imx/time.c +2 -1
@@ -321,7 +321,7 @@ static void __init _mxc_timer_init(int irq, tctl_val =V2_TCTL_FRR |V2_TCTL_WAITEN |MXC_TCTL_TEN ;if (clk_get_rate (clk_per) ==V2_TIMER_RATE_OSC_DIV8 ) { tctl_val |=V2_TCTL_CLK_OSC_DIV8 ; -if (cpu_is_imx6dl () ||cpu_is_imx6sx ()) { +if (cpu_is_imx6dl () ||cpu_is_imx6sx () ||cpu_is_imx7d ()) {/* 24 / 8 = 3 MHz */ __raw_writel (7 <<V2_TPRER_PRE24M , timer_base +MXC_TPRER );
@@ -383,3 +383,4 @@ CLOCKSOURCE_OF_DECLARE(mx53_timer, "fsl,imx53-gpt", mxc_timer_init_dt);CLOCKSOURCE_OF_DECLARE (mx6q_timer,"fsl,imx6q-gpt" , mxc_timer_init_dt);CLOCKSOURCE_OF_DECLARE (mx6sl_timer,"fsl,imx6sl-gpt" , mxc_timer_init_dt);CLOCKSOURCE_OF_DECLARE (mx6sx_timer,"fsl,imx6sx-gpt" , mxc_timer_init_dt); +CLOCKSOURCE_OF_DECLARE (mx7d_timer,"fsl,imx7d-gpt" , mxc_timer_init_dt);
Signature · 1 line
1.9.1
PATCH v2 7/9 ARM: imx: add imx7d clk tree support
In reply to Frank.Li at freescale.comFrom: Frank Li <[email protected]>
Add i.MX7D clk tree support.
Signed-off-by Anson Huang <[email protected]>
Signed-off-by Adrian Alonso <[email protected]>
Signed-off-by Frank Li <[email protected]>
--- arch/arm/mach-imx/clk-imx7d.c | 885 ++++++++++++++++++++++++++++++++++++++++++ arch/arm/mach-imx/clk-pllv3.c | 17 +- arch/arm/mach-imx/clk.h | 8 + 3 files changed, 909 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-imx/clk-imx7d.c
arch/arm/mach-imx/clk-imx7d.c new file +885 -0
@@ -0,0 +1,885 @@ +/* +* Copyright (C) 2014-2015 Freescale Semiconductor, Inc. +* +* The code contained herein is licensed under the GNU General Public +* License. You may obtain a copy of the GNU General Public License +* Version 2 or later at the following locations: +* +* http://www.opensource.org/licenses/gpl-license.html +* http://www.gnu.org/copyleft/gpl.html +*/ + +#include <dt-bindings/clock/imx7d-clock.h> +#include <linux/clk.h> +#include <linux/clkdev.h> +#include <linux/err.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> +#include <linux/types.h> + +#include "clk.h" +#include "common.h" + +static struct clk *clks[IMX7D_END_CLK ]; +static const char *arm_a7_sel[] = {"osc" ,"pll_arm_main_clk" , +"pll_enet_500m_clk" ,"pll_dram_main_clk" , +"pll_sys_main_clk" ,"pll_sys_pfd0_392m_clk" ,"pll_audio_main_clk" , +"pll_usb_main_clk" , }; + +static const char *arm_m4_sel[] = {"osc" ,"pll_sys_main_240m_clk" , +"pll_enet_250m_clk" ,"pll_sys_pfd2_270m_clk" , +"pll_dram_533m_clk" ,"pll_audio_main_clk" ,"pll_video_main_clk" , +"pll_usb_main_clk" , }; + +static const char *arm_m0_sel[] = {"osc" ,"pll_sys_main_120m_clk" , +"pll_enet_125m_clk" ,"pll_sys_pfd2_135m_clk" , +"pll_dram_533m_clk" ,"pll_audio_main_clk" ,"pll_video_main_clk" , +"pll_usb_main_clk" , }; + +static const char *axi_sel[] = {"osc" ,"pll_sys_pfd1_332m_clk" , +"pll_dram_533m_clk" ,"pll_enet_250m_clk" ,"pll_sys_pfd5_clk" , +"pll_audio_main_clk" ,"pll_video_main_clk" ,"pll_sys_pfd7_clk" , }; + +static const char *disp_axi_sel[] = {"osc" ,"pll_sys_pfd1_332m_clk" , +"pll_dram_533m_clk" ,"pll_enet_250m_clk" ,"pll_sys_pfd6_clk" , +"pll_sys_pfd7_clk" ,"pll_audio_main_clk" ,"pll_video_main_clk" , }; + +static const char *enet_axi_sel[] = {"osc" ,"pll_sys_pfd2_270m_clk" , +"pll_dram_533m_clk" ,"pll_enet_250m_clk" , +"pll_sys_main_240m_clk" ,"pll_audio_main_clk" ,"pll_video_main_clk" , +"pll_sys_pfd4_clk" , }; + +static const char *nand_usdhc_bus_sel[] = {"osc" ,"pll_sys_pfd2_270m_clk" , +"pll_dram_533m_clk" ,"pll_sys_main_240m_clk" , +"pll_sys_pfd2_135m_clk" ,"pll_sys_pfd6_clk" ,"pll_enet_250m_clk" , +"pll_audio_main_clk" , }; + +static const char *ahb_channel_sel[] = {"osc" ,"pll_sys_pfd2_135m_clk" , +"pll_dram_533m_clk" ,"pll_sys_pfd0_392m_clk" , +"pll_enet_125m_clk" ,"pll_usb_main_clk" ,"pll_audio_main_clk" , +"pll_video_main_clk" , }; + +static const char *dram_phym_sel[] = {"pll_dram_main_clk" , +"dram_phym_alt_clk" , }; + +static const char *dram_sel[] = {"pll_dram_main_clk" , +"dram_alt_clk" , }; + +static const char *dram_phym_alt_sel[] = {"osc" ,"pll_dram_533m_clk" , +"pll_sys_main_clk" ,"pll_enet_500m_clk" , +"pll_usb_main_clk" ,"pll_sys_pfd7_clk" ,"pll_audio_main_clk" , +"pll_video_main_clk" , }; + +static const char *dram_alt_sel[] = {"osc" ,"pll_dram_533m_clk" , +"pll_sys_main_clk" ,"pll_enet_500m_clk" , +"pll_enet_250m_clk" ,"pll_sys_pfd0_392m_clk" , +"pll_audio_main_clk" ,"pll_sys_pfd2_270m_clk" , }; + +static const char *usb_hsic_sel[] = {"osc" ,"pll_sys_main_clk" , +"pll_usb_main_clk" ,"pll_sys_pfd3_clk" ,"pll_sys_pfd4_clk" , +"pll_sys_pfd5_clk" ,"pll_sys_pfd6_clk" ,"pll_sys_pfd7_clk" , }; + +static const char *pcie_ctrl_sel[] = {"osc" ,"pll_enet_250m_clk" , +"pll_sys_main_240m_clk" ,"pll_sys_pfd2_270m_clk" , +"pll_dram_533m_clk" ,"pll_enet_500m_clk" , +"pll_sys_pfd1_332m_clk" ,"pll_sys_pfd6_clk" , }; + +static const char *pcie_phy_sel[] = {"osc" ,"pll_enet_100m_clk" , +"pll_enet_500m_clk" ,"ext_clk_1" ,"ext_clk_2" ,"ext_clk_3" , +"ext_clk_4" ,"pll_sys_pfd0_392m_clk" , }; + +static const char *epdc_pixel_sel[] = {"osc" ,"pll_sys_pfd1_332m_clk" , +"pll_dram_533m_clk" ,"pll_sys_main_clk" ,"pll_sys_pfd5_clk" , +"pll_sys_pfd6_clk" ,"pll_sys_pfd7_clk" ,"pll_video_main_clk" , }; + +static const char *lcdif_pixel_sel[] = {"osc" ,"pll_sys_pfd5_clk" , +"pll_dram_533m_clk" ,"ext_clk_3" ,"pll_sys_pfd4_clk" , +"pll_sys_pfd2_270m_clk" ,"pll_video_main_clk" , +"pll_usb_main_clk" , }; + +static const char *mipi_dsi_sel[] = {"osc" ,"pll_sys_pfd5_clk" , +"pll_sys_pfd3_clk" ,"pll_sys_main_clk" ,"pll_sys_pfd0_196m_clk" , +"pll_dram_533m_clk" ,"pll_video_main_clk" ,"pll_audio_main_clk" , }; + +static const char *mipi_csi_sel[] = {"osc" ,"pll_sys_pfd4_clk" , +"pll_sys_pfd3_clk" ,"pll_sys_main_clk" ,"pll_sys_pfd0_196m_clk" , +"pll_dram_533m_clk" ,"pll_video_main_clk" ,"pll_audio_main_clk" , }; + +static const char *mipi_dphy_sel[] = {"osc" ,"pll_sys_main_120m_clk" , +"pll_dram_533m_clk" ,"pll_sys_pfd5_clk" ,"ref_1m_clk" ,"ext_clk_2" , +"pll_video_main_clk" ,"ext_clk_3" , }; + +static const char *sai1_sel[] = {"osc" ,"pll_sys_pfd2_135m_clk" , +"pll_audio_main_clk" ,"pll_dram_533m_clk" ,"pll_video_main_clk" , +"pll_sys_pfd4_clk" ,"pll_enet_125m_clk" ,"ext_clk_2" , }; + +static const char *sai2_sel[] = {"osc" ,"pll_sys_pfd2_135m_clk" , +"pll_audio_main_clk" ,"pll_dram_533m_clk" ,"pll_video_main_clk" , +"pll_sys_pfd4_clk" ,"pll_enet_125m_clk" ,"ext_clk_2" , }; + +static const char *sai3_sel[] = {"osc" ,"pll_sys_pfd2_135m_clk" , +"pll_audio_main_clk" ,"pll_dram_533m_clk" ,"pll_video_main_clk" , +"pll_sys_pfd4_clk" ,"pll_enet_125m_clk" ,"ext_clk_3" , }; + +static const char *spdif_sel[] = {"osc" ,"pll_sys_pfd2_135m_clk" , +"pll_audio_main_clk" ,"pll_dram_533m_clk" ,"pll_video_main_clk" , +"pll_sys_pfd4_clk" ,"pll_enet_125m_clk" ,"ext_3_clk" , }; + +static const char *enet1_ref_sel[] = {"osc" ,"pll_enet_125m_clk" , +"pll_enet_50m_clk" ,"pll_enet_25m_clk" , +"pll_sys_main_120m_clk" ,"pll_audio_main_clk" ,"pll_video_main_clk" , +"ext_clk_4" , }; + +static const char *enet1_time_sel[] = {"osc" ,"pll_enet_100m_clk" , +"pll_audio_main_clk" ,"ext_clk_1" ,"ext_clk_2" ,"ext_clk_3" , +"ext_clk_4" ,"pll_video_main_clk" , }; + +static const char *enet2_ref_sel[] = {"osc" ,"pll_enet_125m_clk" , +"pll_enet_50m_clk" ,"pll_enet_25m_clk" , +"pll_sys_main_120m_clk" ,"pll_audio_main_clk" ,"pll_video_main_clk" , +"ext_clk_4" , }; + +static const char *enet2_time_sel[] = {"osc" ,"pll_enet_100m_clk" , +"pll_audio_main_clk" ,"ext_clk_1" ,"ext_clk_2" ,"ext_clk_3" , +"ext_clk_4" ,"pll_video_main_clk" , }; + +static const char *enet_phy_ref_sel[] = {"osc" ,"pll_enet_25m_clk" , +"pll_enet_50m_clk" ,"pll_enet_125m_clk" , +"pll_dram_533m_clk" ,"pll_audio_main_clk" ,"pll_video_main_clk" , +"pll_sys_pfd3_clk" , }; + +static const char *eim_sel[] = {"osc" ,"pll_sys_pfd2_135m_clk" , +"pll_sys_main_120m_clk" ,"pll_dram_533m_clk" , +"pll_sys_pfd2_270m_clk" ,"pll_sys_pfd3_clk" ,"pll_enet_125m_clk" , +"pll_usb_main_clk" , }; + +static const char *nand_sel[] = {"osc" ,"pll_sys_main_clk" , +"pll_dram_533m_clk" ,"pll_sys_pfd0_392m_clk" ,"pll_sys_pfd3_clk" , +"pll_enet_500m_clk" ,"pll_enet_250m_clk" , +"pll_video_main_clk" , }; + +static const char *qspi_sel[] = {"osc" ,"pll_sys_pfd4_clk" , +"pll_dram_533m_clk" ,"pll_enet_500m_clk" ,"pll_sys_pfd3_clk" , +"pll_sys_pfd2_270m_clk" ,"pll_sys_pfd6_clk" ,"pll_sys_pfd7_clk" , }; + +static const char *usdhc1_sel[] = {"osc" ,"pll_sys_pfd0_392m_clk" , +"pll_dram_533m_clk" ,"pll_enet_500m_clk" ,"pll_sys_pfd4_clk" , +"pll_sys_pfd2_270m_clk" ,"pll_sys_pfd6_clk" ,"pll_sys_pfd7_clk" , }; + +static const char *usdhc2_sel[] = {"osc" ,"pll_sys_pfd0_392m_clk" , +"pll_dram_533m_clk" ,"pll_enet_500m_clk" ,"pll_sys_pfd4_clk" , +"pll_sys_pfd2_270m_clk" ,"pll_sys_pfd6_clk" ,"pll_sys_pfd7_clk" , }; + +static const char *usdhc3_sel[] = {"osc" ,"pll_sys_pfd0_392m_clk" , +"pll_dram_533m_clk" ,"pll_enet_500m_clk" ,"pll_sys_pfd4_clk" , +"pll_sys_pfd2_270m_clk" ,"pll_sys_pfd6_clk" ,"pll_sys_pfd7_clk" , }; + +static const char *can1_sel[] = {"osc" ,"pll_sys_main_120m_clk" , +"pll_dram_533m_clk" ,"pll_sys_main_clk" , +"pll_enet_40m_clk" ,"pll_usb_main_clk" ,"ext_clk_1" , +"ext_clk_4" , }; + +static const char *can2_sel[] = {"osc" ,"pll_sys_main_120m_clk" , +"pll_dram_533m_clk" ,"pll_sys_main_clk" , +"pll_enet_40m_clk" ,"pll_usb_main_clk" ,"ext_clk_1" , +"ext_clk_3" , }; + +static const char *i2c1_sel[] = {"osc" ,"pll_sys_main_120m_clk" , +"pll_enet_50m_clk" ,"pll_dram_533m_clk" , +"pll_audio_main_clk" ,"pll_video_main_clk" ,"pll_usb_main_clk" , +"pll_sys_pfd2_135m_clk" , }; + +static const char *i2c2_sel[] = {"osc" ,"pll_sys_main_120m_clk" , +"pll_enet_50m_clk" ,"pll_dram_533m_clk" , +"pll_audio_main_clk" ,"pll_video_main_clk" ,"pll_usb_main_clk" , +"pll_sys_pfd2_135m_clk" , }; + +static const char *i2c3_sel[] = {"osc" ,"pll_sys_main_120m_clk" , +"pll_enet_50m_clk" ,"pll_dram_533m_clk" , +"pll_audio_main_clk" ,"pll_video_main_clk" ,"pll_usb_main_clk" , +"pll_sys_pfd2_135m_clk" , }; + +static const char *i2c4_sel[] = {"osc" ,"pll_sys_main_120m_clk" , +"pll_enet_50m_clk" ,"pll_dram_533m_clk" , +"pll_audio_main_clk" ,"pll_video_main_clk" ,"pll_usb_main_clk" , +"pll_sys_pfd2_135m_clk" , }; + +static const char *uart1_sel[] = {"osc" ,"pll_sys_main_240m_clk" , +"pll_enet_40m_clk" ,"pll_enet_100m_clk" , +"pll_sys_main_clk" ,"ext_clk_2" ,"ext_clk_4" , +"pll_usb_main_clk" , }; + +static const char *uart2_sel[] = {"osc" ,"pll_sys_main_240m_clk" , +"pll_enet_40m_clk" ,"pll_enet_100m_clk" , +"pll_sys_main_clk" ,"ext_clk_2" ,"ext_clk_3" , +"pll_usb_main_clk" , }; + +static const char *uart3_sel[] = {"osc" ,"pll_sys_main_240m_clk" , +"pll_enet_40m_clk" ,"pll_enet_100m_clk" , +"pll_sys_main_clk" ,"ext_clk_2" ,"ext_clk_4" , +"pll_usb_main_clk" , }; + +static const char *uart4_sel[] = {"osc" ,"pll_sys_main_240m_clk" , +"pll_enet_40m_clk" ,"pll_enet_100m_clk" , +"pll_sys_main_clk" ,"ext_clk_2" ,"ext_clk_3" , +"pll_usb_main_clk" , }; + +static const char *uart5_sel[] = {"osc" ,"pll_sys_main_240m_clk" , +"pll_enet_40m_clk" ,"pll_enet_100m_clk" , +"pll_sys_main_clk" ,"ext_clk_2" ,"ext_clk_4" , +"pll_usb_main_clk" , }; + +static const char *uart6_sel[] = {"osc" ,"pll_sys_main_240m_clk" , +"pll_enet_40m_clk" ,"pll_enet_100m_clk" , +"pll_sys_main_clk" ,"ext_clk_2" ,"ext_clk_3" , +"pll_usb_main_clk" , }; + +static const char *uart7_sel[] = {"osc" ,"pll_sys_main_240m_clk" , +"pll_enet_40m_clk" ,"pll_enet_100m_clk" , +"pll_sys_main_clk" ,"ext_clk_2" ,"ext_clk_4" , +"pll_usb_main_clk" , }; + +static const char *ecspi1_sel[] = {"osc" ,"pll_sys_main_240m_clk" , +"pll_enet_40m_clk" ,"pll_sys_main_120m_clk" , +"pll_sys_main_clk" ,"pll_sys_pfd4_clk" ,"pll_enet_250m_clk" , +"pll_usb_main_clk" , }; + +static const char *ecspi2_sel[] = {"osc" ,"pll_sys_main_240m_clk" , +"pll_enet_40m_clk" ,"pll_sys_main_120m_clk" , +"pll_sys_main_clk" ,"pll_sys_pfd4_clk" ,"pll_enet_250m_clk" , +"pll_usb_main_clk" , }; + +static const char *ecspi3_sel[] = {"osc" ,"pll_sys_main_240m_clk" , +"pll_enet_40m_clk" ,"pll_sys_main_120m_clk" , +"pll_sys_main_clk" ,"pll_sys_pfd4_clk" ,"pll_enet_250m_clk" , +"pll_usb_main_clk" , }; + +static const char *ecspi4_sel[] = {"osc" ,"pll_sys_main_240m_clk" , +"pll_enet_40m_clk" ,"pll_sys_main_120m_clk" , +"pll_sys_main_clk" ,"pll_sys_pfd4_clk" ,"pll_enet_250m_clk" , +"pll_usb_main_clk" , }; + +static const char *pwm1_sel[] = {"osc" ,"pll_enet_100m_clk" , +"pll_sys_main_120m_clk" ,"pll_enet_40m_clk" ,"pll_audio_main_clk" , +"ext_clk_1" ,"ref_1m_clk" ,"pll_video_main_clk" , }; + +static const char *pwm2_sel[] = {"osc" ,"pll_enet_100m_clk" , +"pll_sys_main_120m_clk" ,"pll_enet_40m_clk" ,"pll_audio_main_clk" , +"ext_clk_1" ,"ref_1m_clk" ,"pll_video_main_clk" , }; + +static const char *pwm3_sel[] = {"osc" ,"pll_enet_100m_clk" , +"pll_sys_main_120m_clk" ,"pll_enet_40m_clk" ,"pll_audio_main_clk" , +"ext_clk_2" ,"ref_1m_clk" ,"pll_video_main_clk" , }; + +static const char *pwm4_sel[] = {"osc" ,"pll_enet_100m_clk" , +"pll_sys_main_120m_clk" ,"pll_enet_40m_clk" ,"pll_audio_main_clk" , +"ext_clk_2" ,"ref_1m_clk" ,"pll_video_main_clk" , }; + +static const char *flextimer1_sel[] = {"osc" ,"pll_enet_100m_clk" , +"pll_sys_main_120m_clk" ,"pll_enet_40m_clk" ,"pll_audio_main_clk" , +"ext_clk_3" ,"ref_1m_clk" ,"pll_video_main_clk" , }; + +static const char *flextimer2_sel[] = {"osc" ,"pll_enet_100m_clk" , +"pll_sys_main_120m_clk" ,"pll_enet_40m_clk" ,"pll_audio_main_clk" , +"ext_clk_3" ,"ref_1m_clk" ,"pll_video_main_clk" , }; + +static const char *sim1_sel[] = {"osc" ,"pll_sys_pfd2_135m_clk" , +"pll_sys_main_120m_clk" ,"pll_dram_533m_clk" , +"pll_usb_main_clk" ,"pll_audio_main_clk" ,"pll_enet_125m_clk" , +"pll_sys_pfd7_clk" , }; + +static const char *sim2_sel[] = {"osc" ,"pll_sys_pfd2_135m_clk" , +"pll_sys_main_120m_clk" ,"pll_dram_533m_clk" , +"pll_usb_main_clk" ,"pll_video_main_clk" ,"pll_enet_125m_clk" , +"pll_sys_pfd7_clk" , }; + +static const char *gpt1_sel[] = {"osc" ,"pll_enet_100m_clk" , +"pll_sys_pfd0_392m_clk" ,"pll_enet_40m_clk" ,"pll_video_main_clk" , +"ref_1m_clk" ,"pll_audio_main_clk" ,"ext_clk_1" , }; + +static const char *gpt2_sel[] = {"osc" ,"pll_enet_100m_clk" , +"pll_sys_pfd0_392m_clk" ,"pll_enet_40m_clk" ,"pll_video_main_clk" , +"ref_1m_clk" ,"pll_audio_main_clk" ,"ext_clk_2" , }; + +static const char *gpt3_sel[] = {"osc" ,"pll_enet_100m_clk" , +"pll_sys_pfd0_392m_clk" ,"pll_enet_40m_clk" ,"pll_video_main_clk" , +"ref_1m_clk" ,"pll_audio_main_clk" ,"ext_clk_3" , }; + +static const char *gpt4_sel[] = {"osc" ,"pll_enet_100m_clk" , +"pll_sys_pfd0_392m_clk" ,"pll_enet_40m_clk" ,"pll_video_main_clk" , +"ref_1m_clk" ,"pll_audio_main_clk" ,"ext_clk_4" , }; + +static const char *trace_sel[] = {"osc" ,"pll_sys_pfd2_135m_clk" , +"pll_sys_main_120m_clk" ,"pll_dram_533m_clk" , +"pll_enet_125m_clk" ,"pll_usb_main_clk" ,"ext_clk_2" , +"ext_clk_3" , }; + +static const char *wdog_sel[] = {"osc" ,"pll_sys_pfd2_135m_clk" , +"pll_sys_main_120m_clk" ,"pll_dram_533m_clk" , +"pll_enet_125m_clk" ,"pll_usb_main_clk" ,"ref_1m_clk" , +"pll_sys_pfd1_166m_clk" , }; + +static const char *csi_mclk_sel[] = {"osc" ,"pll_sys_pfd2_135m_clk" , +"pll_sys_main_120m_clk" ,"pll_dram_533m_clk" , +"pll_enet_125m_clk" ,"pll_audio_main_clk" ,"pll_video_main_clk" , +"pll_usb_main_clk" , }; + +static const char *audio_mclk_sel[] = {"osc" ,"pll_sys_pfd2_135m_clk" , +"pll_sys_main_120m_clk" ,"pll_dram_533m_clk" , +"pll_enet_125m_clk" ,"pll_audio_main_clk" ,"pll_video_main_clk" , +"pll_usb_main_clk" , }; + +static const char *wrclk_sel[] = {"osc" ,"pll_enet_40m_clk" , +"pll_dram_533m_clk" ,"pll_usb_main_clk" , +"pll_sys_main_240m_clk" ,"pll_sys_pfd2_270m_clk" , +"pll_enet_500m_clk" ,"pll_sys_pfd7_clk" , }; + +static const char *clko1_sel[] = {"osc" ,"pll_sys_main_clk" , +"pll_sys_main_240m_clk" ,"pll_sys_pfd0_196m_clk" ,"pll_sys_pfd3_clk" , +"pll_enet_500m_clk" ,"pll_dram_533m_clk" ,"ref_1m_clk" , }; + +static const char *clko2_sel[] = {"osc" ,"pll_sys_main_240m_clk" , +"pll_sys_pfd0_392m_clk" ,"pll_sys_pfd1_166m_clk" ,"pll_sys_pfd4_clk" , +"pll_audio_main_clk" ,"pll_video_main_clk" ,"osc_32k_clk" , }; + +static const char *lvds1_sel[] = {"pll_arm_main_clk" , +"pll_sys_main_clk" ,"pll_sys_pfd0_392m_clk" ,"pll_sys_pfd1_332m_clk" , +"pll_sys_pfd2_270m_clk" ,"pll_sys_pfd3_clk" ,"pll_sys_pfd4_clk" , +"pll_sys_pfd5_clk" ,"pll_sys_pfd6_clk" ,"pll_sys_pfd7_clk" , +"pll_audio_main_clk" ,"pll_video_main_clk" ,"pll_enet_500m_clk" , +"pll_enet_250m_clk" ,"pll_enet_125m_clk" ,"pll_enet_100m_clk" , +"pll_enet_50m_clk" ,"pll_enet_40m_clk" ,"pll_enet_25m_clk" , +"pll_dram_main_clk" , }; + +static const char *pll_bypass_src_sel[] = {"osc" ,"dummy" , }; +static const char *pll_arm_bypass_sel[] = {"pll_arm_main" ,"pll_arm_main_src" , }; +static const char *pll_dram_bypass_sel[] = {"pll_dram_main" ,"pll_dram_main_src" , }; +static const char *pll_sys_bypass_sel[] = {"pll_sys_main" ,"pll_sys_main_src" , }; +static const char *pll_enet_bypass_sel[] = {"pll_enet_main" ,"pll_enet_main_src" , }; +static const char *pll_audio_bypass_sel[] = {"pll_audio_main" ,"pll_audio_main_src" , }; +static const char *pll_video_bypass_sel[] = {"pll_video_main" ,"pll_video_main_src" , }; + +static int const clks_init_on[]__initconst = { +IMX7D_ARM_A7_ROOT_CLK ,IMX7D_ARM_M4_ROOT_CLK ,IMX7D_ARM_M0_ROOT_CLK , +IMX7D_MAIN_AXI_ROOT_CLK ,IMX7D_DISP_AXI_ROOT_CLK ,IMX7D_ENET_AXI_ROOT_CLK , +IMX7D_DRAM_PHYM_ROOT_CLK ,IMX7D_DRAM_ROOT_CLK , +IMX7D_USB_HSIC_ROOT_CLK ,IMX7D_PCIE_CTRL_ROOT_CLK , +IMX7D_PCIE_PHY_ROOT_CLK ,IMX7D_EPDC_PIXEL_ROOT_CLK , +IMX7D_LCDIF_PIXEL_ROOT_CLK ,IMX7D_MIPI_DSI_ROOT_CLK , +IMX7D_MIPI_CSI_ROOT_CLK ,IMX7D_MIPI_DPHY_ROOT_CLK ,IMX7D_SAI1_ROOT_CLK , +IMX7D_SAI2_ROOT_CLK ,IMX7D_SAI3_ROOT_CLK ,IMX7D_SPDIF_ROOT_CLK , +IMX7D_ENET1_REF_ROOT_CLK ,IMX7D_ENET1_TIME_ROOT_CLK , +IMX7D_ENET2_REF_ROOT_CLK ,IMX7D_ENET2_TIME_ROOT_CLK , +IMX7D_ENET_PHY_REF_ROOT_CLK ,IMX7D_EIM_ROOT_CLK ,IMX7D_NAND_ROOT_CLK , +IMX7D_QSPI_ROOT_CLK ,IMX7D_USDHC1_ROOT_CLK ,IMX7D_USDHC2_ROOT_CLK , +IMX7D_USDHC3_ROOT_CLK ,IMX7D_CAN1_ROOT_CLK ,IMX7D_CAN2_ROOT_CLK , +IMX7D_I2C1_ROOT_CLK ,IMX7D_I2C2_ROOT_CLK ,IMX7D_I2C3_ROOT_CLK , +IMX7D_I2C4_ROOT_CLK ,IMX7D_UART1_ROOT_CLK ,IMX7D_UART2_ROOT_CLK , +IMX7D_UART3_ROOT_CLK ,IMX7D_UART4_ROOT_CLK ,IMX7D_UART5_ROOT_CLK , +IMX7D_UART6_ROOT_CLK ,IMX7D_UART7_ROOT_CLK ,IMX7D_ECSPI1_ROOT_CLK , +IMX7D_ECSPI2_ROOT_CLK ,IMX7D_ECSPI3_ROOT_CLK ,IMX7D_ECSPI4_ROOT_CLK , +IMX7D_PWM1_ROOT_CLK ,IMX7D_PWM2_ROOT_CLK ,IMX7D_PWM3_ROOT_CLK , +IMX7D_PWM4_ROOT_CLK ,IMX7D_FLEXTIMER1_ROOT_CLK ,IMX7D_FLEXTIMER2_ROOT_CLK , +IMX7D_SIM1_ROOT_CLK ,IMX7D_SIM2_ROOT_CLK ,IMX7D_GPT1_ROOT_CLK , +IMX7D_GPT2_ROOT_CLK ,IMX7D_GPT3_ROOT_CLK ,IMX7D_GPT4_ROOT_CLK , +IMX7D_TRACE_ROOT_CLK ,IMX7D_CSI_MCLK_ROOT_CLK , +IMX7D_AUDIO_MCLK_ROOT_CLK ,IMX7D_WRCLK_ROOT_CLK , +}; + +static struct clk_onecell_data clk_data; + +static void __init imx7d_clocks_init (struct device_node *ccm_node) +{ +struct device_node *np; +void __iomem *base; +int i; + + clks[IMX7D_CLK_DUMMY ] =imx_clk_fixed ("dummy" ,0 ); + clks[IMX7D_OSC_24M_CLK ] =of_clk_get_by_name (ccm_node,"osc" ); + + np =of_find_compatible_node (NULL ,NULL ,"fsl,imx7d-anatop" ); + base =of_iomap (np,0 ); +WARN_ON (!base); + + clks[IMX7D_PLL_ARM_MAIN_SRC ] =imx_clk_mux ("pll_arm_main_src" , base +0x60 ,14 ,2 , pll_bypass_src_sel,ARRAY_SIZE (pll_bypass_src_sel)); + clks[IMX7D_PLL_DRAM_MAIN_SRC ] =imx_clk_mux ("pll_dram_main_src" , base +0x70 ,14 ,2 , pll_bypass_src_sel,ARRAY_SIZE (pll_bypass_src_sel)); + clks[IMX7D_PLL_SYS_MAIN_SRC ] =imx_clk_mux ("pll_sys_main_src" , base +0xb0 ,14 ,2 , pll_bypass_src_sel,ARRAY_SIZE (pll_bypass_src_sel)); + clks[IMX7D_PLL_ENET_MAIN_SRC ] =imx_clk_mux ("pll_enet_main_src" , base +0xe0 ,14 ,2 , pll_bypass_src_sel,ARRAY_SIZE (pll_bypass_src_sel)); + clks[IMX7D_PLL_AUDIO_MAIN_SRC ] =imx_clk_mux ("pll_audio_main_src" , base +0xf0 ,14 ,2 , pll_bypass_src_sel,ARRAY_SIZE (pll_bypass_src_sel)); + clks[IMX7D_PLL_VIDEO_MAIN_SRC ] =imx_clk_mux ("pll_video_main_src" , base +0x130 ,14 ,2 , pll_bypass_src_sel,ARRAY_SIZE (pll_bypass_src_sel)); + + clks[IMX7D_PLL_ARM_MAIN ] =imx_clk_pllv3 (IMX_PLLV3_SYS ,"pll_arm_main" ,"pll_arm_main_src" , base +0x60 ,0x7f ); + clks[IMX7D_PLL_DRAM_MAIN ] =imx_clk_pllv3 (IMX_PLLV3_SYS ,"pll_dram_main" ,"pll_dram_main_src" , base +0x70 ,0x7f ); + clks[IMX7D_PLL_SYS_MAIN ] =imx_clk_pllv3 (IMX_PLLV3_SYSV2 ,"pll_sys_main" ,"pll_sys_main_src" , base +0xb0 ,0x1 ); + clks[IMX7D_PLL_ENET_MAIN ] =imx_clk_pllv3 (IMX_PLLV3_ENET ,"pll_enet_main" ,"pll_enet_main_src" , base +0xe0 ,0x0 ); + clks[IMX7D_PLL_AUDIO_MAIN ] =imx_clk_pllv3 (IMX_PLLV3_AV ,"pll_audio_main" ,"pll_audio_main_src" , base +0xf0 ,0x7f ); + clks[IMX7D_PLL_VIDEO_MAIN ] =imx_clk_pllv3 (IMX_PLLV3_AV ,"pll_video_main" ,"pll_video_main_src" , base +0x130 ,0x7f ); + + clks[IMX7D_PLL_ARM_MAIN_BYPASS ] =imx_clk_mux_flags ("pll_arm_main_bypass" , base +0x60 ,16 ,1 , pll_arm_bypass_sel,ARRAY_SIZE (pll_arm_bypass_sel),CLK_SET_RATE_PARENT ); + clks[IMX7D_PLL_DRAM_MAIN_BYPASS ] =imx_clk_mux_flags ("pll_dram_main_bypass" , base +0x70 ,16 ,1 , pll_dram_bypass_sel,ARRAY_SIZE (pll_dram_bypass_sel),CLK_SET_RATE_PARENT ); + clks[IMX7D_PLL_SYS_MAIN_BYPASS ] =imx_clk_mux_flags ("pll_sys_main_bypass" , base +0xb0 ,16 ,1 , pll_sys_bypass_sel,ARRAY_SIZE (pll_sys_bypass_sel),CLK_SET_RATE_PARENT ); + clks[IMX7D_PLL_ENET_MAIN_BYPASS ] =imx_clk_mux_flags ("pll_enet_main_bypass" , base +0xe0 ,16 ,1 , pll_enet_bypass_sel,ARRAY_SIZE (pll_enet_bypass_sel),CLK_SET_RATE_PARENT ); + clks[IMX7D_PLL_AUDIO_MAIN_BYPASS ] =imx_clk_mux_flags ("pll_audio_main_bypass" , base +0xf0 ,16 ,1 , pll_audio_bypass_sel,ARRAY_SIZE (pll_audio_bypass_sel),CLK_SET_RATE_PARENT ); + clks[IMX7D_PLL_VIDEO_MAIN_BYPASS ] =imx_clk_mux_flags ("pll_video_main_bypass" , base +0x130 ,16 ,1 , pll_video_bypass_sel,ARRAY_SIZE (pll_video_bypass_sel),CLK_SET_RATE_PARENT ); + +clk_set_parent (clks[IMX7D_PLL_ARM_MAIN_BYPASS ], clks[IMX7D_PLL_ARM_MAIN ]); +clk_set_parent (clks[IMX7D_PLL_DRAM_MAIN_BYPASS ], clks[IMX7D_PLL_DRAM_MAIN ]); +clk_set_parent (clks[IMX7D_PLL_SYS_MAIN_BYPASS ], clks[IMX7D_PLL_SYS_MAIN ]); +clk_set_parent (clks[IMX7D_PLL_ENET_MAIN_BYPASS ], clks[IMX7D_PLL_ENET_MAIN ]); +clk_set_parent (clks[IMX7D_PLL_AUDIO_MAIN_BYPASS ], clks[IMX7D_PLL_AUDIO_MAIN ]); +clk_set_parent (clks[IMX7D_PLL_VIDEO_MAIN_BYPASS ], clks[IMX7D_PLL_VIDEO_MAIN ]); + + clks[IMX7D_PLL_ARM_MAIN_CLK ] =imx_clk_gate ("pll_arm_main_clk" ,"pll_arm_main_bypass" , base +0x60 ,13 ); + clks[IMX7D_PLL_DRAM_MAIN_CLK ] =imx_clk_gate ("pll_dram_main_clk" ,"pll_dram_main_bypass" , base +0x70 ,13 ); + clks[IMX7D_PLL_SYS_MAIN_CLK ] =imx_clk_gate ("pll_sys_main_clk" ,"pll_sys_main_bypass" , base +0xb0 ,13 ); + clks[IMX7D_PLL_AUDIO_MAIN_CLK ] =imx_clk_gate ("pll_audio_main_clk" ,"pll_audio_main_bypass" , base +0xf0 ,13 ); + clks[IMX7D_PLL_VIDEO_MAIN_CLK ] =imx_clk_gate ("pll_video_main_clk" ,"pll_video_main_bypass" , base +0x130 ,13 ); + + clks[IMX7D_PLL_SYS_PFD0_392M_CLK ] =imx_clk_pfd ("pll_sys_pfd0_392m_clk" ,"pll_sys_main_clk" , base +0xc0 ,0 ); + clks[IMX7D_PLL_SYS_PFD1_332M_CLK ] =imx_clk_pfd ("pll_sys_pfd1_332m_clk" ,"pll_sys_main_clk" , base +0xc0 ,1 ); + clks[IMX7D_PLL_SYS_PFD2_270M_CLK ] =imx_clk_pfd ("pll_sys_pfd2_270m_clk" ,"pll_sys_main_clk" , base +0xc0 ,2 ); + + clks[IMX7D_PLL_SYS_PFD3_CLK ] =imx_clk_pfd ("pll_sys_pfd3_clk" ,"pll_sys_main_clk" , base +0xc0 ,3 ); + clks[IMX7D_PLL_SYS_PFD4_CLK ] =imx_clk_pfd ("pll_sys_pfd4_clk" ,"pll_sys_main_clk" , base +0xd0 ,0 ); + clks[IMX7D_PLL_SYS_PFD5_CLK ] =imx_clk_pfd ("pll_sys_pfd5_clk" ,"pll_sys_main_clk" , base +0xd0 ,1 ); + clks[IMX7D_PLL_SYS_PFD6_CLK ] =imx_clk_pfd ("pll_sys_pfd6_clk" ,"pll_sys_main_clk" , base +0xd0 ,2 ); + clks[IMX7D_PLL_SYS_PFD7_CLK ] =imx_clk_pfd ("pll_sys_pfd7_clk" ,"pll_sys_main_clk" , base +0xd0 ,3 ); + + clks[IMX7D_PLL_SYS_MAIN_480M ] =imx_clk_fixed_factor ("pll_sys_main_480m" ,"pll_sys_main_clk" ,1 ,1 ); + clks[IMX7D_PLL_SYS_MAIN_240M ] =imx_clk_fixed_factor ("pll_sys_main_240m" ,"pll_sys_main_clk" ,1 ,2 ); + clks[IMX7D_PLL_SYS_MAIN_120M ] =imx_clk_fixed_factor ("pll_sys_main_120m" ,"pll_sys_main_clk" ,1 ,4 ); + clks[IMX7D_PLL_DRAM_MAIN_533M ] =imx_clk_fixed_factor ("pll_dram_533m" ,"pll_dram_main_clk" ,1 ,2 ); + + clks[IMX7D_PLL_SYS_MAIN_480M_CLK ] =imx_clk_gate_flags ("pll_sys_main_480m_clk" ,"pll_sys_main_480m" , base +0xb0 ,4 ); + clks[IMX7D_PLL_SYS_MAIN_240M_CLK ] =imx_clk_gate_flags ("pll_sys_main_240m_clk" ,"pll_sys_main_240m" , base +0xb0 ,5 ); + clks[IMX7D_PLL_SYS_MAIN_120M_CLK ] =imx_clk_gate_flags ("pll_sys_main_120m_clk" ,"pll_sys_main_120m" , base +0xb0 ,6 ); + clks[IMX7D_PLL_DRAM_MAIN_533M_CLK ] =imx_clk_gate ("pll_dram_533m_clk" ,"pll_dram_533m" , base +0x70 ,12 ); + + clks[IMX7D_PLL_SYS_PFD0_196M ] =imx_clk_fixed_factor ("pll_sys_pfd0_196m" ,"pll_sys_pfd0_392m_clk" ,1 ,2 ); + clks[IMX7D_PLL_SYS_PFD1_166M ] =imx_clk_fixed_factor ("pll_sys_pfd1_166m" ,"pll_sys_pfd1_332m_clk" ,1 ,2 ); + clks[IMX7D_PLL_SYS_PFD2_135M ] =imx_clk_fixed_factor ("pll_sys_pfd2_135m" ,"pll_sys_pfd2_270m_clk" ,1 ,2 ); + + clks[IMX7D_PLL_SYS_PFD0_196M_CLK ] =imx_clk_gate_flags ("pll_sys_pfd0_196m_clk" ,"pll_sys_pfd0_196m" , base +0xb0 ,26 ); + clks[IMX7D_PLL_SYS_PFD1_166M_CLK ] =imx_clk_gate_flags ("pll_sys_pfd1_166m_clk" ,"pll_sys_pfd1_166m" , base +0xb0 ,27 ); + clks[IMX7D_PLL_SYS_PFD2_135M_CLK ] =imx_clk_gate_flags ("pll_sys_pfd2_135m_clk" ,"pll_sys_pfd2_135m" , base +0xb0 ,28 ); + + clks[IMX7D_PLL_ENET_MAIN_CLK ] =imx_clk_fixed_factor ("pll_enet_main_clk" ,"pll_enet_main_bypass" ,1 ,1 ); + clks[IMX7D_PLL_ENET_MAIN_500M ] =imx_clk_fixed_factor ("pll_enet_500m" ,"pll_enet_main_clk" ,1 ,2 ); + clks[IMX7D_PLL_ENET_MAIN_250M ] =imx_clk_fixed_factor ("pll_enet_250m" ,"pll_enet_main_clk" ,1 ,4 ); + clks[IMX7D_PLL_ENET_MAIN_125M ] =imx_clk_fixed_factor ("pll_enet_125m" ,"pll_enet_main_clk" ,1 ,8 ); + clks[IMX7D_PLL_ENET_MAIN_100M ] =imx_clk_fixed_factor ("pll_enet_100m" ,"pll_enet_main_clk" ,1 ,10 ); + clks[IMX7D_PLL_ENET_MAIN_50M ] =imx_clk_fixed_factor ("pll_enet_50m" ,"pll_enet_main_clk" ,1 ,20 ); + clks[IMX7D_PLL_ENET_MAIN_40M ] =imx_clk_fixed_factor ("pll_enet_40m" ,"pll_enet_main_clk" ,1 ,25 ); + clks[IMX7D_PLL_ENET_MAIN_25M ] =imx_clk_fixed_factor ("pll_enet_25m" ,"pll_enet_main_clk" ,1 ,40 ); + + clks[IMX7D_PLL_ENET_MAIN_500M_CLK ] =imx_clk_gate ("pll_enet_500m_clk" ,"pll_enet_500m" , base +0xe0 ,12 ); + clks[IMX7D_PLL_ENET_MAIN_250M_CLK ] =imx_clk_gate ("pll_enet_250m_clk" ,"pll_enet_250m" , base +0xe0 ,11 ); + clks[IMX7D_PLL_ENET_MAIN_125M_CLK ] =imx_clk_gate ("pll_enet_125m_clk" ,"pll_enet_125m" , base +0xe0 ,10 ); + clks[IMX7D_PLL_ENET_MAIN_100M_CLK ] =imx_clk_gate ("pll_enet_100m_clk" ,"pll_enet_100m" , base +0xe0 ,9 ); + clks[IMX7D_PLL_ENET_MAIN_50M_CLK ] =imx_clk_gate ("pll_enet_50m_clk" ,"pll_enet_50m" , base +0xe0 ,8 ); + clks[IMX7D_PLL_ENET_MAIN_40M_CLK ] =imx_clk_gate ("pll_enet_40m_clk" ,"pll_enet_40m" , base +0xe0 ,7 ); + clks[IMX7D_PLL_ENET_MAIN_25M_CLK ] =imx_clk_gate ("pll_enet_25m_clk" ,"pll_enet_25m" , base +0xe0 ,6 ); + + clks[IMX7D_LVDS1_OUT_SEL ] =imx_clk_mux ("lvds1_sel" , base +0x170 ,0 ,5 , lvds1_sel,ARRAY_SIZE (lvds1_sel)); + clks[IMX7D_LVDS1_OUT_CLK ] =imx_clk_gate_exclusive ("lvds1_out" ,"lvds1_sel" , base +0x170 ,5 ,BIT (6 )); + + np = ccm_node; + base =of_iomap (np,0 ); +WARN_ON (!base); + + clks[IMX7D_ARM_A7_ROOT_SRC ] =imx_clk_mux ("arm_a7_src" , base +0x8000 ,24 ,3 , arm_a7_sel,ARRAY_SIZE (arm_a7_sel)); + clks[IMX7D_ARM_M4_ROOT_SRC ] =imx_clk_mux ("arm_m4_src" , base +0x8080 ,24 ,3 , arm_m4_sel,ARRAY_SIZE (arm_m4_sel)); + clks[IMX7D_ARM_M0_ROOT_SRC ] =imx_clk_mux ("arm_m0_src" , base +0x8100 ,24 ,3 , arm_m0_sel,ARRAY_SIZE (arm_m0_sel)); + clks[IMX7D_MAIN_AXI_ROOT_SRC ] =imx_clk_mux ("axi_src" , base +0x8800 ,24 ,3 , axi_sel,ARRAY_SIZE (axi_sel)); + clks[IMX7D_DISP_AXI_ROOT_SRC ] =imx_clk_mux ("disp_axi_src" , base +0x8880 ,24 ,3 , disp_axi_sel,ARRAY_SIZE (disp_axi_sel)); + clks[IMX7D_ENET_AXI_ROOT_SRC ] =imx_clk_mux ("enet_axi_src" , base +0x8900 ,24 ,3 , enet_axi_sel,ARRAY_SIZE (enet_axi_sel)); + clks[IMX7D_NAND_USDHC_BUS_ROOT_SRC ] =imx_clk_mux ("nand_usdhc_src" , base +0x8980 ,24 ,3 , nand_usdhc_bus_sel,ARRAY_SIZE (nand_usdhc_bus_sel)); + clks[IMX7D_AHB_CHANNEL_ROOT_SRC ] =imx_clk_mux ("ahb_src" , base +0x9000 ,24 ,3 , ahb_channel_sel,ARRAY_SIZE (ahb_channel_sel)); + clks[IMX7D_DRAM_PHYM_ROOT_SRC ] =imx_clk_mux ("dram_phym_src" , base +0x9800 ,24 ,1 , dram_phym_sel,ARRAY_SIZE (dram_phym_sel)); + clks[IMX7D_DRAM_ROOT_SRC ] =imx_clk_mux ("dram_src" , base +0x9880 ,24 ,1 , dram_sel,ARRAY_SIZE (dram_sel)); + clks[IMX7D_DRAM_PHYM_ALT_ROOT_SRC ] =imx_clk_mux ("dram_phym_alt_src" , base +0xa000 ,24 ,3 , dram_phym_alt_sel,ARRAY_SIZE (dram_phym_alt_sel)); + clks[IMX7D_DRAM_ALT_ROOT_SRC ] =imx_clk_mux ("dram_alt_src" , base +0xa080 ,24 ,3 , dram_alt_sel,ARRAY_SIZE (dram_alt_sel)); + clks[IMX7D_USB_HSIC_ROOT_SRC ] =imx_clk_mux ("usb_hsic_src" , base +0xa100 ,24 ,3 , usb_hsic_sel,ARRAY_SIZE (usb_hsic_sel)); + clks[IMX7D_PCIE_CTRL_ROOT_SRC ] =imx_clk_mux ("pcie_ctrl_src" , base +0xa180 ,24 ,3 , pcie_ctrl_sel,ARRAY_SIZE (pcie_ctrl_sel)); + clks[IMX7D_PCIE_PHY_ROOT_SRC ] =imx_clk_mux ("pcie_phy_src" , base +0xa200 ,24 ,3 , pcie_phy_sel,ARRAY_SIZE (pcie_phy_sel)); + clks[IMX7D_EPDC_PIXEL_ROOT_SRC ] =imx_clk_mux ("epdc_pixel_src" , base +0xa280 ,24 ,3 , epdc_pixel_sel,ARRAY_SIZE (epdc_pixel_sel)); + clks[IMX7D_LCDIF_PIXEL_ROOT_SRC ] =imx_clk_mux ("lcdif_pixel_src" , base +0xa300 ,24 ,3 , lcdif_pixel_sel,ARRAY_SIZE (lcdif_pixel_sel)); + clks[IMX7D_MIPI_DSI_ROOT_SRC ] =imx_clk_mux ("mipi_dsi_src" , base +0xa380 ,24 ,3 , mipi_dsi_sel,ARRAY_SIZE (mipi_dsi_sel)); + clks[IMX7D_MIPI_CSI_ROOT_SRC ] =imx_clk_mux ("mipi_csi_src" , base +0xa400 ,24 ,3 , mipi_csi_sel,ARRAY_SIZE (mipi_csi_sel)); + clks[IMX7D_MIPI_DPHY_ROOT_SRC ] =imx_clk_mux ("mipi_dphy_src" , base +0xa480 ,24 ,3 , mipi_dphy_sel,ARRAY_SIZE (mipi_dphy_sel)); + clks[IMX7D_SAI1_ROOT_SRC ] =imx_clk_mux ("sai1_src" , base +0xa500 ,24 ,3 , sai1_sel,ARRAY_SIZE (sai1_sel)); + clks[IMX7D_SAI2_ROOT_SRC ] =imx_clk_mux ("sai2_src" , base +0xa580 ,24 ,3 , sai2_sel,ARRAY_SIZE (sai2_sel)); + clks[IMX7D_SAI3_ROOT_SRC ] =imx_clk_mux ("sai3_src" , base +0xa600 ,24 ,3 , sai3_sel,ARRAY_SIZE (sai3_sel)); + clks[IMX7D_SPDIF_ROOT_SRC ] =imx_clk_mux ("spdif_src" , base +0xa680 ,24 ,3 , spdif_sel,ARRAY_SIZE (spdif_sel)); + clks[IMX7D_ENET1_REF_ROOT_SRC ] =imx_clk_mux ("enet1_ref_src" , base +0xa700 ,24 ,3 , enet1_ref_sel,ARRAY_SIZE (enet1_ref_sel)); + clks[IMX7D_ENET1_TIME_ROOT_SRC ] =imx_clk_mux ("enet1_time_src" , base +0xa780 ,24 ,3 , enet1_time_sel,ARRAY_SIZE (enet1_time_sel)); + clks[IMX7D_ENET2_REF_ROOT_SRC ] =imx_clk_mux ("enet2_ref_src" , base +0xa800 ,24 ,3 , enet2_ref_sel,ARRAY_SIZE (enet2_ref_sel)); + clks[IMX7D_ENET2_TIME_ROOT_SRC ] =imx_clk_mux ("enet2_time_src" , base +0xa880 ,24 ,3 , enet2_time_sel,ARRAY_SIZE (enet2_time_sel)); + clks[IMX7D_ENET_PHY_REF_ROOT_SRC ] =imx_clk_mux ("enet_phy_ref_src" , base +0xa900 ,24 ,3 , enet_phy_ref_sel,ARRAY_SIZE (enet_phy_ref_sel)); + clks[IMX7D_EIM_ROOT_SRC ] =imx_clk_mux ("eim_src" , base +0xa980 ,24 ,3 , eim_sel,ARRAY_SIZE (eim_sel)); + clks[IMX7D_NAND_ROOT_SRC ] =imx_clk_mux ("nand_src" , base +0xaa00 ,24 ,3 , nand_sel,ARRAY_SIZE (nand_sel)); + clks[IMX7D_QSPI_ROOT_SRC ] =imx_clk_mux ("qspi_src" , base +0xaa80 ,24 ,3 , qspi_sel,ARRAY_SIZE (qspi_sel)); + clks[IMX7D_USDHC1_ROOT_SRC ] =imx_clk_mux ("usdhc1_src" , base +0xab00 ,24 ,3 , usdhc1_sel,ARRAY_SIZE (usdhc1_sel)); + clks[IMX7D_USDHC2_ROOT_SRC ] =imx_clk_mux ("usdhc2_src" , base +0xab80 ,24 ,3 , usdhc2_sel,ARRAY_SIZE (usdhc2_sel)); + clks[IMX7D_USDHC3_ROOT_SRC ] =imx_clk_mux ("usdhc3_src" , base +0xac00 ,24 ,3 , usdhc3_sel,ARRAY_SIZE (usdhc3_sel)); + clks[IMX7D_CAN1_ROOT_SRC ] =imx_clk_mux ("can1_src" , base +0xac80 ,24 ,3 , can1_sel,ARRAY_SIZE (can1_sel)); + clks[IMX7D_CAN2_ROOT_SRC ] =imx_clk_mux ("can2_src" , base +0xad00 ,24 ,3 , can2_sel,ARRAY_SIZE (can2_sel)); + clks[IMX7D_I2C1_ROOT_SRC ] =imx_clk_mux ("i2c1_src" , base +0xad80 ,24 ,3 , i2c1_sel,ARRAY_SIZE (i2c1_sel)); + clks[IMX7D_I2C2_ROOT_SRC ] =imx_clk_mux ("i2c2_src" , base +0xae00 ,24 ,3 , i2c2_sel,ARRAY_SIZE (i2c2_sel)); + clks[IMX7D_I2C3_ROOT_SRC ] =imx_clk_mux ("i2c3_src" , base +0xae80 ,24 ,3 , i2c3_sel,ARRAY_SIZE (i2c3_sel)); + clks[IMX7D_I2C4_ROOT_SRC ] =imx_clk_mux ("i2c4_src" , base +0xaf00 ,24 ,3 , i2c4_sel,ARRAY_SIZE (i2c4_sel)); + clks[IMX7D_UART1_ROOT_SRC ] =imx_clk_mux ("uart1_src" , base +0xaf80 ,24 ,3 , uart1_sel,ARRAY_SIZE (uart1_sel)); + clks[IMX7D_UART2_ROOT_SRC ] =imx_clk_mux ("uart2_src" , base +0xb000 ,24 ,3 , uart2_sel,ARRAY_SIZE (uart2_sel)); + clks[IMX7D_UART3_ROOT_SRC ] =imx_clk_mux ("uart3_src" , base +0xb080 ,24 ,3 , uart3_sel,ARRAY_SIZE (uart3_sel)); + clks[IMX7D_UART4_ROOT_SRC ] =imx_clk_mux ("uart4_src" , base +0xb100 ,24 ,3 , uart4_sel,ARRAY_SIZE (uart4_sel)); + clks[IMX7D_UART5_ROOT_SRC ] =imx_clk_mux ("uart5_src" , base +0xb180 ,24 ,3 , uart5_sel,ARRAY_SIZE (uart5_sel)); + clks[IMX7D_UART6_ROOT_SRC ] =imx_clk_mux ("uart6_src" , base +0xb200 ,24 ,3 , uart6_sel,ARRAY_SIZE (uart6_sel)); + clks[IMX7D_UART7_ROOT_SRC ] =imx_clk_mux ("uart7_src" , base +0xb280 ,24 ,3 , uart7_sel,ARRAY_SIZE (uart7_sel)); + clks[IMX7D_ECSPI1_ROOT_SRC ] =imx_clk_mux ("ecspi1_src" , base +0xb300 ,24 ,3 , ecspi1_sel,ARRAY_SIZE (ecspi1_sel)); + clks[IMX7D_ECSPI2_ROOT_SRC ] =imx_clk_mux ("ecspi2_src" , base +0xb380 ,24 ,3 , ecspi2_sel,ARRAY_SIZE (ecspi2_sel)); + clks[IMX7D_ECSPI3_ROOT_SRC ] =imx_clk_mux ("ecspi3_src" , base +0xb400 ,24 ,3 , ecspi3_sel,ARRAY_SIZE (ecspi3_sel)); + clks[IMX7D_ECSPI4_ROOT_SRC ] =imx_clk_mux ("ecspi4_src" , base +0xb480 ,24 ,3 , ecspi4_sel,ARRAY_SIZE (ecspi4_sel)); + clks[IMX7D_PWM1_ROOT_SRC ] =imx_clk_mux ("pwm1_src" , base +0xb500 ,24 ,3 , pwm1_sel,ARRAY_SIZE (pwm1_sel)); + clks[IMX7D_PWM2_ROOT_SRC ] =imx_clk_mux ("pwm2_src" , base +0xb580 ,24 ,3 , pwm2_sel,ARRAY_SIZE (pwm2_sel)); + clks[IMX7D_PWM3_ROOT_SRC ] =imx_clk_mux ("pwm3_src" , base +0xb600 ,24 ,3 , pwm3_sel,ARRAY_SIZE (pwm3_sel)); + clks[IMX7D_PWM4_ROOT_SRC ] =imx_clk_mux ("pwm4_src" , base +0xb680 ,24 ,3 , pwm4_sel,ARRAY_SIZE (pwm4_sel)); + clks[IMX7D_FLEXTIMER1_ROOT_SRC ] =imx_clk_mux ("flextimer1_src" , base +0xb700 ,24 ,3 , flextimer1_sel,ARRAY_SIZE (flextimer1_sel)); + clks[IMX7D_FLEXTIMER2_ROOT_SRC ] =imx_clk_mux ("flextimer2_src" , base +0xb780 ,24 ,3 , flextimer2_sel,ARRAY_SIZE (flextimer2_sel)); + clks[IMX7D_SIM1_ROOT_SRC ] =imx_clk_mux ("sim1_src" , base +0xb800 ,24 ,3 , sim1_sel,ARRAY_SIZE (sim1_sel)); + clks[IMX7D_SIM2_ROOT_SRC ] =imx_clk_mux ("sim2_src" , base +0xb880 ,24 ,3 , sim2_sel,ARRAY_SIZE (sim2_sel)); + clks[IMX7D_GPT1_ROOT_SRC ] =imx_clk_mux ("gpt1_src" , base +0xb900 ,24 ,3 , gpt1_sel,ARRAY_SIZE (gpt1_sel)); + clks[IMX7D_GPT2_ROOT_SRC ] =imx_clk_mux ("gpt2_src" , base +0xb980 ,24 ,3 , gpt2_sel,ARRAY_SIZE (gpt2_sel)); + clks[IMX7D_GPT3_ROOT_SRC ] =imx_clk_mux ("gpt3_src" , base +0xba00 ,24 ,3 , gpt3_sel,ARRAY_SIZE (gpt3_sel)); + clks[IMX7D_GPT4_ROOT_SRC ] =imx_clk_mux ("gpt4_src" , base +0xba80 ,24 ,3 , gpt4_sel,ARRAY_SIZE (gpt4_sel)); + clks[IMX7D_TRACE_ROOT_SRC ] =imx_clk_mux ("trace_src" , base +0xbb00 ,24 ,3 , trace_sel,ARRAY_SIZE (trace_sel)); + clks[IMX7D_WDOG_ROOT_SRC ] =imx_clk_mux ("wdog_src" , base +0xbb80 ,24 ,3 , wdog_sel,ARRAY_SIZE (wdog_sel)); + clks[IMX7D_CSI_MCLK_ROOT_SRC ] =imx_clk_mux ("csi_mclk_src" , base +0xbc00 ,24 ,3 , csi_mclk_sel,ARRAY_SIZE (csi_mclk_sel)); + clks[IMX7D_AUDIO_MCLK_ROOT_SRC ] =imx_clk_mux ("audio_mclk_src" , base +0xbc80 ,24 ,3 , audio_mclk_sel,ARRAY_SIZE (audio_mclk_sel)); + clks[IMX7D_WRCLK_ROOT_SRC ] =imx_clk_mux ("wrclk_src" , base +0xbd00 ,24 ,3 , wrclk_sel,ARRAY_SIZE (wrclk_sel)); + clks[IMX7D_CLKO1_ROOT_SRC ] =imx_clk_mux ("clko1_src" , base +0xbd80 ,24 ,3 , clko1_sel,ARRAY_SIZE (clko1_sel)); + clks[IMX7D_CLKO2_ROOT_SRC ] =imx_clk_mux ("clko2_src" , base +0xbe00 ,24 ,3 , clko2_sel,ARRAY_SIZE (clko2_sel)); + + clks[IMX7D_ARM_A7_ROOT_CG ] =imx_clk_gate ("arm_a7_cg" ,"arm_a7_src" , base +0x8000 ,28 ); + clks[IMX7D_ARM_M4_ROOT_CG ] =imx_clk_gate ("arm_m4_cg" ,"arm_m4_src" , base +0x8080 ,28 ); + clks[IMX7D_ARM_M0_ROOT_CG ] =imx_clk_gate ("arm_m0_cg" ,"arm_m0_src" , base +0x8100 ,28 ); + clks[IMX7D_MAIN_AXI_ROOT_CG ] =imx_clk_gate ("axi_cg" ,"axi_src" , base +0x8800 ,28 ); + clks[IMX7D_DISP_AXI_ROOT_CG ] =imx_clk_gate ("disp_axi_cg" ,"disp_axi_src" , base +0x8880 ,28 ); + clks[IMX7D_ENET_AXI_ROOT_CG ] =imx_clk_gate ("enet_axi_cg" ,"enet_axi_src" , base +0x8900 ,28 ); + clks[IMX7D_NAND_USDHC_BUS_ROOT_CG ] =imx_clk_gate ("nand_usdhc_cg" ,"nand_usdhc_src" , base +0x8980 ,28 ); + clks[IMX7D_AHB_CHANNEL_ROOT_CG ] =imx_clk_gate ("ahb_cg" ,"ahb_src" , base +0x9000 ,28 ); + clks[IMX7D_DRAM_PHYM_ROOT_CG ] =imx_clk_gate ("dram_phym_cg" ,"dram_phym_src" , base +0x9800 ,28 ); + clks[IMX7D_DRAM_ROOT_CG ] =imx_clk_gate ("dram_cg" ,"dram_src" , base +0x9880 ,28 ); + clks[IMX7D_DRAM_PHYM_ALT_ROOT_CG ] =imx_clk_gate ("dram_phym_alt_cg" ,"dram_phym_alt_src" , base +0xa000 ,28 ); + clks[IMX7D_DRAM_ALT_ROOT_CG ] =imx_clk_gate ("dram_alt_cg" ,"dram_alt_src" , base +0xa080 ,28 ); + clks[IMX7D_USB_HSIC_ROOT_CG ] =imx_clk_gate ("usb_hsic_cg" ,"usb_hsic_src" , base +0xa100 ,28 ); + clks[IMX7D_PCIE_CTRL_ROOT_CG ] =imx_clk_gate ("pcie_ctrl_cg" ,"pcie_ctrl_src" , base +0xa180 ,28 ); + clks[IMX7D_PCIE_PHY_ROOT_CG ] =imx_clk_gate ("pcie_phy_cg" ,"pcie_phy_src" , base +0xa200 ,28 ); + clks[IMX7D_EPDC_PIXEL_ROOT_CG ] =imx_clk_gate ("epdc_pixel_cg" ,"epdc_pixel_src" , base +0xa280 ,28 ); + clks[IMX7D_LCDIF_PIXEL_ROOT_CG ] =imx_clk_gate ("lcdif_pixel_cg" ,"lcdif_pixel_src" , base +0xa300 ,28 ); + clks[IMX7D_MIPI_DSI_ROOT_CG ] =imx_clk_gate ("mipi_dsi_cg" ,"mipi_dsi_src" , base +0xa380 ,28 ); + clks[IMX7D_MIPI_CSI_ROOT_CG ] =imx_clk_gate ("mipi_csi_cg" ,"mipi_csi_src" , base +0xa400 ,28 ); + clks[IMX7D_MIPI_DPHY_ROOT_CG ] =imx_clk_gate ("mipi_dphy_cg" ,"mipi_dphy_src" , base +0xa480 ,28 ); + clks[IMX7D_SAI1_ROOT_CG ] =imx_clk_gate ("sai1_cg" ,"sai1_src" , base +0xa500 ,28 ); + clks[IMX7D_SAI2_ROOT_CG ] =imx_clk_gate ("sai2_cg" ,"sai2_src" , base +0xa580 ,28 ); + clks[IMX7D_SAI3_ROOT_CG ] =imx_clk_gate ("sai3_cg" ,"sai3_src" , base +0xa600 ,28 ); + clks[IMX7D_SPDIF_ROOT_CG ] =imx_clk_gate ("spdif_cg" ,"spdif_src" , base +0xa680 ,28 ); + clks[IMX7D_ENET1_REF_ROOT_CG ] =imx_clk_gate ("enet1_ref_cg" ,"enet1_ref_src" , base +0xa700 ,28 ); + clks[IMX7D_ENET1_TIME_ROOT_CG ] =imx_clk_gate ("enet1_time_cg" ,"enet1_time_src" , base +0xa780 ,28 ); + clks[IMX7D_ENET2_REF_ROOT_CG ] =imx_clk_gate ("enet2_ref_cg" ,"enet2_ref_src" , base +0xa800 ,28 ); + clks[IMX7D_ENET2_TIME_ROOT_CG ] =imx_clk_gate ("enet2_time_cg" ,"enet2_time_src" , base +0xa880 ,28 ); + clks[IMX7D_ENET_PHY_REF_ROOT_CG ] =imx_clk_gate ("enet_phy_ref_cg" ,"enet_phy_ref_src" , base +0xa900 ,28 ); + clks[IMX7D_EIM_ROOT_CG ] =imx_clk_gate ("eim_cg" ,"eim_src" , base +0xa980 ,28 ); + clks[IMX7D_NAND_ROOT_CG ] =imx_clk_gate ("nand_cg" ,"nand_src" , base +0xaa00 ,28 ); + clks[IMX7D_QSPI_ROOT_CG ] =imx_clk_gate ("qspi_cg" ,"qspi_src" , base +0xaa80 ,28 ); + clks[IMX7D_USDHC1_ROOT_CG ] =imx_clk_gate ("usdhc1_cg" ,"usdhc1_src" , base +0xab00 ,28 ); + clks[IMX7D_USDHC2_ROOT_CG ] =imx_clk_gate ("usdhc2_cg" ,"usdhc2_src" , base +0xab80 ,28 ); + clks[IMX7D_USDHC3_ROOT_CG ] =imx_clk_gate ("usdhc3_cg" ,"usdhc3_src" , base +0xac00 ,28 ); + clks[IMX7D_CAN1_ROOT_CG ] =imx_clk_gate ("can1_cg" ,"can1_src" , base +0xac80 ,28 ); + clks[IMX7D_CAN2_ROOT_CG ] =imx_clk_gate ("can2_cg" ,"can2_src" , base +0xad00 ,28 ); + clks[IMX7D_I2C1_ROOT_CG ] =imx_clk_gate ("i2c1_cg" ,"i2c1_src" , base +0xad80 ,28 ); + clks[IMX7D_I2C2_ROOT_CG ] =imx_clk_gate ("i2c2_cg" ,"i2c2_src" , base +0xae00 ,28 ); + clks[IMX7D_I2C3_ROOT_CG ] =imx_clk_gate ("i2c3_cg" ,"i2c3_src" , base +0xae80 ,28 ); + clks[IMX7D_I2C4_ROOT_CG ] =imx_clk_gate ("i2c4_cg" ,"i2c4_src" , base +0xaf00 ,28 ); + clks[IMX7D_UART1_ROOT_CG ] =imx_clk_gate ("uart1_cg" ,"uart1_src" , base +0xaf80 ,28 ); + clks[IMX7D_UART2_ROOT_CG ] =imx_clk_gate ("uart2_cg" ,"uart2_src" , base +0xb000 ,28 ); + clks[IMX7D_UART3_ROOT_CG ] =imx_clk_gate ("uart3_cg" ,"uart3_src" , base +0xb080 ,28 ); + clks[IMX7D_UART4_ROOT_CG ] =imx_clk_gate ("uart4_cg" ,"uart4_src" , base +0xb100 ,28 ); + clks[IMX7D_UART5_ROOT_CG ] =imx_clk_gate ("uart5_cg" ,"uart5_src" , base +0xb180 ,28 ); + clks[IMX7D_UART6_ROOT_CG ] =imx_clk_gate ("uart6_cg" ,"uart6_src" , base +0xb200 ,28 ); + clks[IMX7D_UART7_ROOT_CG ] =imx_clk_gate ("uart7_cg" ,"uart7_src" , base +0xb280 ,28 ); + clks[IMX7D_ECSPI1_ROOT_CG ] =imx_clk_gate ("ecspi1_cg" ,"ecspi1_src" , base +0xb300 ,28 ); + clks[IMX7D_ECSPI2_ROOT_CG ] =imx_clk_gate ("ecspi2_cg" ,"ecspi2_src" , base +0xb380 ,28 ); + clks[IMX7D_ECSPI3_ROOT_CG ] =imx_clk_gate ("ecspi3_cg" ,"ecspi3_src" , base +0xb400 ,28 ); + clks[IMX7D_ECSPI4_ROOT_CG ] =imx_clk_gate ("ecspi4_cg" ,"ecspi4_src" , base +0xb480 ,28 ); + clks[IMX7D_PWM1_ROOT_CG ] =imx_clk_gate ("pwm1_cg" ,"pwm1_src" , base +0xb500 ,28 ); + clks[IMX7D_PWM2_ROOT_CG ] =imx_clk_gate ("pwm2_cg" ,"pwm2_src" , base +0xb580 ,28 ); + clks[IMX7D_PWM3_ROOT_CG ] =imx_clk_gate ("pwm3_cg" ,"pwm3_src" , base +0xb600 ,28 ); + clks[IMX7D_PWM4_ROOT_CG ] =imx_clk_gate ("pwm4_cg" ,"pwm4_src" , base +0xb680 ,28 ); + clks[IMX7D_FLEXTIMER1_ROOT_CG ] =imx_clk_gate ("flextimer1_cg" ,"flextimer1_src" , base +0xb700 ,28 ); + clks[IMX7D_FLEXTIMER2_ROOT_CG ] =imx_clk_gate ("flextimer2_cg" ,"flextimer2_src" , base +0xb780 ,28 ); + clks[IMX7D_SIM1_ROOT_CG ] =imx_clk_gate ("sim1_cg" ,"sim1_src" , base +0xb800 ,28 ); + clks[IMX7D_SIM2_ROOT_CG ] =imx_clk_gate ("sim2_cg" ,"sim2_src" , base +0xb880 ,28 ); + clks[IMX7D_GPT1_ROOT_CG ] =imx_clk_gate ("gpt1_cg" ,"gpt1_src" , base +0xb900 ,28 ); + clks[IMX7D_GPT2_ROOT_CG ] =imx_clk_gate ("gpt2_cg" ,"gpt2_src" , base +0xb980 ,28 ); + clks[IMX7D_GPT3_ROOT_CG ] =imx_clk_gate ("gpt3_cg" ,"gpt3_src" , base +0xbA00 ,28 ); + clks[IMX7D_GPT4_ROOT_CG ] =imx_clk_gate ("gpt4_cg" ,"gpt4_src" , base +0xbA80 ,28 ); + clks[IMX7D_TRACE_ROOT_CG ] =imx_clk_gate ("trace_cg" ,"trace_src" , base +0xbb00 ,28 ); + clks[IMX7D_WDOG_ROOT_CG ] =imx_clk_gate ("wdog_cg" ,"wdog_src" , base +0xbb80 ,28 ); + clks[IMX7D_CSI_MCLK_ROOT_CG ] =imx_clk_gate ("csi_mclk_cg" ,"csi_mclk_src" , base +0xbc00 ,28 ); + clks[IMX7D_AUDIO_MCLK_ROOT_CG ] =imx_clk_gate ("audio_mclk_cg" ,"audio_mclk_src" , base +0xbc80 ,28 ); + clks[IMX7D_WRCLK_ROOT_CG ] =imx_clk_gate ("wrclk_cg" ,"wrclk_src" , base +0xbd00 ,28 ); + clks[IMX7D_CLKO1_ROOT_CG ] =imx_clk_gate ("clko1_cg" ,"clko1_src" , base +0xbd80 ,28 ); + clks[IMX7D_CLKO2_ROOT_CG ] =imx_clk_gate ("clko2_cg" ,"clko2_src" , base +0xbe00 ,28 ); + + clks[IMX7D_MAIN_AXI_ROOT_PRE_DIV ] =imx_clk_divider ("axi_pre_div" ,"axi_cg" , base +0x8800 ,16 ,3 ); + clks[IMX7D_DISP_AXI_ROOT_PRE_DIV ] =imx_clk_divider ("disp_axi_pre_div" ,"disp_axi_cg" , base +0x8880 ,16 ,3 ); + clks[IMX7D_ENET_AXI_ROOT_PRE_DIV ] =imx_clk_divider ("enet_axi_pre_div" ,"enet_axi_cg" , base +0x8900 ,16 ,3 ); + clks[IMX7D_NAND_USDHC_BUS_ROOT_PRE_DIV ] =imx_clk_divider ("nand_usdhc_pre_div" ,"nand_usdhc_cg" , base +0x8980 ,16 ,3 ); + clks[IMX7D_AHB_CHANNEL_ROOT_PRE_DIV ] =imx_clk_divider ("ahb_pre_div" ,"ahb_cg" , base +0x9000 ,16 ,3 ); + clks[IMX7D_DRAM_PHYM_ALT_ROOT_PRE_DIV ] =imx_clk_divider ("dram_phym_alt_pre_div" ,"dram_phym_alt_cg" , base +0xa000 ,16 ,3 ); + clks[IMX7D_DRAM_ALT_ROOT_PRE_DIV ] =imx_clk_divider ("dram_alt_pre_div" ,"dram_alt_cg" , base +0xa080 ,16 ,3 ); + clks[IMX7D_USB_HSIC_ROOT_PRE_DIV ] =imx_clk_divider ("usb_hsic_pre_div" ,"usb_hsic_cg" , base +0xa100 ,16 ,3 ); + clks[IMX7D_PCIE_CTRL_ROOT_PRE_DIV ] =imx_clk_divider ("pcie_ctrl_pre_div" ,"pcie_ctrl_cg" , base +0xa180 ,16 ,3 ); + clks[IMX7D_PCIE_PHY_ROOT_PRE_DIV ] =imx_clk_divider ("pcie_phy_pre_div" ,"pcie_phy_cg" , base +0xa200 ,16 ,3 ); + clks[IMX7D_EPDC_PIXEL_ROOT_PRE_DIV ] =imx_clk_divider ("epdc_pixel_pre_div" ,"epdc_pixel_cg" , base +0xa280 ,16 ,3 ); + clks[IMX7D_LCDIF_PIXEL_ROOT_PRE_DIV ] =imx_clk_divider ("lcdif_pixel_pre_div" ,"lcdif_pixel_cg" , base +0xa300 ,16 ,3 ); + clks[IMX7D_MIPI_DSI_ROOT_PRE_DIV ] =imx_clk_divider ("mipi_dsi_pre_div" ,"mipi_dsi_cg" , base +0xa380 ,16 ,3 ); + clks[IMX7D_MIPI_CSI_ROOT_PRE_DIV ] =imx_clk_divider ("mipi_csi_pre_div" ,"mipi_csi_cg" , base +0xa400 ,16 ,3 ); + clks[IMX7D_MIPI_DPHY_ROOT_PRE_DIV ] =imx_clk_divider ("mipi_dphy_pre_div" ,"mipi_dphy_cg" , base +0xa480 ,16 ,3 ); + clks[IMX7D_SAI1_ROOT_PRE_DIV ] =imx_clk_divider ("sai1_pre_div" ,"sai1_cg" , base +0xa500 ,16 ,3 ); + clks[IMX7D_SAI2_ROOT_PRE_DIV ] =imx_clk_divider ("sai2_pre_div" ,"sai2_cg" , base +0xa580 ,16 ,3 ); + clks[IMX7D_SAI3_ROOT_PRE_DIV ] =imx_clk_divider ("sai3_pre_div" ,"sai3_cg" , base +0xa600 ,16 ,3 ); + clks[IMX7D_SPDIF_ROOT_PRE_DIV ] =imx_clk_divider ("spdif_pre_div" ,"spdif_cg" , base +0xa680 ,16 ,3 ); + clks[IMX7D_ENET1_REF_ROOT_PRE_DIV ] =imx_clk_divider ("enet1_ref_pre_div" ,"enet1_ref_cg" , base +0xa700 ,16 ,3 ); + clks[IMX7D_ENET1_TIME_ROOT_PRE_DIV ] =imx_clk_divider ("enet1_time_pre_div" ,"enet1_time_cg" , base +0xa780 ,16 ,3 ); + clks[IMX7D_ENET2_REF_ROOT_PRE_DIV ] =imx_clk_divider ("enet2_ref_pre_div" ,"enet2_ref_cg" , base +0xa800 ,16 ,3 ); + clks[IMX7D_ENET2_TIME_ROOT_PRE_DIV ] =imx_clk_divider ("enet2_time_pre_div" ,"enet2_time_cg" , base +0xa880 ,16 ,3 ); + clks[IMX7D_ENET_PHY_REF_ROOT_PRE_DIV ] =imx_clk_divider ("enet_phy_ref_pre_div" ,"enet_phy_ref_cg" , base +0xa900 ,16 ,3 ); + clks[IMX7D_EIM_ROOT_PRE_DIV ] =imx_clk_divider ("eim_pre_div" ,"eim_cg" , base +0xa980 ,16 ,3 ); + clks[IMX7D_NAND_ROOT_PRE_DIV ] =imx_clk_divider ("nand_pre_div" ,"nand_cg" , base +0xaa00 ,16 ,3 ); + clks[IMX7D_QSPI_ROOT_PRE_DIV ] =imx_clk_divider ("qspi_pre_div" ,"qspi_cg" , base +0xaa80 ,16 ,3 ); + clks[IMX7D_USDHC1_ROOT_PRE_DIV ] =imx_clk_divider ("usdhc1_pre_div" ,"usdhc1_cg" , base +0xab00 ,16 ,3 ); + clks[IMX7D_USDHC2_ROOT_PRE_DIV ] =imx_clk_divider ("usdhc2_pre_div" ,"usdhc2_cg" , base +0xab80 ,16 ,3 ); + clks[IMX7D_USDHC3_ROOT_PRE_DIV ] =imx_clk_divider ("usdhc3_pre_div" ,"usdhc3_cg" , base +0xac00 ,16 ,3 ); + clks[IMX7D_CAN1_ROOT_PRE_DIV ] =imx_clk_divider ("can1_pre_div" ,"can1_cg" , base +0xac80 ,16 ,3 ); + clks[IMX7D_CAN2_ROOT_PRE_DIV ] =imx_clk_divider ("can2_pre_div" ,"can2_cg" , base +0xad00 ,16 ,3 ); + clks[IMX7D_I2C1_ROOT_PRE_DIV ] =imx_clk_divider ("i2c1_pre_div" ,"i2c1_cg" , base +0xad80 ,16 ,3 ); + clks[IMX7D_I2C2_ROOT_PRE_DIV ] =imx_clk_divider ("i2c2_pre_div" ,"i2c2_cg" , base +0xae00 ,16 ,3 ); + clks[IMX7D_I2C3_ROOT_PRE_DIV ] =imx_clk_divider ("i2c3_pre_div" ,"i2c3_cg" , base +0xae80 ,16 ,3 ); + clks[IMX7D_I2C4_ROOT_PRE_DIV ] =imx_clk_divider ("i2c4_pre_div" ,"i2c4_cg" , base +0xaf00 ,16 ,3 ); + clks[IMX7D_UART1_ROOT_PRE_DIV ] =imx_clk_divider ("uart1_pre_div" ,"uart1_cg" , base +0xaf80 ,16 ,3 ); + clks[IMX7D_UART2_ROOT_PRE_DIV ] =imx_clk_divider ("uart2_pre_div" ,"uart2_cg" , base +0xb000 ,16 ,3 ); + clks[IMX7D_UART3_ROOT_PRE_DIV ] =imx_clk_divider ("uart3_pre_div" ,"uart3_cg" , base +0xb080 ,16 ,3 ); + clks[IMX7D_UART4_ROOT_PRE_DIV ] =imx_clk_divider ("uart4_pre_div" ,"uart4_cg" , base +0xb100 ,16 ,3 ); + clks[IMX7D_UART5_ROOT_PRE_DIV ] =imx_clk_divider ("uart5_pre_div" ,"uart5_cg" , base +0xb180 ,16 ,3 ); + clks[IMX7D_UART6_ROOT_PRE_DIV ] =imx_clk_divider ("uart6_pre_div" ,"uart6_cg" , base +0xb200 ,16 ,3 ); + clks[IMX7D_UART7_ROOT_PRE_DIV ] =imx_clk_divider ("uart7_pre_div" ,"uart7_cg" , base +0xb280 ,16 ,3 ); + clks[IMX7D_ECSPI1_ROOT_PRE_DIV ] =imx_clk_divider ("ecspi1_pre_div" ,"ecspi1_cg" , base +0xb300 ,16 ,3 ); + clks[IMX7D_ECSPI2_ROOT_PRE_DIV ] =imx_clk_divider ("ecspi2_pre_div" ,"ecspi2_cg" , base +0xb380 ,16 ,3 ); + clks[IMX7D_ECSPI3_ROOT_PRE_DIV ] =imx_clk_divider ("ecspi3_pre_div" ,"ecspi3_cg" , base +0xb400 ,16 ,3 ); + clks[IMX7D_ECSPI4_ROOT_PRE_DIV ] =imx_clk_divider ("ecspi4_pre_div" ,"ecspi4_cg" , base +0xb480 ,16 ,3 ); + clks[IMX7D_PWM1_ROOT_PRE_DIV ] =imx_clk_divider ("pwm1_pre_div" ,"pwm1_cg" , base +0xb500 ,16 ,3 ); + clks[IMX7D_PWM2_ROOT_PRE_DIV ] =imx_clk_divider ("pwm2_pre_div" ,"pwm2_cg" , base +0xb580 ,16 ,3 ); + clks[IMX7D_PWM3_ROOT_PRE_DIV ] =imx_clk_divider ("pwm3_pre_div" ,"pwm3_cg" , base +0xb600 ,16 ,3 ); + clks[IMX7D_PWM4_ROOT_PRE_DIV ] =imx_clk_divider ("pwm4_pre_div" ,"pwm4_cg" , base +0xb680 ,16 ,3 ); + clks[IMX7D_FLEXTIMER1_ROOT_PRE_DIV ] =imx_clk_divider ("flextimer1_pre_div" ,"flextimer1_cg" , base +0xb700 ,16 ,3 ); + clks[IMX7D_FLEXTIMER2_ROOT_PRE_DIV ] =imx_clk_divider ("flextimer2_pre_div" ,"flextimer2_cg" , base +0xb780 ,16 ,3 ); + clks[IMX7D_SIM1_ROOT_PRE_DIV ] =imx_clk_divider ("sim1_pre_div" ,"sim1_cg" , base +0xb800 ,16 ,3 ); + clks[IMX7D_SIM2_ROOT_PRE_DIV ] =imx_clk_divider ("sim2_pre_div" ,"sim2_cg" , base +0xb880 ,16 ,3 ); + clks[IMX7D_GPT1_ROOT_PRE_DIV ] =imx_clk_divider ("gpt1_pre_div" ,"gpt1_cg" , base +0xb900 ,16 ,3 ); + clks[IMX7D_GPT2_ROOT_PRE_DIV ] =imx_clk_divider ("gpt2_pre_div" ,"gpt2_cg" , base +0xb980 ,16 ,3 ); + clks[IMX7D_GPT3_ROOT_PRE_DIV ] =imx_clk_divider ("gpt3_pre_div" ,"gpt3_cg" , base +0xba00 ,16 ,3 ); + clks[IMX7D_GPT4_ROOT_PRE_DIV ] =imx_clk_divider ("gpt4_pre_div" ,"gpt4_cg" , base +0xba80 ,16 ,3 ); + clks[IMX7D_TRACE_ROOT_PRE_DIV ] =imx_clk_divider ("trace_pre_div" ,"trace_cg" , base +0xbb00 ,16 ,3 ); + clks[IMX7D_WDOG_ROOT_PRE_DIV ] =imx_clk_divider ("wdog_pre_div" ,"wdog_cg" , base +0xbb80 ,16 ,3 ); + clks[IMX7D_CSI_MCLK_ROOT_PRE_DIV ] =imx_clk_divider ("csi_mclk_pre_div" ,"csi_mclk_cg" , base +0xbc00 ,16 ,3 ); + clks[IMX7D_AUDIO_MCLK_ROOT_PRE_DIV ] =imx_clk_divider ("audio_mclk_pre_div" ,"audio_mclk_cg" , base +0xbc80 ,16 ,3 ); + clks[IMX7D_WRCLK_ROOT_PRE_DIV ] =imx_clk_divider ("wrclk_pre_div" ,"wrclk_cg" , base +0xbd00 ,16 ,3 ); + clks[IMX7D_CLKO1_ROOT_PRE_DIV ] =imx_clk_divider ("clko1_pre_div" ,"clko1_cg" , base +0xbd80 ,16 ,3 ); + clks[IMX7D_CLKO2_ROOT_PRE_DIV ] =imx_clk_divider ("clko2_pre_div" ,"clko2_cg" , base +0xbe00 ,16 ,3 ); + + clks[IMX7D_ARM_A7_ROOT_DIV ] =imx_clk_divider ("arm_a7_div" ,"arm_a7_cg" , base +0x8000 ,0 ,3 ); + clks[IMX7D_ARM_M4_ROOT_DIV ] =imx_clk_divider ("arm_m4_div" ,"arm_m4_cg" , base +0x8080 ,0 ,3 ); + clks[IMX7D_ARM_M0_ROOT_DIV ] =imx_clk_divider ("arm_m0_div" ,"arm_m0_cg" , base +0x8100 ,0 ,3 ); + clks[IMX7D_MAIN_AXI_ROOT_DIV ] =imx_clk_divider ("axi_post_div" ,"axi_pre_div" , base +0x8800 ,0 ,6 ); + clks[IMX7D_DISP_AXI_ROOT_DIV ] =imx_clk_divider ("disp_axi_post_div" ,"disp_axi_pre_div" , base +0x8880 ,0 ,6 ); + clks[IMX7D_ENET_AXI_ROOT_DIV ] =imx_clk_divider ("enet_axi_post_div" ,"enet_axi_pre_div" , base +0x8900 ,0 ,6 ); + clks[IMX7D_NAND_USDHC_BUS_ROOT_DIV ] =imx_clk_divider ("nand_usdhc_post_div" ,"nand_usdhc_pre_div" , base +0x8980 ,0 ,6 ); + clks[IMX7D_AHB_CHANNEL_ROOT_DIV ] =imx_clk_divider ("ahb_post_div" ,"ahb_pre_div" , base +0x9000 ,0 ,6 ); + clks[IMX7D_DRAM_ROOT_DIV ] =imx_clk_divider ("dram_post_div" ,"dram_cg" , base +0x9880 ,0 ,3 ); + clks[IMX7D_DRAM_PHYM_ALT_ROOT_DIV ] =imx_clk_divider ("dram_phym_alt_post_div" ,"dram_phym_alt_pre_div" , base +0xa000 ,0 ,3 ); + clks[IMX7D_DRAM_ALT_ROOT_DIV ] =imx_clk_divider ("dram_alt_post_div" ,"dram_alt_pre_div" , base +0xa080 ,0 ,3 ); + clks[IMX7D_USB_HSIC_ROOT_DIV ] =imx_clk_divider ("usb_hsic_post_div" ,"usb_hsic_pre_div" , base +0xa100 ,0 ,6 ); + clks[IMX7D_PCIE_CTRL_ROOT_DIV ] =imx_clk_divider ("pcie_ctrl_post_div" ,"pcie_ctrl_pre_div" , base +0xa180 ,0 ,6 ); + clks[IMX7D_PCIE_PHY_ROOT_DIV ] =imx_clk_divider ("pcie_phy_post_div" ,"pcie_phy_pre_div" , base +0xa200 ,0 ,6 ); + clks[IMX7D_EPDC_PIXEL_ROOT_DIV ] =imx_clk_divider ("epdc_pixel_post_div" ,"epdc_pixel_pre_div" , base +0xa280 ,0 ,6 ); + clks[IMX7D_LCDIF_PIXEL_ROOT_DIV ] =imx_clk_divider ("lcdif_pixel_post_div" ,"lcdif_pixel_pre_div" , base +0xa300 ,0 ,6 ); + clks[IMX7D_MIPI_DSI_ROOT_DIV ] =imx_clk_divider ("mipi_dsi_post_div" ,"mipi_dsi_pre_div" , base +0xa380 ,0 ,6 ); + clks[IMX7D_MIPI_CSI_ROOT_DIV ] =imx_clk_divider ("mipi_csi_post_div" ,"mipi_csi_pre_div" , base +0xa400 ,0 ,6 ); + clks[IMX7D_MIPI_DPHY_ROOT_DIV ] =imx_clk_divider ("mipi_dphy_post_div" ,"mipi_csi_dphy_div" , base +0xa480 ,0 ,6 ); + clks[IMX7D_SAI1_ROOT_DIV ] =imx_clk_divider ("sai1_post_div" ,"sai1_pre_div" , base +0xa500 ,0 ,6 ); + clks[IMX7D_SAI2_ROOT_DIV ] =imx_clk_divider ("sai2_post_div" ,"sai2_pre_div" , base +0xa580 ,0 ,6 ); + clks[IMX7D_SAI3_ROOT_DIV ] =imx_clk_divider ("sai3_post_div" ,"sai3_pre_div" , base +0xa600 ,0 ,6 ); + clks[IMX7D_SPDIF_ROOT_DIV ] =imx_clk_divider ("spdif_post_div" ,"spdif_pre_div" , base +0xa680 ,0 ,6 ); + clks[IMX7D_ENET1_REF_ROOT_DIV ] =imx_clk_divider ("enet1_ref_post_div" ,"enet1_ref_pre_div" , base +0xa700 ,0 ,6 ); + clks[IMX7D_ENET1_TIME_ROOT_DIV ] =imx_clk_divider ("enet1_time_post_div" ,"enet1_time_pre_div" , base +0xa780 ,0 ,6 ); + clks[IMX7D_ENET2_REF_ROOT_DIV ] =imx_clk_divider ("enet2_ref_post_div" ,"enet2_ref_pre_div" , base +0xa800 ,0 ,6 ); + clks[IMX7D_ENET2_TIME_ROOT_DIV ] =imx_clk_divider ("enet2_time_post_div" ,"enet2_time_pre_div" , base +0xa880 ,0 ,6 ); + clks[IMX7D_ENET_PHY_REF_ROOT_DIV ] =imx_clk_divider ("enet_phy_ref_post_div" ,"enet_phy_ref_pre_div" , base +0xa900 ,0 ,6 ); + clks[IMX7D_EIM_ROOT_DIV ] =imx_clk_divider ("eim_post_div" ,"eim_pre_div" , base +0xa980 ,0 ,6 ); + clks[IMX7D_NAND_ROOT_DIV ] =imx_clk_divider ("nand_post_div" ,"nand_pre_div" , base +0xaa00 ,0 ,6 ); + clks[IMX7D_QSPI_ROOT_DIV ] =imx_clk_divider ("qspi_post_div" ,"qspi_pre_div" , base +0xaa80 ,0 ,6 ); + clks[IMX7D_USDHC1_ROOT_DIV ] =imx_clk_divider ("usdhc1_post_div" ,"usdhc1_pre_div" , base +0xab00 ,0 ,6 ); + clks[IMX7D_USDHC2_ROOT_DIV ] =imx_clk_divider ("usdhc2_post_div" ,"usdhc2_pre_div" , base +0xab80 ,0 ,6 ); + clks[IMX7D_USDHC3_ROOT_DIV ] =imx_clk_divider ("usdhc3_post_div" ,"usdhc3_pre_div" , base +0xac00 ,0 ,6 ); + clks[IMX7D_CAN1_ROOT_DIV ] =imx_clk_divider ("can1_post_div" ,"can1_pre_div" , base +0xac80 ,0 ,6 ); + clks[IMX7D_CAN2_ROOT_DIV ] =imx_clk_divider ("can2_post_div" ,"can2_pre_div" , base +0xad00 ,0 ,6 ); + clks[IMX7D_I2C1_ROOT_DIV ] =imx_clk_divider ("i2c1_post_div" ,"i2c1_pre_div" , base +0xad80 ,0 ,6 ); + clks[IMX7D_I2C2_ROOT_DIV ] =imx_clk_divider ("i2c2_post_div" ,"i2c2_pre_div" , base +0xae00 ,0 ,6 ); + clks[IMX7D_I2C3_ROOT_DIV ] =imx_clk_divider ("i2c3_post_div" ,"i2c3_pre_div" , base +0xae80 ,0 ,6 ); + clks[IMX7D_I2C4_ROOT_DIV ] =imx_clk_divider ("i2c4_post_div" ,"i2c4_pre_div" , base +0xaf00 ,0 ,6 ); + clks[IMX7D_UART1_ROOT_DIV ] =imx_clk_divider ("uart1_post_div" ,"uart1_pre_div" , base +0xaf80 ,0 ,6 ); + clks[IMX7D_UART2_ROOT_DIV ] =imx_clk_divider ("uart2_post_div" ,"uart2_pre_div" , base +0xb000 ,0 ,6 ); + clks[IMX7D_UART3_ROOT_DIV ] =imx_clk_divider ("uart3_post_div" ,"uart3_pre_div" , base +0xb080 ,0 ,6 ); + clks[IMX7D_UART4_ROOT_DIV ] =imx_clk_divider ("uart4_post_div" ,"uart4_pre_div" , base +0xb100 ,0 ,6 ); + clks[IMX7D_UART5_ROOT_DIV ] =imx_clk_divider ("uart5_post_div" ,"uart5_pre_div" , base +0xb180 ,0 ,6 ); + clks[IMX7D_UART6_ROOT_DIV ] =imx_clk_divider ("uart6_post_div" ,"uart6_pre_div" , base +0xb200 ,0 ,6 ); + clks[IMX7D_UART7_ROOT_DIV ] =imx_clk_divider ("uart7_post_div" ,"uart7_pre_div" , base +0xb280 ,0 ,6 ); + clks[IMX7D_ECSPI1_ROOT_DIV ] =imx_clk_divider ("ecspi1_post_div" ,"ecspi1_pre_div" , base +0xb300 ,0 ,6 ); + clks[IMX7D_ECSPI2_ROOT_DIV ] =imx_clk_divider ("ecspi2_post_div" ,"ecspi2_pre_div" , base +0xb380 ,0 ,6 ); + clks[IMX7D_ECSPI3_ROOT_DIV ] =imx_clk_divider ("ecspi3_post_div" ,"ecspi3_pre_div" , base +0xb400 ,0 ,6 ); + clks[IMX7D_ECSPI4_ROOT_DIV ] =imx_clk_divider ("ecspi4_post_div" ,"ecspi4_pre_div" , base +0xb480 ,0 ,6 ); + clks[IMX7D_PWM1_ROOT_DIV ] =imx_clk_divider ("pwm1_post_div" ,"pwm1_pre_div" , base +0xb500 ,0 ,6 ); + clks[IMX7D_PWM2_ROOT_DIV ] =imx_clk_divider ("pwm2_post_div" ,"pwm2_pre_div" , base +0xb580 ,0 ,6 ); + clks[IMX7D_PWM3_ROOT_DIV ] =imx_clk_divider ("pwm3_post_div" ,"pwm3_pre_div" , base +0xb600 ,0 ,6 ); + clks[IMX7D_PWM4_ROOT_DIV ] =imx_clk_divider ("pwm4_post_div" ,"pwm4_pre_div" , base +0xb680 ,0 ,6 ); + clks[IMX7D_FLEXTIMER1_ROOT_DIV ] =imx_clk_divider ("flextimer1_post_div" ,"flextimer1_pre_div" , base +0xb700 ,0 ,6 ); + clks[IMX7D_FLEXTIMER2_ROOT_DIV ] =imx_clk_divider ("flextimer2_post_div" ,"flextimer2_pre_div" , base +0xb780 ,0 ,6 ); + clks[IMX7D_SIM1_ROOT_DIV ] =imx_clk_divider ("sim1_post_div" ,"sim1_pre_div" , base +0xb800 ,0 ,6 ); + clks[IMX7D_SIM2_ROOT_DIV ] =imx_clk_divider ("sim2_post_div" ,"sim2_pre_div" , base +0xb880 ,0 ,6 ); + clks[IMX7D_GPT1_ROOT_DIV ] =imx_clk_divider ("gpt1_post_div" ,"gpt1_pre_div" , base +0xb900 ,0 ,6 ); + clks[IMX7D_GPT2_ROOT_DIV ] =imx_clk_divider ("gpt2_post_div" ,"gpt2_pre_div" , base +0xb980 ,0 ,6 ); + clks[IMX7D_GPT3_ROOT_DIV ] =imx_clk_divider ("gpt3_post_div" ,"gpt3_pre_div" , base +0xba00 ,0 ,6 ); + clks[IMX7D_GPT4_ROOT_DIV ] =imx_clk_divider ("gpt4_post_div" ,"gpt4_pre_div" , base +0xba80 ,0 ,6 ); + clks[IMX7D_TRACE_ROOT_DIV ] =imx_clk_divider ("trace_post_div" ,"trace_pre_div" , base +0xbb00 ,0 ,6 ); + clks[IMX7D_WDOG_ROOT_DIV ] =imx_clk_divider ("wdog_post_div" ,"wdog_pre_div" , base +0xbb80 ,0 ,6 ); + clks[IMX7D_CSI_MCLK_ROOT_DIV ] =imx_clk_divider ("csi_mclk_post_div" ,"csi_mclk_pre_div" , base +0xbc00 ,0 ,6 ); + clks[IMX7D_AUDIO_MCLK_ROOT_DIV ] =imx_clk_divider ("audio_mclk_post_div" ,"audio_mclk_pre_div" , base +0xbc80 ,0 ,6 ); + clks[IMX7D_WRCLK_ROOT_DIV ] =imx_clk_divider ("wrclk_post_div" ,"wrclk_pre_div" , base +0xbd00 ,0 ,6 ); + clks[IMX7D_CLKO1_ROOT_DIV ] =imx_clk_divider ("clko1_post_div" ,"clko1_pre_div" , base +0xbd80 ,0 ,6 ); + clks[IMX7D_CLKO2_ROOT_DIV ] =imx_clk_divider ("clko2_post_div" ,"clko2_pre_div" , base +0xbe00 ,0 ,6 ); + + clks[IMX7D_ARM_A7_ROOT_CLK ] =imx_clk_gate2 ("arm_a7_root_clk" ,"arm_a7_div" , base +0x4000 ,0 ); + clks[IMX7D_ARM_M4_ROOT_CLK ] =imx_clk_gate2 ("arm_m4_root_clk" ,"arm_m4_div" , base +0x4010 ,0 ); + clks[IMX7D_ARM_M0_ROOT_CLK ] =imx_clk_gate2 ("arm_m0_root_clk" ,"arm_m0_div" , base +0x4020 ,0 ); + clks[IMX7D_MAIN_AXI_ROOT_CLK ] =imx_clk_gate2 ("main_axi_root_clk" ,"axi_post_div" , base +0x4040 ,0 ); + clks[IMX7D_DISP_AXI_ROOT_CLK ] =imx_clk_gate2 ("disp_axi_root_clk" ,"disp_axi_post_div" , base +0x4050 ,0 ); + clks[IMX7D_ENET_AXI_ROOT_CLK ] =imx_clk_gate2 ("enet_axi_root_clk" ,"enet_axi_post_div" , base +0x4060 ,0 ); + clks[IMX7D_OCRAM_CLK ] =imx_clk_gate2 ("ocram_clk" ,"axi_post_div" , base +0x4110 ,0 ); + clks[IMX7D_OCRAM_S_CLK ] =imx_clk_gate2 ("ocram_s_clk" ,"ahb_post_div" , base +0x4120 ,0 ); + clks[IMX7D_NAND_USDHC_BUS_ROOT_CLK ] =imx_clk_gate2 ("nand_usdhc_root_clk" ,"nand_usdhc_post_div" , base +0x4130 ,0 ); + clks[IMX7D_AHB_CHANNEL_ROOT_CLK ] =imx_clk_gate2 ("ahb_root_clk" ,"ahb_post_div" , base +0x4200 ,0 ); + clks[IMX7D_DRAM_ROOT_CLK ] =imx_clk_gate2 ("dram_root_clk" ,"dram_post_div" , base +0x4130 ,0 ); + clks[IMX7D_DRAM_PHYM_ROOT_CLK ] =imx_clk_gate2 ("dram_phym_root_clk" ,"dram_phym_cg" , base +0x4130 ,0 ); + clks[IMX7D_DRAM_PHYM_ALT_ROOT_CLK ] =imx_clk_gate2 ("dram_phym_alt_root_clk" ,"dram_phym_alt_post_div" , base +0x4130 ,0 ); + clks[IMX7D_DRAM_ALT_ROOT_CLK ] =imx_clk_gate2 ("dram_alt_root_clk" ,"dram_alt_post_div" , base +0x4130 ,0 ); + clks[IMX7D_USB_HSIC_ROOT_CLK ] =imx_clk_gate2 ("usb_hsic_root_clk" ,"usb_hsic_post_div" , base +0x4420 ,0 ); + clks[IMX7D_PCIE_CTRL_ROOT_CLK ] =imx_clk_gate2 ("pcie_ctrl_root_clk" ,"pcie_ctrl_post_div" , base +0x4600 ,0 ); + clks[IMX7D_PCIE_PHY_ROOT_CLK ] =imx_clk_gate2 ("pcie_phy_root_clk" ,"pcie_phy_post_div" , base +0x4600 ,0 ); + clks[IMX7D_EPDC_PIXEL_ROOT_CLK ] =imx_clk_gate2 ("epdc_pixel_root_clk" ,"epdc_pixel_post_div" , base +0x44a0 ,0 ); + clks[IMX7D_LCDIF_PIXEL_ROOT_CLK ] =imx_clk_gate2 ("lcdif_pixel_root_clk" ,"lcdif_pixel_post_div" , base +0x44b0 ,0 ); + clks[IMX7D_MIPI_DSI_ROOT_CLK ] =imx_clk_gate2 ("mipi_dsi_root_clk" ,"mipi_dsi_post_div" , base +0x4650 ,0 ); + clks[IMX7D_MIPI_CSI_ROOT_CLK ] =imx_clk_gate2 ("mipi_csi_root_clk" ,"mipi_csi_post_div" , base +0x4640 ,0 ); + clks[IMX7D_MIPI_DPHY_ROOT_CLK ] =imx_clk_gate2 ("mipi_dphy_root_clk" ,"mipi_dphy_post_div" , base +0x4660 ,0 ); + clks[IMX7D_SAI1_ROOT_CLK ] =imx_clk_gate2 ("sai1_root_clk" ,"sai1_post_div" , base +0x48c0 ,0 ); + clks[IMX7D_SAI2_ROOT_CLK ] =imx_clk_gate2 ("sai2_root_clk" ,"sai2_post_div" , base +0x48d0 ,0 ); + clks[IMX7D_SAI3_ROOT_CLK ] =imx_clk_gate2 ("sai3_root_clk" ,"sai3_post_div" , base +0x48e0 ,0 ); + clks[IMX7D_SPDIF_ROOT_CLK ] =imx_clk_gate2 ("spdif_root_clk" ,"spdif_post_div" , base +0x44d0 ,0 ); + clks[IMX7D_ENET1_REF_ROOT_CLK ] =imx_clk_gate2 ("enet1_ref_root_clk" ,"enet1_ref_post_div" , base +0x44e0 ,0 ); + clks[IMX7D_ENET1_TIME_ROOT_CLK ] =imx_clk_gate2 ("enet1_time_root_clk" ,"enet1_time_post_div" , base +0x44f0 ,0 ); + clks[IMX7D_ENET2_REF_ROOT_CLK ] =imx_clk_gate2 ("enet2_ref_root_clk" ,"enet2_ref_post_div" , base +0x4500 ,0 ); + clks[IMX7D_ENET2_TIME_ROOT_CLK ] =imx_clk_gate2 ("enet2_time_root_clk" ,"enet2_time_post_div" , base +0x4510 ,0 ); + clks[IMX7D_ENET_PHY_REF_ROOT_CLK ] =imx_clk_gate2 ("enet_phy_ref_root_clk" ,"enet_phy_ref_post_div" , base +0x4520 ,0 ); + clks[IMX7D_EIM_ROOT_CLK ] =imx_clk_gate2 ("eim_root_clk" ,"eim_post_div" , base +0x4160 ,0 ); + clks[IMX7D_NAND_ROOT_CLK ] =imx_clk_gate2 ("nand_root_clk" ,"nand_post_div" , base +0x4140 ,0 ); + clks[IMX7D_QSPI_ROOT_CLK ] =imx_clk_gate2 ("qspi_root_clk" ,"qspi_post_div" , base +0x4150 ,0 ); + clks[IMX7D_USDHC1_ROOT_CLK ] =imx_clk_gate2 ("usdhc1_root_clk" ,"usdhc1_post_div" , base +0x46c0 ,0 ); + clks[IMX7D_USDHC2_ROOT_CLK ] =imx_clk_gate2 ("usdhc2_root_clk" ,"usdhc2_post_div" , base +0x46d0 ,0 ); + clks[IMX7D_USDHC3_ROOT_CLK ] =imx_clk_gate2 ("usdhc3_root_clk" ,"usdhc3_post_div" , base +0x46e0 ,0 ); + clks[IMX7D_CAN1_ROOT_CLK ] =imx_clk_gate2 ("can1_root_clk" ,"can1_post_div" , base +0x4740 ,0 ); + clks[IMX7D_CAN2_ROOT_CLK ] =imx_clk_gate2 ("can2_root_clk" ,"can2_post_div" , base +0x4750 ,0 ); + clks[IMX7D_I2C1_ROOT_CLK ] =imx_clk_gate2 ("i2c1_root_clk" ,"i2c1_post_div" , base +0x4880 ,0 ); + clks[IMX7D_I2C2_ROOT_CLK ] =imx_clk_gate2 ("i2c2_root_clk" ,"i2c2_post_div" , base +0x4890 ,0 ); + clks[IMX7D_I2C3_ROOT_CLK ] =imx_clk_gate2 ("i2c3_root_clk" ,"i2c3_post_div" , base +0x48a0 ,0 ); + clks[IMX7D_I2C4_ROOT_CLK ] =imx_clk_gate2 ("i2c4_root_clk" ,"i2c4_post_div" , base +0x48b0 ,0 ); + clks[IMX7D_UART1_ROOT_CLK ] =imx_clk_gate2 ("uart1_root_clk" ,"uart1_post_div" , base +0x4940 ,0 ); + clks[IMX7D_UART2_ROOT_CLK ] =imx_clk_gate2 ("uart2_root_clk" ,"uart2_post_div" , base +0x4950 ,0 ); + clks[IMX7D_UART3_ROOT_CLK ] =imx_clk_gate2 ("uart3_root_clk" ,"uart3_post_div" , base +0x4960 ,0 ); + clks[IMX7D_UART4_ROOT_CLK ] =imx_clk_gate2 ("uart4_root_clk" ,"uart4_post_div" , base +0x4970 ,0 ); + clks[IMX7D_UART5_ROOT_CLK ] =imx_clk_gate2 ("uart5_root_clk" ,"uart5_post_div" , base +0x4980 ,0 ); + clks[IMX7D_UART6_ROOT_CLK ] =imx_clk_gate2 ("uart6_root_clk" ,"uart6_post_div" , base +0x4990 ,0 ); + clks[IMX7D_UART7_ROOT_CLK ] =imx_clk_gate2 ("uart7_root_clk" ,"uart7_post_div" , base +0x49a0 ,0 ); + clks[IMX7D_ECSPI1_ROOT_CLK ] =imx_clk_gate2 ("ecspi1_root_clk" ,"ecspi1_post_div" , base +0x4780 ,0 ); + clks[IMX7D_ECSPI2_ROOT_CLK ] =imx_clk_gate2 ("ecspi2_root_clk" ,"ecspi2_post_div" , base +0x4790 ,0 ); + clks[IMX7D_ECSPI3_ROOT_CLK ] =imx_clk_gate2 ("ecspi3_root_clk" ,"ecspi3_post_div" , base +0x47a0 ,0 ); + clks[IMX7D_ECSPI4_ROOT_CLK ] =imx_clk_gate2 ("ecspi4_root_clk" ,"ecspi4_post_div" , base +0x47b0 ,0 ); + clks[IMX7D_PWM1_ROOT_CLK ] =imx_clk_gate2 ("pwm1_root_clk" ,"pwm1_post_div" , base +0x4840 ,0 ); + clks[IMX7D_PWM2_ROOT_CLK ] =imx_clk_gate2 ("pwm2_root_clk" ,"pwm2_post_div" , base +0x4850 ,0 ); + clks[IMX7D_PWM3_ROOT_CLK ] =imx_clk_gate2 ("pwm3_root_clk" ,"pwm3_post_div" , base +0x4860 ,0 ); + clks[IMX7D_PWM4_ROOT_CLK ] =imx_clk_gate2 ("pwm4_root_clk" ,"pwm4_post_div" , base +0x4870 ,0 ); + clks[IMX7D_FLEXTIMER1_ROOT_CLK ] =imx_clk_gate2 ("flextimer1_root_clk" ,"flextimer1_post_div" , base +0x4800 ,0 ); + clks[IMX7D_FLEXTIMER2_ROOT_CLK ] =imx_clk_gate2 ("flextimer2_root_clk" ,"flextimer2_post_div" , base +0x4810 ,0 ); + clks[IMX7D_SIM1_ROOT_CLK ] =imx_clk_gate2 ("sim1_root_clk" ,"sim1_post_div" , base +0x4900 ,0 ); + clks[IMX7D_SIM2_ROOT_CLK ] =imx_clk_gate2 ("sim2_root_clk" ,"sim2_post_div" , base +0x4910 ,0 ); + clks[IMX7D_GPT1_ROOT_CLK ] =imx_clk_gate2 ("gpt1_root_clk" ,"gpt1_post_div" , base +0x47c0 ,0 ); + clks[IMX7D_GPT2_ROOT_CLK ] =imx_clk_gate2 ("gpt2_root_clk" ,"gpt2_post_div" , base +0x47d0 ,0 ); + clks[IMX7D_GPT3_ROOT_CLK ] =imx_clk_gate2 ("gpt3_root_clk" ,"gpt3_post_div" , base +0x47e0 ,0 ); + clks[IMX7D_GPT4_ROOT_CLK ] =imx_clk_gate2 ("gpt4_root_clk" ,"gpt4_post_div" , base +0x47f0 ,0 ); + clks[IMX7D_TRACE_ROOT_CLK ] =imx_clk_gate2 ("trace_root_clk" ,"trace_post_div" , base +0x4300 ,0 ); + clks[IMX7D_WDOG1_ROOT_CLK ] =imx_clk_gate2 ("wdog1_root_clk" ,"wdog_post_div" , base +0x49c0 ,0 ); + clks[IMX7D_WDOG2_ROOT_CLK ] =imx_clk_gate2 ("wdog2_root_clk" ,"wdog_post_div" , base +0x49d0 ,0 ); + clks[IMX7D_WDOG3_ROOT_CLK ] =imx_clk_gate2 ("wdog3_root_clk" ,"wdog_post_div" , base +0x49e0 ,0 ); + clks[IMX7D_WDOG4_ROOT_CLK ] =imx_clk_gate2 ("wdog4_root_clk" ,"wdog_post_div" , base +0x49f0 ,0 ); + clks[IMX7D_CSI_MCLK_ROOT_CLK ] =imx_clk_gate2 ("csi_mclk_root_clk" ,"csi_mclk_post_div" , base +0x4490 ,0 ); + clks[IMX7D_AUDIO_MCLK_ROOT_CLK ] =imx_clk_gate2 ("audio_mclk_root_clk" ,"audio_mclk_post_div" , base +0x4790 ,0 ); + clks[IMX7D_WRCLK_ROOT_CLK ] =imx_clk_gate2 ("wrclk_root_clk" ,"wrclk_post_div" , base +0x47a0 ,0 ); + + clks[IMX7D_GPT_3M_CLK ] =imx_clk_fixed_factor ("gpt_3m" ,"osc" ,1 ,8 ); + +for (i =0 ; i <ARRAY_SIZE (clks); i++) +if (IS_ERR (clks[i])) +pr_err ("i.MX7D clk %d: register failed with %ld\n" , + i,PTR_ERR (clks[i])); + + clk_data.clks = clks; + clk_data.clk_num =ARRAY_SIZE (clks); +of_clk_add_provider (np, of_clk_src_onecell_get, &clk_data); + +clk_register_clkdev (clks[IMX7D_GPT1_ROOT_CLK ],"ipg" ,"imx-gpt.0" ); +clk_register_clkdev (clks[IMX7D_GPT_3M_CLK ],"gpt_3m" ,"imx-gpt.0" ); + +for (i =0 ; i <IMX7D_END_CLK ; i++) +clk_prepare_enable (clks[i]); + +/* use old gpt clk setting, gpt1 root clk must be twice as gpt counter freq */ +clk_set_parent (clks[IMX7D_GPT1_ROOT_SRC ], clks[IMX7D_OSC_24M_CLK ]); + +/* +* init enet clock source: +* AXI clock source is 250Mhz +* Phy refrence clock is 25Mhz +* 1588 time clock source is 100Mhz +*/ +clk_set_parent (clks[IMX7D_ENET_AXI_ROOT_SRC ], clks[IMX7D_PLL_ENET_MAIN_250M_CLK ]); +clk_set_parent (clks[IMX7D_ENET_PHY_REF_ROOT_SRC ], clks[IMX7D_PLL_ENET_MAIN_25M_CLK ]); +clk_set_parent (clks[IMX7D_ENET1_TIME_ROOT_SRC ], clks[IMX7D_PLL_ENET_MAIN_100M_CLK ]); +clk_set_parent (clks[IMX7D_ENET2_TIME_ROOT_SRC ], clks[IMX7D_PLL_ENET_MAIN_100M_CLK ]); + +/* set uart module clock's parent clock source that must be great then 80Mhz */ +clk_set_parent (clks[IMX7D_UART1_ROOT_SRC ], clks[IMX7D_OSC_24M_CLK ]); + +} +CLK_OF_DECLARE (imx7d,"fsl,imx7d-ccm" , imx7d_clocks_init);
arch/arm/mach-imx/clk-pllv3.c +16 -1
@@ -18,18 +18,24 @@#include <linux/jiffies.h> #include <linux/err.h> #include "clk.h" +#include "common.h" +#include "hardware.h" #define PLL_NUM_OFFSET 0x10#define PLL_DENOM_OFFSET 0x20#define BM_PLL_POWER (0x1 << 12)#define BM_PLL_LOCK (0x1 << 31) +#define BM_PLL_ENABLE (0x1 << 13) +#define BM_PLL_BYPASS (0x1 << 16) +#define ENET_PLL_POWER (0x1 << 5)/** * struct clk_pllv3 - IMX PLL clock version 3 * @clk_hw: clock source * @base: base address of PLL registers * @powerup_set: set POWER bit to power up the PLL +* @powerdown: pll powerdown offset bit * @div_mask: mask of divider bits * @div_shift: shift of divider bits *
@@ -40,6 +46,7 @@ struct clk_pllv3 {struct clk_hw hw;void __iomem *base;bool powerup_set; +u32 powerdown;u32 div_mask;u32 div_shift; };
@@ -49,7 +56,7 @@ struct clk_pllv3 {static int clk_pllv3_wait_lock (struct clk_pllv3 *pll) {unsigned long timeout = jiffies +msecs_to_jiffies (10 ); -u32 val =readl_relaxed (pll->base) &BM_PLL_POWER ; +u32 val =readl_relaxed (pll->base) & pll->powerdown;/* No need to wait for lock when pll is not powered up */ if ((pll->powerup_set && !val) || (!pll->powerup_set && val))
@@ -309,12 +316,20 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,case IMX_PLLV3_ENET : ops = &clk_pllv3_enet_ops;break ; +case IMX_PLLV3_SYSV2 : + ops = &clk_pllv3_ops; +break ;default : ops = &clk_pllv3_ops; } pll->base = base; pll->div_mask = div_mask; +if (cpu_is_imx7d () &&strcmp (name,"pll_enet_main" ) ==0 ) + pll->powerdown =ENET_PLL_POWER ; +else + pll->powerdown =BM_PLL_POWER ; + init.name = name; init.ops = ops; init.flags =0 ;
arch/arm/mach-imx/clk.h +8 -0
@@ -23,6 +23,7 @@ enum imx_pllv3_type {IMX_PLLV3_USB_VF610 ,IMX_PLLV3_AV ,IMX_PLLV3_ENET , +IMX_PLLV3_SYSV2 }; struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
@@ -101,6 +102,13 @@ static inline struct clk *imx_clk_gate(const char *name, const char *parent, shift, 0, &imx_ccm_lock); } +static inline struct clk *imx_clk_gate_flags (const char *name,const char *parent, +void __iomem *reg,u8 shift) +{ +return clk_register_gate (NULL , name, parent,CLK_SET_RATE_PARENT , + reg, shift,CLK_GATE_SET_TO_DISABLE , &imx_ccm_lock); +} +static inline struct clk *imx_clk_gate_dis (const char *name,const char *parent,void __iomem *reg,u8 shift) {
Signature · 1 line
1.9.1
PATCH v2 8/9 arm: dts: add imx7d-sdb support
In reply to Frank.Li at freescale.comFrom: Frank Li <[email protected]>
add imx7d sdb board support
Signed-off-by Frank Li <[email protected]>
--- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/imx7d-sdb.dts | 723 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 725 insertions(+) create mode 100644 arch/arm/boot/dts/imx7d-sdb.dts
arch/arm/boot/dts/Makefile +2 -0
@@ -313,6 +313,8 @@ dtb-$(CONFIG_SOC_IMX6SX) += \ imx6sx-sabreauto.dtb \ imx6sx-sdb-reva.dtb \ imx6sx-sdb.dtb +dtb-$(CONFIG_SOC_IMX7D) += \ + imx7d-sdb.dtb dtb-$(CONFIG_SOC_LS1021A) += \ ls1021a-qds.dtb \ ls1021a-twr.dtb
arch/arm/boot/dts/imx7d-sdb.dts new file +723 -0
723 lines not on this page · raw message
Signature · 1 line
1.9.1
Fabio Estevam
maintainerPATCH v2 8/9 arm: dts: add imx7d-sdb support
Hi Frank,
arch/arm/boot/dts/imx7d-sdb.dts line 33
Quoted 4 lines · On Thu, Apr 16, 2015 at 4:17 PM, <[email protected]> wrote:
arch/arm/boot/dts/imx7d-sdb.dts new file +4
-0+ pxp_v4l2_out { + compatible = "fsl,imx7d-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + };
Not supported in mainline. Please remove it.
arch/arm/boot/dts/imx7d-sdb.dts line 89
Quoted 4 lines
arch/arm/boot/dts/imx7d-sdb.dts new file +4
-0+ bcmdhd_wlan_0: bcmdhd_wlan at 0 { + compatible = "android,bcmdhd_wlan"; + wlreg_on-supply = <&wlreg_on>; + };
Same here.
arch/arm/boot/dts/imx7d-sdb.dts line 102
Quoted 13 lines
arch/arm/boot/dts/imx7d-sdb.dts new file +13
-0+ + sound { + compatible = "fsl,imx7d-evk-wm8960", + "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + cpu-dai = <&sai1>; + audio-codec = <&codec>; + codec-master; + }; + + sound-hdmi { + compatible = "fsl,imx7d-sdb-sii902x", + "fsl,imx-audio-sii902x";
Not supported in mainline.
arch/arm/boot/dts/imx7d-sdb.dts line 317
Quoted 2 lines
arch/arm/boot/dts/imx7d-sdb.dts new file +2
-0+ sii902x: sii902x at 39 { + compatible = "SiI,sii902x";
Same here.
arch/arm/boot/dts/imx7d-sdb.dts line 352
Quoted 9 lines
+&iomuxc {
arch/arm/boot/dts/imx7d-sdb.dts new file +8
-0+ pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + imx7d-sdb { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 + MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x80000000 /* bt reg on */
Please avoid using 0x80000000 for pad configuration. Use the real value instead, so that we don't rely on the bootloader settings.
PATCH v2 9/9 ARM: config: imx_v6_v7_defconfig add imx7d support
In reply to Frank.Li at freescale.comFrom: Frank Li <[email protected]>
Add imx7d support
Signed-off-by Frank Li <[email protected]>
--- arch/arm/configs/imx_v6_v7_defconfig | 1 + 1 file changed, 1 insertion(+)
arch/arm/configs/imx_v6_v7_defconfig +1 -0
@@ -38,6 +38,7 @@ CONFIG_SOC_IMX53=y CONFIG_SOC_IMX6Q=y CONFIG_SOC_IMX6SL=y CONFIG_SOC_IMX6SX=y +CONFIG_SOC_IMX7D=y CONFIG_SOC_VF610=y CONFIG_PCI=y CONFIG_PCI_IMX6=y
Signature · 1 line
1.9.1