i.MX6-SabreAuto: EIM: pull PAD_EIM_D18 low for NOR probe

From: Alison Chaiken <[email protected]>

PAD_EIM_D18 must be pulled low at boot in order for the parallel NOR connected to the EIM switch to probe properly. Otherwise cfi_qry_present() may return "U-V-]" rather than "Q-R-Y" if the PAD_EIM_D18 is high. Add a nor-gpios property to the nor node in the SabreAuto device-tree and add a function to the imx-weim probe to set GPIO5 to drive the pad.

Signed-off-by Alison Chaiken <[email protected]>

---
 arch/arm/boot/dts/imx6qdl-sabreauto.dtsi |  1 +
 drivers/bus/imx-weim.c                   | 43 ++++++++++++++++++++++++++++++++
 2 files changed, 44 insertions(+)

arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +0 -0

index 009abd6..dd5e3bc 100644

arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +0 -0

 	};
 };

drivers/bus/imx-weim.c +36 -0

index 0958b69..b3c2ca6 100644
@@ -14,6 +14,8 @@
 #include <linux/mfd/syscon.h>
 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
 #include <linux/regmap.h>
+#include <linux/of_gpio.h>
+#include <linux/gpio.h>
 
 struct imx_weim_devtype {
 	unsigned int	cs_count;

@@ -108,6 +110,40 @@ err:
 	return -EINVAL;
 }
 
+/* set the GPIO to control PAD_EIM_D18 so cfi_qry_present() works properly */
+static int __init nor_gpio_setup(struct device_node *np, struct device *parent)
+{
+	unsigned nor_gpio, level;
+	enum of_gpio_flags of_flags;
+	int ret;
+
+	nor_gpio = of_get_named_gpio_flags(np, "nor-gpios", 0, &of_flags);
+
+	/* this child is not a NOR chip */
+	if (!nor_gpio)
+		return 0;
+
+	if (gpio_is_valid(nor_gpio)) {
+		ret = devm_gpio_request_one(parent, nor_gpio,
+					GPIOF_DIR_OUT, "nor-gpio");
+	} else {
+		ret = -ENODEV;
+		goto out;
+	}
+
+	if (ret < 0)
+		goto out;
+
+	level = ((of_flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1);
+
+	gpio_set_value(nor_gpio, level);
+
+	return 0;
+out:
+	dev_err(parent, "Unable to request EIM_D18 GPIO for NOR.\n");
+	return ret;
+}
+
 /* Parse and set the timing for this device. */
 static int __init weim_timing_setup(struct device_node *np, void __iomem *base,
 				    const struct imx_weim_devtype *devtype)

@@ -160,6 +196,13 @@ static int __init weim_parse_dt(struct platform_device *pdev,
 				child->full_name);
 			return ret;
 		}

+ linux-arm-kernel, maintainers, devicetree

Shawn, Sascha: should this driver be listed under the Freescale IMX MAINTAINERS entry?

Quoted 20 lines

From: Alison Chaiken <[email protected]>

PAD_EIM_D18 must be pulled low at boot in order for the parallel NOR connected to the EIM switch to probe properly. Otherwise cfi_qry_present() may return "U-V-]" rather than "Q-R-Y" if the PAD_EIM_D18 is high. Add a nor-gpios property to the nor node in the SabreAuto device-tree and add a function to the imx-weim probe to set GPIO5 to drive the pad.

Signed-off-by Alison Chaiken <[email protected]>

---
 arch/arm/boot/dts/imx6qdl-sabreauto.dtsi |  1 +
 drivers/bus/imx-weim.c                   | 43 ++++++++++++++++++++++++++++++++
 2 files changed, 44 insertions(+)

arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +0 -0

index 009abd6..dd5e3bc 100644

arch/arm/boot/dts/imx6qdl-sabreauto.dtsi line 457

Quoted 4 lines

arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +1 -0

@@ -454,5 +454,6 @@
 		bank-width = <2>;
 		fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
 				0x0000c000 0x1404a38e 0x00000000>;
+		nor-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;

Such a binding needs to be documented. Also, if it's going to be named generically like that, it needs to be generically useful and supported under MTD code, not platform-specific bus code.

So what pin is this, exactly? A write-protect pin? An address pin? A toaster control, where the toaster is keeping the flash too hot?

From: Alison Chaiken <[email protected]>

EIM_D18 pin of i.MX6 CPU is connected to the WEIM switch, to which pin DQ2 of the parallel NOR is also attached. Use GPIO5, pin 4 to steer the switch to connect the pin to the parallel NOR at boot. If the GPIO is not set LOW, the probe of the NOR fails when cfi_qry_present() returns "U-V-]" rather than "Q-R-Y" because bit 2 is erroneously high. Implement control of the GPIO by adding a steering-gpios property to the nor child node of the WEIM in the SabreAuto device-tree. Also add a function to the imx-weim probe to set GPIO5 to drive the pad.

Signed-off-by Alison Chaiken <[email protected]>

---
 Documentation/devicetree/bindings/bus/imx-weim.txt | 10 +++++
 arch/arm/boot/dts/imx6qdl-sabreauto.dtsi           |  1 +
 drivers/bus/imx-weim.c                             | 46 ++++++++++++++++++++++
 3 files changed, 57 insertions(+)

Documentation/devicetree/bindings/bus/imx-weim.txt +0 -0

index 6630d84..359fb26 100644
@@ -59,6 +59,15 @@ Timing property for child nodes. It is mandatory, not optional.
 			there are six registers: CSxGCR1, CSxGCR2, CSxRCR1,

From: Alison Chaiken <[email protected]>

Create an imx6-sabreauto-weim-nor.dtsi file whose inclusion in a DTS file sets GPIO5 to the level at boot that the WEIM-NOR device requires. The GPIO is set via the gpio-hogging mechanism.

Signed-off-by Alison Chaiken <[email protected]>

---
 arch/arm/boot/dts/imx6-sabreauto-weim-nor.dtsi | 56 ++++++++++++++++++++++++++
 1 file changed, 56 insertions(+)
 create mode 100644 arch/arm/boot/dts/imx6-sabreauto-weim-nor.dtsi

arch/arm/boot/dts/imx6-sabreauto-weim-nor.dtsi new file +15 -0

new file mode 100644
index 0000000..940a908
@@ -0,0 +1,56 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ * Copyright (c) 2015 Mentor Graphics Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/ {
+	soc {

arch/arm/boot/dts/imx6-sabreauto-weim-nor.dtsi new file +13 -0

+
+				weim_nor {
+					 gpio-hog;
+					 gpios = <4 0>;
+					 output-low;
+					 line-name = "weim-nor-gpio";
+				};
+			};
+		};
+	};
+};
+
+&weim {

From: Alison Chaiken <[email protected]>

Create an imx6qdl-sabreauto-weim-nor.dtsi file whose inclusion in a DTS file sets GPIO5 to the level at boot that the WEIM-NOR device requires. The GPIO is set via the gpio-hogging mechanism. Devices whose pinmux needs conflict with those of NOR are disabled.

Signed-off-by Alison Chaiken <[email protected]>

---
 arch/arm/boot/dts/imx6qdl-sabreauto-weim-nor.dtsi | 43 +++++++++++++++++++++++
 1 file changed, 43 insertions(+)
 create mode 100644 arch/arm/boot/dts/imx6qdl-sabreauto-weim-nor.dtsi

arch/arm/boot/dts/imx6qdl-sabreauto-weim-nor.dtsi new file +43 -0

new file mode 100644
index 0000000..a126335
@@ -0,0 +1,43 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ * Copyright (c) 2015 Mentor Graphics Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+&gpio5 {
+	weim_nor {
+		gpio-hog;
+		gpios = <4 0>;
+		output-low;
+		line-name = "weim-nor-gpio";
+	};
+};
+
+&weim {
+	status = "okay";
+};
+
+/* Disable devices that have pinmux conflicts with WEIM */
+
+&i2c3 {
+	status = "disabled";
+};
+
+&uart3 {
+	status = "disabled";
+};
+
+&ecspi1 {
+	status = "disabled";
+};
+
+&usdhc3 {
+	status = "disabled";
+};

Signature · 1 line

2.1.4

arch/arm/boot/dts/imx6-sabreauto-weim-nor.dtsi line 48

Quoted 7 lines · On Sun, Apr 19, 2015 at 02:02:23PM -0700…

+&i2c3 {

arch/arm/boot/dts/imx6-sabreauto-weim-nor.dtsi new file +6 -0

+	status = "disabled";
+};
+
+&uart3 {
+	status = "disabled";
+};

i2c3 and uart3 are not enabled for this board, why do you have to disable them here?

arch/arm/boot/dts/imx6-sabreauto-weim-nor.dtsi line 56

Quoted 8 lines

arch/arm/boot/dts/imx6-sabreauto-weim-nor.dtsi new file +8 -0

+
+&ecspi1 {
+	status = "disabled";
+};
+
+&usdhc3 {
+	status = "disabled";
+};

usdhc3 uses other pins than the weim controller. Why do you have to disable it?