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gpio: mvmfp: support newer MFP bit definitions

PATCH In review Rob Herring 3 participants 9 messages Mar 23, 2015 – May 5, 2015

Subsystems (7)
Arm i.MX and Layerscape GPIO MMC, SD and SDIO Tegra architecture support +3 more subsystems
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Rob Herring

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#0 lore raw

PATCH 1/1 gpio: mvmfp: support newer MFP bit definitions

From: Xiang Wang <[email protected]>

1. The bits 11..10 for mfp driver strength is only valid for aspen and old xscale family, for newer Marvell chip, this range has been moved to 12..11.
2. add sleep bit support

Signed-off-by Xiang Wang <[email protected]>
[robh: rebase to current mainline]
Signed-off-by Rob Herring <[email protected]>
---
 drivers/gpio/mvmfp.c | 14 ++------
 include/mvmfp.h      | 90 +++++++++++++++++++++++++++++++---------------------
 2 files changed, 55 insertions(+), 49 deletions(-)
drivers/gpio/mvmfp.c +2 -12
index 97bbe99..43ecf66 100644
@@ -43,18 +43,8 @@ void mfp_config(u32 *mfp_cfgs)
 
 		/* Write a mfg register as per configuration */
 		val = 0;
-		if (cfg_val & MFP_AF_FLAG)
-			/* Abstract and program Afternate-Func Selection */
-			val |= cfg_val & MFP_AF_MASK;
-		if (cfg_val & MFP_EDGE_FLAG)
-			/* Abstract and program Edge configuration */
-			val |= cfg_val & MFP_LPM_EDGE_MASK;
-		if (cfg_val & MFP_DRIVE_FLAG)
-			/* Abstract and program Drive configuration */
-			val |= cfg_val & MFP_DRIVE_MASK;
-		if (cfg_val & MFP_PULL_FLAG)
-			/* Abstract and program Pullup/down configuration */
-			val |= cfg_val & MFP_PULL_MASK;
+		if (cfg_val & MFP_VALUE_MASK)
+			val |= cfg_val & MFP_VALUE_MASK;
 
 		writel(val, p_mfpr);
 	} while (1);
include/mvmfp.h +53 -37

114 lines not on this page · raw message

Signature · 1 line
2.1.0
author
#1 lore raw

PATCH 1/1 mmc: remove the MMC_MODE_HC flag

High capacity support is not a host capability, but a device capability that is queried via the OCR. The flag in the operating conditions request argument can just be set unconditionally. This matches the Linux implementation.

Signed-off-by Rob Herring <[email protected]>
Cc Pantelis Antoniou <[email protected]>
---
 drivers/mmc/dw_mmc.c     | 2 +-
 drivers/mmc/fsl_esdhc.c  | 2 +-
 drivers/mmc/kona_sdhci.c | 1 -
 drivers/mmc/mmc.c        | 7 ++-----
 drivers/mmc/mvebu_mmc.c  | 2 +-
 drivers/mmc/mxsmmc.c     | 3 +--
 drivers/mmc/omap_hsmmc.c | 3 +--
 drivers/mmc/s3c_sdi.c    | 2 +-
 drivers/mmc/s5p_sdhci.c  | 1 -
 drivers/mmc/sh_mmcif.c   | 2 +-
 drivers/mmc/sunxi_mmc.c  | 2 +-
 drivers/mmc/tegra_mmc.c  | 2 +-
 drivers/mmc/zynq_sdhci.c | 2 --
 include/mmc.h            | 1 -
 14 files changed, 11 insertions(+), 21 deletions(-)
drivers/mmc/dw_mmc.c +1 -1
index 76fa0b0..53a8aca 100644
@@ -388,7 +388,7 @@ int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
 		host->cfg.host_caps |= MMC_MODE_4BIT;
 		host->cfg.host_caps &= ~MMC_MODE_8BIT;
 	}
-	host->cfg.host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_HC;
+	host->cfg.host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
 
 	host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
drivers/mmc/fsl_esdhc.c +1 -1
index db4d251..f99ad47 100644
@@ -620,7 +620,7 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
 		return -1;
 	}
 
-	cfg->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC;
+	cfg->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
 #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
 	cfg->cfg.host_caps |= MMC_MODE_DDR_52MHz;
 #endif
drivers/mmc/kona_sdhci.c +0 -1
index f804f4c..3653d00 100644
@@ -121,7 +121,6 @@ int kona_sdhci_init(int dev_index, u32 min_clk, u32 quirks)
 	host->name = "kona-sdhci";
 	host->ioaddr = reg_base;
 	host->quirks = quirks;
-	host->host_caps = MMC_MODE_HC;
 
 	if (init_kona_mmc_core(host)) {
 		free(host);
drivers/mmc/mmc.c +2 -5
index a13769e..ea00753 100644
@@ -359,15 +359,12 @@ static int mmc_send_op_cond_iter(struct mmc *mmc, struct mmc_cmd *cmd,
 	cmd->cmdidx = MMC_CMD_SEND_OP_COND;
 	cmd->resp_type = MMC_RSP_R3;
 	cmd->cmdarg = 0;
-	if (use_arg && !mmc_host_is_spi(mmc)) {
-		cmd->cmdarg =
+	if (use_arg && !mmc_host_is_spi(mmc))
+		cmd->cmdarg = OCR_HCS |
 			(mmc->cfg->voltages &
 			(mmc->op_cond_response & OCR_VOLTAGE_MASK)) |
 			(mmc->op_cond_response & OCR_ACCESS_MODE);
 
-		if (mmc->cfg->host_caps & MMC_MODE_HC)
-			cmd->cmdarg |= OCR_HCS;
-	}
 	err = mmc_send_cmd(mmc, cmd, NULL);
 	if (err)
 		return err;
drivers/mmc/mvebu_mmc.c +1 -1
index 8ca0904..056aef5 100644
@@ -418,7 +418,7 @@ static struct mmc_config mvebu_mmc_cfg = {
 	.f_min		= MVEBU_MMC_BASE_FAST_CLOCK / MVEBU_MMC_BASE_DIV_MAX,
 	.f_max		= MVEBU_MMC_CLOCKRATE_MAX,
 	.voltages	= MMC_VDD_32_33 | MMC_VDD_33_34,
-	.host_caps	= MMC_MODE_4BIT | MMC_MODE_HS | MMC_MODE_HC |
+	.host_caps	= MMC_MODE_4BIT | MMC_MODE_HS |
 			  MMC_MODE_HS_52MHz,
 	.part_type	= PART_TYPE_DOS,
 	.b_max		= CONFIG_SYS_MMC_MAX_BLK_COUNT,
drivers/mmc/mxsmmc.c +1 -2
index 2fa4eee..31fb3ab 100644
@@ -405,8 +405,7 @@ int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int))
 	priv->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
 
 	priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT |
-			 MMC_MODE_HS_52MHz | MMC_MODE_HS |
-			 MMC_MODE_HC;
+			 MMC_MODE_HS_52MHz | MMC_MODE_HS;
 
 	/*
 	 * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz
drivers/mmc/omap_hsmmc.c +1 -2
index dc725cb..8238a7e 100644
@@ -651,8 +651,7 @@ int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
 	if (priv_data == NULL)
 		return -1;
 
-	host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS |
-			     MMC_MODE_HC;
+	host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
 
 	switch (dev_index) {
 	case 0:
drivers/mmc/s3c_sdi.c +1 -1
index 1b5b705..02d1138 100644
@@ -298,7 +298,7 @@ int s3cmmc_initialize(bd_t *bis, int (*getcd)(struct mmc *),
 	cfg->name = "S3C MMC";
 	cfg->ops = &s3cmmc_ops;
 	cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
-	cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_HC | MMC_MODE_HS;
+	cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_HS;
 	cfg->f_min = 400000;
 	cfg->f_max = get_PCLK() / 2;
 	cfg->b_max = 0x80;
drivers/mmc/s5p_sdhci.c +0 -1
index 0eec731..8e1968a 100644
@@ -76,7 +76,6 @@ static int s5p_sdhci_core_init(struct sdhci_host *host)
 	host->set_control_reg = &s5p_sdhci_set_control_reg;
 	host->set_clock = set_mmc_clk;
 
-	host->host_caps = MMC_MODE_HC;
 	if (host->bus_width == 8)
 		host->host_caps |= MMC_MODE_8BIT;
drivers/mmc/sh_mmcif.c +1 -1
index 76ba93b..f92cf00 100644
@@ -577,7 +577,7 @@ static struct mmc_config sh_mmcif_cfg = {
 	.name		= DRIVER_NAME,
 	.ops		= &sh_mmcif_ops,
 	.host_caps	= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT |
-			  MMC_MODE_8BIT | MMC_MODE_HC,
+			  MMC_MODE_8BIT,
 	.voltages	= MMC_VDD_32_33 | MMC_VDD_33_34,
 	.b_max		= CONFIG_SYS_MMC_MAX_BLK_COUNT,
 };
drivers/mmc/sunxi_mmc.c +1 -1
index 2233545..0b7eb12 100644
@@ -449,7 +449,7 @@ struct mmc *sunxi_mmc_init(int sdc_no)
 
 	cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
 	cfg->host_caps = MMC_MODE_4BIT;
-	cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC;
+	cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
 	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 
 	cfg->f_min = 400000;
drivers/mmc/tegra_mmc.c +1 -1
index 2cd8cf1..ca41b4d 100644
@@ -559,7 +559,7 @@ static int do_mmc_init(int dev_index)
 		host->cfg.host_caps |= MMC_MODE_8BIT;
 	if (host->width >= 4)
 		host->cfg.host_caps |= MMC_MODE_4BIT;
-	host->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC;
+	host->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
 
 	/*
 	 * min freq is for card identification, and is the highest
drivers/mmc/zynq_sdhci.c +0 -2
index 7887f11..a92f12d 100644
@@ -29,8 +29,6 @@ int zynq_sdhci_init(phys_addr_t regbase)
 		       SDHCI_QUIRK_BROKEN_R1B;
 	host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
 
-	host->host_caps = MMC_MODE_HC;
-
 	add_sdhci(host, 52000000, 52000000 >> 9);
 	return 0;
 }
include/mmc.h +0 -1
index 2ad0f19..bdb003c 100644
@@ -55,7 +55,6 @@
 #define MMC_MODE_4BIT		(1 << 2)
 #define MMC_MODE_8BIT		(1 << 3)
 #define MMC_MODE_SPI		(1 << 4)
-#define MMC_MODE_HC		(1 << 5)
 #define MMC_MODE_DDR_52MHz	(1 << 6)
 
 #define SD_DATA_4BIT	0x00040000
Signature · 1 line
2.1.0
#2 lore raw

PATCH 1/1 mmc: remove the MMC_MODE_HC flag

Hi Rob,

Quoted 219 lines · Rob Herring

High capacity support is not a host capability, but a device capability that is queried via the OCR. The flag in the operating conditions request argument can just be set unconditionally. This matches the Linux implementation.

Signed-off-by Rob Herring <[email protected]>
Cc Pantelis Antoniou <[email protected]>

---

drivers/mmc/dw_mmc.c     | 2 +-
drivers/mmc/fsl_esdhc.c  | 2 +-
drivers/mmc/kona_sdhci.c | 1 -
drivers/mmc/mmc.c        | 7 ++-----
drivers/mmc/mvebu_mmc.c  | 2 +-
drivers/mmc/mxsmmc.c     | 3 +--
drivers/mmc/omap_hsmmc.c | 3 +--
drivers/mmc/s3c_sdi.c    | 2 +-
drivers/mmc/s5p_sdhci.c  | 1 -
drivers/mmc/sh_mmcif.c   | 2 +-
drivers/mmc/sunxi_mmc.c  | 2 +-
drivers/mmc/tegra_mmc.c  | 2 +-
drivers/mmc/zynq_sdhci.c | 2 --
include/mmc.h            | 1 -
14 files changed, 11 insertions(+), 21 deletions(-)
drivers/mmc/dw_mmc.c +1 -1
index 76fa0b0..53a8aca 100644
@@ -388,7 +388,7 @@ int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
 		host->cfg.host_caps |= MMC_MODE_4BIT;
 		host->cfg.host_caps &= ~MMC_MODE_8BIT;
 	}
-	host->cfg.host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_HC;
+	host->cfg.host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
 
 	host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
drivers/mmc/fsl_esdhc.c +1 -1
index db4d251..f99ad47 100644
@@ -620,7 +620,7 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
 		return -1;
 	}
 
-	cfg->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC;
+	cfg->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
 #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
 	cfg->cfg.host_caps |= MMC_MODE_DDR_52MHz;
 #endif
drivers/mmc/kona_sdhci.c +0 -1
index f804f4c..3653d00 100644
@@ -121,7 +121,6 @@ int kona_sdhci_init(int dev_index, u32 min_clk, u32 quirks)
 	host->name = "kona-sdhci";
 	host->ioaddr = reg_base;
 	host->quirks = quirks;
-	host->host_caps = MMC_MODE_HC;
 
 	if (init_kona_mmc_core(host)) {
 		free(host);
drivers/mmc/mmc.c +2 -5
index a13769e..ea00753 100644
@@ -359,15 +359,12 @@ static int mmc_send_op_cond_iter(struct mmc *mmc, struct mmc_cmd *cmd,
 	cmd->cmdidx = MMC_CMD_SEND_OP_COND;
 	cmd->resp_type = MMC_RSP_R3;
 	cmd->cmdarg = 0;
-	if (use_arg && !mmc_host_is_spi(mmc)) {
-		cmd->cmdarg =
+	if (use_arg && !mmc_host_is_spi(mmc))
+		cmd->cmdarg = OCR_HCS |
 			(mmc->cfg->voltages &
 			(mmc->op_cond_response & OCR_VOLTAGE_MASK)) |
 			(mmc->op_cond_response & OCR_ACCESS_MODE);
 
-		if (mmc->cfg->host_caps & MMC_MODE_HC)
-			cmd->cmdarg |= OCR_HCS;
-	}
 	err = mmc_send_cmd(mmc, cmd, NULL);
 	if (err)
 		return err;
drivers/mmc/mvebu_mmc.c +1 -1
index 8ca0904..056aef5 100644
@@ -418,7 +418,7 @@ static struct mmc_config mvebu_mmc_cfg = {
 	.f_min		= MVEBU_MMC_BASE_FAST_CLOCK / MVEBU_MMC_BASE_DIV_MAX,
 	.f_max		= MVEBU_MMC_CLOCKRATE_MAX,
 	.voltages	= MMC_VDD_32_33 | MMC_VDD_33_34,
-	.host_caps	= MMC_MODE_4BIT | MMC_MODE_HS | MMC_MODE_HC |
+	.host_caps	= MMC_MODE_4BIT | MMC_MODE_HS |
 			  MMC_MODE_HS_52MHz,
 	.part_type	= PART_TYPE_DOS,
 	.b_max		= CONFIG_SYS_MMC_MAX_BLK_COUNT,
drivers/mmc/mxsmmc.c +1 -2
index 2fa4eee..31fb3ab 100644
@@ -405,8 +405,7 @@ int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int))
 	priv->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
 
 	priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT |
-			 MMC_MODE_HS_52MHz | MMC_MODE_HS |
-			 MMC_MODE_HC;
+			 MMC_MODE_HS_52MHz | MMC_MODE_HS;
 
 	/*
 	 * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz
drivers/mmc/omap_hsmmc.c +1 -2
index dc725cb..8238a7e 100644
@@ -651,8 +651,7 @@ int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
 	if (priv_data == NULL)
 		return -1;
 
-	host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS |
-			     MMC_MODE_HC;
+	host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
 
 	switch (dev_index) {
 	case 0:
drivers/mmc/s3c_sdi.c +1 -1
index 1b5b705..02d1138 100644
@@ -298,7 +298,7 @@ int s3cmmc_initialize(bd_t *bis, int (*getcd)(struct mmc *),
 	cfg->name = "S3C MMC";
 	cfg->ops = &s3cmmc_ops;
 	cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
-	cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_HC | MMC_MODE_HS;
+	cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_HS;
 	cfg->f_min = 400000;
 	cfg->f_max = get_PCLK() / 2;
 	cfg->b_max = 0x80;
drivers/mmc/s5p_sdhci.c +0 -1
index 0eec731..8e1968a 100644
@@ -76,7 +76,6 @@ static int s5p_sdhci_core_init(struct sdhci_host *host)
 	host->set_control_reg = &s5p_sdhci_set_control_reg;
 	host->set_clock = set_mmc_clk;
 
-	host->host_caps = MMC_MODE_HC;
 	if (host->bus_width == 8)
 		host->host_caps |= MMC_MODE_8BIT;
drivers/mmc/sh_mmcif.c +1 -1
index 76ba93b..f92cf00 100644
@@ -577,7 +577,7 @@ static struct mmc_config sh_mmcif_cfg = {
 	.name		= DRIVER_NAME,
 	.ops		= &sh_mmcif_ops,
 	.host_caps	= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT |
-			  MMC_MODE_8BIT | MMC_MODE_HC,
+			  MMC_MODE_8BIT,
 	.voltages	= MMC_VDD_32_33 | MMC_VDD_33_34,
 	.b_max		= CONFIG_SYS_MMC_MAX_BLK_COUNT,
 };
drivers/mmc/sunxi_mmc.c +1 -1
index 2233545..0b7eb12 100644
@@ -449,7 +449,7 @@ struct mmc *sunxi_mmc_init(int sdc_no)
 
 	cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
 	cfg->host_caps = MMC_MODE_4BIT;
-	cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC;
+	cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
 	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 
 	cfg->f_min = 400000;
drivers/mmc/tegra_mmc.c +1 -1
index 2cd8cf1..ca41b4d 100644
@@ -559,7 +559,7 @@ static int do_mmc_init(int dev_index)
 		host->cfg.host_caps |= MMC_MODE_8BIT;
 	if (host->width >= 4)
 		host->cfg.host_caps |= MMC_MODE_4BIT;
-	host->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC;
+	host->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
 
 	/*
 	 * min freq is for card identification, and is the highest
drivers/mmc/zynq_sdhci.c +0 -2
index 7887f11..a92f12d 100644
@@ -29,8 +29,6 @@ int zynq_sdhci_init(phys_addr_t regbase)
 		       SDHCI_QUIRK_BROKEN_R1B;
 	host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
 
-	host->host_caps = MMC_MODE_HC;
-
 	add_sdhci(host, 52000000, 52000000 >> 9);
 	return 0;
 }
include/mmc.h +0 -1
index 2ad0f19..bdb003c 100644
@@ -55,7 +55,6 @@
 #define MMC_MODE_4BIT		(1 << 2)
 #define MMC_MODE_8BIT		(1 << 3)
 #define MMC_MODE_SPI		(1 << 4)
-#define MMC_MODE_HC		(1 << 5)
 #define MMC_MODE_DDR_52MHz	(1 << 6)
 
 #define SD_DATA_4BIT	0x00040000
Signature · 1 line
2.1.0

Hand merged and applied. Thanks.

? Pantelis

author
#3 lore raw

PATCH 1/1 mmc: sdhci: add timeout setting for response busy command

In reply to Rob Herring

From: Kevin Liu <[email protected]>

Timeout interrupt also work for response busy command(R1b) like cmd38/cmd6. So need to set it accordingly. Current code only set timeout for data command.

Signed-off-by Kevin Liu <[email protected]>
Signed-off-by Rob Herring <[email protected]>
Cc Pantelis Antoniou <[email protected]>
---
 drivers/mmc/sdhci.c | 2 ++
 1 file changed, 2 insertions(+)
drivers/mmc/sdhci.c +2 -0
index 78e958e..8faeca3 100644
@@ -213,6 +213,8 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
 				SDHCI_BLOCK_SIZE);
 		sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 		sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
+	} else if (cmd->resp_type & MMC_RSP_BUSY) {
+		sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
 	}
 
 	sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
Signature · 1 line
2.1.0
Applied
#4 lore raw

PATCH 1/1 mmc: sdhci: add timeout setting for response busy command

Hi Rob,

Quoted 31 lines · Rob Herring

From: Kevin Liu <[email protected]>

Timeout interrupt also work for response busy command(R1b) like cmd38/cmd6. So need to set it accordingly. Current code only set timeout for data command.

Signed-off-by Kevin Liu <[email protected]>
Signed-off-by Rob Herring <[email protected]>
Cc Pantelis Antoniou <[email protected]>

---
drivers/mmc/sdhci.c | 2 ++

1 file changed, 2 insertions(+)
drivers/mmc/sdhci.c +2 -0
index 78e958e..8faeca3 100644
@@ -213,6 +213,8 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
 				SDHCI_BLOCK_SIZE);
 		sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 		sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
+	} else if (cmd->resp_type & MMC_RSP_BUSY) {
+		sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
 	}
 
 	sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
Signature · 1 line
2.1.0

Thanks, Applied.

? Pantelis

author
#5 lore raw

PATCH 1/1 mvgpio: remove CONFIG_SHEEVA_88SV331xV5 dependency

In reply to Rob Herring

From: Zhou Zhu <[email protected]>

The Marvell GPIO driver can be used on Marvell platforms other than Sheeva, so remove the ifdef to enable it for others.

Signed-off-by Rob Herring <[email protected]>
---
 drivers/gpio/mvgpio.h | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)
drivers/gpio/mvgpio.h +1 -5
index a3f17a0..1de7395 100644
@@ -14,9 +14,8 @@
 
 #include <common.h>
 
-#ifdef CONFIG_SHEEVA_88SV331xV5
 /*
- * GPIO Register map for SHEEVA 88SV331xV5
+ * GPIO Register map for Marvell SOCs
  */
 struct gpio_reg {
 	u32 gplr;	/* Pin Level Register - 0x0000 */

@@ -51,8 +50,5 @@ struct gpio_reg {
 	u32 pad12[2];
 	u32 apmask;	/* Bitwise Mask of Edge Detect Register - 0x009C */
 };
-#else
-#error "CPU core subversion not defined"
-#endif
 
 #endif /* __MVGPIO_H__ */
Signature · 1 line
2.1.0
#6 lore raw

[U-Boot] mvgpio: remove CONFIG_SHEEVA_88SV331xV5 dependency

Quoted 6 lines · Rob Herring

From: Zhou Zhu <[email protected]>

The Marvell GPIO driver can be used on Marvell platforms other than Sheeva, so remove the ifdef to enable it for others.

Signed-off-by Rob Herring <[email protected]>

Applied to u-boot/master, thanks!

Signature · 8 lines
Tom
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#7 lore raw
In reply to Rob Herring
Quoted 10 lines · Rob Herring

From: Xiang Wang <[email protected]>

1. The bits 11..10 for mfp driver strength is only valid for aspen and old xscale family, for newer Marvell chip, this range has been moved to 12..11.
2. add sleep bit support

Signed-off-by Xiang Wang <[email protected]>
[robh: rebase to current mainline]
Signed-off-by Rob Herring <[email protected]>

Applied to u-boot/master, thanks!

Signature · 8 lines
Tom
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#8 lore raw
In reply to Rob Herring
Quoted 10 lines · Rob Herring

From: Xiang Wang <[email protected]>

1. The bits 11..10 for mfp driver strength is only valid for aspen and old xscale family, for newer Marvell chip, this range has been moved to 12..11.
2. add sleep bit support

Signed-off-by Xiang Wang <[email protected]>
[robh: rebase to current mainline]
Signed-off-by Rob Herring <[email protected]>

Applied to u-boot/master, thanks!

Signature · 8 lines
Tom
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