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drivers:usb:fsl: Add XHCI driver support

PATCH Superseded Ramneek Mehresh 2 participants 2 messages Apr 23, 2015 – Apr 24, 2015

Subsystems (3)
Arm (32-bit) USB USB xHCI driver

v2 of 3 Superseded Latest is v3 →

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Ramneek Mehresh

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#0 lore raw

PATCH v2 2/4 drivers:usb:fsl: Add XHCI driver support

Add xhci driver support for all FSL socs

Signed-off-by Ramneek Mehresh <[email protected]>

---

 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |   6 ++
 drivers/usb/host/Makefile                         |   1 +
 drivers/usb/host/xhci-fsl.c                       | 107 ++++++++++++++++++++++
 include/linux/usb/xhci-fsl.h                      |  54 +++++++++++
 4 files changed, 168 insertions(+)
 create mode 100644 drivers/usb/host/xhci-fsl.c
 create mode 100644 include/linux/usb/xhci-fsl.h
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +6 -0
index 3a64afc..9c1f1ce 100644
@@ -538,4 +538,10 @@ struct ccsr_cci400 {
 	} pcounter[4];			/* Performance Counter */
 	u8 res_e004[0x10000 - 0xe004];
 };
+
+/* USB-XHCI */
+#define FSL_XHCI_BASE 0x3100000
+#define FSL_OCP1_SCP_BASE 0x4a084c00
+#define FSL_OTG_WRAPPER_BASE 0x4A020000
+
 #endif	/* __ASM_ARCH_LS102XA_IMMAP_H_ */
drivers/usb/host/Makefile +1 -0
index c0d95cf..7c94439 100644
@@ -52,6 +52,7 @@ obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o
 obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o
 obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o
 obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o
+obj-$(CONFIG_USB_XHCI_FSL) += xhci-fsl.o
 obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
 obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
 obj-$(CONFIG_USB_XHCI_UNIPHIER) += xhci-uniphier.o
drivers/usb/host/xhci-fsl.c new file +107 -0

107 lines not on this page · raw message

include/linux/usb/xhci-fsl.h new file +54 -0

54 lines not on this page · raw message

Signature · 1 line
1.8.3.1
#1 lore raw

PATCH v2 2/4 drivers:usb:fsl: Add XHCI driver support

Quoted 3 lines · Ramneek Mehresh

Add xhci driver support for all FSL socs

Signed-off-by Ramneek Mehresh <[email protected]>

Next time, please follow

http://www.denx.de/wiki/view/U-Boot/Patches#Sending_updated_patch_versions

Quoted 15 lines
---
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |   6 ++
 drivers/usb/host/Makefile                         |   1 +
 drivers/usb/host/xhci-fsl.c                       | 107
++++++++++++++++++++++ include/linux/usb/xhci-fsl.h                      |
 54 +++++++++++ 4 files changed, 168 insertions(+)
 create mode 100644 drivers/usb/host/xhci-fsl.c
 create mode 100644 include/linux/usb/xhci-fsl.h
(quoted diff) +0 -0

b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 3a64afc..9c1f1ce 100644

arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h struct ccsr_cci400 { · line 547

Quoted 10 lines
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +6 -0
@@ -538,4 +538,10 @@ struct ccsr_cci400 {
 	} pcounter[4];			/* Performance Counter */
 	u8 res_e004[0x10000 - 0xe004];
 };
+
+/* USB-XHCI */
+#define FSL_XHCI_BASE 0x3100000
+#define FSL_OCP1_SCP_BASE 0x4a084c00
+#define FSL_OTG_WRAPPER_BASE 0x4A020000
+
 #endif	/* __ASM_ARCH_LS102XA_IMMAP_H_ */

This file looks like a dumpster . Maybe it's about time for someone in Freescale to clean that mess up. I don't want you to fix it before this patchset is applied, but certainly this could use some fixing.

[...]

arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h

Quoted 5 lines
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +5 -0
+static int fsl_xhci_core_exit(struct fsl_xhci *fsl_xhci)
+{
+	/* Currently fsl socs do not support PHY shutdown from
+	 * sw. But this support may be added in future socs.
+	 */

Multiline comment ;-)

Quoted 2 lines
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +2 -0
+	return 0;
+}

[...]

Quoted 16 lines
include/linux/usb/xhci-fsl.h new file +10 -0
new file mode 100644
index 0000000..8eaab2c
@@ -0,0 +1,54 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * FSL USB HOST xHCI Controller
+ *
+ * Author: Ramneek Mehresh<[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+

include/linux/usb/xhci-fsl.h line 20

Quoted 10 lines
include/linux/usb/xhci-fsl.h new file +10 -0
+#ifndef _ASM_ARCH_XHCI_FSL_H_
+#define _ASM_ARCH_XHCI_FSL_H_
+
+/* Default to the FSL XHCI defines */
+#define USB3_PWRCTL_CLK_CMD_MASK	0x3FE000
+#define USB3_PWRCTL_CLK_FREQ_MASK	0xFFC
+#define USB3_PHY_PARTIAL_RX_POWERON     BIT(6)
+#define USB3_PHY_RX_POWERON		BIT(14)
+#define USB3_PHY_TX_POWERON		BIT(15)
+#define USB3_PHY_TX_RX_POWERON	(USB3_PHY_RX_POWERON |

USB3_PHY_TX_POWERON)

include/linux/usb/xhci-fsl.h line 22

Quoted 2 lines
include/linux/usb/xhci-fsl.h new file +2 -0
+#define USB3_PWRCTL_CLK_CMD_SHIFT   14
+#define USB3_PWRCTL_CLK_FREQ_SHIFT	22

How much of this is actually DWC3 stuff please ? Or are all these bits really FSL-specific ?