Skip to contentSkip to conversation

drivers:usb:dwc3: Add DWC3 controller driver support

PATCH New Ramneek Mehresh 2 participants 6 messages Apr 28, 2015

Subsystems (3)
Arm (32-bit) USB USB xHCI driver
lore
Share & tools
lore

Ramneek Mehresh

author
#0 lore raw

PATCH 1/5 drivers:usb:dwc3: Add DWC3 controller driver support

Add support for DWC3 XHCI controller driver

Signed-off-by Ramneek Mehresh <[email protected]>
---
 drivers/usb/host/Makefile    |  1 +
 drivers/usb/host/xhci-dwc3.c | 74 ++++++++++++++++++++++++++++++++++++++++++++
 include/linux/usb/dwc3.h     |  4 +++
 3 files changed, 79 insertions(+)
 create mode 100644 drivers/usb/host/xhci-dwc3.c
drivers/usb/host/Makefile +1 -0
index 7658f87..c0d95cf 100644
@@ -49,6 +49,7 @@ obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o
 
 # xhci
 obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o
+obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o
 obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o
 obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o
 obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
drivers/usb/host/xhci-dwc3.c new file +74 -0

74 lines not on this page · raw message

include/linux/usb/dwc3.h +4 -0
index 7edc760..c21878c 100644
@@ -191,4 +191,8 @@ struct dwc3 {					/* offset: 0xC100 */
 #define DWC3_DCTL_CSFTRST			(1 << 30)
 #define DWC3_DCTL_LSFTRST			(1 << 29)
 
+void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode);
+void dwc3_core_soft_reset(struct dwc3 *dwc3_reg);
+int dwc3_core_init(struct dwc3 *dwc3_reg);
+void usb_phy_reset(struct dwc3 *dwc3_reg);
 #endif /* __DWC3_H_ */
Signature · 1 line
1.8.3.1
author
#1 lore raw

PATCH v3 2/5 drivers:usb:fsl: Add XHCI driver support

Add xhci driver support for all FSL socs

Signed-off-by Ramneek Mehresh <[email protected]>

---
Changes for v3:
- use FSL_USB_XHCI_ADDR for controller addr
- corrected multiline comment

 drivers/usb/host/Makefile    |   1 +
 drivers/usb/host/xhci-fsl.c  | 109 +++++++++++++++++++++++++++++++++++++++++++
 include/linux/usb/xhci-fsl.h |  54 +++++++++++++++++++++
 3 files changed, 164 insertions(+)
 create mode 100644 drivers/usb/host/xhci-fsl.c
 create mode 100644 include/linux/usb/xhci-fsl.h
drivers/usb/host/Makefile +1 -0
index c0d95cf..7c94439 100644
@@ -52,6 +52,7 @@ obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o
 obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o
 obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o
 obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o
+obj-$(CONFIG_USB_XHCI_FSL) += xhci-fsl.o
 obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
 obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
 obj-$(CONFIG_USB_XHCI_UNIPHIER) += xhci-uniphier.o
drivers/usb/host/xhci-fsl.c new file +109 -0

109 lines not on this page · raw message

include/linux/usb/xhci-fsl.h new file +54 -0

54 lines not on this page · raw message

Signature · 1 line
1.8.3.1
author
#2 lore raw

PATCH 3/5 arch:arm:fsl: Add XHCI support for LS1021A

In reply to Ramneek Mehresh

Add base register address information for USB
XHCI controller on LS1021A

Signed-off-by Ramneek Mehresh <[email protected]>
---
 arch/arm/include/asm/arch-ls102xa/config.h        |  1 +
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 10 ++++++++++
 2 files changed, 11 insertions(+)
arch/arm/include/asm/arch-ls102xa/config.h +1 -0
index 6561ce6..f672341 100644
@@ -35,6 +35,7 @@
 #define CONFIG_SYS_NS16550_COM1			(CONFIG_SYS_IMMR + 0x011c0500)
 #define CONFIG_SYS_NS16550_COM2			(CONFIG_SYS_IMMR + 0x011d0500)
 #define CONFIG_SYS_DCU_ADDR			(CONFIG_SYS_IMMR + 0x01ce0000)
+#define CONFIG_SYS_LS102XA_XHCI_USB1_ADDR	(CONFIG_SYS_IMMR + 0x02100000)
 #define CONFIG_SYS_LS102XA_USB1_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET)
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +10 -0
index 3a64afc..b5f570e 100644
@@ -538,4 +538,14 @@ struct ccsr_cci400 {
 	} pcounter[4];			/* Performance Counter */
 	u8 res_e004[0x10000 - 0xe004];
 };
+
+/* USB-XHCI */
+#define FSL_XHCI_BASE	0x3100000
+#define FSL_OCP1_SCP_BASE	0x4a084c00
+#define FSL_OTG_WRAPPER_BASE	0x4A020000
+
+#define CONFIG_SYS_FSL_XHCI_USB1_ADDR	CONFIG_SYS_LS102XA_XHCI_USB1_ADDR
+#define CONFIG_SYS_FSL_XHCI_USB2_ADDR	0
+#define FSL_USB_XHCI_ADDR	{CONFIG_SYS_FSL_XHCI_USB1_ADDR, \
+					CONFIG_SYS_FSL_XHCI_USB2_ADDR}
 #endif	/* __ASM_ARCH_LS102XA_IMMAP_H_ */
Signature · 1 line
1.8.3.1
author
#3 lore raw

PATCH v3 4/5 include:configs:ls1021atwr: Enable USB IP support

In reply to Ramneek Mehresh

Enable USB IP support for both EHCI and XHCI for
ls1021atwr platform

Signed-off-by Ramneek Mehresh <[email protected]>

---
Changes for v3:
- corrected multiline comment
- moved out xhci controller soc specific
base addresse(s) to soc file

 include/configs/ls1021atwr.h | 38 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)
include/configs/ls1021atwr.h +38 -0
index a13876b..a96bc22 100644
@@ -28,6 +28,44 @@
 #define CONFIG_SYS_INIT_RAM_SIZE	OCRAM_SIZE
 
 /*
+ * USB
+ */
+
+/*
+ * EHCI Support - disbaled by default as
+ * there is no signal coming out of soc on
+ * this board for this controller. However,
+ * the silicon still has this controller,
+ * and anyone can use this controller by
+ * taking signals out on their board.
+ */
+
+/*#define CONFIG_HAS_FSL_DR_USB*/
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#endif
+
+/* XHCI Support - enabled by default */
+#define CONFIG_HAS_FSL_XHCI_USB
+
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+#define CONFIG_USB_XHCI_FSL
+#define CONFIG_USB_XHCI_DWC3
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_MAX_CONTROLLER_COUNT        1
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS     2
+#endif
+
+#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB)
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_EXT2
+#endif
+
+/*
  * Generic Timer Definitions
  */
 #define GENERIC_TIMER_CLK		12500000
Signature · 1 line
1.8.3.1
author
#4 lore raw

PATCH 5/5 include:configs:ls1021aqds: Enable USB IP support

In reply to Ramneek Mehresh

Enable USB IP support for both EHCI and XHCI for
ls1021aqds platform

Signed-off-by Ramneek Mehresh <[email protected]>
---
 include/configs/ls1021aqds.h | 22 +++++++++++++++++-----
 1 file changed, 17 insertions(+), 5 deletions(-)
include/configs/ls1021aqds.h +17 -5
index 5de416d..1aa2f94 100644
@@ -423,19 +423,31 @@ unsigned long get_board_ddr_clk(void);
 /*
  * USB
  */
-#define CONFIG_HAS_FSL_DR_USB
+/* EHCI Support - disbaled by default */
+/*#define CONFIG_HAS_FSL_DR_USB*/
 
 #ifdef CONFIG_HAS_FSL_DR_USB
 #define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#endif
 
-#ifdef CONFIG_USB_EHCI
+/*XHCI Support - enabled by default*/
+#define CONFIG_HAS_FSL_XHCI_USB
+
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+#define CONFIG_USB_XHCI_FSL
+#define CONFIG_USB_XHCI_DWC3
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_MAX_CONTROLLER_COUNT		1
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS	2
+#endif
+
+#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB)
 #define CONFIG_CMD_USB
 #define CONFIG_USB_STORAGE
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #define CONFIG_CMD_EXT2
 #endif
-#endif
 
 /*
  * Video
Signature · 1 line
1.8.3.1