firmware: qcom: scm: Split out 32-bit specific SCM code

Add an implementation of the SCM interface that works on ARM64/64-bit SoCs

drivers/firmware/qcom_scm-64.c new file +37 -0

+static int qcom_scm_set_boot_addr(void *entry, const cpumask_t *cpus, int flags)
+{
+       struct qcom_scm_desc desc = {0};
+       unsigned int cpu = cpumask_first(cpus);
+       u64 mpidr_el1 = cpu_logical_map(cpu);
+
+       /* For now we assume only a single cpu is set in the mask */
+       WARN_ON(cpumask_weight(cpus) != 1);
+
+       if (mpidr_el1 & ~MPIDR_HWID_BITMASK) {
+               pr_err("CPU%d:Failed to set boot address\n", cpu);
+               return -ENOSYS;
+       }
+
+       desc.args[0] = virt_to_phys(entry);
+       desc.args[1] = BIT(MPIDR_AFFINITY_LEVEL(mpidr_el1, 0));
+       desc.args[2] = BIT(MPIDR_AFFINITY_LEVEL(mpidr_el1, 1));
+       desc.args[3] = BIT(MPIDR_AFFINITY_LEVEL(mpidr_el1, 2));
+       desc.args[4] = ~0ULL;
+       desc.args[5] = QCOM_SCM_FLAG_HLOS | flags;
+       desc.arginfo = QCOM_SCM_ARGS(6);
+
+       return qcom_scm_call(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_ADDR_MC, &desc);
+}
+
+int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
+{
+       int flags = QCOM_SCM_FLAG_COLDBOOT_MC;
+
+       return qcom_scm_set_boot_addr(entry, cpus, flags);
+}
+
+int __qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
+{
+       int flags = QCOM_SCM_FLAG_WARMBOOT_MC;
+
+       return qcom_scm_set_boot_addr(entry, cpus, flags);

Hi Kumar,

Quoted 1 line · Kumar Gala

Add an implementation of the SCM interface that works on ARM64/64-bit SoCs

What is the intended use of this on arm64 SoCs?

Given the negative reaction to the SMP bringup [1] code that seems to be the only user, I'm somewhat confused as to why this is being pushed as a non-RFC in the mean time.

Are there other users of this interface code? If so, could you please mention that in the commit message. I'd also ask that you would Cc me on future postings of this series.

[?]

Quoted 43 lines

drivers/firmware/qcom_scm-64.c new file +42 -0

+static int qcom_scm_set_boot_addr(void *entry, const cpumask_t *cpus, int flags)
+{
+       struct qcom_scm_desc desc = {0};
+       unsigned int cpu = cpumask_first(cpus);
+       u64 mpidr_el1 = cpu_logical_map(cpu);
+
+       /* For now we assume only a single cpu is set in the mask */
+       WARN_ON(cpumask_weight(cpus) != 1);
+
+       if (mpidr_el1 & ~MPIDR_HWID_BITMASK) {
+               pr_err("CPU%d:Failed to set boot address\n", cpu);
+               return -ENOSYS;
+       }
+
+       desc.args[0] = virt_to_phys(entry);
+       desc.args[1] = BIT(MPIDR_AFFINITY_LEVEL(mpidr_el1, 0));
+       desc.args[2] = BIT(MPIDR_AFFINITY_LEVEL(mpidr_el1, 1));
+       desc.args[3] = BIT(MPIDR_AFFINITY_LEVEL(mpidr_el1, 2));
+       desc.args[4] = ~0ULL;
+       desc.args[5] = QCOM_SCM_FLAG_HLOS | flags;
+       desc.arginfo = QCOM_SCM_ARGS(6);
+
+       return qcom_scm_call(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_ADDR_MC, &desc);
+}
+
+int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
+{
+       int flags = QCOM_SCM_FLAG_COLDBOOT_MC;
+
+       return qcom_scm_set_boot_addr(entry, cpus, flags);
+}
+
+int __qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
+{
+       int flags = QCOM_SCM_FLAG_WARMBOOT_MC;
+
+       return qcom_scm_set_boot_addr(entry, cpus, flags);
+}
+
+void __qcom_scm_cpu_power_down(u32 flags)
+{
+       struct qcom_scm_desc desc = {0};

drivers/firmware/qcom_scm-64.c line 422

Quoted 5 lines

drivers/firmware/qcom_scm-64.c new file +5 -0

+       desc.args[0] = flags & QCOM_SCM_FLUSH_FLAG_MASK;
+       desc.arginfo = QCOM_SCM_ARGS(1);
+
+       qcom_scm_call_atomic(QCOM_SCM_SVC_BOOT, QCOM_SCM_CMD_TERMINATE_PC, &desc);
+}

As mentioned in the other thread, I don't want to see this for arm64, and must NAK this portion.

Quoted 18 lines · Mark Rutland

Hi Kumar,

Quoted 1 line · Kumar Gala

Add an implementation of the SCM interface that works on ARM64/64-bit SoCs

What is the intended use of this on arm64 SoCs?

Given the negative reaction to the SMP bringup [1] code that seems to be the only user, I'm somewhat confused as to why this is being pushed as a non-RFC in the mean time.

Are there other users of this interface code? If so, could you please mention that in the commit message. I'd also ask that you would Cc me on future postings of this series.

Quoted 1 line

[?]

The SCM interface is needed for other things like display:

https://patchwork.kernel.org/patch/6198691/

Quoted 42 lines

Quoted 42 lines

drivers/firmware/qcom_scm-64.c new file +42 -0

+static int qcom_scm_set_boot_addr(void *entry, const cpumask_t *cpus, int flags)
+{
+       struct qcom_scm_desc desc = {0};
+       unsigned int cpu = cpumask_first(cpus);
+       u64 mpidr_el1 = cpu_logical_map(cpu);
+
+       /* For now we assume only a single cpu is set in the mask */
+       WARN_ON(cpumask_weight(cpus) != 1);
+
+       if (mpidr_el1 & ~MPIDR_HWID_BITMASK) {
+               pr_err("CPU%d:Failed to set boot address\n", cpu);
+               return -ENOSYS;
+       }
+
+       desc.args[0] = virt_to_phys(entry);
+       desc.args[1] = BIT(MPIDR_AFFINITY_LEVEL(mpidr_el1, 0));
+       desc.args[2] = BIT(MPIDR_AFFINITY_LEVEL(mpidr_el1, 1));
+       desc.args[3] = BIT(MPIDR_AFFINITY_LEVEL(mpidr_el1, 2));
+       desc.args[4] = ~0ULL;
+       desc.args[5] = QCOM_SCM_FLAG_HLOS | flags;
+       desc.arginfo = QCOM_SCM_ARGS(6);
+
+       return qcom_scm_call(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_ADDR_MC, &desc);
+}
+
+int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
+{
+       int flags = QCOM_SCM_FLAG_COLDBOOT_MC;
+
+       return qcom_scm_set_boot_addr(entry, cpus, flags);
+}
+
+int __qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
+{
+       int flags = QCOM_SCM_FLAG_WARMBOOT_MC;
+
+       return qcom_scm_set_boot_addr(entry, cpus, flags);
+}
+
+void __qcom_scm_cpu_power_down(u32 flags)
+{
+       struct qcom_scm_desc desc = {0};

Quoted 8 lines

drivers/firmware/qcom_scm-64.c line 422

Quoted 5 lines

drivers/firmware/qcom_scm-64.c new file +5 -0

+       desc.args[0] = flags & QCOM_SCM_FLUSH_FLAG_MASK;
+       desc.arginfo = QCOM_SCM_ARGS(1);
+
+       qcom_scm_call_atomic(QCOM_SCM_SVC_BOOT, QCOM_SCM_CMD_TERMINATE_PC, &desc);
+}

As mentioned in the other thread, I don't want to see this for arm64, and must NAK this portion.

I can have these return an error code, but we want to keep the interface the same between the 32-bit and 64-bit.

Quoted 18 lines · Kumar Gala

Quoted 18 lines · Mark Rutland

Hi Kumar,

Quoted 1 line · Kumar Gala

Add an implementation of the SCM interface that works on ARM64/64-bit SoCs

What is the intended use of this on arm64 SoCs?

Given the negative reaction to the SMP bringup [1] code that seems to be the only user, I'm somewhat confused as to why this is being pushed as a non-RFC in the mean time.

Are there other users of this interface code? If so, could you please mention that in the commit message. I'd also ask that you would Cc me on future postings of this series.

Quoted 5 lines

Quoted 1 line

[?]

The SCM interface is needed for other things like display:

https://patchwork.kernel.org/patch/6198691/

Thanks for the link. It would be good if you could mention some users in the commit message.

Quoted 52 lines

Quoted 51 lines

Quoted 38 lines

drivers/firmware/qcom_scm-64.c new file +37 -0

+static int qcom_scm_set_boot_addr(void *entry, const cpumask_t *cpus, int flags)
+{
+       struct qcom_scm_desc desc = {0};
+       unsigned int cpu = cpumask_first(cpus);
+       u64 mpidr_el1 = cpu_logical_map(cpu);
+
+       /* For now we assume only a single cpu is set in the mask */
+       WARN_ON(cpumask_weight(cpus) != 1);
+
+       if (mpidr_el1 & ~MPIDR_HWID_BITMASK) {
+               pr_err("CPU%d:Failed to set boot address\n", cpu);
+               return -ENOSYS;
+       }
+
+       desc.args[0] = virt_to_phys(entry);
+       desc.args[1] = BIT(MPIDR_AFFINITY_LEVEL(mpidr_el1, 0));
+       desc.args[2] = BIT(MPIDR_AFFINITY_LEVEL(mpidr_el1, 1));
+       desc.args[3] = BIT(MPIDR_AFFINITY_LEVEL(mpidr_el1, 2));
+       desc.args[4] = ~0ULL;
+       desc.args[5] = QCOM_SCM_FLAG_HLOS | flags;
+       desc.arginfo = QCOM_SCM_ARGS(6);
+
+       return qcom_scm_call(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_ADDR_MC, &desc);
+}
+
+int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
+{
+       int flags = QCOM_SCM_FLAG_COLDBOOT_MC;
+
+       return qcom_scm_set_boot_addr(entry, cpus, flags);
+}
+
+int __qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
+{
+       int flags = QCOM_SCM_FLAG_WARMBOOT_MC;
+
+       return qcom_scm_set_boot_addr(entry, cpus, flags);

drivers/firmware/qcom_scm-64.c line 422

Quoted 10 lines

drivers/firmware/qcom_scm-64.c new file +10 -0

+}
+
+void __qcom_scm_cpu_power_down(u32 flags)
+{
+       struct qcom_scm_desc desc = {0};
+       desc.args[0] = flags & QCOM_SCM_FLUSH_FLAG_MASK;
+       desc.arginfo = QCOM_SCM_ARGS(1);
+
+       qcom_scm_call_atomic(QCOM_SCM_SVC_BOOT, QCOM_SCM_CMD_TERMINATE_PC, &desc);
+}

As mentioned in the other thread, I don't want to see this for arm64, and must NAK this portion.

Quoted 1 line

I can have these return an error code, but we want to keep the interface the same between the 32-bit and 64-bit.

I don't follow. If nothing calls these on the 64-bit side, then there's no interface they need to be there for.

Thanks,
Mark.

(quoted diff) +12 -0

+			  "x14", "x15", "x16", "x17");
+	} while (r0 == QCOM_SCM_INTERRUPTED);
+
+	if (ret1)
+		*ret1 = r1;
+	if (ret2)
+		*ret2 = r2;
+	if (ret3)
+		*ret3 = r3;
+
+	return r0;
+}

(quoted diff) +4 -0

+			"x14", "x15", "x16", "x17");
+
+	} while (r0 == QCOM_SCM_INTERRUPTED);
+

Review

Quoted 10 lines · Kumar Gala

(quoted diff) +10 -0

+
+int __qcom_scm_call_armv8_64(u64 x0, u64 x1, u64 x2, u64 x3, u64 x4, u64 x5,
+				u64 *ret1, u64 *ret2, u64 *ret3)
+{
+	register u64 r0 asm("r0") = x0;
+	register u64 r1 asm("r1") = x1;
+	register u64 r2 asm("r2") = x2;
+	register u64 r3 asm("r3") = x3;
+	register u64 r4 asm("r4") = x4;
+	register u64 r5 asm("r5") = x5;

This should set x6 to 0.

    register u32 r6 asm("r6") = 0;

for example.

Review

Quoted 13 lines

(quoted diff) +13 -0

+
+	do {
+		asm volatile(
+			__asmeq("%0", "x0")
+			__asmeq("%1", "x1")
+			__asmeq("%2", "x2")
+			__asmeq("%3", "x3")
+			__asmeq("%4", "x0")
+			__asmeq("%5", "x1")
+			__asmeq("%6", "x2")
+			__asmeq("%7", "x3")
+			__asmeq("%8", "x4")
+			__asmeq("%9", "x5")

And then the asmeq thing here for x6.

Review

Quoted 7 lines

(quoted diff) +7 -0

+#ifdef REQUIRES_SEC
+			".arch_extension sec\n"
+#endif
+			"smc	#0\n"
+			: "=r" (r0), "=r" (r1), "=r" (r2), "=r" (r3)
+			: "r" (r0), "r" (r1), "r" (r2), "r" (r3), "r" (r4),
+			  "r" (r5)

And add x6 as an input here.

Review

Quoted 1 line

(quoted diff) +1 -0

+			: "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13",

and remove x6 as a clobber.

Quoted 12 lines

(quoted diff) +12 -0

+			  "x14", "x15", "x16", "x17");
+	} while (r0 == QCOM_SCM_INTERRUPTED);
+
+	if (ret1)
+		*ret1 = r1;
+	if (ret2)
+		*ret2 = r2;
+	if (ret3)
+		*ret3 = r3;
+
+	return r0;
+}

Review

Quoted 10 lines

(quoted diff) +10 -0

+
+int __qcom_scm_call_armv8_32(u32 w0, u32 w1, u32 w2, u32 w3, u32 w4, u32 w5,
+				u64 *ret1, u64 *ret2, u64 *ret3)
+{
+	register u32 r0 asm("r0") = w0;
+	register u32 r1 asm("r1") = w1;
+	register u32 r2 asm("r2") = w2;
+	register u32 r3 asm("r3") = w3;
+	register u32 r4 asm("r4") = w4;
+	register u32 r5 asm("r5") = w5;

This needs to set r6 to 0 as well

    register u32 r6 asm("r6") = 0;

for example.

Review

Quoted 13 lines

(quoted diff) +13 -0

+
+	do {
+		asm volatile(
+			__asmeq("%0", "x0")
+			__asmeq("%1", "x1")
+			__asmeq("%2", "x2")
+			__asmeq("%3", "x3")
+			__asmeq("%4", "x0")
+			__asmeq("%5", "x1")
+			__asmeq("%6", "x2")
+			__asmeq("%7", "x3")
+			__asmeq("%8", "x4")
+			__asmeq("%9", "x5")

And then another asmeq thing here for x6.

Review

Quoted 7 lines

(quoted diff) +7 -0

+#ifdef REQUIRES_SEC
+			".arch_extension sec\n"
+#endif
+			"smc	#0\n"
+			: "=r" (r0), "=r" (r1), "=r" (r2), "=r" (r3)
+			: "r" (r0), "r" (r1), "r" (r2), "r" (r3), "r" (r4),
+			  "r" (r5)

And then add r6 here as an input

Review

Quoted 1 line

(quoted diff) +1 -0

+			: "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13",

And remove r6 from the clobber.

Quoted 5 lines

(quoted diff) +4 -0

+			"x14", "x15", "x16", "x17");
+
+	} while (r0 == QCOM_SCM_INTERRUPTED);
+

Review

Quoted 10 lines

(quoted diff) +10 -0

+	if (ret1)
+		*ret1 = r1;
+	if (ret2)
+		*ret2 = r2;
+	if (ret3)
+		*ret3 = r3;
+
+	return r0;
+}
+

Here's a totally untested patch for that.

Signed-off-by Stephen Boyd <[email protected]>

----8<-----

drivers/firmware/qcom_scm-64.c +6 -2

index a95fd9b5d576..8f7e65ff524c 100644
@@ -114,6 +114,7 @@ int __qcom_scm_call_armv8_64(u64 x0, u64 x1, u64 x2, u64 x3, u64 x4, u64 x5,
 	register u64 r3 asm("r3") = x3;
 	register u64 r4 asm("r4") = x4;
 	register u64 r5 asm("r5") = x5;
+	register u64 r6 asm("r5") = 0;
 	do {
 		asm volatile(

@@ -127,14 +128,15 @@ int __qcom_scm_call_armv8_64(u64 x0, u64 x1, u64 x2, u64 x3, u64 x4, u64 x5,
 			__asmeq("%7", "x3")
 			__asmeq("%8", "x4")
 			__asmeq("%9", "x5")
+			__asmeq("%10", "x6")
 #ifdef REQUIRES_SEC
 			".arch_extension sec\n"
 #endif
 			"smc	#0\n"
 			: "=r" (r0), "=r" (r1), "=r" (r2), "=r" (r3)
 			: "r" (r0), "r" (r1), "r" (r2), "r" (r3), "r" (r4),
-			  "r" (r5)
-			: "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13",
+			  "r" (r5), "r" (r6)
+			: "x7", "x8", "x9", "x10", "x11", "x12", "x13",
 			  "x14", "x15", "x16", "x17");
 	} while (r0 == QCOM_SCM_INTERRUPTED);

@@ -157,6 +159,7 @@ int __qcom_scm_call_armv8_32(u32 w0, u32 w1, u32 w2, u32 w3, u32 w4, u32 w5,
 	register u32 r3 asm("r3") = w3;
 	register u32 r4 asm("r4") = w4;
 	register u32 r5 asm("r5") = w5;
+	register u32 r6 asm("r6") = 0;
 	do {
 		asm volatile(

@@ -170,14 +173,15 @@ int __qcom_scm_call_armv8_32(u32 w0, u32 w1, u32 w2, u32 w3, u32 w4, u32 w5,
 			__asmeq("%7", "x3")
 			__asmeq("%8", "x4")
 			__asmeq("%9", "x5")
+			__asmeq("%10", "x6")
 #ifdef REQUIRES_SEC
 			".arch_extension sec\n"
 #endif