clk: ux500: ape[ate|trace]clk are scaleable
Subsystems (2)
PATCH 1/1 clk: ux500: ape[ate|trace]clk are scaleable
The APEATCLK and APETRACECLK are actually scaleable so register them as scaleable clocks.
Cc Ulf Hansson <[email protected]>
Signed-off-by Linus Walleij <[email protected]>
--- drivers/clk/ux500/u8500_clk.c | 7 ++++--- drivers/clk/ux500/u8500_of_clk.c | 4 ++-- 2 files changed, 6 insertions(+), 5 deletions(-)
drivers/clk/ux500/u8500_clk.c +4 -3
@@ -116,11 +116,12 @@ void u8500_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,clk_register_clkdev (clk,NULL ,"hdmi" );clk_register_clkdev (clk,"hdmi" ,"mcde" ); - clk =clk_reg_prcmu_gate ("apeatclk" ,NULL ,PRCMU_APEATCLK ,CLK_IS_ROOT ); + clk =clk_reg_prcmu_scalable ("apeatclk" ,NULL ,PRCMU_APEATCLK ,0 , +CLK_IS_ROOT |CLK_SET_RATE_GATE );clk_register_clkdev (clk,NULL ,"apeat" ); - clk =clk_reg_prcmu_gate ("apetraceclk" ,NULL ,PRCMU_APETRACECLK , -CLK_IS_ROOT ); + clk =clk_reg_prcmu_scalable ("apetraceclk" ,NULL ,PRCMU_APETRACECLK ,0 , +CLK_IS_ROOT |CLK_SET_RATE_GATE );clk_register_clkdev (clk,NULL ,"apetrace" ); clk =clk_reg_prcmu_gate ("mcdeclk" ,NULL ,PRCMU_MCDECLK ,CLK_IS_ROOT );
drivers/clk/ux500/u8500_of_clk.c +2 -2
@@ -166,8 +166,8 @@ void u8500_of_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base, clk =clk_reg_prcmu_gate ("apeatclk" ,NULL ,PRCMU_APEATCLK ,CLK_IS_ROOT ); prcmu_clk[PRCMU_APEATCLK ] = clk; - clk =clk_reg_prcmu_gate ("apetraceclk" ,NULL ,PRCMU_APETRACECLK , -CLK_IS_ROOT ); + clk =clk_reg_prcmu_scalable ("apetraceclk" ,NULL ,PRCMU_APETRACECLK ,0 , +CLK_IS_ROOT |CLK_SET_RATE_GATE ); prcmu_clk[PRCMU_APETRACECLK ] = clk; clk =clk_reg_prcmu_gate ("mcdeclk" ,NULL ,PRCMU_MCDECLK ,CLK_IS_ROOT );
Signature · 1 line
1.9.3
Quoted 5 lines · Linus Walleij
The APEATCLK and APETRACECLK are actually scaleable so register them as scaleable clocks.
Cc Ulf Hansson <[email protected]>Signed-off-by Linus Walleij <[email protected]>
Acked-by Ulf Hansson <[email protected]>
Kind regards
Uffe
Quoted 43 lines
--- drivers/clk/ux500/u8500_clk.c | 7 ++++--- drivers/clk/ux500/u8500_of_clk.c | 4 ++-- 2 files changed, 6 insertions(+), 5 deletions(-)drivers/clk/ux500/u8500_clk.c +4
-3@@ -116,11 +116,12 @@ void u8500_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,clk_register_clkdev (clk,NULL ,"hdmi" );clk_register_clkdev (clk,"hdmi" ,"mcde" ); - clk =clk_reg_prcmu_gate ("apeatclk" ,NULL ,PRCMU_APEATCLK ,CLK_IS_ROOT ); + clk =clk_reg_prcmu_scalable ("apeatclk" ,NULL ,PRCMU_APEATCLK ,0 , +CLK_IS_ROOT |CLK_SET_RATE_GATE );clk_register_clkdev (clk,NULL ,"apeat" ); - clk =clk_reg_prcmu_gate ("apetraceclk" ,NULL ,PRCMU_APETRACECLK , -CLK_IS_ROOT ); + clk =clk_reg_prcmu_scalable ("apetraceclk" ,NULL ,PRCMU_APETRACECLK ,0 , +CLK_IS_ROOT |CLK_SET_RATE_GATE );clk_register_clkdev (clk,NULL ,"apetrace" ); clk =clk_reg_prcmu_gate ("mcdeclk" ,NULL ,PRCMU_MCDECLK ,CLK_IS_ROOT );drivers/clk/ux500/u8500_of_clk.c +2
-3@@ -166,8 +166,8 @@ void u8500_of_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base, clk =clk_reg_prcmu_gate ("apeatclk" ,NULL ,PRCMU_APEATCLK ,CLK_IS_ROOT ); prcmu_clk[PRCMU_APEATCLK ] = clk; - clk =clk_reg_prcmu_gate ("apetraceclk" ,NULL ,PRCMU_APETRACECLK , -CLK_IS_ROOT ); + clk =clk_reg_prcmu_scalable ("apetraceclk" ,NULL ,PRCMU_APETRACECLK ,0 , +CLK_IS_ROOT |CLK_SET_RATE_GATE ); prcmu_clk[PRCMU_APETRACECLK ] = clk; clk =clk_reg_prcmu_gate ("mcdeclk" ,NULL ,PRCMU_MCDECLK ,CLK_IS_ROOT ); --1.9.3
Stephen Boyd
AppliedQuoted 9 lines · Ulf Hansson
Quoted 5 lines · Linus Walleij
The APEATCLK and APETRACECLK are actually scaleable so register them as scaleable clocks.
Cc Ulf Hansson <[email protected]>Signed-off-by Linus Walleij <[email protected]>Acked-by Ulf Hansson <[email protected]>
Applied to clk-next.
Signature · 2 lines
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