Add GPIO driver for Freescale Vybrid platform
Subsystems (5)
cover Add GPIO driver for Freescale Vybrid platform
This patch-set adds GPIO driver, DSPI and device tree support for Freescale Vybrid platform and Toradex Colibri Vybrid VF50, VF61 modules.
Following cases are tested with Vybrid GPIO driver:
- with DM, without DT
- with DM and DT
Both the above cases were tested on Toradex Colibri Vybrid VF50, VF61 modules and both works fine.
- The patchset is based and tested on the latest master branch.
Bhuvanchandra DV (9):
dm: gpio: uclass: Add flag to control sequence numbering
dm: gpio: vf610: Add GPIO driver support
colibri_vf: Add pinmux entries for GPIOs
colibri_vf: Enable GPIO support
arm: vf610: Add clock support for DSPI
arm: vf610: Add iomux support for DSPI
vf610: dts: Add device tree support
colibri-vf: Enable SPI support
colibri_vf: Add separate defconfig for device tree support
Sanchayan Maity (2):
usb: ehci-vf: Add weak function for board specific initialisation
colibri_vf: Enable board specific USB initialisation for USB pen gpio
arch/arm/cpu/armv7/vf610/generic.c | 7 ++ arch/arm/dts/Makefile | 3 + arch/arm/dts/vf-colibri.dtsi | 21 ++++ arch/arm/dts/vf.dtsi | 100 +++++++++++++++ arch/arm/dts/vf500-colibri.dts | 18 +++ arch/arm/dts/vf610-colibri.dts | 18 +++ arch/arm/imx-common/iomux-v3.c | 26 ++++ arch/arm/include/asm/arch-vf610/clock.h | 1 + arch/arm/include/asm/arch-vf610/crm_regs.h | 4 + arch/arm/include/asm/arch-vf610/gpio.h | 29 +++++ arch/arm/include/asm/arch-vf610/imx-regs.h | 5 + arch/arm/include/asm/arch-vf610/iomux-vf610.h | 59 +++++++++ arch/arm/include/asm/imx-common/iomux-v3.h | 6 + board/toradex/colibri_vf/colibri_vf.c | 106 ++++++++++++++++ configs/colibri_vf_defconfig | 1 + configs/colibri_vf_dtb_defconfig | 6 + drivers/gpio/Kconfig | 7 ++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-uclass.c | 1 + drivers/gpio/vybrid_gpio.c | 169 ++++++++++++++++++++++++++ drivers/usb/host/ehci-vf.c | 8 ++ include/configs/colibri_vf.h | 16 +++ 22 files changed, 612 insertions(+) create mode 100644 arch/arm/dts/vf-colibri.dtsi create mode 100644 arch/arm/dts/vf.dtsi create mode 100644 arch/arm/dts/vf500-colibri.dts create mode 100644 arch/arm/dts/vf610-colibri.dts create mode 100644 arch/arm/include/asm/arch-vf610/gpio.h create mode 100644 configs/colibri_vf_dtb_defconfig create mode 100644 drivers/gpio/vybrid_gpio.c
Signature · 1 line
2.1.0
PATCH 1/11 dm: gpio: uclass: Add flag to control sequence numbering
Like SPI and I2C few GPIO controllers also have multiple chip instances. This patch adds the flag 'DM_UC_FLAG_SEQ_ALIAS' in gpio_uclass driver to control device sequence numbering. By defalut the dev->r_seq for gpio_uclass will alwalys returns -1, which leads the gpio driver probe failure when using the driver with device trees.
--- drivers/gpio/gpio-uclass.c | 1 + 1 file changed, 1 insertion(+)
drivers/gpio/gpio-uclass.c +1 -0
@@ -757,6 +757,7 @@ static int gpio_pre_remove(struct udevice *dev)UCLASS_DRIVER (gpio) = { .id =UCLASS_GPIO , .name ="gpio" , + .flags =DM_UC_FLAG_SEQ_ALIAS , .post_probe = gpio_post_probe, .pre_remove = gpio_pre_remove, .per_device_auto_alloc_size =sizeof (struct gpio_dev_priv ),
Signature · 1 line
2.1.0
PATCH 2/11 dm: gpio: vf610: Add GPIO driver support
In reply to Bhuvanchandra DVAdd GPIO driver support to Freescale VF610
--- arch/arm/imx-common/iomux-v3.c | 26 +++++ arch/arm/include/asm/arch-vf610/gpio.h | 29 +++++ arch/arm/include/asm/arch-vf610/imx-regs.h | 5 + arch/arm/include/asm/imx-common/iomux-v3.h | 6 + drivers/gpio/Kconfig | 7 ++ drivers/gpio/Makefile | 1 + drivers/gpio/vybrid_gpio.c | 169 +++++++++++++++++++++++++++++ 7 files changed, 243 insertions(+) create mode 100644 arch/arm/include/asm/arch-vf610/gpio.h create mode 100644 drivers/gpio/vybrid_gpio.c
arch/arm/imx-common/iomux-v3.c +26 -0
@@ -92,3 +92,29 @@ void imx_iomux_set_gpr_register(int group, int start_bit, reg |= (value << start_bit);writel (reg, base + group *4 ); } + +#ifdef CONFIG_IOMUX_SHARE_CONF_REG +void imx_iomux_gpio_set_direction (unsigned int gpio, +unsigned int direction) +{ +u32 reg; +/* +* Only on Vybrid the input/output buffer enable flags +* are part of the shared mux/conf register. +*/ + reg =readl (base + (gpio <<2 )); + +if (direction) + reg |=0x2 ; +else + reg &= ~0x2 ; + +writel (reg, base + (gpio <<2 )); +} + +void imx_iomux_gpio_get_function (unsigned int gpio,u32 *gpio_state) +{ + *gpio_state =readl (base + (gpio <<2 )) & + ((0X07 <<PAD_MUX_MODE_SHIFT ) |PAD_CTL_OBE_IBE_ENABLE ); +} +#endif
arch/arm/include/asm/arch-vf610/gpio.h new file +29 -0
@@ -0,0 +1,29 @@ +/* +* Copyright (C) 2015 +* Bhuvanchandra DV, Toradex, Inc. +* +* SPDX-License-Identifier: GPL-2.0 +*/ + +#ifndef __ASM_ARCH_VF610_GPIO_H +#define __ASM_ARCH_VF610_GPIO_H + +#define VYBRID_GPIO_COUNT 32 +#define VF610_GPIO_DIRECTION_IN 0x0 +#define VF610_GPIO_DIRECTION_OUT 0x1 + +/* GPIO registers */ +struct vybrid_gpio_regs { +u32 gpio_pdor; +u32 gpio_psor; +u32 gpio_pcor; +u32 gpio_ptor; +u32 gpio_pdir; +}; + +struct vybrid_gpio_platdata { +unsigned int chip; +u32 base; +const char *port_name; +}; +#endif /* __ASM_ARCH_VF610_GPIO_H */
arch/arm/include/asm/arch-vf610/imx-regs.h +5 -0
@@ -81,6 +81,11 @@#define VREG_DIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006D000)#define SRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006E000)#define CMU_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006F000) +#define GPIO0_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF000) +#define GPIO1_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF040) +#define GPIO2_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF080) +#define GPIO3_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF0C0) +#define GPIO4_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF100)/* AIPS 1 */ #define OCOTP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00025000)
arch/arm/include/asm/imx-common/iomux-v3.h +6 -0
@@ -187,6 +187,12 @@ void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,*/ void imx_iomux_set_gpr_register (int group,int start_bit,int num_bits,int value); +#ifdef CONFIG_IOMUX_SHARE_CONF_REG +void imx_iomux_gpio_set_direction (unsigned int gpio, +unsigned int direction); +void imx_iomux_gpio_get_function (unsigned int gpio, +u32 *gpio_state); +#endif /* macros for declaring and using pinmux array */ #if defined(CONFIG_MX6QDL )
drivers/gpio/Kconfig +7 -0
@@ -35,3 +35,10 @@ config SANDBOX_GPIO_COUNT are specified using the device tree. But you can also have a number of 'anonymous' GPIOs that do not belong to any device or bank. Select a suitable value depending on your needs. + +config VYBRID_GPIO + bool "Vybrid GPIO driver" + depends on DM + default n + help + Say yes here to support Vybrid vf610 GPIOs.
drivers/gpio/Makefile +1 -0
@@ -45,3 +45,4 @@ obj-$(CONFIG_SUNXI_GPIO) += sunxi_gpio.o obj-$(CONFIG_LPC32XX_GPIO) += lpc32xx_gpio.o obj-$(CONFIG_STM32_GPIO) += stm32_gpio.o obj-$(CONFIG_ZYNQ_GPIO) += zynq_gpio.o +obj-$(CONFIG_VYBRID_GPIO) += vybrid_gpio.o
drivers/gpio/vybrid_gpio.c new file +169 -0
169 lines not on this page · raw message
Signature · 1 line
2.1.0
PATCH 3/11 colibri_vf: Add pinmux entries for GPIOs
In reply to Bhuvanchandra DVInorder to use the pins as GPIO, apart from setting the alt-function, pinmuxing need to be done, this patch adds pinmux entries of few GPIOs.
--- arch/arm/include/asm/arch-vf610/iomux-vf610.h | 49 ++++++++++++++++++++++ board/toradex/colibri_vf/colibri_vf.c | 60 +++++++++++++++++++++++++++ 2 files changed, 109 insertions(+)
arch/arm/include/asm/arch-vf610/iomux-vf610.h +49 -0
@@ -32,22 +32,56 @@#define VF610_QSPI_PAD_CTRL (PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_150ohm | \ PAD_CTL_PUS_22K_UP | PAD_CTL_OBE_IBE_ENABLE) +#define VF610_GPIO_PAD_CTRL (PAD_CTL_SPEED_MED | PAD_CTL_DSE_50ohm | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_IBE_ENABLE) +enum {VF610_PAD_PTA6__RMII0_CLKIN =IOMUX_PAD (0x0000 ,0x0000 ,2 , __NA_,0 ,VF610_ENET_PAD_CTRL ),VF610_PAD_PTA6__RMII0_CLKOUT =IOMUX_PAD (0x0000 ,0x0000 ,1 , __NA_,0 ,VF610_ENET_PAD_CTRL ), +VF610_PAD_PTA7__GPIO_134 =IOMUX_PAD (0x0218 ,0x0218 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ), +VF610_PAD_PTA17__GPIO_7 =IOMUX_PAD (0x001c ,0x001c ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ), +VF610_PAD_PTA20__GPIO_10 =IOMUX_PAD (0x0028 ,0x0028 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ), +VF610_PAD_PTA21__GPIO_11 =IOMUX_PAD (0x002c ,0x002c ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ), +VF610_PAD_PTA30__GPIO_20 =IOMUX_PAD (0x0050 ,0x0050 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ), +VF610_PAD_PTA31__GPIO_21 =IOMUX_PAD (0x0054 ,0x0054 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ), +VF610_PAD_PTB0__GPIO_22 =IOMUX_PAD (0x0058 ,0x0058 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ), +VF610_PAD_PTB1__GPIO_23 =IOMUX_PAD (0x005C ,0x005C ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ),VF610_PAD_PTB4__UART1_TX =IOMUX_PAD (0x0068 ,0x0068 ,2 ,0x0380 ,0 ,VF610_UART_PAD_CTRL ),VF610_PAD_PTB5__UART1_RX =IOMUX_PAD (0x006c ,0x006c ,2 ,0x037c ,0 ,VF610_UART_PAD_CTRL ), +VF610_PAD_PTB6__GPIO_28 =IOMUX_PAD (0x0070 ,0x0070 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ), +VF610_PAD_PTB7__GPIO_29 =IOMUX_PAD (0x0074 ,0x0074 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ), +VF610_PAD_PTB8__GPIO_30 =IOMUX_PAD (0x0078 ,0x0078 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ), +VF610_PAD_PTB9__GPIO_31 =IOMUX_PAD (0x007C ,0x007C ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ),VF610_PAD_PTB10__UART0_TX =IOMUX_PAD (0x0080 ,0x0080 ,1 , __NA_,0 ,VF610_UART_PAD_CTRL ),VF610_PAD_PTB11__UART0_RX =IOMUX_PAD (0x0084 ,0x0084 ,1 , __NA_,0 ,VF610_UART_PAD_CTRL ), +VF610_PAD_PTB12__GPIO_34 =IOMUX_PAD (0x0088 ,0x0088 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ), +VF610_PAD_PTB13__GPIO_35 =IOMUX_PAD (0x008c ,0x008c ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ), +VF610_PAD_PTB16__GPIO_38 =IOMUX_PAD (0x0098 ,0x0098 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ), +VF610_PAD_PTB17__GPIO_39 =IOMUX_PAD (0x009c ,0x009c ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ), +VF610_PAD_PTB18__GPIO_40 =IOMUX_PAD (0x00a0 ,0x00a0 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ), +VF610_PAD_PTB21__GPIO_43 =IOMUX_PAD (0x00ac ,0x00ac ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ), +VF610_PAD_PTB22__GPIO_44 =IOMUX_PAD (0x00b0 ,0x00b0 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ), +VF610_PAD_PTB23__GPIO_93 =IOMUX_PAD (0x0174 ,0x0174 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ), +VF610_PAD_PTB26__GPIO_96 =IOMUX_PAD (0x0180 ,0x0180 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ), +VF610_PAD_PTB28__GPIO_98 =IOMUX_PAD (0x0188 ,0x0188 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ), +VF610_PAD_PTC1__GPIO_46 =IOMUX_PAD (0x00b8 ,0x00b8 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ),VF610_PAD_PTC1__RMII0_MDIO =IOMUX_PAD (0x00b8 ,0x00b8 ,1 , __NA_,0 ,VF610_ENET_PAD_CTRL ), +VF610_PAD_PTC0__GPIO_45 =IOMUX_PAD (0x00b4 ,0x00b4 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ),VF610_PAD_PTC0__RMII0_MDC =IOMUX_PAD (0x00b4 ,0x00b4 ,1 , __NA_,0 ,VF610_ENET_PAD_CTRL ),VF610_PAD_PTC2__RMII0_CRS_DV =IOMUX_PAD (0x00bc ,0x00bc ,1 , __NA_,0 ,VF610_ENET_PAD_CTRL ), +VF610_PAD_PTC2__GPIO_47 =IOMUX_PAD (0x00bc ,0x00bc ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ),VF610_PAD_PTC3__RMII0_RD1 =IOMUX_PAD (0x00c0 ,0x00c0 ,1 , __NA_,0 ,VF610_ENET_PAD_CTRL ), +VF610_PAD_PTC3__GPIO_48 =IOMUX_PAD (0x00c0 ,0x00c0 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ),VF610_PAD_PTC4__RMII0_RD0 =IOMUX_PAD (0x00c4 ,0x00c4 ,1 , __NA_,0 ,VF610_ENET_PAD_CTRL ), +VF610_PAD_PTC4__GPIO_49 =IOMUX_PAD (0x00c4 ,0x00c4 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ),VF610_PAD_PTC5__RMII0_RXER =IOMUX_PAD (0x00c8 ,0x00c8 ,1 , __NA_,0 ,VF610_ENET_PAD_CTRL ), +VF610_PAD_PTC5__GPIO_50 =IOMUX_PAD (0x00c8 ,0x00c8 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ),VF610_PAD_PTC6__RMII0_TD1 =IOMUX_PAD (0x00cc ,0x00cc ,1 , __NA_,0 ,VF610_ENET_PAD_CTRL ), +VF610_PAD_PTC6__GPIO_51 =IOMUX_PAD (0x00cc ,0x00cc ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ),VF610_PAD_PTC7__RMII0_TD0 =IOMUX_PAD (0x00D0 ,0x00D0 ,1 , __NA_,0 ,VF610_ENET_PAD_CTRL ), +VF610_PAD_PTC7__GPIO_52 =IOMUX_PAD (0x00D0 ,0x00D0 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ),VF610_PAD_PTC8__RMII0_TXEN =IOMUX_PAD (0x00D4 ,0x00D4 ,1 , __NA_,0 ,VF610_ENET_PAD_CTRL ), +VF610_PAD_PTC8__GPIO_53 =IOMUX_PAD (0x00D4 ,0x00D4 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ),VF610_PAD_PTC10__RMII1_MDIO =IOMUX_PAD (0x00dc ,0x00dc ,1 , __NA_,0 ,VF610_ENET_PAD_CTRL ),VF610_PAD_PTC9__RMII1_MDC =IOMUX_PAD (0x00d8 ,0x00d8 ,1 , __NA_,0 ,VF610_ENET_PAD_CTRL ),VF610_PAD_PTC11__RMII1_CRS_DV =IOMUX_PAD (0x00e0 ,0x00e0 ,1 , __NA_,0 ,VF610_ENET_PAD_CTRL ),
@@ -57,6 +91,8 @@ enum {VF610_PAD_PTC15__RMII1_TD1 =IOMUX_PAD (0x00f0 ,0x00f0 ,1 , __NA_,0 ,VF610_ENET_PAD_CTRL ),VF610_PAD_PTC16__RMII1_TD0 =IOMUX_PAD (0x00f4 ,0x00f4 ,1 , __NA_,0 ,VF610_ENET_PAD_CTRL ),VF610_PAD_PTC17__RMII1_TXEN =IOMUX_PAD (0x00f8 ,0x00f8 ,1 , __NA_,0 ,VF610_ENET_PAD_CTRL ), +VF610_PAD_PTC29__GPIO_102 =IOMUX_PAD (0x0198 ,0x0198 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ), +VF610_PAD_PTC30__GPIO_103 =IOMUX_PAD (0x019c ,0x019c ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ),VF610_PAD_PTA24__ESDHC1_CLK =IOMUX_PAD (0x0038 ,0x0038 ,5 , __NA_,0 ,VF610_SDHC_PAD_CTRL ),VF610_PAD_PTA25__ESDHC1_CMD =IOMUX_PAD (0x003c ,0x003c ,5 , __NA_,0 ,VF610_SDHC_PAD_CTRL ), VF610_PAD_PTA26__ESDHC1_DAT0 = IOMUX_PAD(0x0040, 0x0040, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
@@ -66,13 +102,21 @@ enum {VF610_PAD_PTB14__I2C0_SCL =IOMUX_PAD (0x0090 ,0x0090 ,2 ,0x033c ,1 ,VF610_I2C_PAD_CTRL ),VF610_PAD_PTB15__I2C0_SDA =IOMUX_PAD (0x0094 ,0x0094 ,2 ,0x0340 ,1 ,VF610_I2C_PAD_CTRL ),VF610_PAD_PTD31__NF_IO15 =IOMUX_PAD (0x00fc ,0x00fc ,2 , __NA_,0 ,VF610_NFC_IO_PAD_CTRL ), +VF610_PAD_PTD31__GPIO_63 =IOMUX_PAD (0x00fc ,0x00fc ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ),VF610_PAD_PTD30__NF_IO14 =IOMUX_PAD (0x0100 ,0x0100 ,2 , __NA_,0 ,VF610_NFC_IO_PAD_CTRL ), +VF610_PAD_PTD30__GPIO_64 =IOMUX_PAD (0x0100 ,0x0100 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ),VF610_PAD_PTD29__NF_IO13 =IOMUX_PAD (0x0104 ,0x0104 ,2 , __NA_,0 ,VF610_NFC_IO_PAD_CTRL ), +VF610_PAD_PTD29__GPIO_65 =IOMUX_PAD (0x0104 ,0x0104 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ),VF610_PAD_PTD28__NF_IO12 =IOMUX_PAD (0x0108 ,0x0108 ,2 , __NA_,0 ,VF610_NFC_IO_PAD_CTRL ), +VF610_PAD_PTD28__GPIO_66 =IOMUX_PAD (0x0108 ,0x0108 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ),VF610_PAD_PTD27__NF_IO11 =IOMUX_PAD (0x010c ,0x010c ,2 , __NA_,0 ,VF610_NFC_IO_PAD_CTRL ), +VF610_PAD_PTD27__GPIO_67 =IOMUX_PAD (0x010c ,0x010c ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ),VF610_PAD_PTD26__NF_IO10 =IOMUX_PAD (0x0110 ,0x0110 ,2 , __NA_,0 ,VF610_NFC_IO_PAD_CTRL ), +VF610_PAD_PTD26__GPIO_68 =IOMUX_PAD (0x0110 ,0x0110 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ),VF610_PAD_PTD25__NF_IO9 =IOMUX_PAD (0x0114 ,0x0114 ,2 , __NA_,0 ,VF610_NFC_IO_PAD_CTRL ), +VF610_PAD_PTD25__GPIO_69 =IOMUX_PAD (0x0114 ,0x0114 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ),VF610_PAD_PTD24__NF_IO8 =IOMUX_PAD (0x0118 ,0x0118 ,2 , __NA_,0 ,VF610_NFC_IO_PAD_CTRL ), +VF610_PAD_PTD24__GPIO_70 =IOMUX_PAD (0x0118 ,0x0118 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ),VF610_PAD_PTD23__NF_IO7 =IOMUX_PAD (0x011c ,0x011c ,2 , __NA_,0 ,VF610_NFC_IO_PAD_CTRL ),VF610_PAD_PTD0__QSPI0_A_QSCK =IOMUX_PAD (0x013c ,0x013c ,1 , __NA_,0 ,VF610_QSPI_PAD_CTRL ), VF610_PAD_PTD1__QSPI0_A_CS0 = IOMUX_PAD(0x0140, 0x0140, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
@@ -83,9 +127,14 @@ enum {VF610_PAD_PTD7__QSPI0_B_QSCK =IOMUX_PAD (0x0158 ,0x0158 ,1 , __NA_,0 ,VF610_QSPI_PAD_CTRL ),VF610_PAD_PTD8__QSPI0_B_CS0 =IOMUX_PAD (0x015c ,0x015c ,1 , __NA_,0 ,VF610_QSPI_PAD_CTRL ),VF610_PAD_PTD9__QSPI0_B_DATA3 =IOMUX_PAD (0x0160 ,0x0160 ,1 , __NA_,0 ,VF610_QSPI_PAD_CTRL ), +VF610_PAD_PTD9__GPIO_88 =IOMUX_PAD (0x0160 ,0x0160 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ),VF610_PAD_PTD10__QSPI0_B_DATA2 =IOMUX_PAD (0x0164 ,0x0164 ,1 , __NA_,0 ,VF610_QSPI_PAD_CTRL ), +VF610_PAD_PTD10__GPIO_89 =IOMUX_PAD (0x0164 ,0x0164 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ),VF610_PAD_PTD11__QSPI0_B_DATA1 =IOMUX_PAD (0x0168 ,0x0168 ,1 , __NA_,0 ,VF610_QSPI_PAD_CTRL ), +VF610_PAD_PTD11__GPIO_90 =IOMUX_PAD (0x0168 ,0x0168 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ),VF610_PAD_PTD12__QSPI0_B_DATA0 =IOMUX_PAD (0x016c ,0x016c ,1 , __NA_,0 ,VF610_QSPI_PAD_CTRL ), +VF610_PAD_PTD12__GPIO_91 =IOMUX_PAD (0x016c ,0x016c ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ), +VF610_PAD_PTD13__GPIO_92 =IOMUX_PAD (0x0170 ,0x0170 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ),VF610_PAD_PTD22__NF_IO6 =IOMUX_PAD (0x0120 ,0x0120 ,2 , __NA_,0 ,VF610_NFC_IO_PAD_CTRL ),VF610_PAD_PTD21__NF_IO5 =IOMUX_PAD (0x0124 ,0x0124 ,2 , __NA_,0 ,VF610_NFC_IO_PAD_CTRL ), VF610_PAD_PTD20__NF_IO4 = IOMUX_PAD(0x0128, 0x0128, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
board/toradex/colibri_vf/colibri_vf.c +60 -0
72 lines not on this page · raw message
Signature · 1 line
2.1.0
PATCH 4/11 colibri_vf: Enable GPIO support
In reply to Bhuvanchandra DV--- configs/colibri_vf_defconfig | 1 + include/configs/colibri_vf.h | 5 +++++ 2 files changed, 6 insertions(+)
configs/colibri_vf_defconfig +1 -0
@@ -1,3 +1,4 @@ CONFIG_ARM=y CONFIG_TARGET_COLIBRI_VF=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_vf/imximage.cfg,ENV_IS_IN_NAND,IMX_NAND" +CONFIG_DM=y
include/configs/colibri_vf.h +5 -0
@@ -55,6 +55,11 @@#define CONFIG_SYS_MAX_NAND_DEVICE 1#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR +/* GPIO support */ +#define CONFIG_DM_GPIO +#define CONFIG_CMD_GPIO +#define CONFIG_VYBRID_GPIO +/* Dynamic MTD partition support */ #define CONFIG_CMD_MTDPARTS /* Enable 'mtdparts' command line support */ #define CONFIG_MTD_PARTITIONS
Signature · 1 line
2.1.0
PATCH 5/11 arm: vf610: Add clock support for DSPI
In reply to Bhuvanchandra DV--- arch/arm/cpu/armv7/vf610/generic.c | 7 +++++++ arch/arm/include/asm/arch-vf610/clock.h | 1 + arch/arm/include/asm/arch-vf610/crm_regs.h | 4 ++++ 3 files changed, 12 insertions(+)
arch/arm/cpu/armv7/vf610/generic.c +7 -0
@@ -198,6 +198,11 @@ static u32 get_i2c_clk(void)return get_ipg_clk (); } +static u32 get_dspi_clk (void ) +{ +return get_ipg_clk (); +} +unsigned int mxc_get_clock (enum mxc_clock clk) {switch (clk) {
@@ -215,6 +220,8 @@ unsigned int mxc_get_clock(enum mxc_clock clk)return get_fec_clk ();case MXC_I2C_CLK :return get_i2c_clk (); +case MXC_DSPI_CLK : +return get_dspi_clk ();default :break ; }
arch/arm/include/asm/arch-vf610/clock.h +1 -0
@@ -17,6 +17,7 @@ enum mxc_clock {MXC_ESDHC_CLK ,MXC_FEC_CLK ,MXC_I2C_CLK , + MXC_DSPI_CLK, };void enable_ocotp_clk (unsigned char enable);
arch/arm/include/asm/arch-vf610/crm_regs.h +4 -0
@@ -189,6 +189,8 @@ struct anadig_reg {#define CCM_REG_CTRL_MASK 0xffffffff#define CCM_CCGR0_UART0_CTRL_MASK (0x3 << 14)#define CCM_CCGR0_UART1_CTRL_MASK (0x3 << 16) +#define CCM_CCGR0_DSPI0_CTRL_MASK (0x3 << 24) +#define CCM_CCGR0_DSPI1_CTRL_MASK (0x3 << 26)#define CCM_CCGR1_USBC0_CTRL_MASK (0x3 << 8)#define CCM_CCGR1_PIT_CTRL_MASK (0x3 << 14)#define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 << 28)
@@ -206,6 +208,8 @@ struct anadig_reg {#define CCM_CCGR4_GPC_CTRL_MASK (0x3 << 24)#define CCM_CCGR4_I2C0_CTRL_MASK (0x3 << 12)#define CCM_CCGR6_OCOTP_CTRL_MASK (0x3 << 10) +#define CCM_CCGR6_DSPI2_CTRL_MASK (0x3 << 24) +#define CCM_CCGR6_DSPI3_CTRL_MASK (0x3 << 26)#define CCM_CCGR6_DDRMC_CTRL_MASK (0x3 << 28)#define CCM_CCGR7_SDHC1_CTRL_MASK (0x3 << 4)#define CCM_CCGR7_USBC1_CTRL_MASK (0x3 << 8)
Signature · 1 line
2.1.0
PATCH 6/11 arm: vf610: Add iomux support for DSPI
In reply to Bhuvanchandra DVAdd iomux definitions for DSPI second instance.
--- arch/arm/include/asm/arch-vf610/iomux-vf610.h | 9 +++++++++ board/toradex/colibri_vf/colibri_vf.c | 21 +++++++++++++++++++++ 2 files changed, 30 insertions(+)
arch/arm/include/asm/arch-vf610/iomux-vf610.h +9 -0
@@ -35,6 +35,11 @@#define VF610_GPIO_PAD_CTRL (PAD_CTL_SPEED_MED | PAD_CTL_DSE_50ohm | \ PAD_CTL_PUS_47K_UP | PAD_CTL_IBE_ENABLE) +#define VF610_DSPI_PAD_CTRL (PAD_CTL_OBE_ENABLE | PAD_CTL_DSE_20ohm | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH) +#define VF610_DSPI_SIN_PAD_CTRL (PAD_CTL_IBE_ENABLE | PAD_CTL_DSE_20ohm | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH) +enum {VF610_PAD_PTA6__RMII0_CLKIN =IOMUX_PAD (0x0000 ,0x0000 ,2 , __NA_,0 ,VF610_ENET_PAD_CTRL ),VF610_PAD_PTA6__RMII0_CLKOUT =IOMUX_PAD (0x0000 ,0x0000 ,1 , __NA_,0 ,VF610_ENET_PAD_CTRL ),
@@ -91,6 +96,10 @@ enum {VF610_PAD_PTC15__RMII1_TD1 =IOMUX_PAD (0x00f0 ,0x00f0 ,1 , __NA_,0 ,VF610_ENET_PAD_CTRL ),VF610_PAD_PTC16__RMII1_TD0 =IOMUX_PAD (0x00f4 ,0x00f4 ,1 , __NA_,0 ,VF610_ENET_PAD_CTRL ),VF610_PAD_PTC17__RMII1_TXEN =IOMUX_PAD (0x00f8 ,0x00f8 ,1 , __NA_,0 ,VF610_ENET_PAD_CTRL ), +VF610_PAD_PTD5__DSPI1_CS0 =IOMUX_PAD (0x0150 ,0x0150 ,3 ,0x300 ,1 ,VF610_DSPI_PAD_CTRL ), +VF610_PAD_PTD6__DSPI1_SIN =IOMUX_PAD (0x0154 ,0x0154 ,3 ,0x2fc ,1 ,VF610_DSPI_SIN_PAD_CTRL ), +VF610_PAD_PTD7__DSPI1_SOUT =IOMUX_PAD (0x0158 ,0x0158 ,3 , __NA_,0 ,VF610_DSPI_PAD_CTRL ), +VF610_PAD_PTD8__DSPI1_SCK =IOMUX_PAD (0x015c ,0x015c ,3 ,0x2f8 ,1 ,VF610_DSPI_PAD_CTRL ),VF610_PAD_PTC29__GPIO_102 =IOMUX_PAD (0x0198 ,0x0198 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ),VF610_PAD_PTC30__GPIO_103 =IOMUX_PAD (0x019c ,0x019c ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ), VF610_PAD_PTA24__ESDHC1_CLK = IOMUX_PAD(0x0038, 0x0038, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
board/toradex/colibri_vf/colibri_vf.c +21 -0
@@ -146,6 +146,20 @@ static void setup_iomux_nfc(void) }#endif +#ifdef CONFIG_FSL_DSPI +static void setup_iomux_dspi (void ) +{ +static const iomux_v3_cfg_t dspi1_pads[] = { +VF610_PAD_PTD5__DSPI1_CS0 , +VF610_PAD_PTD6__DSPI1_SIN , +VF610_PAD_PTD7__DSPI1_SOUT , +VF610_PAD_PTD8__DSPI1_SCK , + }; + +imx_iomux_v3_setup_multiple_pads (dspi1_pads,ARRAY_SIZE (dspi1_pads)); +} +#endif +#ifdef CONFIG_VYBRID_GPIO static void setup_iomux_gpio (void ) {
@@ -252,6 +266,9 @@ static void clock_init(void)clrsetbits_le32 (&ccm->ccgr0,CCM_REG_CTRL_MASK ,CCM_CCGR0_UART0_CTRL_MASK ); +#ifdef CONFIG_FSL_DSPI +setbits_le32 (&ccm->ccgr0,CCM_CCGR0_DSPI1_CTRL_MASK ); +#endif clrsetbits_le32 (&ccm->ccgr1,CCM_REG_CTRL_MASK ,CCM_CCGR1_PIT_CTRL_MASK |CCM_CCGR1_WDOGA5_CTRL_MASK ); clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
@@ -364,6 +381,10 @@ int board_early_init_f(void)setup_iomux_gpio ();#endif +#ifdef CONFIG_FSL_DSPI +setup_iomux_dspi (); +#endif +return 0 ; }
Signature · 1 line
2.1.0
PATCH 7/11 vf610: dts: Add device tree support
In reply to Bhuvanchandra DVAdd device tree files for Freescale Vybrid platform and Toradex Colibri VF50, VF61 modules.
Device tree files are taken from upstream Kernel. Removed the stuff which are not used/supported yet in U-Boot.
--- arch/arm/dts/Makefile | 3 ++ arch/arm/dts/vf-colibri.dtsi | 21 +++++++++ arch/arm/dts/vf.dtsi | 100 +++++++++++++++++++++++++++++++++++++++++ arch/arm/dts/vf500-colibri.dts | 18 ++++++++ arch/arm/dts/vf610-colibri.dts | 18 ++++++++ 5 files changed, 160 insertions(+) create mode 100644 arch/arm/dts/vf-colibri.dtsi create mode 100644 arch/arm/dts/vf.dtsi create mode 100644 arch/arm/dts/vf500-colibri.dts create mode 100644 arch/arm/dts/vf610-colibri.dts
arch/arm/dts/Makefile +3 -0
@@ -130,6 +130,9 @@ dtb-$(CONFIG_MACH_SUN9I) += \ sun9i-a80-optimus.dtb \ sun9i-a80-cubieboard4.dtb +dtb-$(CONFIG_VF610) += vf500-colibri.dtb \ + vf610-colibri.dtb + targets += $(dtb-y) DTC_FLAGS += -R 4 -p 0x1000
arch/arm/dts/vf-colibri.dtsi new file +21 -0
@@ -0,0 +1,21 @@ +/* + * Copyright 2014 Toradex AG + * + * SPDX-License-Identifier: GPL-2.0+ or X11 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#include "vf.dtsi" + +&dspi1 { + status = "okay"; + bus-num = <1>; + + spi_cmd: sspi at 0 { + reg = <0>; + spi-max-frequency = <50000000>; + }; +};
arch/arm/dts/vf.dtsi new file +100 -0
100 lines not on this page · raw message
arch/arm/dts/vf500-colibri.dts new file +18 -0
@@ -0,0 +1,18 @@ +/* + * Copyright 2014 Toradex AG + * + * SPDX-License-Identifier: GPL-2.0+ or X11 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +/dts-v1/; +#include "vf-colibri.dtsi" + +/ { + model = "Toradex Colibri VF50"; + compatible = "toradex,vf500-colibri_vf50", "toradex,vf500-colibri_vf50", "fsl,vf500"; +};
arch/arm/dts/vf610-colibri.dts new file +18 -0
@@ -0,0 +1,18 @@ +/* + * Copyright 2014 Toradex AG + * + * SPDX-License-Identifier: GPL-2.0+ or X11 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +/dts-v1/; +#include "vf-colibri.dtsi" + +/ { + model = "Toradex Colibri VF61"; + compatible = "toradex,vf610-colibri_vf61", "toradex,vf610-colibri_vf61", "fsl,vf610"; +};
Signature · 1 line
2.1.0
PATCH 8/11 colibri-vf: Enable SPI support
In reply to Bhuvanchandra DV--- include/configs/colibri_vf.h | 11 +++++++++++ 1 file changed, 11 insertions(+)
include/configs/colibri_vf.h +11 -0
@@ -273,4 +273,15 @@#define CONFIG_USB_GADGET_MASS_STORAGE #define CONFIG_CMD_USB_MASS_STORAGE +/* Enable SPI support */ +#define CONFIG_DM_SPI +#define CONFIG_CMD_SPI +#define CONFIG_FSL_DSPI + +#ifndef CONFIG_OF_CONTROL +#undef CONFIG_DM_SPI +#undef CONFIG_CMD_SPI +#undef CONFIG_FSL_DSPI +#endif +#endif /* __CONFIG_H */
Signature · 1 line
2.1.0
PATCH 9/11 colibri_vf: Add separate defconfig for device tree support
In reply to Bhuvanchandra DVMost of the drivers available for Vybrid are not yet converted to OF model to use device tree model, only few drivers like SPI and GPIO drivers use device trees.
Add separate defconfig for who needs to use device tree model. Later this can be integrated to single defconfig.
--- configs/colibri_vf_dtb_defconfig | 6 ++++++ 1 file changed, 6 insertions(+) create mode 100644 configs/colibri_vf_dtb_defconfig
configs/colibri_vf_dtb_defconfig new file +6 -0
@@ -0,0 +1,6 @@ +CONFIG_ARM=y +CONFIG_TARGET_COLIBRI_VF=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_vf/imximage.cfg,ENV_IS_IN_NAND,IMX_NAND" +CONFIG_DM=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="vf610-colibri"
Signature · 1 line
2.1.0
PATCH 9/11 colibri_vf: Add separate defconfig for device tree support
Hi Bhuvanchandra,
Quoted 19 lines · Bhuvanchandra DV
Most of the drivers available for Vybrid are not yet converted to OF model to use device tree model, only few drivers like SPI and GPIO drivers use device trees.
Add separate defconfig for who needs to use device tree model. Later this can be integrated to single defconfig.Signed-off-by Bhuvanchandra DV <[email protected]>--- configs/colibri_vf_dtb_defconfig | 6 ++++++ 1 file changed, 6 insertions(+) create mode 100644 configs/colibri_vf_dtb_defconfigconfigs/colibri_vf_dtb_defconfig new file +0
-0
configs/colibri_vf_dtb_defconfig line 6
Quoted 6 lines
configs/colibri_vf_dtb_defconfig new file +6
-0@@ -0,0 +1,6 @@ +CONFIG_ARM=y +CONFIG_TARGET_COLIBRI_VF=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_vf/imximage.cfg,ENV_IS_IN_NAND,IMX_NAND" +CONFIG_DM=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="vf610-colibri"
This patch is broken because NAND setup is missing and the board colibri_vf_dtp is not built.
Indeed, it is fixed with:
(quoted diff) +0 -0
b/configs/colibri_vf_dtb_defconfig
index 28ff1e9..88ecbdc 100644
configs/colibri_vf_dtb_defconfig +0 -0
@@ -4,3 +4,5 @@
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_vf/imximage.cfg,ENV_I
CONFIG_DM=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="vf610-colibri"
+CONFIG_NAND_VF610_NFC=y
+CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES=y
Please add these to your patch and resubmit, thanks !
Best regards,
Stefano Babic
Signature · 5 lines
===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de =====================================================================
PATCH 9/11 colibri_vf: Add separate defconfig for device tree support
Hello Stefano,
Quoted 48 lines · Stefano Babic
Hi Bhuvanchandra,
Quoted 19 lines · Bhuvanchandra DV
Most of the drivers available for Vybrid are not yet converted to OF model to use device tree model, only few drivers like SPI and GPIO drivers use device trees.
Add separate defconfig for who needs to use device tree model. Later this can be integrated to single defconfig.Signed-off-by Bhuvanchandra DV <[email protected]>--- configs/colibri_vf_dtb_defconfig | 6 ++++++ 1 file changed, 6 insertions(+)create mode 100644 configs/colibri_vf_dtb_defconfig
configs/colibri_vf_dtb_defconfig new file +0
-0configs/colibri_vf_dtb_defconfig line 6
Quoted 6 lines
configs/colibri_vf_dtb_defconfig new file +6
-0@@ -0,0 +1,6 @@ +CONFIG_ARM=y +CONFIG_TARGET_COLIBRI_VF=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_vf/imximage.cfg,ENV_IS_IN_NAND,IMX_NAND" +CONFIG_DM=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="vf610-colibri"This patch is broken because NAND setup is missing and the board
colibri_vf_dtpis not built.Indeed, it is fixed with:
configs/colibri_vf_dtb_defconfig +0
-0@@ -4,3 +4,5 @@
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_vf/imximage.cfg,ENV_I
CONFIG_DM=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="vf610-colibri"configs/colibri_vf_dtb_defconfig +2
-0+CONFIG_NAND_VF610_NFC=y +CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES=y
Quoted 1 line
Please add these to your patch and resubmit, thanks !
Will add this and resubmit the patchset.
Quoted 4 lines
Best regards,
Stefano Babic
Best regards,
Bhuvan
PATCH 10/11 usb: ehci-vf: Add weak function for board specific initialisation
In reply to Bhuvanchandra DVFrom: Sanchayan Maity <[email protected]>
Add a weak function board_ehci_hcd_init which can be used by the board file for board specific initialisation.
--- drivers/usb/host/ehci-vf.c | 8 ++++++++ 1 file changed, 8 insertions(+)
drivers/usb/host/ehci-vf.c +8 -0
@@ -121,6 +121,11 @@ static void usb_oc_config(int index)setbits_le32 (ctrl,UCTRL_OVER_CUR_DIS ); } +int __weak board_ehci_hcd_init (int port) +{ +return 0 ; +} +int ehci_hcd_init (int index,enum usb_init_type init,struct ehci_hccr **hccr,struct ehci_hcor **hcor) {
@@ -136,6 +141,9 @@ int ehci_hcd_init(int index, enum usb_init_type init, ehci = (struct usb_ehci *)nc_reg_bases[index]; +/* Do board specific initialisation */ +board_ehci_hcd_init (index); +usb_power_config (index);usb_oc_config (index);usb_internal_phy_clock_gate (index);
Signature · 1 line
2.1.0
PATCH 10/11 usb: ehci-vf: Add weak function for board specific initialisation
Quoted 6 lines · Bhuvanchandra DV
From: Sanchayan Maity <[email protected]>
Add a weak function
board_ehci_hcd_initwhich can be used by the board file for board specific initialisation.Signed-off-by Sanchayan Maity <[email protected]>
What I do not like is that you're sending a patch series which affects multiple subsystems and which contains patches which should go through multiple trees. Yet, you submit it all in one huge series.
I guess the best way out of this is to push all this stuff via u-boot-imx now?
Best regards,
Marek Vasut
PATCH 10/11 usb: ehci-vf: Add weak function for board specific initialisation
Hello Marek,
Quoted 6 lines · Marek Vasut
Quoted 5 lines · Bhuvanchandra DV
From: Sanchayan Maity <[email protected]>
Add a weak function
board_ehci_hcd_initwhich can be used by the board file for board specific initialisation.
Quoted 7 lines
Quoted 1 line
Signed-off-by Sanchayan Maity <[email protected]>Acked-by Marek Vasut <[email protected]>What I do not like is that you're sending a patch series which affects multiple subsystems and which contains patches which should go through multiple trees. Yet, you submit it all in one huge series.
If required I can send in the last two patches affecting the USB susbsystem later once the rest of the patchset gets merged, if this is not acceptable?.
Since these last two were dependent on the GPIO patches I thought perhaps it is better that they go along with the GPIO patches as a coherent whole.
Quoted 5 lines
I guess the best way out of this is to push all this stuff via u-boot-imx now?
Best regards,
Marek Vasut
Thanks & Regards,
Sanchayan Maity.
PATCH 10/11 usb: ehci-vf: Add weak function for board specific initialisation
Quoted 1 line · maitysanchayan at gmail.com
Hello Marek,
Hi!
Quoted 15 lines · Marek Vasut
Quoted 6 lines · Bhuvanchandra DV
Quoted 5 lines
From: Sanchayan Maity <[email protected]>
Add a weak function
board_ehci_hcd_initwhich can be used by the board file for board specific initialisation.Quoted 7 lines
Quoted 1 line
Signed-off-by Sanchayan Maity <[email protected]>Acked-by Marek Vasut <[email protected]>What I do not like is that you're sending a patch series which affects multiple subsystems and which contains patches which should go through multiple trees. Yet, you submit it all in one huge series.
Quoted 7 lines
If required I can send in the last two patches affecting the USB susbsystem later once the rest of the patchset gets merged, if this is not acceptable?.
Since these last two were dependent on the GPIO patches I thought perhaps it is better that they go along with the GPIO patches as a coherent whole.
I think if there's no oposition, just push this all via u-boot-imx . I don't plan to block it, but subsystem stuff should usually go though subsystem trees.
Best regards,
Marek Vasut
PATCH 11/11 colibri_vf: Enable board specific USB initialisation for USB pen gpio
In reply to Bhuvanchandra DVFrom: Sanchayan Maity <[email protected]>
Add IOMUX for the pad used as USB pen. This needs to be driven low for the Iris and Viola boards where it is pulled up high by default. This is required for the USB host functionality to work on these boards. Use the board specific weak initialisation function, to drive the pin low which would be called on "usb start".
--- arch/arm/include/asm/arch-vf610/iomux-vf610.h | 1 + board/toradex/colibri_vf/colibri_vf.c | 25 +++++++++++++++++++++++++ 2 files changed, 26 insertions(+)
arch/arm/include/asm/arch-vf610/iomux-vf610.h +1 -0
@@ -131,6 +131,7 @@ enum {VF610_PAD_PTD1__QSPI0_A_CS0 =IOMUX_PAD (0x0140 ,0x0140 ,1 , __NA_,0 ,VF610_QSPI_PAD_CTRL ),VF610_PAD_PTD2__QSPI0_A_DATA3 =IOMUX_PAD (0x0144 ,0x0144 ,1 , __NA_,0 ,VF610_QSPI_PAD_CTRL ),VF610_PAD_PTD3__QSPI0_A_DATA2 =IOMUX_PAD (0x0148 ,0x0148 ,1 , __NA_,0 ,VF610_QSPI_PAD_CTRL ), +VF610_PAD_PTD4__GPIO_83 =IOMUX_PAD (0x014C ,0x014C ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ),VF610_PAD_PTD4__QSPI0_A_DATA1 =IOMUX_PAD (0x014c ,0x014c ,1 , __NA_,0 ,VF610_QSPI_PAD_CTRL ),VF610_PAD_PTD5__QSPI0_A_DATA0 =IOMUX_PAD (0x0150 ,0x0150 ,1 , __NA_,0 ,VF610_QSPI_PAD_CTRL ), VF610_PAD_PTD7__QSPI0_B_QSCK = IOMUX_PAD(0x0158, 0x0158, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
board/toradex/colibri_vf/colibri_vf.c +25 -0
@@ -20,6 +20,7 @@#include <netdev.h> #include <i2c.h> #include <g_dnl.h> +#include <asm/gpio.h> DECLARE_GLOBAL_DATA_PTR ;
@@ -32,6 +33,12 @@ DECLARE_GLOBAL_DATA_PTR;#define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \ PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE) +#define USB_PEN_GPIO 83 + +static const iomux_v3_cfg_t usb_pads[] = { +VF610_PAD_PTD4__GPIO_83 , +}; +int dram_init (void ) {static const struct ddr3_jedec_timings timings = {
@@ -464,3 +471,21 @@ int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)return 0 ; } + +#ifdef CONFIG_USB_EHCI_VF +int board_ehci_hcd_init (int port) +{ +imx_iomux_v3_setup_multiple_pads (usb_pads,ARRAY_SIZE (usb_pads)); + +switch (port) { +case 0 : +/* USBC does not have PEN, also configured as USB client only */ +break ; +case 1 : +gpio_request (USB_PEN_GPIO ,"usb-pen-gpio" ); +gpio_direction_output (USB_PEN_GPIO ,0 ); +break ; + } +return 0 ; +} +#endif
Signature · 1 line
2.1.0
cover Add GPIO driver for Freescale Vybrid platform
In reply to Bhuvanchandra DVHello Stefano,
Quoted 23 lines · Bhuvanchandra DV
This patch-set adds GPIO driver, DSPI and device tree support for Freescale Vybrid platform and Toradex Colibri Vybrid VF50, VF61 modules.
Following cases are tested with Vybrid GPIO driver:
- with DM, without DT
- with DM and DT
Both the above cases were tested on Toradex Colibri Vybrid VF50, VF61 modules and both works fine.- The patchset is based and tested on the latest master branch.
Bhuvanchandra DV (9):
dm: gpio: uclass: Add flag to control sequence numbering
dm: gpio: vf610: Add GPIO driver support
colibri_vf: Add pinmux entries for GPIOs
colibri_vf: Enable GPIO support
arm: vf610: Add clock support for DSPI
arm: vf610: Add iomux support for DSPI
vf610: dts: Add device tree support
colibri-vf: Enable SPI support
colibri_vf: Add separate defconfig for device tree support
Quoted 3 lines
Sanchayan Maity (2):
usb: ehci-vf: Add weak function for board specific initialisation
colibri_vf: Enable board specific USB initialisation for USB pen gpio
Submitted these patches in single series, as few of the patches are interdependent, thought it would be easy to keep them in same series.
Shall we split this patchset as per the custodian maintainers to pick?
Patchset 1: Add GPIO driver support for Freescale Vybrid platform, enable support for GPIO support on Toradex Colibri VF50, VF61 modules.
Patchset 2: Add device tree support for Freescale Vybrid Platform, Toradex Colibri VF50, VF61 modules.
Patchset 3: Add DSPI support for Toradex Colibri VF50, VF61 modules.
Patchset 4: Add weak function for board specific USB initialization for Freescale Vybrid platform.
Quoted 24 lines
arch/arm/cpu/armv7/vf610/generic.c | 7 ++ arch/arm/dts/Makefile | 3 + arch/arm/dts/vf-colibri.dtsi | 21 ++++ arch/arm/dts/vf.dtsi | 100 +++++++++++++++ arch/arm/dts/vf500-colibri.dts | 18 +++ arch/arm/dts/vf610-colibri.dts | 18 +++ arch/arm/imx-common/iomux-v3.c | 26 ++++ arch/arm/include/asm/arch-vf610/clock.h | 1 + arch/arm/include/asm/arch-vf610/crm_regs.h | 4 + arch/arm/include/asm/arch-vf610/gpio.h | 29 +++++ arch/arm/include/asm/arch-vf610/imx-regs.h | 5 + arch/arm/include/asm/arch-vf610/iomux-vf610.h | 59 +++++++++ arch/arm/include/asm/imx-common/iomux-v3.h | 6 + board/toradex/colibri_vf/colibri_vf.c | 106 ++++++++++++++++ configs/colibri_vf_defconfig | 1 + configs/colibri_vf_dtb_defconfig | 6 + drivers/gpio/Kconfig | 7 ++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-uclass.c | 1 + drivers/gpio/vybrid_gpio.c | 169 ++++++++++++++++++++++++++ drivers/usb/host/ehci-vf.c | 8 ++ include/configs/colibri_vf.h | 16 +++ 22 files changed, 612 insertions(+)
Quoted 8 lines
create mode 100644
arch/arm/dts/vf-colibri.dtsicreate mode 100644arch/arm/dts/vf.dtsi
create mode 100644arch/arm/dts/vf500-colibri.dtscreate mode 100644arch/arm/dts/vf610-colibri.dtscreate mode 100644arch/arm/include/asm/arch-vf610/gpio.hcreate mode 100644 configs/colibri_vf_dtb_defconfig create mode 100644drivers/gpio/vybrid_gpio.c
Best regards,
Bhuvan
cover Add GPIO driver for Freescale Vybrid platform
Hi,
Quoted 38 lines · Bhuvanchandra DV
Hello Stefano,
Quoted 23 lines · Bhuvanchandra DV
This patch-set adds GPIO driver, DSPI and device tree support for Freescale Vybrid platform and Toradex Colibri Vybrid VF50, VF61 modules.
Following cases are tested with Vybrid GPIO driver:
- with DM, without DT
- with DM and DT
Both the above cases were tested on Toradex Colibri Vybrid VF50, VF61 modules and both works fine.- The patchset is based and tested on the latest master branch.
Bhuvanchandra DV (9):
dm: gpio: uclass: Add flag to control sequence numbering
dm: gpio: vf610: Add GPIO driver support
colibri_vf: Add pinmux entries for GPIOs
colibri_vf: Enable GPIO support
arm: vf610: Add clock support for DSPI
arm: vf610: Add iomux support for DSPI
vf610: dts: Add device tree support
colibri-vf: Enable SPI support
colibri_vf: Add separate defconfig for device tree supportQuoted 3 lines
Sanchayan Maity (2):
usb: ehci-vf: Add weak function for board specific initialisation
colibri_vf: Enable board specific USB initialisation for USB pen gpioSubmitted these patches in single series, as few of the patches are interdependent, thought it would be easy to keep them in same series.
Shall we split this patchset as per the custodian maintainers to pick?
Patchset 1: Add GPIO driver support for Freescale Vybrid platform, enable support for GPIO support on Toradex Colibri VF50, VF61 modules.
Quoted 7 lines
Patchset 2: Add device tree support for Freescale Vybrid Platform, Toradex Colibri VF50, VF61 modules.
Patchset 3: Add DSPI support for Toradex Colibri VF50, VF61 modules.
Patchset 4: Add weak function for board specific USB initialization for Freescale Vybrid platform.
Generally, if a maintainer acks a patch, the patch could then be applied into another tree if this makes sense and avoid to introduce breakage, maybe in both trees. You patchset is related to u-boot-imx with exception for the USB part, but Marek has already acked it. I will check you patches soon, but I think it is ok if the whole patchset flows into u-boot-imx.
Best regards,
Stefano Babic
Signature · 5 lines
===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de =====================================================================
cover Add GPIO driver for Freescale Vybrid platform
Hello,
Quoted 49 lines · Stefano Babic
Hi,
Quoted 38 lines · Bhuvanchandra DV
Hello Stefano,
Quoted 23 lines · Bhuvanchandra DV
This patch-set adds GPIO driver, DSPI and device tree support for Freescale Vybrid platform and Toradex Colibri Vybrid VF50, VF61 modules.
Following cases are tested with Vybrid GPIO driver:
- with DM, without DT
- with DM and DT
Both the above cases were tested on Toradex Colibri Vybrid VF50, VF61 modules and both works fine.- The patchset is based and tested on the latest master branch.
Bhuvanchandra DV (9):
dm: gpio: uclass: Add flag to control sequence numbering
dm: gpio: vf610: Add GPIO driver support
colibri_vf: Add pinmux entries for GPIOs
colibri_vf: Enable GPIO support
arm: vf610: Add clock support for DSPI
arm: vf610: Add iomux support for DSPI
vf610: dts: Add device tree support
colibri-vf: Enable SPI support
colibri_vf: Add separate defconfig for device tree supportQuoted 3 lines
Sanchayan Maity (2):
usb: ehci-vf: Add weak function for board specific initialisation
colibri_vf: Enable board specific USB initialisation for USB pen gpioSubmitted these patches in single series, as few of the patches are interdependent, thought it would be easy to keep them in same series.
Shall we split this patchset as per the custodian maintainers to pick?
Patchset 1: Add GPIO driver support for Freescale Vybrid platform, enable support for GPIO support on Toradex Colibri VF50, VF61 modules.
Quoted 7 lines
Patchset 2: Add device tree support for Freescale Vybrid Platform, Toradex Colibri VF50, VF61 modules.
Patchset 3: Add DSPI support for Toradex Colibri VF50, VF61 modules.
Patchset 4: Add weak function for board specific USB initialization for Freescale Vybrid platform.
Quoted 7 lines
Generally, if a maintainer acks a patch, the patch could then be applied into another tree if this makes sense and avoid to introduce breakage, maybe in both trees. You patchset is related to u-boot-imx with exception for the USB part, but Marek has already acked it. I will check you patches soon, but I think it is ok if the whole patchset flows into u-boot-imx.
Ping!
Quoted 3 lines
Best regards,
Stefano Babic
Best regards,
Bhuvan
cover Add GPIO driver for Freescale Vybrid platform
Hi,
Quoted 9 lines · Bhuvanchandra DV
Quoted 7 lines
Generally, if a maintainer acks a patch, the patch could then be applied into another tree if this makes sense and avoid to introduce breakage, maybe in both trees. You patchset is related to u-boot-imx with exception for the USB part, but Marek has already acked it. I will check you patches soon, but I think it is ok if the whole patchset flows into u-boot-imx.
Ping!
Ready for merge - patches will flow in today.
Best regards,
Stefano Babic
Signature · 5 lines
===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de =====================================================================
v2 cover Add GPIO driver for Freescale Vybrid platform
In reply to Bhuvanchandra DVChanges since V1:
Fix the broken patches
Bhuvanchandra DV (9):
dm: gpio: uclass: Add flag to control sequence numbering
dm: gpio: vf610: Add GPIO driver support
colibri_vf: Add pinmux entries for GPIOs
colibri_vf: Enable GPIO support
arm: vf610: Add clock support for DSPI
arm: vf610: Add iomux support for DSPI
vf610: dts: Add device tree support
colibri-vf: Enable SPI support
colibri_vf: Add separate defconfig for device tree support
Sanchayan Maity (2):
usb: ehci-vf: Add weak function for board specific initialisation
colibri_vf: Enable board specific USB initialisation for USB pen gpio
arch/arm/cpu/armv7/vf610/generic.c | 7 ++ arch/arm/dts/Makefile | 3 + arch/arm/dts/vf-colibri.dtsi | 21 ++++ arch/arm/dts/vf.dtsi | 100 +++++++++++++++ arch/arm/dts/vf500-colibri.dts | 18 +++ arch/arm/dts/vf610-colibri.dts | 18 +++ arch/arm/imx-common/iomux-v3.c | 26 ++++ arch/arm/include/asm/arch-vf610/clock.h | 1 + arch/arm/include/asm/arch-vf610/crm_regs.h | 4 + arch/arm/include/asm/arch-vf610/gpio.h | 29 +++++ arch/arm/include/asm/arch-vf610/imx-regs.h | 5 + arch/arm/include/asm/arch-vf610/iomux-vf610.h | 59 +++++++++ arch/arm/include/asm/imx-common/iomux-v3.h | 6 + board/toradex/colibri_vf/colibri_vf.c | 106 ++++++++++++++++ configs/colibri_vf_defconfig | 1 + configs/colibri_vf_dtb_defconfig | 8 ++ drivers/gpio/Kconfig | 7 ++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-uclass.c | 1 + drivers/gpio/vybrid_gpio.c | 169 ++++++++++++++++++++++++++ drivers/usb/host/ehci-vf.c | 8 ++ include/configs/colibri_vf.h | 16 +++ 22 files changed, 614 insertions(+) create mode 100644 arch/arm/dts/vf-colibri.dtsi create mode 100644 arch/arm/dts/vf.dtsi create mode 100644 arch/arm/dts/vf500-colibri.dts create mode 100644 arch/arm/dts/vf610-colibri.dts create mode 100644 arch/arm/include/asm/arch-vf610/gpio.h create mode 100644 configs/colibri_vf_dtb_defconfig create mode 100644 drivers/gpio/vybrid_gpio.c
Signature · 1 line
2.1.0
PATCH v2 1/11 dm: gpio: uclass: Add flag to control sequence numbering
Like SPI and I2C few GPIO controllers also have multiple chip instances. This patch adds the flag 'DM_UC_FLAG_SEQ_ALIAS' in gpio_uclass driver to control device sequence numbering. By defalut the dev->r_seq for gpio_uclass will alwalys returns -1, which leads the gpio driver probe failure when using the driver with device trees.
--- drivers/gpio/gpio-uclass.c | 1 + 1 file changed, 1 insertion(+)
drivers/gpio/gpio-uclass.c +1 -0
@@ -757,6 +757,7 @@ static int gpio_pre_remove(struct udevice *dev)UCLASS_DRIVER (gpio) = { .id =UCLASS_GPIO , .name ="gpio" , + .flags =DM_UC_FLAG_SEQ_ALIAS , .post_probe = gpio_post_probe, .pre_remove = gpio_pre_remove, .per_device_auto_alloc_size =sizeof (struct gpio_dev_priv ),
Signature · 1 line
2.1.0
PATCH v2 2/11 dm: gpio: vf610: Add GPIO driver support
In reply to Bhuvanchandra DVAdd GPIO driver support to Freescale VF610
--- arch/arm/imx-common/iomux-v3.c | 26 +++++ arch/arm/include/asm/arch-vf610/gpio.h | 29 +++++ arch/arm/include/asm/arch-vf610/imx-regs.h | 5 + arch/arm/include/asm/imx-common/iomux-v3.h | 6 + drivers/gpio/Kconfig | 7 ++ drivers/gpio/Makefile | 1 + drivers/gpio/vybrid_gpio.c | 169 +++++++++++++++++++++++++++++ 7 files changed, 243 insertions(+) create mode 100644 arch/arm/include/asm/arch-vf610/gpio.h create mode 100644 drivers/gpio/vybrid_gpio.c
arch/arm/imx-common/iomux-v3.c +26 -0
@@ -92,3 +92,29 @@ void imx_iomux_set_gpr_register(int group, int start_bit, reg |= (value << start_bit);writel (reg, base + group *4 ); } + +#ifdef CONFIG_IOMUX_SHARE_CONF_REG +void imx_iomux_gpio_set_direction (unsigned int gpio, +unsigned int direction) +{ +u32 reg; +/* +* Only on Vybrid the input/output buffer enable flags +* are part of the shared mux/conf register. +*/ + reg =readl (base + (gpio <<2 )); + +if (direction) + reg |=0x2 ; +else + reg &= ~0x2 ; + +writel (reg, base + (gpio <<2 )); +} + +void imx_iomux_gpio_get_function (unsigned int gpio,u32 *gpio_state) +{ + *gpio_state =readl (base + (gpio <<2 )) & + ((0X07 <<PAD_MUX_MODE_SHIFT ) |PAD_CTL_OBE_IBE_ENABLE ); +} +#endif
arch/arm/include/asm/arch-vf610/gpio.h new file +29 -0
@@ -0,0 +1,29 @@ +/* +* Copyright (C) 2015 +* Bhuvanchandra DV, Toradex, Inc. +* +* SPDX-License-Identifier: GPL-2.0 +*/ + +#ifndef __ASM_ARCH_VF610_GPIO_H +#define __ASM_ARCH_VF610_GPIO_H + +#define VYBRID_GPIO_COUNT 32 +#define VF610_GPIO_DIRECTION_IN 0x0 +#define VF610_GPIO_DIRECTION_OUT 0x1 + +/* GPIO registers */ +struct vybrid_gpio_regs { +u32 gpio_pdor; +u32 gpio_psor; +u32 gpio_pcor; +u32 gpio_ptor; +u32 gpio_pdir; +}; + +struct vybrid_gpio_platdata { +unsigned int chip; +u32 base; +const char *port_name; +}; +#endif /* __ASM_ARCH_VF610_GPIO_H */
arch/arm/include/asm/arch-vf610/imx-regs.h +5 -0
@@ -81,6 +81,11 @@#define VREG_DIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006D000)#define SRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006E000)#define CMU_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006F000) +#define GPIO0_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF000) +#define GPIO1_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF040) +#define GPIO2_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF080) +#define GPIO3_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF0C0) +#define GPIO4_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF100)/* AIPS 1 */ #define OCOTP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00025000)
arch/arm/include/asm/imx-common/iomux-v3.h +6 -0
@@ -187,6 +187,12 @@ void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,*/ void imx_iomux_set_gpr_register (int group,int start_bit,int num_bits,int value); +#ifdef CONFIG_IOMUX_SHARE_CONF_REG +void imx_iomux_gpio_set_direction (unsigned int gpio, +unsigned int direction); +void imx_iomux_gpio_get_function (unsigned int gpio, +u32 *gpio_state); +#endif /* macros for declaring and using pinmux array */ #if defined(CONFIG_MX6QDL )
drivers/gpio/Kconfig +7 -0
@@ -35,3 +35,10 @@ config SANDBOX_GPIO_COUNT are specified using the device tree. But you can also have a number of 'anonymous' GPIOs that do not belong to any device or bank. Select a suitable value depending on your needs. + +config VYBRID_GPIO + bool "Vybrid GPIO driver" + depends on DM + default n + help + Say yes here to support Vybrid vf610 GPIOs.
drivers/gpio/Makefile +1 -0
@@ -45,3 +45,4 @@ obj-$(CONFIG_SUNXI_GPIO) += sunxi_gpio.o obj-$(CONFIG_LPC32XX_GPIO) += lpc32xx_gpio.o obj-$(CONFIG_STM32_GPIO) += stm32_gpio.o obj-$(CONFIG_ZYNQ_GPIO) += zynq_gpio.o +obj-$(CONFIG_VYBRID_GPIO) += vybrid_gpio.o
drivers/gpio/vybrid_gpio.c new file +169 -0
169 lines not on this page · raw message
Signature · 1 line
2.1.0
PATCH v2 3/11 colibri_vf: Add pinmux entries for GPIOs
In reply to Bhuvanchandra DVInorder to use the pins as GPIO, apart from setting the alt-function, pinmuxing need to be done, this patch adds pinmux entries of few GPIOs.
--- arch/arm/include/asm/arch-vf610/iomux-vf610.h | 49 ++++++++++++++++++++++ board/toradex/colibri_vf/colibri_vf.c | 60 +++++++++++++++++++++++++++ 2 files changed, 109 insertions(+)
arch/arm/include/asm/arch-vf610/iomux-vf610.h +49 -0
@@ -32,22 +32,56 @@#define VF610_QSPI_PAD_CTRL (PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_150ohm | \ PAD_CTL_PUS_22K_UP | PAD_CTL_OBE_IBE_ENABLE) +#define VF610_GPIO_PAD_CTRL (PAD_CTL_SPEED_MED | PAD_CTL_DSE_50ohm | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_IBE_ENABLE) +enum {VF610_PAD_PTA6__RMII0_CLKIN =IOMUX_PAD (0x0000 ,0x0000 ,2 , __NA_,0 ,VF610_ENET_PAD_CTRL ),VF610_PAD_PTA6__RMII0_CLKOUT =IOMUX_PAD (0x0000 ,0x0000 ,1 , __NA_,0 ,VF610_ENET_PAD_CTRL ), +VF610_PAD_PTA7__GPIO_134 =IOMUX_PAD (0x0218 ,0x0218 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ), +VF610_PAD_PTA17__GPIO_7 =IOMUX_PAD (0x001c ,0x001c ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ), +VF610_PAD_PTA20__GPIO_10 =IOMUX_PAD (0x0028 ,0x0028 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ), +VF610_PAD_PTA21__GPIO_11 =IOMUX_PAD (0x002c ,0x002c ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ), +VF610_PAD_PTA30__GPIO_20 =IOMUX_PAD (0x0050 ,0x0050 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ), +VF610_PAD_PTA31__GPIO_21 =IOMUX_PAD (0x0054 ,0x0054 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ), +VF610_PAD_PTB0__GPIO_22 =IOMUX_PAD (0x0058 ,0x0058 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ), +VF610_PAD_PTB1__GPIO_23 =IOMUX_PAD (0x005C ,0x005C ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ),VF610_PAD_PTB4__UART1_TX =IOMUX_PAD (0x0068 ,0x0068 ,2 ,0x0380 ,0 ,VF610_UART_PAD_CTRL ),VF610_PAD_PTB5__UART1_RX =IOMUX_PAD (0x006c ,0x006c ,2 ,0x037c ,0 ,VF610_UART_PAD_CTRL ), +VF610_PAD_PTB6__GPIO_28 =IOMUX_PAD (0x0070 ,0x0070 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ), +VF610_PAD_PTB7__GPIO_29 =IOMUX_PAD (0x0074 ,0x0074 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ), +VF610_PAD_PTB8__GPIO_30 =IOMUX_PAD (0x0078 ,0x0078 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ), +VF610_PAD_PTB9__GPIO_31 =IOMUX_PAD (0x007C ,0x007C ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ),VF610_PAD_PTB10__UART0_TX =IOMUX_PAD (0x0080 ,0x0080 ,1 , __NA_,0 ,VF610_UART_PAD_CTRL ),VF610_PAD_PTB11__UART0_RX =IOMUX_PAD (0x0084 ,0x0084 ,1 , __NA_,0 ,VF610_UART_PAD_CTRL ), +VF610_PAD_PTB12__GPIO_34 =IOMUX_PAD (0x0088 ,0x0088 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ), +VF610_PAD_PTB13__GPIO_35 =IOMUX_PAD (0x008c ,0x008c ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ), +VF610_PAD_PTB16__GPIO_38 =IOMUX_PAD (0x0098 ,0x0098 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ), +VF610_PAD_PTB17__GPIO_39 =IOMUX_PAD (0x009c ,0x009c ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ), +VF610_PAD_PTB18__GPIO_40 =IOMUX_PAD (0x00a0 ,0x00a0 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ), +VF610_PAD_PTB21__GPIO_43 =IOMUX_PAD (0x00ac ,0x00ac ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ), +VF610_PAD_PTB22__GPIO_44 =IOMUX_PAD (0x00b0 ,0x00b0 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ), +VF610_PAD_PTB23__GPIO_93 =IOMUX_PAD (0x0174 ,0x0174 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ), +VF610_PAD_PTB26__GPIO_96 =IOMUX_PAD (0x0180 ,0x0180 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ), +VF610_PAD_PTB28__GPIO_98 =IOMUX_PAD (0x0188 ,0x0188 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ), +VF610_PAD_PTC1__GPIO_46 =IOMUX_PAD (0x00b8 ,0x00b8 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ),VF610_PAD_PTC1__RMII0_MDIO =IOMUX_PAD (0x00b8 ,0x00b8 ,1 , __NA_,0 ,VF610_ENET_PAD_CTRL ), +VF610_PAD_PTC0__GPIO_45 =IOMUX_PAD (0x00b4 ,0x00b4 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ),VF610_PAD_PTC0__RMII0_MDC =IOMUX_PAD (0x00b4 ,0x00b4 ,1 , __NA_,0 ,VF610_ENET_PAD_CTRL ),VF610_PAD_PTC2__RMII0_CRS_DV =IOMUX_PAD (0x00bc ,0x00bc ,1 , __NA_,0 ,VF610_ENET_PAD_CTRL ), +VF610_PAD_PTC2__GPIO_47 =IOMUX_PAD (0x00bc ,0x00bc ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ),VF610_PAD_PTC3__RMII0_RD1 =IOMUX_PAD (0x00c0 ,0x00c0 ,1 , __NA_,0 ,VF610_ENET_PAD_CTRL ), +VF610_PAD_PTC3__GPIO_48 =IOMUX_PAD (0x00c0 ,0x00c0 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ),VF610_PAD_PTC4__RMII0_RD0 =IOMUX_PAD (0x00c4 ,0x00c4 ,1 , __NA_,0 ,VF610_ENET_PAD_CTRL ), +VF610_PAD_PTC4__GPIO_49 =IOMUX_PAD (0x00c4 ,0x00c4 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ),VF610_PAD_PTC5__RMII0_RXER =IOMUX_PAD (0x00c8 ,0x00c8 ,1 , __NA_,0 ,VF610_ENET_PAD_CTRL ), +VF610_PAD_PTC5__GPIO_50 =IOMUX_PAD (0x00c8 ,0x00c8 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ),VF610_PAD_PTC6__RMII0_TD1 =IOMUX_PAD (0x00cc ,0x00cc ,1 , __NA_,0 ,VF610_ENET_PAD_CTRL ), +VF610_PAD_PTC6__GPIO_51 =IOMUX_PAD (0x00cc ,0x00cc ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ),VF610_PAD_PTC7__RMII0_TD0 =IOMUX_PAD (0x00D0 ,0x00D0 ,1 , __NA_,0 ,VF610_ENET_PAD_CTRL ), +VF610_PAD_PTC7__GPIO_52 =IOMUX_PAD (0x00D0 ,0x00D0 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ),VF610_PAD_PTC8__RMII0_TXEN =IOMUX_PAD (0x00D4 ,0x00D4 ,1 , __NA_,0 ,VF610_ENET_PAD_CTRL ), +VF610_PAD_PTC8__GPIO_53 =IOMUX_PAD (0x00D4 ,0x00D4 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ),VF610_PAD_PTC10__RMII1_MDIO =IOMUX_PAD (0x00dc ,0x00dc ,1 , __NA_,0 ,VF610_ENET_PAD_CTRL ),VF610_PAD_PTC9__RMII1_MDC =IOMUX_PAD (0x00d8 ,0x00d8 ,1 , __NA_,0 ,VF610_ENET_PAD_CTRL ),VF610_PAD_PTC11__RMII1_CRS_DV =IOMUX_PAD (0x00e0 ,0x00e0 ,1 , __NA_,0 ,VF610_ENET_PAD_CTRL ),
@@ -57,6 +91,8 @@ enum {VF610_PAD_PTC15__RMII1_TD1 =IOMUX_PAD (0x00f0 ,0x00f0 ,1 , __NA_,0 ,VF610_ENET_PAD_CTRL ),VF610_PAD_PTC16__RMII1_TD0 =IOMUX_PAD (0x00f4 ,0x00f4 ,1 , __NA_,0 ,VF610_ENET_PAD_CTRL ),VF610_PAD_PTC17__RMII1_TXEN =IOMUX_PAD (0x00f8 ,0x00f8 ,1 , __NA_,0 ,VF610_ENET_PAD_CTRL ), +VF610_PAD_PTC29__GPIO_102 =IOMUX_PAD (0x0198 ,0x0198 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ), +VF610_PAD_PTC30__GPIO_103 =IOMUX_PAD (0x019c ,0x019c ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ),VF610_PAD_PTA24__ESDHC1_CLK =IOMUX_PAD (0x0038 ,0x0038 ,5 , __NA_,0 ,VF610_SDHC_PAD_CTRL ),VF610_PAD_PTA25__ESDHC1_CMD =IOMUX_PAD (0x003c ,0x003c ,5 , __NA_,0 ,VF610_SDHC_PAD_CTRL ), VF610_PAD_PTA26__ESDHC1_DAT0 = IOMUX_PAD(0x0040, 0x0040, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
@@ -66,13 +102,21 @@ enum {VF610_PAD_PTB14__I2C0_SCL =IOMUX_PAD (0x0090 ,0x0090 ,2 ,0x033c ,1 ,VF610_I2C_PAD_CTRL ),VF610_PAD_PTB15__I2C0_SDA =IOMUX_PAD (0x0094 ,0x0094 ,2 ,0x0340 ,1 ,VF610_I2C_PAD_CTRL ),VF610_PAD_PTD31__NF_IO15 =IOMUX_PAD (0x00fc ,0x00fc ,2 , __NA_,0 ,VF610_NFC_IO_PAD_CTRL ), +VF610_PAD_PTD31__GPIO_63 =IOMUX_PAD (0x00fc ,0x00fc ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ),VF610_PAD_PTD30__NF_IO14 =IOMUX_PAD (0x0100 ,0x0100 ,2 , __NA_,0 ,VF610_NFC_IO_PAD_CTRL ), +VF610_PAD_PTD30__GPIO_64 =IOMUX_PAD (0x0100 ,0x0100 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ),VF610_PAD_PTD29__NF_IO13 =IOMUX_PAD (0x0104 ,0x0104 ,2 , __NA_,0 ,VF610_NFC_IO_PAD_CTRL ), +VF610_PAD_PTD29__GPIO_65 =IOMUX_PAD (0x0104 ,0x0104 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ),VF610_PAD_PTD28__NF_IO12 =IOMUX_PAD (0x0108 ,0x0108 ,2 , __NA_,0 ,VF610_NFC_IO_PAD_CTRL ), +VF610_PAD_PTD28__GPIO_66 =IOMUX_PAD (0x0108 ,0x0108 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ),VF610_PAD_PTD27__NF_IO11 =IOMUX_PAD (0x010c ,0x010c ,2 , __NA_,0 ,VF610_NFC_IO_PAD_CTRL ), +VF610_PAD_PTD27__GPIO_67 =IOMUX_PAD (0x010c ,0x010c ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ),VF610_PAD_PTD26__NF_IO10 =IOMUX_PAD (0x0110 ,0x0110 ,2 , __NA_,0 ,VF610_NFC_IO_PAD_CTRL ), +VF610_PAD_PTD26__GPIO_68 =IOMUX_PAD (0x0110 ,0x0110 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ),VF610_PAD_PTD25__NF_IO9 =IOMUX_PAD (0x0114 ,0x0114 ,2 , __NA_,0 ,VF610_NFC_IO_PAD_CTRL ), +VF610_PAD_PTD25__GPIO_69 =IOMUX_PAD (0x0114 ,0x0114 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ),VF610_PAD_PTD24__NF_IO8 =IOMUX_PAD (0x0118 ,0x0118 ,2 , __NA_,0 ,VF610_NFC_IO_PAD_CTRL ), +VF610_PAD_PTD24__GPIO_70 =IOMUX_PAD (0x0118 ,0x0118 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ),VF610_PAD_PTD23__NF_IO7 =IOMUX_PAD (0x011c ,0x011c ,2 , __NA_,0 ,VF610_NFC_IO_PAD_CTRL ),VF610_PAD_PTD0__QSPI0_A_QSCK =IOMUX_PAD (0x013c ,0x013c ,1 , __NA_,0 ,VF610_QSPI_PAD_CTRL ), VF610_PAD_PTD1__QSPI0_A_CS0 = IOMUX_PAD(0x0140, 0x0140, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
@@ -83,9 +127,14 @@ enum {VF610_PAD_PTD7__QSPI0_B_QSCK =IOMUX_PAD (0x0158 ,0x0158 ,1 , __NA_,0 ,VF610_QSPI_PAD_CTRL ),VF610_PAD_PTD8__QSPI0_B_CS0 =IOMUX_PAD (0x015c ,0x015c ,1 , __NA_,0 ,VF610_QSPI_PAD_CTRL ),VF610_PAD_PTD9__QSPI0_B_DATA3 =IOMUX_PAD (0x0160 ,0x0160 ,1 , __NA_,0 ,VF610_QSPI_PAD_CTRL ), +VF610_PAD_PTD9__GPIO_88 =IOMUX_PAD (0x0160 ,0x0160 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ),VF610_PAD_PTD10__QSPI0_B_DATA2 =IOMUX_PAD (0x0164 ,0x0164 ,1 , __NA_,0 ,VF610_QSPI_PAD_CTRL ), +VF610_PAD_PTD10__GPIO_89 =IOMUX_PAD (0x0164 ,0x0164 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ),VF610_PAD_PTD11__QSPI0_B_DATA1 =IOMUX_PAD (0x0168 ,0x0168 ,1 , __NA_,0 ,VF610_QSPI_PAD_CTRL ), +VF610_PAD_PTD11__GPIO_90 =IOMUX_PAD (0x0168 ,0x0168 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ),VF610_PAD_PTD12__QSPI0_B_DATA0 =IOMUX_PAD (0x016c ,0x016c ,1 , __NA_,0 ,VF610_QSPI_PAD_CTRL ), +VF610_PAD_PTD12__GPIO_91 =IOMUX_PAD (0x016c ,0x016c ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ), +VF610_PAD_PTD13__GPIO_92 =IOMUX_PAD (0x0170 ,0x0170 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ),VF610_PAD_PTD22__NF_IO6 =IOMUX_PAD (0x0120 ,0x0120 ,2 , __NA_,0 ,VF610_NFC_IO_PAD_CTRL ),VF610_PAD_PTD21__NF_IO5 =IOMUX_PAD (0x0124 ,0x0124 ,2 , __NA_,0 ,VF610_NFC_IO_PAD_CTRL ), VF610_PAD_PTD20__NF_IO4 = IOMUX_PAD(0x0128, 0x0128, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
board/toradex/colibri_vf/colibri_vf.c +60 -0
72 lines not on this page · raw message
Signature · 1 line
2.1.0
PATCH v2 3/11 colibri_vf: Add pinmux entries for GPIOs
Quoted 279 lines · Bhuvanchandra DV
Inorder to use the pins as GPIO, apart from setting the alt-function, pinmuxing need to be done, this patch adds pinmux entries of few GPIOs.
Signed-off-by Bhuvanchandra DV <[email protected]>--- arch/arm/include/asm/arch-vf610/iomux-vf610.h | 49 ++++++++++++++++++++++ board/toradex/colibri_vf/colibri_vf.c | 60 +++++++++++++++++++++++++++ 2 files changed, 109 insertions(+)arch/arm/include/asm/arch-vf610/iomux-vf610.h +14
-0@@ -32,22 +32,56 @@#define VF610_QSPI_PAD_CTRL (PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_150ohm | \ PAD_CTL_PUS_22K_UP | PAD_CTL_OBE_IBE_ENABLE) +#define VF610_GPIO_PAD_CTRL (PAD_CTL_SPEED_MED | PAD_CTL_DSE_50ohm | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_IBE_ENABLE) +enum {VF610_PAD_PTA6__RMII0_CLKIN =IOMUX_PAD (0x0000 ,0x0000 ,2 , __NA_,0 ,VF610_ENET_PAD_CTRL ),VF610_PAD_PTA6__RMII0_CLKOUT =IOMUX_PAD (0x0000 ,0x0000 ,1 , __NA_,0 ,VF610_ENET_PAD_CTRL ), +VF610_PAD_PTA7__GPIO_134 =IOMUX_PAD (0x0218 ,0x0218 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ), +VF610_PAD_PTA17__GPIO_7 =IOMUX_PAD (0x001c ,0x001c ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ), +VF610_PAD_PTA20__GPIO_10 =IOMUX_PAD (0x0028 ,0x0028 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ), +VF610_PAD_PTA21__GPIO_11 =IOMUX_PAD (0x002c ,0x002c ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ), +VF610_PAD_PTA30__GPIO_20 =IOMUX_PAD (0x0050 ,0x0050 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ), +VF610_PAD_PTA31__GPIO_21 =IOMUX_PAD (0x0054 ,0x0054 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ), +VF610_PAD_PTB0__GPIO_22 =IOMUX_PAD (0x0058 ,0x0058 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ), +VF610_PAD_PTB1__GPIO_23 =IOMUX_PAD (0x005C ,0x005C ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ),VF610_PAD_PTB4__UART1_TX =IOMUX_PAD (0x0068 ,0x0068 ,2 ,0x0380 ,0 ,VF610_UART_PAD_CTRL ),VF610_PAD_PTB5__UART1_RX =IOMUX_PAD (0x006c ,0x006c ,2 ,0x037c ,0 ,VF610_UART_PAD_CTRL ), +VF610_PAD_PTB6__GPIO_28 =IOMUX_PAD (0x0070 ,0x0070 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ), +VF610_PAD_PTB7__GPIO_29 =IOMUX_PAD (0x0074 ,0x0074 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ), + VF610_PAD_PTB8__GPIO_30 = IOMUX_PAD(0x0078, 0x0078, 0, __NA_, 0,
VF610_GPIO_PAD_CTRL),arch/arm/include/asm/arch-vf610/iomux-vf610.h +1
-0+ VF610_PAD_PTB9__GPIO_31 = IOMUX_PAD(0x007C, 0x007C, 0, __NA_, 0,
VF610_GPIO_PAD_CTRL),
VF610_PAD_PTB10__UART0_TX= IOMUX_PAD(0x0080,0x0080, 1,__NA_, 0,VF610_UART_PAD_CTRL),
VF610_PAD_PTB11__UART0_RX= IOMUX_PAD(0x0084,0x0084, 1,__NA_, 0,VF610_UART_PAD_CTRL),arch/arm/include/asm/arch-vf610/iomux-vf610.h +1
-0+ VF610_PAD_PTB12__GPIO_34 = IOMUX_PAD(0x0088, 0x0088, 0, __NA_, 0,
VF610_GPIO_PAD_CTRL),arch/arm/include/asm/arch-vf610/iomux-vf610.h +1
-0+ VF610_PAD_PTB13__GPIO_35 = IOMUX_PAD(0x008c, 0x008c, 0, __NA_, 0,
VF610_GPIO_PAD_CTRL),arch/arm/include/asm/arch-vf610/iomux-vf610.h +1
-0+ VF610_PAD_PTB16__GPIO_38 = IOMUX_PAD(0x0098, 0x0098, 0, __NA_, 0,
VF610_GPIO_PAD_CTRL),arch/arm/include/asm/arch-vf610/iomux-vf610.h +1
-0+ VF610_PAD_PTB17__GPIO_39 = IOMUX_PAD(0x009c, 0x009c, 0, __NA_, 0,
VF610_GPIO_PAD_CTRL),arch/arm/include/asm/arch-vf610/iomux-vf610.h +1
-0+ VF610_PAD_PTB18__GPIO_40 = IOMUX_PAD(0x00a0, 0x00a0, 0, __NA_, 0,
VF610_GPIO_PAD_CTRL),arch/arm/include/asm/arch-vf610/iomux-vf610.h +1
-0+ VF610_PAD_PTB21__GPIO_43 = IOMUX_PAD(0x00ac, 0x00ac, 0, __NA_, 0,
VF610_GPIO_PAD_CTRL),arch/arm/include/asm/arch-vf610/iomux-vf610.h +1
-0+ VF610_PAD_PTB22__GPIO_44 = IOMUX_PAD(0x00b0, 0x00b0, 0, __NA_, 0,
VF610_GPIO_PAD_CTRL),arch/arm/include/asm/arch-vf610/iomux-vf610.h +1
-0+ VF610_PAD_PTB23__GPIO_93 = IOMUX_PAD(0x0174, 0x0174, 0, __NA_, 0,
VF610_GPIO_PAD_CTRL),arch/arm/include/asm/arch-vf610/iomux-vf610.h +1
-0+ VF610_PAD_PTB26__GPIO_96 = IOMUX_PAD(0x0180, 0x0180, 0, __NA_, 0,
VF610_GPIO_PAD_CTRL),arch/arm/include/asm/arch-vf610/iomux-vf610.h +1
-0+ VF610_PAD_PTB28__GPIO_98 = IOMUX_PAD(0x0188, 0x0188, 0, __NA_, 0,
VF610_GPIO_PAD_CTRL),arch/arm/include/asm/arch-vf610/iomux-vf610.h +1
-0+ VF610_PAD_PTC1__GPIO_46 = IOMUX_PAD(0x00b8, 0x00b8, 0, __NA_, 0,
VF610_GPIO_PAD_CTRL),
VF610_PAD_PTC1__RMII0_MDIO= IOMUX_PAD(0x00b8,0x00b8, 1,__NA_, 0,VF610_ENET_PAD_CTRL),arch/arm/include/asm/arch-vf610/iomux-vf610.h +1
-0+ VF610_PAD_PTC0__GPIO_45 = IOMUX_PAD(0x00b4, 0x00b4, 0, __NA_, 0,
VF610_GPIO_PAD_CTRL),
VF610_PAD_PTC0__RMII0_MDC= IOMUX_PAD(0x00b4,0x00b4, 1,__NA_, 0,VF610_ENET_PAD_CTRL),
VF610_PAD_PTC2__RMII0_CRS_DV= IOMUX_PAD(0x00bc,0x00bc, 1,__NA_,
0,VF610_ENET_PAD_CTRL),arch/arm/include/asm/arch-vf610/iomux-vf610.h +1
-0+ VF610_PAD_PTC2__GPIO_47 = IOMUX_PAD(0x00bc, 0x00bc, 0, __NA_, 0,
VF610_GPIO_PAD_CTRL),
VF610_PAD_PTC3__RMII0_RD1= IOMUX_PAD(0x00c0,0x00c0, 1,__NA_, 0,VF610_ENET_PAD_CTRL),arch/arm/include/asm/arch-vf610/iomux-vf610.h +1
-0+ VF610_PAD_PTC3__GPIO_48 = IOMUX_PAD(0x00c0, 0x00c0, 0, __NA_, 0,
VF610_GPIO_PAD_CTRL),
VF610_PAD_PTC4__RMII0_RD0= IOMUX_PAD(0x00c4,0x00c4, 1,__NA_, 0,VF610_ENET_PAD_CTRL),arch/arm/include/asm/arch-vf610/iomux-vf610.h +1
-0+ VF610_PAD_PTC4__GPIO_49 = IOMUX_PAD(0x00c4, 0x00c4, 0, __NA_, 0,
VF610_GPIO_PAD_CTRL),
VF610_PAD_PTC5__RMII0_RXER= IOMUX_PAD(0x00c8,0x00c8, 1,__NA_, 0,VF610_ENET_PAD_CTRL),arch/arm/include/asm/arch-vf610/iomux-vf610.h +1
-0+ VF610_PAD_PTC5__GPIO_50 = IOMUX_PAD(0x00c8, 0x00c8, 0, __NA_, 0,
VF610_GPIO_PAD_CTRL),
VF610_PAD_PTC6__RMII0_TD1= IOMUX_PAD(0x00cc,0x00cc, 1,__NA_, 0,VF610_ENET_PAD_CTRL),arch/arm/include/asm/arch-vf610/iomux-vf610.h +1
-0+ VF610_PAD_PTC6__GPIO_51 = IOMUX_PAD(0x00cc, 0x00cc, 0, __NA_, 0,
VF610_GPIO_PAD_CTRL),
VF610_PAD_PTC7__RMII0_TD0= IOMUX_PAD(0x00D0,0x00D0, 1,__NA_, 0,VF610_ENET_PAD_CTRL),arch/arm/include/asm/arch-vf610/iomux-vf610.h +1
-0+ VF610_PAD_PTC7__GPIO_52 = IOMUX_PAD(0x00D0, 0x00D0, 0, __NA_, 0,
VF610_GPIO_PAD_CTRL),
VF610_PAD_PTC8__RMII0_TXEN= IOMUX_PAD(0x00D4,0x00D4, 1,__NA_, 0,VF610_ENET_PAD_CTRL),arch/arm/include/asm/arch-vf610/iomux-vf610.h +1
-0+ VF610_PAD_PTC8__GPIO_53 = IOMUX_PAD(0x00D4, 0x00D4, 0, __NA_, 0,
VF610_GPIO_PAD_CTRL),
VF610_PAD_PTC10__RMII1_MDIO= IOMUX_PAD(0x00dc,0x00dc, 1,__NA_,
0,VF610_ENET_PAD_CTRL),
VF610_PAD_PTC9__RMII1_MDC= IOMUX_PAD(0x00d8,0x00d8, 1,__NA_, 0,VF610_ENET_PAD_CTRL),
VF610_PAD_PTC11__RMII1_CRS_DV= IOMUX_PAD(0x00e0,0x00e0, 1,__NA_,
0,VF610_ENET_PAD_CTRL),arch/arm/include/asm/arch-vf610/iomux-vf610.h +1
-0@@ -57,6 +91,8 @@ enum {VF610_PAD_PTC15__RMII1_TD1 =IOMUX_PAD (0x00f0 ,0x00f0 ,1 , __NA_,0 ,VF610_ENET_PAD_CTRL ),VF610_PAD_PTC16__RMII1_TD0 =IOMUX_PAD (0x00f4 ,0x00f4 ,1 , __NA_,0 ,VF610_ENET_PAD_CTRL ),VF610_PAD_PTC17__RMII1_TXEN =IOMUX_PAD (0x00f8 ,0x00f8 ,1 , __NA_,0 ,VF610_ENET_PAD_CTRL ), + VF610_PAD_PTC29__GPIO_102 = IOMUX_PAD(0x0198, 0x0198, 0, __NA_, 0,
VF610_GPIO_PAD_CTRL),arch/arm/include/asm/arch-vf610/iomux-vf610.h +1
-0+ VF610_PAD_PTC30__GPIO_103 = IOMUX_PAD(0x019c, 0x019c, 0, __NA_, 0,
VF610_GPIO_PAD_CTRL),
VF610_PAD_PTA24__ESDHC1_CLK= IOMUX_PAD(0x0038,0x0038, 5,__NA_,
0,VF610_SDHC_PAD_CTRL),
VF610_PAD_PTA25__ESDHC1_CMD= IOMUX_PAD(0x003c,0x003c, 5,__NA_,
0,VF610_SDHC_PAD_CTRL),
VF610_PAD_PTA26__ESDHC1_DAT0= IOMUX_PAD(0x0040,0x0040, 5,__NA_,
0,VF610_SDHC_PAD_CTRL),arch/arm/include/asm/arch-vf610/iomux-vf610.h +3
-0@@ -66,13 +102,21 @@ enum {VF610_PAD_PTB14__I2C0_SCL =IOMUX_PAD (0x0090 ,0x0090 ,2 ,0x033c ,1 ,VF610_I2C_PAD_CTRL ),VF610_PAD_PTB15__I2C0_SDA =IOMUX_PAD (0x0094 ,0x0094 ,2 ,0x0340 ,1 ,VF610_I2C_PAD_CTRL ),VF610_PAD_PTD31__NF_IO15 =IOMUX_PAD (0x00fc ,0x00fc ,2 , __NA_,0 ,VF610_NFC_IO_PAD_CTRL ), +VF610_PAD_PTD31__GPIO_63 =IOMUX_PAD (0x00fc ,0x00fc ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ),VF610_PAD_PTD30__NF_IO14 =IOMUX_PAD (0x0100 ,0x0100 ,2 , __NA_,0 ,VF610_NFC_IO_PAD_CTRL ), +VF610_PAD_PTD30__GPIO_64 =IOMUX_PAD (0x0100 ,0x0100 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ),VF610_PAD_PTD29__NF_IO13 =IOMUX_PAD (0x0104 ,0x0104 ,2 , __NA_,0 ,VF610_NFC_IO_PAD_CTRL ), +VF610_PAD_PTD29__GPIO_65 =IOMUX_PAD (0x0104 ,0x0104 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ), VF610_PAD_PTD28__NF_IO12 = IOMUX_PAD(0x0108, 0x0108, 2, __NA_, 0,
VF610_NFC_IO_PAD_CTRL),arch/arm/include/asm/arch-vf610/iomux-vf610.h +1
-0+ VF610_PAD_PTD28__GPIO_66 = IOMUX_PAD(0x0108, 0x0108, 0, __NA_, 0,
VF610_GPIO_PAD_CTRL),
VF610_PAD_PTD27__NF_IO11= IOMUX_PAD(0x010c,0x010c, 2,__NA_, 0,VF610_NFC_IO_PAD_CTRL),arch/arm/include/asm/arch-vf610/iomux-vf610.h +1
-0+ VF610_PAD_PTD27__GPIO_67 = IOMUX_PAD(0x010c, 0x010c, 0, __NA_, 0,
VF610_GPIO_PAD_CTRL),
VF610_PAD_PTD26__NF_IO10= IOMUX_PAD(0x0110,0x0110, 2,__NA_, 0,VF610_NFC_IO_PAD_CTRL),arch/arm/include/asm/arch-vf610/iomux-vf610.h +1
-0+ VF610_PAD_PTD26__GPIO_68 = IOMUX_PAD(0x0110, 0x0110, 0, __NA_, 0,
VF610_GPIO_PAD_CTRL),
VF610_PAD_PTD25__NF_IO9= IOMUX_PAD(0x0114,0x0114, 2,__NA_, 0,VF610_NFC_IO_PAD_CTRL),arch/arm/include/asm/arch-vf610/iomux-vf610.h +1
-0+ VF610_PAD_PTD25__GPIO_69 = IOMUX_PAD(0x0114, 0x0114, 0, __NA_, 0,
VF610_GPIO_PAD_CTRL),
VF610_PAD_PTD24__NF_IO8= IOMUX_PAD(0x0118,0x0118, 2,__NA_, 0,VF610_NFC_IO_PAD_CTRL),arch/arm/include/asm/arch-vf610/iomux-vf610.h +1
-0+ VF610_PAD_PTD24__GPIO_70 = IOMUX_PAD(0x0118, 0x0118, 0, __NA_, 0,
VF610_GPIO_PAD_CTRL),
VF610_PAD_PTD23__NF_IO7= IOMUX_PAD(0x011c,0x011c, 2,__NA_, 0,VF610_NFC_IO_PAD_CTRL),
VF610_PAD_PTD0__QSPI0_A_QSCK= IOMUX_PAD(0x013c,0x013c, 1,__NA_,
0,VF610_QSPI_PAD_CTRL),
VF610_PAD_PTD1__QSPI0_A_CS0= IOMUX_PAD(0x0140,0x0140, 1,__NA_,
0,VF610_QSPI_PAD_CTRL),arch/arm/include/asm/arch-vf610/iomux-vf610.h +2
-0@@ -83,9 +127,14 @@ enum {VF610_PAD_PTD7__QSPI0_B_QSCK =IOMUX_PAD (0x0158 ,0x0158 ,1 , __NA_,0 ,VF610_QSPI_PAD_CTRL ),VF610_PAD_PTD8__QSPI0_B_CS0 =IOMUX_PAD (0x015c ,0x015c ,1 , __NA_,0 ,VF610_QSPI_PAD_CTRL ),VF610_PAD_PTD9__QSPI0_B_DATA3 =IOMUX_PAD (0x0160 ,0x0160 ,1 , __NA_,0 ,VF610_QSPI_PAD_CTRL ), +VF610_PAD_PTD9__GPIO_88 =IOMUX_PAD (0x0160 ,0x0160 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ),VF610_PAD_PTD10__QSPI0_B_DATA2 =IOMUX_PAD (0x0164 ,0x0164 ,1 , __NA_,0 ,VF610_QSPI_PAD_CTRL ), + VF610_PAD_PTD10__GPIO_89 = IOMUX_PAD(0x0164, 0x0164, 0, __NA_, 0,
VF610_GPIO_PAD_CTRL),
VF610_PAD_PTD11__QSPI0_B_DATA1= IOMUX_PAD(0x0168,0x0168, 1,__NA_, 0,VF610_QSPI_PAD_CTRL),arch/arm/include/asm/arch-vf610/iomux-vf610.h +1
-0+ VF610_PAD_PTD11__GPIO_90 = IOMUX_PAD(0x0168, 0x0168, 0, __NA_, 0,
VF610_GPIO_PAD_CTRL),
VF610_PAD_PTD12__QSPI0_B_DATA0= IOMUX_PAD(0x016c,0x016c, 1,__NA_, 0,VF610_QSPI_PAD_CTRL),arch/arm/include/asm/arch-vf610/iomux-vf610.h +1
-0+ VF610_PAD_PTD12__GPIO_91 = IOMUX_PAD(0x016c, 0x016c, 0, __NA_, 0,
VF610_GPIO_PAD_CTRL),arch/arm/include/asm/arch-vf610/iomux-vf610.h +1
-0+ VF610_PAD_PTD13__GPIO_92 = IOMUX_PAD(0x0170, 0x0170, 0, __NA_, 0,
VF610_GPIO_PAD_CTRL),
VF610_PAD_PTD22__NF_IO6= IOMUX_PAD(0x0120,0x0120, 2,__NA_, 0,VF610_NFC_IO_PAD_CTRL),
VF610_PAD_PTD21__NF_IO5= IOMUX_PAD(0x0124,0x0124, 2,__NA_, 0,VF610_NFC_IO_PAD_CTRL),
VF610_PAD_PTD20__NF_IO4= IOMUX_PAD(0x0128,0x0128, 2,__NA_, 0,VF610_NFC_IO_PAD_CTRL),board/toradex/colibri_vf/colibri_vf.c +56
-0@@ -146,6 +146,62 @@ static void setup_iomux_nfc(void) }#endif +#ifdef CONFIG_VYBRID_GPIO +static void setup_iomux_gpio (void ) +{ +static const iomux_v3_cfg_t gpio_pads[] = { +VF610_PAD_PTA17__GPIO_7 , +VF610_PAD_PTA20__GPIO_10 , +VF610_PAD_PTA21__GPIO_11 , +VF610_PAD_PTA30__GPIO_20 , +VF610_PAD_PTA31__GPIO_21 , +VF610_PAD_PTB0__GPIO_22 , +VF610_PAD_PTB1__GPIO_23 , +VF610_PAD_PTB6__GPIO_28 , +VF610_PAD_PTB7__GPIO_29 , +VF610_PAD_PTB8__GPIO_30 , +VF610_PAD_PTB9__GPIO_31 , +VF610_PAD_PTB12__GPIO_34 , +VF610_PAD_PTB13__GPIO_35 , +VF610_PAD_PTB16__GPIO_38 , +VF610_PAD_PTB17__GPIO_39 , +VF610_PAD_PTB18__GPIO_40 , +VF610_PAD_PTB21__GPIO_43 , +VF610_PAD_PTB22__GPIO_44 , +VF610_PAD_PTC0__GPIO_45 , +VF610_PAD_PTC1__GPIO_46 , +VF610_PAD_PTC2__GPIO_47 , +VF610_PAD_PTC3__GPIO_48 , +VF610_PAD_PTC4__GPIO_49 , +VF610_PAD_PTC5__GPIO_50 , +VF610_PAD_PTC6__GPIO_51 , +VF610_PAD_PTC7__GPIO_52 , +VF610_PAD_PTC8__GPIO_53 , +VF610_PAD_PTD31__GPIO_63 , +VF610_PAD_PTD30__GPIO_64 , +VF610_PAD_PTD29__GPIO_65 , +VF610_PAD_PTD28__GPIO_66 , +VF610_PAD_PTD27__GPIO_67 , +VF610_PAD_PTD26__GPIO_68 , +VF610_PAD_PTD25__GPIO_69 , +VF610_PAD_PTD24__GPIO_70 , +VF610_PAD_PTD9__GPIO_88 , +VF610_PAD_PTD10__GPIO_89 , +VF610_PAD_PTD11__GPIO_90 , +VF610_PAD_PTD12__GPIO_91 , +VF610_PAD_PTD13__GPIO_92 , +VF610_PAD_PTB23__GPIO_93 , +VF610_PAD_PTB26__GPIO_96 , +VF610_PAD_PTB28__GPIO_98 , +VF610_PAD_PTC29__GPIO_102 , +VF610_PAD_PTC30__GPIO_103 , +VF610_PAD_PTA7__GPIO_134 , + }; + +imx_iomux_v3_setup_multiple_pads (gpio_pads,ARRAY_SIZE (gpio_pads)); +} +#endif +#ifdef CONFIG_FSL_ESDHC struct fsl_esdhc_cfg esdhc_cfg[1 ] = { {ESDHC1_BASE_ADDR},
board/toradex/colibri_vf/colibri_vf.c int board_early_init_f(void) · line 368
Quoted 9 lines
board/toradex/colibri_vf/colibri_vf.c +4
-0@@ -304,6 +360,10 @@ int board_early_init_f(void)setup_iomux_nfc ();#endif +#ifdef CONFIG_VYBRID_GPIO +setup_iomux_gpio (); +#endif +return 0 ; }
--
Stefan
PATCH v2 4/11 colibri_vf: Enable GPIO support
In reply to Bhuvanchandra DV--- configs/colibri_vf_defconfig | 1 + include/configs/colibri_vf.h | 5 +++++ 2 files changed, 6 insertions(+)
configs/colibri_vf_defconfig +1 -0
@@ -3,3 +3,4 @@ CONFIG_TARGET_COLIBRI_VF=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_vf/imximage.cfg,ENV_IS_IN_NAND,IMX_NAND" CONFIG_NAND_VF610_NFC=y CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES=y +CONFIG_DM=y
include/configs/colibri_vf.h +5 -0
@@ -54,6 +54,11 @@#define CONFIG_SYS_MAX_NAND_DEVICE 1#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR +/* GPIO support */ +#define CONFIG_DM_GPIO +#define CONFIG_CMD_GPIO +#define CONFIG_VYBRID_GPIO +/* Dynamic MTD partition support */ #define CONFIG_CMD_MTDPARTS /* Enable 'mtdparts' command line support */ #define CONFIG_MTD_PARTITIONS
Signature · 1 line
2.1.0
PATCH v2 5/11 arm: vf610: Add clock support for DSPI
In reply to Bhuvanchandra DV--- arch/arm/cpu/armv7/vf610/generic.c | 7 +++++++ arch/arm/include/asm/arch-vf610/clock.h | 1 + arch/arm/include/asm/arch-vf610/crm_regs.h | 4 ++++ 3 files changed, 12 insertions(+)
arch/arm/cpu/armv7/vf610/generic.c +7 -0
@@ -198,6 +198,11 @@ static u32 get_i2c_clk(void)return get_ipg_clk (); } +static u32 get_dspi_clk (void ) +{ +return get_ipg_clk (); +} +unsigned int mxc_get_clock (enum mxc_clock clk) {switch (clk) {
@@ -215,6 +220,8 @@ unsigned int mxc_get_clock(enum mxc_clock clk)return get_fec_clk ();case MXC_I2C_CLK :return get_i2c_clk (); +case MXC_DSPI_CLK : +return get_dspi_clk ();default :break ; }
arch/arm/include/asm/arch-vf610/clock.h +1 -0
@@ -17,6 +17,7 @@ enum mxc_clock {MXC_ESDHC_CLK ,MXC_FEC_CLK ,MXC_I2C_CLK , + MXC_DSPI_CLK, };void enable_ocotp_clk (unsigned char enable);
arch/arm/include/asm/arch-vf610/crm_regs.h +4 -0
@@ -189,6 +189,8 @@ struct anadig_reg {#define CCM_REG_CTRL_MASK 0xffffffff#define CCM_CCGR0_UART0_CTRL_MASK (0x3 << 14)#define CCM_CCGR0_UART1_CTRL_MASK (0x3 << 16) +#define CCM_CCGR0_DSPI0_CTRL_MASK (0x3 << 24) +#define CCM_CCGR0_DSPI1_CTRL_MASK (0x3 << 26)#define CCM_CCGR1_USBC0_CTRL_MASK (0x3 << 8)#define CCM_CCGR1_PIT_CTRL_MASK (0x3 << 14)#define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 << 28)
@@ -206,6 +208,8 @@ struct anadig_reg {#define CCM_CCGR4_GPC_CTRL_MASK (0x3 << 24)#define CCM_CCGR4_I2C0_CTRL_MASK (0x3 << 12)#define CCM_CCGR6_OCOTP_CTRL_MASK (0x3 << 10) +#define CCM_CCGR6_DSPI2_CTRL_MASK (0x3 << 24) +#define CCM_CCGR6_DSPI3_CTRL_MASK (0x3 << 26)#define CCM_CCGR6_DDRMC_CTRL_MASK (0x3 << 28)#define CCM_CCGR7_SDHC1_CTRL_MASK (0x3 << 4)#define CCM_CCGR7_USBC1_CTRL_MASK (0x3 << 8)
Signature · 1 line
2.1.0
PATCH v2 6/11 arm: vf610: Add iomux support for DSPI
In reply to Bhuvanchandra DVAdd iomux definitions for DSPI second instance.
--- arch/arm/include/asm/arch-vf610/iomux-vf610.h | 9 +++++++++ board/toradex/colibri_vf/colibri_vf.c | 21 +++++++++++++++++++++ 2 files changed, 30 insertions(+)
arch/arm/include/asm/arch-vf610/iomux-vf610.h +9 -0
@@ -35,6 +35,11 @@#define VF610_GPIO_PAD_CTRL (PAD_CTL_SPEED_MED | PAD_CTL_DSE_50ohm | \ PAD_CTL_PUS_47K_UP | PAD_CTL_IBE_ENABLE) +#define VF610_DSPI_PAD_CTRL (PAD_CTL_OBE_ENABLE | PAD_CTL_DSE_20ohm | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH) +#define VF610_DSPI_SIN_PAD_CTRL (PAD_CTL_IBE_ENABLE | PAD_CTL_DSE_20ohm | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH) +enum {VF610_PAD_PTA6__RMII0_CLKIN =IOMUX_PAD (0x0000 ,0x0000 ,2 , __NA_,0 ,VF610_ENET_PAD_CTRL ),VF610_PAD_PTA6__RMII0_CLKOUT =IOMUX_PAD (0x0000 ,0x0000 ,1 , __NA_,0 ,VF610_ENET_PAD_CTRL ),
@@ -91,6 +96,10 @@ enum {VF610_PAD_PTC15__RMII1_TD1 =IOMUX_PAD (0x00f0 ,0x00f0 ,1 , __NA_,0 ,VF610_ENET_PAD_CTRL ),VF610_PAD_PTC16__RMII1_TD0 =IOMUX_PAD (0x00f4 ,0x00f4 ,1 , __NA_,0 ,VF610_ENET_PAD_CTRL ),VF610_PAD_PTC17__RMII1_TXEN =IOMUX_PAD (0x00f8 ,0x00f8 ,1 , __NA_,0 ,VF610_ENET_PAD_CTRL ), +VF610_PAD_PTD5__DSPI1_CS0 =IOMUX_PAD (0x0150 ,0x0150 ,3 ,0x300 ,1 ,VF610_DSPI_PAD_CTRL ), +VF610_PAD_PTD6__DSPI1_SIN =IOMUX_PAD (0x0154 ,0x0154 ,3 ,0x2fc ,1 ,VF610_DSPI_SIN_PAD_CTRL ), +VF610_PAD_PTD7__DSPI1_SOUT =IOMUX_PAD (0x0158 ,0x0158 ,3 , __NA_,0 ,VF610_DSPI_PAD_CTRL ), +VF610_PAD_PTD8__DSPI1_SCK =IOMUX_PAD (0x015c ,0x015c ,3 ,0x2f8 ,1 ,VF610_DSPI_PAD_CTRL ),VF610_PAD_PTC29__GPIO_102 =IOMUX_PAD (0x0198 ,0x0198 ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ),VF610_PAD_PTC30__GPIO_103 =IOMUX_PAD (0x019c ,0x019c ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ), VF610_PAD_PTA24__ESDHC1_CLK = IOMUX_PAD(0x0038, 0x0038, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
board/toradex/colibri_vf/colibri_vf.c +21 -0
@@ -146,6 +146,20 @@ static void setup_iomux_nfc(void) }#endif +#ifdef CONFIG_FSL_DSPI +static void setup_iomux_dspi (void ) +{ +static const iomux_v3_cfg_t dspi1_pads[] = { +VF610_PAD_PTD5__DSPI1_CS0 , +VF610_PAD_PTD6__DSPI1_SIN , +VF610_PAD_PTD7__DSPI1_SOUT , +VF610_PAD_PTD8__DSPI1_SCK , + }; + +imx_iomux_v3_setup_multiple_pads (dspi1_pads,ARRAY_SIZE (dspi1_pads)); +} +#endif +#ifdef CONFIG_VYBRID_GPIO static void setup_iomux_gpio (void ) {
@@ -252,6 +266,9 @@ static void clock_init(void)clrsetbits_le32 (&ccm->ccgr0,CCM_REG_CTRL_MASK ,CCM_CCGR0_UART0_CTRL_MASK ); +#ifdef CONFIG_FSL_DSPI +setbits_le32 (&ccm->ccgr0,CCM_CCGR0_DSPI1_CTRL_MASK ); +#endif clrsetbits_le32 (&ccm->ccgr1,CCM_REG_CTRL_MASK ,CCM_CCGR1_PIT_CTRL_MASK |CCM_CCGR1_WDOGA5_CTRL_MASK ); clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
@@ -364,6 +381,10 @@ int board_early_init_f(void)setup_iomux_gpio ();#endif +#ifdef CONFIG_FSL_DSPI +setup_iomux_dspi (); +#endif +return 0 ; }
Signature · 1 line
2.1.0
PATCH v2 7/11 vf610: dts: Add device tree support
In reply to Bhuvanchandra DVAdd device tree files for Freescale Vybrid platform and Toradex Colibri VF50, VF61 modules.
Device tree files are taken from upstream Kernel. Removed the stuff which are not used/supported yet in U-Boot.
--- arch/arm/dts/Makefile | 3 ++ arch/arm/dts/vf-colibri.dtsi | 21 +++++++++ arch/arm/dts/vf.dtsi | 100 +++++++++++++++++++++++++++++++++++++++++ arch/arm/dts/vf500-colibri.dts | 18 ++++++++ arch/arm/dts/vf610-colibri.dts | 18 ++++++++ 5 files changed, 160 insertions(+) create mode 100644 arch/arm/dts/vf-colibri.dtsi create mode 100644 arch/arm/dts/vf.dtsi create mode 100644 arch/arm/dts/vf500-colibri.dts create mode 100644 arch/arm/dts/vf610-colibri.dts
arch/arm/dts/Makefile +3 -0
@@ -130,6 +130,9 @@ dtb-$(CONFIG_MACH_SUN9I) += \ sun9i-a80-optimus.dtb \ sun9i-a80-cubieboard4.dtb +dtb-$(CONFIG_VF610) += vf500-colibri.dtb \ + vf610-colibri.dtb + targets += $(dtb-y) DTC_FLAGS += -R 4 -p 0x1000
arch/arm/dts/vf-colibri.dtsi new file +21 -0
@@ -0,0 +1,21 @@ +/* + * Copyright 2014 Toradex AG + * + * SPDX-License-Identifier: GPL-2.0+ or X11 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#include "vf.dtsi" + +&dspi1 { + status = "okay"; + bus-num = <1>; + + spi_cmd: sspi at 0 { + reg = <0>; + spi-max-frequency = <50000000>; + }; +};
arch/arm/dts/vf.dtsi new file +100 -0
100 lines not on this page · raw message
arch/arm/dts/vf500-colibri.dts new file +18 -0
@@ -0,0 +1,18 @@ +/* + * Copyright 2014 Toradex AG + * + * SPDX-License-Identifier: GPL-2.0+ or X11 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +/dts-v1/; +#include "vf-colibri.dtsi" + +/ { + model = "Toradex Colibri VF50"; + compatible = "toradex,vf500-colibri_vf50", "toradex,vf500-colibri_vf50", "fsl,vf500"; +};
arch/arm/dts/vf610-colibri.dts new file +18 -0
@@ -0,0 +1,18 @@ +/* + * Copyright 2014 Toradex AG + * + * SPDX-License-Identifier: GPL-2.0+ or X11 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +/dts-v1/; +#include "vf-colibri.dtsi" + +/ { + model = "Toradex Colibri VF61"; + compatible = "toradex,vf610-colibri_vf61", "toradex,vf610-colibri_vf61", "fsl,vf610"; +};
Signature · 1 line
2.1.0
PATCH v2 8/11 colibri-vf: Enable SPI support
In reply to Bhuvanchandra DV--- include/configs/colibri_vf.h | 11 +++++++++++ 1 file changed, 11 insertions(+)
include/configs/colibri_vf.h +11 -0
@@ -272,4 +272,15 @@#define CONFIG_USB_GADGET_MASS_STORAGE #define CONFIG_CMD_USB_MASS_STORAGE +/* Enable SPI support */ +#define CONFIG_DM_SPI +#define CONFIG_CMD_SPI +#define CONFIG_FSL_DSPI + +#ifndef CONFIG_OF_CONTROL +#undef CONFIG_DM_SPI +#undef CONFIG_CMD_SPI +#undef CONFIG_FSL_DSPI +#endif +#endif /* __CONFIG_H */
Signature · 1 line
2.1.0
PATCH v2 8/11 colibri-vf: Enable SPI support
Quoted 15 lines · Bhuvanchandra DV
Signed-off-by Bhuvanchandra DV <[email protected]>--- include/configs/colibri_vf.h | 11 +++++++++++ 1 file changed, 11 insertions(+)include/configs/colibri_vf.h +2
-0@@ -272,4 +272,15 @@#define CONFIG_USB_GADGET_MASS_STORAGE #define CONFIG_CMD_USB_MASS_STORAGE +/* Enable SPI support */ +#define CONFIG_DM_SPI
include/configs/colibri_vf.h line 286
Quoted 10 lines
include/configs/colibri_vf.h +9
-0+#define CONFIG_CMD_SPI +#define CONFIG_FSL_DSPI + +#ifndef CONFIG_OF_CONTROL +#undef CONFIG_DM_SPI +#undef CONFIG_CMD_SPI +#undef CONFIG_FSL_DSPI +#endif +#endif /* __CONFIG_H */
Hm, any specific reason we need to define them unconditionally first? Couldn't we just inverse the logic and safe the undefs?
#ifdef CONFIG_OF_CONTROL
#define CONFIG_DM_SPI
#define CONFIG_CMD_SPI
#define CONFIG_FSL_DSPI
#endif
--
Stefan
PATCH v2 8/11 colibri-vf: Enable SPI support
Hello Stefan,
Quoted 29 lines · Stefan Agner
Quoted 15 lines · Bhuvanchandra DV
Signed-off-by Bhuvanchandra DV <[email protected]>--- include/configs/colibri_vf.h | 11 +++++++++++ 1 file changed, 11 insertions(+)include/configs/colibri_vf.h +2
-0@@ -272,4 +272,15 @@#define CONFIG_USB_GADGET_MASS_STORAGE #define CONFIG_CMD_USB_MASS_STORAGE +/* Enable SPI support */ +#define CONFIG_DM_SPI include/configs/colibri_vf.h line 286
Quoted 10 lines
include/configs/colibri_vf.h +9
-0+#define CONFIG_CMD_SPI +#define CONFIG_FSL_DSPI + +#ifndef CONFIG_OF_CONTROL +#undef CONFIG_DM_SPI +#undef CONFIG_CMD_SPI +#undef CONFIG_FSL_DSPI +#endif +#endif /* __CONFIG_H */ Hm, any specific reason we need to define them unconditionally first?
Quoted 8 lines
Couldn't we just inverse the logic and safe the undefs?
#ifdef
CONFIG_OF_CONTROL
#defineCONFIG_DM_SPI
#defineCONFIG_CMD_SPI
#defineCONFIG_FSL_DSPI
#endif
Agreed to inverse the logic, as in both the above cases DSPI support is enabled by default when OF_CONTROL was defined. Your suggestion sounds good. Will update it accordingly, thanks!
Quoted 3 lines
--
Stefan
Best regards,
Bhuvan
PATCH v2 9/11 colibri_vf: Add separate defconfig for device tree support
In reply to Bhuvanchandra DVMost of the drivers available for Vybrid are not yet converted to OF model to use device tree model, only few drivers like SPI and GPIO drivers use device trees.
Add separate defconfig for who needs to use device tree model. Later this can be integrated to single defconfig.
--- configs/colibri_vf_dtb_defconfig | 8 ++++++++ 1 file changed, 8 insertions(+) create mode 100644 configs/colibri_vf_dtb_defconfig
configs/colibri_vf_dtb_defconfig new file +8 -0
@@ -0,0 +1,8 @@ +CONFIG_ARM=y +CONFIG_TARGET_COLIBRI_VF=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_vf/imximage.cfg,ENV_IS_IN_NAND,IMX_NAND" +CONFIG_NAND_VF610_NFC=y +CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES=y +CONFIG_DM=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="vf610-colibri"
Signature · 1 line
2.1.0
PATCH v2 9/11 colibri_vf: Add separate defconfig for device tree support
Quoted 18 lines · Bhuvanchandra DV
Most of the drivers available for Vybrid are not yet converted to OF model to use device tree model, only few drivers like SPI and GPIO drivers use device trees.
Add separate defconfig for who needs to use device tree model. Later this can be integrated to single defconfig.Signed-off-by Bhuvanchandra DV <[email protected]>--- configs/colibri_vf_dtb_defconfig | 8 ++++++++ 1 file changed, 8 insertions(+) create mode 100644 configs/colibri_vf_dtb_defconfigconfigs/colibri_vf_dtb_defconfig new file +0
-0
configs/colibri_vf_dtb_defconfig line 8
Quoted 8 lines
configs/colibri_vf_dtb_defconfig new file +8
-0@@ -0,0 +1,8 @@ +CONFIG_ARM=y +CONFIG_TARGET_COLIBRI_VF=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_vf/imximage.cfg,ENV_IS_IN_NAND,IMX_NAND" +CONFIG_NAND_VF610_NFC=y +CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES=y +CONFIG_DM=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="vf610-colibri"
One minor nit: Can you add this new file to the list of files in our boards maintainer file?
board/toradex/colibri_vf/MAINTAINERS
But otherwise:
--
Stefan
PATCH v2 9/11 colibri_vf: Add separate defconfig for device tree support
Quoted 31 lines · Stefan Agner
Quoted 18 lines · Bhuvanchandra DV
Most of the drivers available for Vybrid are not yet converted to OF model to use device tree model, only few drivers like SPI and GPIO drivers use device trees.
Add separate defconfig for who needs to use device tree model. Later this can be integrated to single defconfig.Signed-off-by Bhuvanchandra DV <[email protected]>--- configs/colibri_vf_dtb_defconfig | 8 ++++++++ 1 file changed, 8 insertions(+)create mode 100644 configs/colibri_vf_dtb_defconfig
configs/colibri_vf_dtb_defconfig new file +0
-0configs/colibri_vf_dtb_defconfig line 8
Quoted 8 lines
configs/colibri_vf_dtb_defconfig new file +8
-0@@ -0,0 +1,8 @@ +CONFIG_ARM=y +CONFIG_TARGET_COLIBRI_VF=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_vf/imximage.cfg,ENV_IS_IN_NAND,IMX_NAND" +CONFIG_NAND_VF610_NFC=y +CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES=y +CONFIG_DM=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="vf610-colibri"One minor nit: Can you add this new file to the list of files in our boards maintainer file?
Quoted 1 line
board/toradex/colibri_vf/MAINTAINERS
Sure, will add it.
Quoted 7 lines
But otherwise:
Acked-by Stefan Agner <[email protected]>--
Stefan
Best regards,
Bhuvan
PATCH v2 10/11 usb: ehci-vf: Add weak function for board specific initialisation
In reply to Bhuvanchandra DVFrom: Sanchayan Maity <[email protected]>
Add a weak function board_ehci_hcd_init which can be used by the board file for board specific initialisation.
--- drivers/usb/host/ehci-vf.c | 8 ++++++++ 1 file changed, 8 insertions(+)
drivers/usb/host/ehci-vf.c +8 -0
@@ -121,6 +121,11 @@ static void usb_oc_config(int index)setbits_le32 (ctrl,UCTRL_OVER_CUR_DIS ); } +int __weak board_ehci_hcd_init (int port) +{ +return 0 ; +} +int ehci_hcd_init (int index,enum usb_init_type init,struct ehci_hccr **hccr,struct ehci_hcor **hcor) {
@@ -136,6 +141,9 @@ int ehci_hcd_init(int index, enum usb_init_type init, ehci = (struct usb_ehci *)nc_reg_bases[index]; +/* Do board specific initialisation */ +board_ehci_hcd_init (index); +usb_power_config (index);usb_oc_config (index);usb_internal_phy_clock_gate (index);
Signature · 1 line
2.1.0
PATCH v2 11/11 colibri_vf: Enable board specific USB initialisation for USB pen gpio
In reply to Bhuvanchandra DVFrom: Sanchayan Maity <[email protected]>
Add IOMUX for the pad used as USB pen. This needs to be driven low for the Iris and Viola boards where it is pulled up high by default. This is required for the USB host functionality to work on these boards. Use the board specific weak initialisation function, to drive the pin low which would be called on "usb start".
--- arch/arm/include/asm/arch-vf610/iomux-vf610.h | 1 + board/toradex/colibri_vf/colibri_vf.c | 25 +++++++++++++++++++++++++ 2 files changed, 26 insertions(+)
arch/arm/include/asm/arch-vf610/iomux-vf610.h +1 -0
@@ -131,6 +131,7 @@ enum {VF610_PAD_PTD1__QSPI0_A_CS0 =IOMUX_PAD (0x0140 ,0x0140 ,1 , __NA_,0 ,VF610_QSPI_PAD_CTRL ),VF610_PAD_PTD2__QSPI0_A_DATA3 =IOMUX_PAD (0x0144 ,0x0144 ,1 , __NA_,0 ,VF610_QSPI_PAD_CTRL ),VF610_PAD_PTD3__QSPI0_A_DATA2 =IOMUX_PAD (0x0148 ,0x0148 ,1 , __NA_,0 ,VF610_QSPI_PAD_CTRL ), +VF610_PAD_PTD4__GPIO_83 =IOMUX_PAD (0x014C ,0x014C ,0 , __NA_,0 ,VF610_GPIO_PAD_CTRL ),VF610_PAD_PTD4__QSPI0_A_DATA1 =IOMUX_PAD (0x014c ,0x014c ,1 , __NA_,0 ,VF610_QSPI_PAD_CTRL ),VF610_PAD_PTD5__QSPI0_A_DATA0 =IOMUX_PAD (0x0150 ,0x0150 ,1 , __NA_,0 ,VF610_QSPI_PAD_CTRL ), VF610_PAD_PTD7__QSPI0_B_QSCK = IOMUX_PAD(0x0158, 0x0158, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
board/toradex/colibri_vf/colibri_vf.c +25 -0
@@ -20,6 +20,7 @@#include <netdev.h> #include <i2c.h> #include <g_dnl.h> +#include <asm/gpio.h> DECLARE_GLOBAL_DATA_PTR ;
@@ -32,6 +33,12 @@ DECLARE_GLOBAL_DATA_PTR;#define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \ PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE) +#define USB_PEN_GPIO 83 + +static const iomux_v3_cfg_t usb_pads[] = { +VF610_PAD_PTD4__GPIO_83 , +}; +int dram_init (void ) {static const struct ddr3_jedec_timings timings = {
@@ -464,3 +471,21 @@ int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)return 0 ; } + +#ifdef CONFIG_USB_EHCI_VF +int board_ehci_hcd_init (int port) +{ +imx_iomux_v3_setup_multiple_pads (usb_pads,ARRAY_SIZE (usb_pads)); + +switch (port) { +case 0 : +/* USBC does not have PEN, also configured as USB client only */ +break ; +case 1 : +gpio_request (USB_PEN_GPIO ,"usb-pen-gpio" ); +gpio_direction_output (USB_PEN_GPIO ,0 ); +break ; + } +return 0 ; +} +#endif
Signature · 1 line
2.1.0
PATCH v2 11/11 colibri_vf: Enable board specific USB initialisation for USB pen gpio
Quoted 73 lines · Bhuvanchandra DV
From: Sanchayan Maity <[email protected]>
Add IOMUX for the pad used as USB pen. This needs to be driven low for the Iris and Viola boards where it is pulled up high by default. This is required for the USB host functionality to work on these boards. Use the board specific weak initialisation function, to drive the pin low which would be called on "usb start".
Signed-off-by Sanchayan Maity <[email protected]>--- arch/arm/include/asm/arch-vf610/iomux-vf610.h | 1 + board/toradex/colibri_vf/colibri_vf.c | 25 +++++++++++++++++++++++++ 2 files changed, 26 insertions(+)arch/arm/include/asm/arch-vf610/iomux-vf610.h +1
-0@@ -131,6 +131,7 @@ enum {VF610_PAD_PTD1__QSPI0_A_CS0 =IOMUX_PAD (0x0140 ,0x0140 ,1 , __NA_,0 ,VF610_QSPI_PAD_CTRL ),VF610_PAD_PTD2__QSPI0_A_DATA3 =IOMUX_PAD (0x0144 ,0x0144 ,1 , __NA_,0 ,VF610_QSPI_PAD_CTRL ),VF610_PAD_PTD3__QSPI0_A_DATA2 =IOMUX_PAD (0x0148 ,0x0148 ,1 , __NA_,0 ,VF610_QSPI_PAD_CTRL ), + VF610_PAD_PTD4__GPIO_83 = IOMUX_PAD(0x014C, 0x014C, 0,
__NA_, 0,VF610_GPIO_PAD_CTRL),
VF610_PAD_PTD4__QSPI0_A_DATA1= IOMUX_PAD(0x014c,0x014c, 1,__NA_,
0,VF610_QSPI_PAD_CTRL),
VF610_PAD_PTD5__QSPI0_A_DATA0= IOMUX_PAD(0x0150,0x0150, 1,__NA_,
0,VF610_QSPI_PAD_CTRL),
VF610_PAD_PTD7__QSPI0_B_QSCK= IOMUX_PAD(0x0158,0x0158, 1,__NA_,
0,VF610_QSPI_PAD_CTRL),board/toradex/colibri_vf/colibri_vf.c +15
-0@@ -20,6 +20,7 @@#include <netdev.h> #include <i2c.h> #include <g_dnl.h> +#include <asm/gpio.h> DECLARE_GLOBAL_DATA_PTR ;@@ -32,6 +33,12 @@ DECLARE_GLOBAL_DATA_PTR;#define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \ PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE) +#define USB_PEN_GPIO 83 + +static const iomux_v3_cfg_t usb_pads[] = { +VF610_PAD_PTD4__GPIO_83 , +}; +int dram_init (void ) {static const struct ddr3_jedec_timings timings = {@@ -464,3 +471,21 @@ int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)return 0 ; } + +#ifdef CONFIG_USB_EHCI_VF +int board_ehci_hcd_init (int port) +{ +imx_iomux_v3_setup_multiple_pads (usb_pads,ARRAY_SIZE (usb_pads)); + +switch (port) { +case 0 :
board/toradex/colibri_vf/colibri_vf.c int g_dnl_bind_fixup(struct usb_device_descriptor · line 491
Quoted 10 lines
board/toradex/colibri_vf/colibri_vf.c +10
-0+/* USBC does not have PEN, also configured as USB client only */ +break ; +case 1 : +gpio_request (USB_PEN_GPIO ,"usb-pen-gpio" ); +gpio_direction_output (USB_PEN_GPIO ,0 ); + break; + } +return 0 ; +} +#endif
--
Stefan