Add Freescale i.mx7d support
Subsystems (5)
v10 cover Add Freescale i.mx7d support
From: Frank Li <[email protected]>
Add basic support for chip imx7d.
- MSL
- Clock support. All clock enabled.
- pinctrl support
- SD Card support
Change from v9 to 10
- Change IMX_PLLV3_ENET_MX7 to IMX_PLLV3_ENET_IMX7
- Change to IMX7_ENET_PLL_POWER
- sort makefile alphabetically
- change to Hz.
- Remove clks_init_on
- Change comment to 80 column
Change from v8 to v9
- seperate clk-pllv3.c change to new patch
- clk-imx7: Change to IMX7D_CLK_END
- clk-imx7: remove BM_PLL_ENABLE and BM_PLL_BYPASS
- clk-pllv3: remove IMX_PLLV3_SYSV2
- clk-imx7: Remove imx_clk_gate_flags
- dts:remove clock-frequency = <100000>
- dts: add reg=<3>;
- remove _1 of pinctrl_hog_1
- move iomux to bottom
- Add imx7d description in imx7d.dtsi
Change from v7 to v8
- exclude patchs already accepted.
- Remove SOC_IMX7
- Remove static map
- Remove #include <linux/phy.h>
- Remove .restart = mxc_restart,
- Remove mx7d.h
- consistent indetation in imx7d.dtsi
- Change document remove "ipp_di0" and "ipp_di1"
- Remove GPC because needn't it now, will added back at SMP enable patch
- Remove imx21-uart compatible string
- use i.mx6sx timer compatible string, so remove time.c change
- correct typo imx6sx
- dt file add cpu1
Change from v6 to v7
- Move clk to driver/clk/imx
- Remove iomux-lpsr part
- Remove parents clocks node in imx7d.dtsi
Change from v5 to v6
- dual license for dts
- fix typo statue
- Remove smp_operations
- Remove GPT check cpu_is_mx7() by use old compatible mode
- Remove dts arch_timer part, which not used in this patch series
- correct GIC reg map
Change from v4 to v5
- Remove imx7d_map_io()
- Remove clk_register_clkdev(clks[IMX7D_GPT1_ROOT_CLK], "ipg", "imx-gpt.0");
- Remove clk_register_clkdev(clks[IMX7D_GPT_3M_CLK], "gpt_3m", "imx-gpt.0");
- Add comment about enable all clock
- Add Type IMX_PLLV3_ENET_IMX7 and remove cpu_is_imx7d()
Change from v3 to v4
- Fixed the problem review by Russel king
Remove __mxc_arch_type
Remove MXC_ARCH_CA7
use new smp_operation for ca7 platform
- imx7d.dtsi remove unecessary part for bring up
- imx7d-sdb.dsi, just enable uart i2c and sd card
- Add device tree binding document for timer, clock and pinctrl
Change from v2 to v3
- remove unsupport part in imx7d-sdb.dtb
Change from V1 to V2:
- split patch1 to three small one to avoid 100k maillist limitation.
- fix imx7d.dtsi code style problem
Frank Li (4):
ARM: clk: imx: update pllv3 to support imx7
ARM: imx: add imx7d clk tree support
ARM: dts: add imx7d soc dtsi file
ARM: dts: add imx7d-sdb support
arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/imx7d-sdb.dts | 408 +++++++++++++++ arch/arm/boot/dts/imx7d.dtsi | 486 ++++++++++++++++++ drivers/clk/imx/Makefile | 1 + drivers/clk/imx/clk-imx7d.c | 860 ++++++++++++++++++++++++++++++++ drivers/clk/imx/clk-pllv3.c | 9 +- drivers/clk/imx/clk.h | 1 + include/dt-bindings/clock/imx7d-clock.h | 450 +++++++++++++++++ 8 files changed, 2216 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/imx7d-sdb.dts create mode 100644 arch/arm/boot/dts/imx7d.dtsi create mode 100644 drivers/clk/imx/clk-imx7d.c create mode 100644 include/dt-bindings/clock/imx7d-clock.h
Signature · 1 line
1.9.1
PATCH v10 1/4 ARM: clk: imx: update pllv3 to support imx7
From: Frank Li <[email protected]>
Add type IMX_PLLV3_ENET_IMX7
Signed-off-by Frank Li <[email protected]>
--- drivers/clk/imx/clk-pllv3.c | 9 ++++++++- drivers/clk/imx/clk.h | 1 + 2 files changed, 9 insertions(+), 1 deletion(-)
drivers/clk/imx/clk-pllv3.c +8 -1
@@ -24,12 +24,14 @@#define BM_PLL_POWER (0x1 << 12)#define BM_PLL_LOCK (0x1 << 31) +#define IMX7_ENET_PLL_POWER (0x1 << 5)/** * struct clk_pllv3 - IMX PLL clock version 3 * @clk_hw: clock source * @base: base address of PLL registers * @powerup_set: set POWER bit to power up the PLL +* @powerdown: pll powerdown offset bit * @div_mask: mask of divider bits * @div_shift: shift of divider bits *
@@ -40,6 +42,7 @@ struct clk_pllv3 {struct clk_hw hw;void __iomem *base;bool powerup_set; +u32 powerdown;u32 div_mask;u32 div_shift; };
@@ -49,7 +52,7 @@ struct clk_pllv3 {static int clk_pllv3_wait_lock (struct clk_pllv3 *pll) {unsigned long timeout = jiffies +msecs_to_jiffies (10 ); -u32 val =readl_relaxed (pll->base) &BM_PLL_POWER ; +u32 val =readl_relaxed (pll->base) & pll->powerdown;/* No need to wait for lock when pll is not powered up */ if ((pll->powerup_set && !val) || (!pll->powerup_set && val))
@@ -293,6 +296,8 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,if (!pll)return ERR_PTR (-ENOMEM ); + pll->powerdown =BM_PLL_POWER ; +switch (type) {case IMX_PLLV3_SYS : ops = &clk_pllv3_sys_ops;
@@ -306,6 +311,8 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,case IMX_PLLV3_AV : ops = &clk_pllv3_av_ops;break ; +case IMX_PLLV3_ENET_IMX7 : + pll->powerdown =IMX7_ENET_PLL_POWER ;case IMX_PLLV3_ENET : ops = &clk_pllv3_enet_ops;break ;
drivers/clk/imx/clk.h +1 -0
@@ -39,6 +39,7 @@ enum imx_pllv3_type {IMX_PLLV3_USB_VF610 ,IMX_PLLV3_AV ,IMX_PLLV3_ENET , + IMX_PLLV3_ENET_IMX7, }; struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
Signature · 1 line
1.9.1
PATCH v10 2/4 ARM: imx: add imx7d clk tree support
In reply to Frank.Li at freescale.comFrom: Frank Li <[email protected]>
Add i.MX7D clk tree support.
Enable all clock to bring up imx7.
Clock framework need be modified a little since imx7d change clock design. otherwise system will halt and block the other part upstream.
All clock refine need wait for Dong Aisheng's patch
clk: support clocks which requires parent clock on during operation Or other solution ready.
Signed-off-by Anson Huang <[email protected]>
Signed-off-by Adrian Alonso <[email protected]>
Signed-off-by Frank Li <[email protected]>
--- drivers/clk/imx/Makefile | 1 + drivers/clk/imx/clk-imx7d.c | 860 ++++++++++++++++++++++++++++++++ include/dt-bindings/clock/imx7d-clock.h | 450 +++++++++++++++++ 3 files changed, 1311 insertions(+) create mode 100644 drivers/clk/imx/clk-imx7d.c create mode 100644 include/dt-bindings/clock/imx7d-clock.h
drivers/clk/imx/Makefile +1 -0
@@ -22,4 +22,5 @@ obj-$(CONFIG_SOC_IMX5) += clk-imx51-imx53.o obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o obj-$(CONFIG_SOC_IMX6SX) += clk-imx6sx.o +obj-$(CONFIG_SOC_IMX7D) += clk-imx7d.o obj-$(CONFIG_SOC_VF610) += clk-vf610.o
drivers/clk/imx/clk-imx7d.c new file +860 -0
860 lines not on this page · raw message
include/dt-bindings/clock/imx7d-clock.h new file +450 -0
450 lines not on this page · raw message
Signature · 1 line
1.9.1
PATCH v10 3/4 ARM: dts: add imx7d soc dtsi file
In reply to Frank.Li at freescale.comFrom: Frank Li <[email protected]>
imx7d intergrates the unique display controller for EPD panel, pixel engines and graphics engines to make it a ideal solution for EPD based devices such as eReader, Signage, as well as any application rely on the bistable charactersic of the EPD panel.
imx7d include two ARM Cortex A7 Core and one Cortex-M4 core. Included Main Peripheral
- DDR3\LP-DDR2
- GPMI\BCH\APBH DMA(NAND flash support)
- QSPI
- WEIM Nor
- LCDIF\MIPI DSI
- CSI\MIPI CSI
- EPDC
- PCIe RC\EP
- USB OTG\Host
- CAN x2
- I2C x4
- SIMv2 x2
- ENET -x2
- uSDHC x3
- eCSPI x1
- PWM x4
- OCOTP (fuse)
- GPT x4
- WDOG x4
- Flex Timer x2
Signed-off-by Anson Huang <[email protected]>
Signed-off-by Frank Li <[email protected]>
--- arch/arm/boot/dts/imx7d.dtsi | 486 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 486 insertions(+) create mode 100644 arch/arm/boot/dts/imx7d.dtsi
arch/arm/boot/dts/imx7d.dtsi new file +486 -0
@@ -0,0 +1,486 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include <dt-bindings/clock/imx7d-clock.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include "imx7d-pinfunc.h" +#include "skeleton.dtsi" + +/ { + aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + gpio5 = &gpio6; + gpio6 = &gpio7; + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + i2c3 = &i2c4; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + serial5 = &uart6; + serial6 = &uart7; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu at 0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + operating-points = < + /* KHz uV */ + 996000 1075000 + 792000 975000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clks IMX7D_ARM_A7_ROOT_CLK>, <&clks IMX7D_ARM_A7_ROOT_SRC>, + <&clks IMX7D_PLL_ARM_MAIN_CLK>, <&clks IMX7D_PLL_SYS_MAIN_CLK>; + clock-names = "arm", "arm_root_src", "pll_arm", "pll_sys_main"; + }; + + cpu1: cpu at 1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <1>; + }; + }; + + intc: interrupt-controller at 31001000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x31001000 0x1000>, + <0x31002000 0x1000>, + <0x31004000 0x2000>, + <0x31006000 0x2000>; + }; + + ckil: clock-cki { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "ckil"; + }; + + osc: clock-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc"; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&intc>; + ranges; + + aips1: aips-bus at 30000000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x30000000 0x400000>; + ranges; + + gpio1: gpio at 30200000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30200000 0x10000>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */ + <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */ + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio at 30210000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30210000 0x10000>; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio at 30220000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30220000 0x10000>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio at 30230000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30230000 0x10000>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio5: gpio at 30240000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30240000 0x10000>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio6: gpio at 30250000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30250000 0x10000>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio7: gpio at 30260000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30260000 0x10000>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpt1: gpt at 302d0000 { + compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; + reg = <0x302d0000 0x10000>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_GPT1_ROOT_CLK>; + clock-names = "ipg", "per"; + }; + + gpt2: gpt at 302e0000 { + compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; + reg = <0x302e0000 0x10000>; + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_GPT2_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + gpt3: gpt at 302f0000 { + compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; + reg = <0x302f0000 0x10000>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_GPT3_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + gpt4: gpt at 30300000 { + compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; + reg = <0x30300000 0x10000>; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_GPT4_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + iomuxc: iomuxc at 30330000 { + compatible = "fsl,imx7d-iomuxc"; + reg = <0x30330000 0x10000>; + }; + + gpr: iomuxc-gpr at 30340000 { + compatible = "fsl,imx7d-iomuxc-gpr", "syscon"; + reg = <0x30340000 0x10000>; + }; + + ocotp: ocotp-ctrl at 30350000 { + compatible = "syscon"; + reg = <0x30350000 0x10000>; + clocks = <&clks IMX7D_CLK_DUMMY>; + status = "disabled"; + }; + + anatop: anatop at 30360000 { + compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop", + "syscon", "simple-bus"; + reg = <0x30360000 0x10000>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + + reg_1p0d: regulator-vdd1p0d at 210 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vdd1p0d"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1200000>; + anatop-reg-offset = <0x210>; + anatop-vol-bit-shift = <8>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <8>; + anatop-min-voltage = <800000>; + anatop-max-voltage = <1200000>; + anatop-enable-bit = <31>; + }; + }; + + snvs: snvs at 30370000 { + compatible = "fsl,sec-v4.0-mon", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x30370000 0x10000>; + + snvs-rtc-lp at 34 { + compatible = "fsl,sec-v4.0-mon-rtc-lp"; + reg = <0x34 0x58>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + clks: ccm at 30380000 { + compatible = "fsl,imx7d-ccm"; + reg = <0x30380000 0x10000>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + #clock-cells = <1>; + clocks = <&ckil>, <&osc>; + clock-names = "ckil", "osc"; + }; + + src: src at 30390000 { + compatible = "fsl,imx7d-src", "fsl,imx51-src", "syscon"; + reg = <0x30390000 0x10000>; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + #reset-cells = <1>; + }; + }; + + aips3: aips-bus at 30800000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x30800000 0x400000>; + ranges; + + uart1: serial at 30860000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30860000 0x10000>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_UART1_ROOT_CLK>, + <&clks IMX7D_UART1_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart2: serial at 30870000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30870000 0x10000>; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_UART2_ROOT_CLK>, + <&clks IMX7D_UART2_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart3: serial at 30880000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30880000 0x10000>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_UART3_ROOT_CLK>, + <&clks IMX7D_UART3_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + i2c1: i2c at 30a20000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; + reg = <0x30a20000 0x10000>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_I2C1_ROOT_CLK>; + status = "disabled"; + }; + + i2c2: i2c at 30a30000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; + reg = <0x30a30000 0x10000>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_I2C2_ROOT_CLK>; + status = "disabled"; + }; + + i2c3: i2c at 30a40000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; + reg = <0x30a40000 0x10000>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_I2C3_ROOT_CLK>; + status = "disabled"; + }; + + i2c4: i2c at 30a50000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; + reg = <0x30a50000 0x10000>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_I2C4_ROOT_CLK>; + status = "disabled"; + }; + + uart4: serial at 30a60000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30a60000 0x10000>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_UART4_ROOT_CLK>, + <&clks IMX7D_UART4_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart5: serial at 30a70000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30a70000 0x10000>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_UART5_ROOT_CLK>, + <&clks IMX7D_UART5_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart6: serial at 30a80000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30a80000 0x10000>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_UART6_ROOT_CLK>, + <&clks IMX7D_UART6_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart7: serial at 30a90000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30a90000 0x10000>; + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_UART7_ROOT_CLK>, + <&clks IMX7D_UART7_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + usdhc1: usdhc at 30b40000 { + compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; + reg = <0x30b40000 0x10000>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_USDHC1_ROOT_CLK>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + usdhc2: usdhc at 30b50000 { + compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; + reg = <0x30b50000 0x10000>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_USDHC2_ROOT_CLK>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + usdhc3: usdhc at 30b60000 { + compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; + reg = <0x30b60000 0x10000>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_USDHC3_ROOT_CLK>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + }; + }; +};
Signature · 1 line
1.9.1
PATCH v10 4/4 ARM: dts: add imx7d-sdb support
In reply to Frank.Li at freescale.comFrom: Frank Li <[email protected]>
add imx7d sdb board support
Signed-off-by Frank Li <[email protected]>
--- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/imx7d-sdb.dts | 408 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 410 insertions(+) create mode 100644 arch/arm/boot/dts/imx7d-sdb.dts
arch/arm/boot/dts/Makefile +2 -0
@@ -313,6 +313,8 @@ dtb-$(CONFIG_SOC_IMX6SX) += \ imx6sx-sabreauto.dtb \ imx6sx-sdb-reva.dtb \ imx6sx-sdb.dtb +dtb-$(CONFIG_SOC_IMX7D) += \ + imx7d-sdb.dtb dtb-$(CONFIG_SOC_LS1021A) += \ ls1021a-qds.dtb \ ls1021a-twr.dtb
arch/arm/boot/dts/imx7d-sdb.dts new file +408 -0
408 lines not on this page · raw message
Signature · 1 line
1.9.1
Shawn Guo
Appliedv10 cover Add Freescale i.mx7d support
In reply to Frank.Li at freescale.comQuoted 5 lines · Frank.Li at freescale.com
Frank Li (4):
ARM: clk: imx: update pllv3 to support imx7
ARM: imx: add imx7d clk tree support
ARM: dts: add imx7d soc dtsi file
ARM: dts: add imx7d-sdb support
Applied all, thanks.