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imx: dma: correct MXS_DMA_ALIGNMENT

PATCH New Peng Fan 4 participants 6 messages May 20, 2015 – May 26, 2015

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Arm (32-bit) Arm i.MX and Layerscape
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Peng Fan

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#0 lore raw

PATCH 1/1 imx: dma: correct MXS_DMA_ALIGNMENT

We should not hardcode MXS_DMA_ALIGNMENT to 32, since we can not guarantee that socs' cache line size is 32 bytes.
If on chips whose cache line size is 64 bytes, error occurs:
"

NAND:  ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0
ERROR: v7_dcache_inval_range - stop address is not aligned - 0xbdf1f4a0
ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0

"
Align MXS_DMA_ALIGNMENT with ARCH_DMA_MINALIGN whose value is same to CONFIG_SYS_CACHELINE_SIZE if CONFIG_SYS_CACHELINE_SIZE defined.

Signed-off-by Peng Fan <[email protected]>
---
 arch/arm/include/asm/imx-common/dma.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm/include/asm/imx-common/dma.h +1 -1
index d5c1f7f..7d421b3 100644
@@ -22,7 +22,7 @@
 #define	DMA_PIO_WORDS		CONFIG_ARCH_DMA_PIO_WORDS
 #endif
 
-#define MXS_DMA_ALIGNMENT	32
+#define MXS_DMA_ALIGNMENT	ARCH_DMA_MINALIGN
 
 /*
  * MXS DMA channels
Signature · 1 line
1.8.4
#1 lore raw

PATCH 1/1 imx: dma: correct MXS_DMA_ALIGNMENT

Quoted 3 lines · Peng Fan

We should not hardcode MXS_DMA_ALIGNMENT to 32, since we can not guarantee that socs' cache line size is 32 bytes.
If on chips whose cache line size is 64 bytes, error occurs:

Which chips are those?

Quoted 8 lines

NAND: ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0 ERROR: v7_dcache_inval_range - stop address is not aligned - 0xbdf1f4a0 ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0 "
Align MXS_DMA_ALIGNMENT with ARCH_DMA_MINALIGN whose value is same to CONFIG_SYS_CACHELINE_SIZE if CONFIG_SYS_CACHELINE_SIZE defined.

Signed-off-by Peng Fan <[email protected]>
Acked-by Marek Vasut <[email protected]>

Best regards,
Marek Vasut

#2 lore raw

PATCH 1/1 imx: dma: correct MXS_DMA_ALIGNMENT

Hi Marek,

Quoted 6 lines · Marek Vasut
Quoted 3 lines · Peng Fan

We should not hardcode MXS_DMA_ALIGNMENT to 32, since we can not guarantee that socs' cache line size is 32 bytes.
If on chips whose cache line size is 64 bytes, error occurs:

Which chips are those?

i.MX7's L1 Cache line size is 64 bytes.

Quoted 8 lines
Quoted 8 lines

NAND: ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0 ERROR: v7_dcache_inval_range - stop address is not aligned - 0xbdf1f4a0 ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0 "
Align MXS_DMA_ALIGNMENT with ARCH_DMA_MINALIGN whose value is same to CONFIG_SYS_CACHELINE_SIZE if CONFIG_SYS_CACHELINE_SIZE defined.

Quoted 6 lines
Quoted 1 line
Signed-off-by Peng Fan <[email protected]>
Acked-by Marek Vasut <[email protected]>

Best regards,
Marek Vasut

Regards,
Peng.

#3 lore raw

PATCH 1/1 imx: dma: correct MXS_DMA_ALIGNMENT

Quoted 1 line · Peng Fan

Hi Marek,

Hi!

Quoted 9 lines · Marek Vasut
Quoted 6 lines · Peng Fan
Quoted 4 lines

We should not hardcode MXS_DMA_ALIGNMENT to 32, since we can not guarantee that socs' cache line size is 32 bytes.

If on chips whose cache line size is 64 bytes, error occurs:

Which chips are those?

i.MX7's L1 Cache line size is 64 bytes.

Oh, I didn't know this was a public info. Oki, thanks for clarifying :)

Quoted 9 lines
Quoted 9 lines
Quoted 8 lines

NAND: ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0 ERROR: v7_dcache_inval_range - stop address is not aligned - 0xbdf1f4a0 ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0 "
Align MXS_DMA_ALIGNMENT with ARCH_DMA_MINALIGN whose value is same to CONFIG_SYS_CACHELINE_SIZE if CONFIG_SYS_CACHELINE_SIZE defined.

Signed-off-by Peng Fan <[email protected]>
Quoted 7 lines
Quoted 4 lines
Acked-by Marek Vasut <[email protected]>

Best regards,
Marek Vasut

Regards,
Peng.

Best regards,
Marek Vasut

#4 lore raw

PATCH 1/1 imx: dma: correct MXS_DMA_ALIGNMENT

In reply to Peng Fan

Hi Stefano,

Quoted 21 lines · Peng Fan

Hi Marek,

Quoted 6 lines · Marek Vasut
Quoted 3 lines · Peng Fan

We should not hardcode MXS_DMA_ALIGNMENT to 32, since we can not guarantee that socs' cache line size is 32 bytes.
If on chips whose cache line size is 64 bytes, error occurs:

Which chips are those?

i.MX7's L1 Cache line size is 64 bytes.

Quoted 11 lines
Quoted 9 lines

NAND: ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0 ERROR: v7_dcache_inval_range - stop address is not aligned - 0xbdf1f4a0 ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0 "
Align MXS_DMA_ALIGNMENT with ARCH_DMA_MINALIGN whose value is same to CONFIG_SYS_CACHELINE_SIZE if CONFIG_SYS_CACHELINE_SIZE defined.

Signed-off-by Peng Fan <[email protected]>
Acked-by Marek Vasut <[email protected]>

Will you apply this patch?

Quoted 7 lines
Quoted 3 lines

Best regards,
Marek Vasut

Regards,
Peng.

Regards,
Peng

#5 lore raw

PATCH 1/1 imx: dma: correct MXS_DMA_ALIGNMENT

In reply to Peng Fan
Quoted 22 lines · Peng Fan

We should not hardcode MXS_DMA_ALIGNMENT to 32, since we can not guarantee that socs' cache line size is 32 bytes.
If on chips whose cache line size is 64 bytes, error occurs:
"

NAND:  ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0
ERROR: v7_dcache_inval_range - stop address is not aligned - 0xbdf1f4a0
ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0

"
Align MXS_DMA_ALIGNMENT with ARCH_DMA_MINALIGN whose value is same to CONFIG_SYS_CACHELINE_SIZE if CONFIG_SYS_CACHELINE_SIZE defined.

Signed-off-by Peng Fan <[email protected]>
---
 arch/arm/include/asm/imx-common/dma.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm/include/asm/imx-common/dma.h +0 -0
index d5c1f7f..7d421b3 100644

arch/arm/include/asm/imx-common/dma.h line 28

Quoted 8 lines
arch/arm/include/asm/imx-common/dma.h +1 -1
@@ -22,7 +22,7 @@
 #define	DMA_PIO_WORDS		CONFIG_ARCH_DMA_PIO_WORDS
 #endif
 
-#define MXS_DMA_ALIGNMENT	32
+#define MXS_DMA_ALIGNMENT	ARCH_DMA_MINALIGN
 
 /*
  * MXS DMA channels

Applied to u-boot-imx, thanks!

Best regards,
Stefano Babic

Signature · 5 lines
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