Add Microblaze configuration options

Microblaze stack protection is configurable and isn't always enabled. This patch allows the stack protection to be disabled from the CPU properties.

Signed-off-by Alistair Francis <[email protected]>

---
V3:
- Enable stack protection by default
V2:
- Change the variable name to stackprot
- Include protection for the second time stack protection is enabled
- Disable stack protection by default
Changes since RFC:
- Move the cfg.stackproc check into translate.c
- Set the PVR register

 target-microblaze/cpu-qom.h   |    5 +++++
 target-microblaze/cpu.c       |    5 +++++
 target-microblaze/cpu.h       |    1 +
 target-microblaze/translate.c |    4 ++--
 4 files changed, 13 insertions(+), 2 deletions(-)

target-microblaze/cpu-qom.h +5 -0

index e3e0701..e08adb9 100644
@@ -59,6 +59,11 @@ typedef struct MicroBlazeCPU {
     uint32_t base_vectors;
     /*< public >*/
 
+    /* Microblaze Configuration Settings */
+    struct {
+        bool stackprot;
+    } cfg;
+
     CPUMBState env;
 } MicroBlazeCPU;
 

target-microblaze/cpu.c +5 -0

index 95be540..d3dad4a 100644
@@ -114,6 +114,9 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
                         | PVR2_USE_FPU2_MASK \
                         | PVR2_FPU_EXC_MASK \
                         | 0;
+
+    env->pvr.regs[0] |= cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0;
+
     env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family.  */
     env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);
 

@@ -156,6 +159,8 @@ static const VMStateDescription vmstate_mb_cpu = {
 
 static Property mb_properties[] = {
     DEFINE_PROP_UINT32("xlnx.base-vectors", MicroBlazeCPU, base_vectors, 0),
+    DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot,
+                     true),
     DEFINE_PROP_END_OF_LIST(),
 };
 

target-microblaze/cpu.h +1 -0

index e4c1cde..481f463 100644
@@ -128,6 +128,7 @@ typedef struct CPUMBState CPUMBState;
 #define PVR0_FAULT			0x00100000
 #define PVR0_VERSION_MASK               0x0000FF00
 #define PVR0_USER1_MASK                 0x000000FF
+#define PVR0_SPROT_MASK                 0x00000001
 
 /* User 2 PVR mask */
 #define PVR1_USER2_MASK                 0xFFFFFFFF

target-microblaze/translate.c +2 -2

index 4068946..bd10b40 100644
@@ -862,7 +862,7 @@ static inline TCGv *compute_ldst_addr(DisasContext *dc, TCGv *t)
     int stackprot = 0;
 
     /* All load/stores use ra.  */
-    if (dc->ra == 1) {
+    if (dc->ra == 1 && dc->cpu->cfg.stackprot) {
         stackprot = 1;
     }
 

@@ -875,7 +875,7 @@ static inline TCGv *compute_ldst_addr(DisasContext *dc, TCGv *t)
             return &cpu_R[dc->ra];
         }
 
-        if (dc->rb == 1) {
+        if (dc->rb == 1 && dc->cpu->cfg.stackprot) {
             stackprot = 1;
         }
 

Signature · 1 line

1.7.1

Originally the use-fpu PVR bits were manually set for each machine. This is a hassle and difficult to read, instead set them based on the CPU properties.

Signed-off-by Alistair Francis <[email protected]>

Reviewed-by Peter Crosthwaite <[email protected]>

---
V3:
- Add comments explaing the FPU levels
V2:
- Remove unnecessary declaration of r
Changes since RFC:
- Tidy up the if logic

 hw/microblaze/petalogix_ml605_mmu.c |    7 +++++--
 target-microblaze/cpu-qom.h         |    1 +
 target-microblaze/cpu.c             |   13 ++++++++++---
 target-microblaze/translate.c       |   10 +++-------
 4 files changed, 19 insertions(+), 12 deletions(-)

hw/microblaze/petalogix_ml605_mmu.c +5 -2

index 48c264b..05c120a 100644
@@ -71,9 +71,8 @@ static void machine_cpu_reset(MicroBlazeCPU *cpu)
     env->pvr.regs[10] = 0x0e000000; /* virtex 6 */
     /* setup pvr to match kernel setting */
     env->pvr.regs[5] |= PVR5_DCACHE_WRITEBACK_MASK;
-    env->pvr.regs[0] |= PVR0_USE_FPU_MASK | PVR0_ENDI;
+    env->pvr.regs[0] |= PVR0_ENDI;
     env->pvr.regs[0] = (env->pvr.regs[0] & ~PVR0_VERSION_MASK) | (0x14 << 8);
-    env->pvr.regs[2] ^= PVR2_USE_FPU2_MASK;
     env->pvr.regs[4] = 0xc56b8000;
     env->pvr.regs[5] = 0xc56be000;
 }

@@ -95,6 +94,10 @@ petalogix_ml605_init(MachineState *machine)
 
     /* init CPUs */
     cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU));
+    /* Use FPU but don't use floating point conversion and square
+     * root instructions
+     */
+    object_property_set_int(OBJECT(cpu), 1, "use-fpu", &error_abort);
     object_property_set_bool(OBJECT(cpu), true, "realized", &error_abort);
 
     /* Attach emulated BRAM through the LMB.  */

target-microblaze/cpu-qom.h +1 -0

index dd04199..a6474f9 100644
@@ -63,6 +63,7 @@ typedef struct MicroBlazeCPU {
     struct {
         bool stackprot;
         uint32_t base_vectors;
+        uint8_t usefpu;
     } cfg;
 
     CPUMBState env;

target-microblaze/cpu.c +10 -3

index 0f805d3..b857056 100644
@@ -110,12 +110,14 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
                         | PVR2_USE_DIV_MASK \
                         | PVR2_USE_HW_MUL_MASK \
                         | PVR2_USE_MUL64_MASK \
-                        | PVR2_USE_FPU_MASK \
-                        | PVR2_USE_FPU2_MASK \
                         | PVR2_FPU_EXC_MASK \
                         | 0;
 
-    env->pvr.regs[0] |= cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0;
+    env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |
+                        (cpu->cfg.usefpu ? PVR0_USE_FPU_MASK : 0);
+
+    env->pvr.regs[2] |= (cpu->cfg.usefpu ? PVR2_USE_FPU_MASK : 0) |
+                        (cpu->cfg.usefpu > 1 ? PVR2_USE_FPU2_MASK : 0);
 
     env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family.  */
     env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);

@@ -161,6 +163,11 @@ static Property mb_properties[] = {
     DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0),
     DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot,
                      true),
+    /* If use-fpu > 0 - FPU is enabled
+     * If use-fpu = 2 - Floating point conversion and square root instructions
+     *                  are enabled
+     */
+    DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.usefpu, 2),
     DEFINE_PROP_END_OF_LIST(),
 };
 

target-microblaze/translate.c +3 -7

index bd10b40..8187700 100644
@@ -1411,15 +1411,11 @@ static void dec_rts(DisasContext *dc)
 
 static int dec_check_fpuv2(DisasContext *dc)
 {
-    int r;
-
-    r = dc->cpu->env.pvr.regs[2] & PVR2_USE_FPU2_MASK;
-
-    if (!r && (dc->tb_flags & MSR_EE_FLAG)) {
+    if ((dc->cpu->cfg.usefpu != 2) && (dc->tb_flags & MSR_EE_FLAG)) {
         tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_FPU);
         t_gen_raise_exception(dc, EXCP_HW_EXCP);
     }
-    return r;
+    return (dc->cpu->cfg.usefpu == 2) ? 0 : PVR2_USE_FPU2_MASK;
 }
 
 static void dec_fpu(DisasContext *dc)

@@ -1428,7 +1424,7 @@ static void dec_fpu(DisasContext *dc)
 
     if ((dc->tb_flags & MSR_EE_FLAG)
           && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
-          && !((dc->cpu->env.pvr.regs[2] & PVR2_USE_FPU_MASK))) {
+          && (dc->cpu->cfg.usefpu != 1)) {
         tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
         t_gen_raise_exception(dc, EXCP_HW_EXCP);
         return;

Signature · 1 line

1.7.1

Stack protection is not available when the MMU is enabled. As the MMU is enabled by default, disable stack protection by default.

Signed-off-by Alistair Francis <[email protected]>

---

 target-microblaze/cpu.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

target-microblaze/cpu.c +1 -1

index b857056..13ae49a 100644
@@ -162,7 +162,7 @@ static const VMStateDescription vmstate_mb_cpu = {
 static Property mb_properties[] = {
     DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0),
     DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot,
-                     true),
+                     false),
     /* If use-fpu > 0 - FPU is enabled
      * If use-fpu = 2 - Floating point conversion and square root instructions
      *                  are enabled

Signature · 1 line

1.7.1

Firstly this patch series tidies up some code and removes a "xlnx." prefix.

Then it moves the Microblaze PVR registers to the end of the CPUMBState to preserve them during reset. This allows most of the operations on them to be moved from the reset to the realise. Except for the machine specific ones which will be moved when the other properties are converted across to standard QEMU props, after this patch series is accepted (either merged or the method I'm using is approved). See the individual commit for more details.

Next it adds the "use-stack-protection" property to the Microblaze CPU, which allows stack protection to be disabled.

It also converts the previously hardcoded method of enabling the FPU to use standard QEMU properties. This simplifies the logic in the target-microblaze translate.c.

V3:
- Split disabling stack protection into a seperate patch
- Add comments detailing the use-fpu values
V2:
- Small fixes
- Disable stack protection by default
- Remove the memset and cpu_reset functions from the MB realise
Changes since RFC:
- Preserve the PVR registers during resets
- Move most of the logic into realise functions
- Small name and function changes

Alistair Francis (6):
target-microblaze: Fix up indentation
target-microblaze: Preserve the pvr registers during reset
target-microblaze: Allow the stack protection to be disabled
target-microblaze: Tidy up the base-vectors property
target-microblaze: Convert use-fpu to a CPU property
target-microblaze: Disable stack protection by default

 hw/microblaze/petalogix_ml605_mmu.c |    7 +++-
 target-microblaze/cpu-qom.h         |    9 +++++-
 target-microblaze/cpu.c             |   60 ++++++++++++++++++++++-------------
 target-microblaze/cpu.h             |   11 ++++--
 target-microblaze/helper.c          |    8 ++--
 target-microblaze/op_helper.c       |   10 +++---
 target-microblaze/translate.c       |   14 +++-----
 7 files changed, 72 insertions(+), 47 deletions(-)

Quoted 20 lines · Alistair Francis

Firstly this patch series tidies up some code and removes a "xlnx." prefix.

Then it moves the Microblaze PVR registers to the end of the CPUMBState to preserve them during reset. This allows most of the operations on them to be moved from the reset to the realise. Except for the machine specific ones which will be moved when the other properties are converted across to standard QEMU props, after this patch series is accepted (either merged or the method I'm using is approved). See the individual commit for more details.

Next it adds the "use-stack-protection" property to the Microblaze CPU, which allows stack protection to be disabled.

It also converts the previously hardcoded method of enabling the FPU to use standard QEMU properties. This simplifies the logic in the target-microblaze translate.c.

Quoted 11 lines

V3:
- Split disabling stack protection into a seperate patch
- Add comments detailing the use-fpu values
V2:
- Small fixes
- Disable stack protection by default
- Remove the memset and cpu_reset functions from the MB realise
Changes since RFC:
- Preserve the PVR registers during resets
- Move most of the logic into realise functions
- Small name and function changes

Thanks Alistair,

I've added this into my MicroBlaze queue.

Cheers,
Edgar

Quoted 18 lines

Alistair Francis (6):
target-microblaze: Fix up indentation
target-microblaze: Preserve the pvr registers during reset
target-microblaze: Allow the stack protection to be disabled
target-microblaze: Tidy up the base-vectors property
target-microblaze: Convert use-fpu to a CPU property
target-microblaze: Disable stack protection by default

 hw/microblaze/petalogix_ml605_mmu.c |    7 +++-
 target-microblaze/cpu-qom.h         |    9 +++++-
 target-microblaze/cpu.c             |   60 ++++++++++++++++++++++-------------
 target-microblaze/cpu.h             |   11 ++++--
 target-microblaze/helper.c          |    8 ++--
 target-microblaze/op_helper.c       |   10 +++---
 target-microblaze/translate.c       |   14 +++-----
 7 files changed, 72 insertions(+), 47 deletions(-)