clk: meson: Add clock controller

From: Carlo Caione <[email protected]>

This patchset introduces preliminary support for the clock controller found on Amlogic MesonX SoCs and enables it for the Meson8b.

DTS patches with support for Meson8b SoCs will follow.

Changelog:

v1->v2:
* fix double CLK_IGNORE_UNUSED in clk-pll.c
* fix comment in meson8b-clkc.h

v2->v3:
* fix includes
* use divider_* functions for clk-cpu
* fix memory leak in meson_clk_register_composite()
* mask operations now use GENMASK
* const-ify global configuration variables in meson8b-clkc.c
* several more small fixes

Carlo Caione (3):
clk: meson: Add support for Meson clock controller
clk: meson: Document bindings for Meson8b clock controller
clk: meson8b: Add support for Meson8b clocks

 .../bindings/clock/amlogic,meson8b-clkc.txt        |  40 ++++
 drivers/clk/Makefile                               |   1 +
 drivers/clk/meson/Makefile                         |   6 +
 drivers/clk/meson/clk-cpu.c                        | 234 +++++++++++++++++++
 drivers/clk/meson/clk-pll.c                        | 227 +++++++++++++++++++
 drivers/clk/meson/clkc.c                           | 247 +++++++++++++++++++++
 drivers/clk/meson/clkc.h                           | 187 ++++++++++++++++
 drivers/clk/meson/meson8b-clkc.c                   | 196 ++++++++++++++++
 include/dt-bindings/clock/meson8b-clkc.h           |  25 +++
 9 files changed, 1163 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
 create mode 100644 drivers/clk/meson/Makefile
 create mode 100644 drivers/clk/meson/clk-cpu.c
 create mode 100644 drivers/clk/meson/clk-pll.c
 create mode 100644 drivers/clk/meson/clkc.c
 create mode 100644 drivers/clk/meson/clkc.h
 create mode 100644 drivers/clk/meson/meson8b-clkc.c
 create mode 100644 include/dt-bindings/clock/meson8b-clkc.h

1.9.1

From: Carlo Caione <[email protected]>

This patchset adds the infrastructure for registering and managing the core clocks found on Amlogic MesonX SoCs. In particular:

- PLLs
- CPU clock
- Fixed rate clocks, fixed factor clocks, ...

---
 drivers/clk/Makefile                     |   1 +
 drivers/clk/meson/Makefile               |   5 +
 drivers/clk/meson/clk-cpu.c              | 234 +++++++++++++++++++++++++++++
 drivers/clk/meson/clk-pll.c              | 227 ++++++++++++++++++++++++++++
 drivers/clk/meson/clkc.c                 | 247 +++++++++++++++++++++++++++++++
 drivers/clk/meson/clkc.h                 | 187 +++++++++++++++++++++++
 include/dt-bindings/clock/meson8b-clkc.h |  25 ++++
 7 files changed, 926 insertions(+)
 create mode 100644 drivers/clk/meson/Makefile
 create mode 100644 drivers/clk/meson/clk-cpu.c
 create mode 100644 drivers/clk/meson/clk-pll.c
 create mode 100644 drivers/clk/meson/clkc.c
 create mode 100644 drivers/clk/meson/clkc.h
 create mode 100644 include/dt-bindings/clock/meson8b-clkc.h

index 3d00c25..9c4ddb1 100644
@@ -55,6 +55,7 @@ ifeq ($(CONFIG_COMMON_CLK), y)
 obj-$(CONFIG_ARCH_MMP)			+= mmp/
 endif
 obj-$(CONFIG_PLAT_ORION)		+= mvebu/
+obj-$(CONFIG_ARCH_MESON)		+= meson/
 obj-$(CONFIG_ARCH_MXS)			+= mxs/
 obj-$(CONFIG_MACH_PISTACHIO)		+= pistachio/
 obj-$(CONFIG_COMMON_CLK_PXA)		+= pxa/

new file mode 100644
index 0000000..66c6d8d
@@ -0,0 +1,5 @@
+#
+# Makefile for Meson specific clk
+#
+
+obj-y += clkc.o clk-pll.o clk-cpu.o

new file mode 100644
index 0000000..bd2720d
@@ -0,0 +1,25 @@
+/*
+ * Meson8b clock tree IDs
+ */
+
+#ifndef __MESON8B_CLKC_H
+#define __MESON8B_CLKC_H
+
+#define CLKID_UNUSED		0
+#define CLKID_XTAL		1
+#define CLKID_PLL_FIXED		2
+#define CLKID_PLL_VID		3
+#define CLKID_PLL_SYS		4
+#define CLKID_FCLK_DIV2		5
+#define CLKID_FCLK_DIV3		6
+#define CLKID_FCLK_DIV4		7
+#define CLKID_FCLK_DIV5		8
+#define CLKID_FCLK_DIV7		9
+#define CLKID_CLK81		10
+#define CLKID_MALI		11
+#define CLKID_CPUCLK		12
+#define CLKID_ZERO		13
+
+#define CLK_NR_CLKS		(CLKID_ZERO + 1)
+
+#endif /* __MESON8B_CLKC_H */

1.9.1

From: Carlo Caione <[email protected]>

Add documentation for the clock controller.

---
 .../bindings/clock/amlogic,meson8b-clkc.txt        | 40 ++++++++++++++++++++++
 1 file changed, 40 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt

new file mode 100644
index 0000000..2b7b3fa
@@ -0,0 +1,40 @@
+* Amlogic Meson8b Clock and Reset Unit
+
+The Amlogic Meson8b clock controller generates and supplies clock to various
+controllers within the SoC.
+
+Required Properties:
+
+- compatible: should be "amlogic,meson8b-clkc"
+- reg: it must be composed by two tuples:
+	0) physical base address of the xtal register and length of memory
+	   mapped region.
+	1) physical base address of the clock controller and length of memory
+	   mapped region.
+
+- #clock-cells: should be 1.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume. All available clocks are defined as
+preprocessor macros in the dt-bindings/clock/meson8b-clkc.h header and can be
+used in device tree sources.
+
+Example: Clock controller node:
+
+	clkc: clock-controller at c1104000 {
+		#clock-cells = <1>;
+		compatible = "amlogic,meson8b-clkc";
+		reg = <0xc1108000 0x4>, <0xc1104000 0x460>;
+	};
+
+
+Example: UART controller node that consumes the clock generated by the clock
+  controller:
+
+	uart_AO: serial at c81004c0 {
+		compatible = "amlogic,meson-uart";
+		reg = <0xc81004c0 0x14>;
+		interrupts = <0 90 1>;
+		clocks = <&clkc CLKID_CLK81>;
+		status = "disabled";
+	};

1.9.1

From: Carlo Caione <[email protected]>

This patch adds support for the basic clocks found on the Amlogic Meson8b SoCs.

---
 drivers/clk/meson/Makefile       |   1 +
 drivers/clk/meson/meson8b-clkc.c | 196 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 197 insertions(+)
 create mode 100644 drivers/clk/meson/meson8b-clkc.c

index 66c6d8d..6d45531 100644
@@ -3,3 +3,4 @@
 #
 
 obj-y += clkc.o clk-pll.o clk-cpu.o
+obj-y += meson8b-clkc.o

1.9.1

Did you want to send the dts changes through arm-soc? Do they depend on the header file that is included here? clk-next is not stable and shouldn't be pulled into other developer's trees, so if we need some stable commit to give off to arm-soc for v4.2 we need to know soon. Or we can split the header file off into a different patch and send it through both arm-soc and clk tree.

Otherwise the patches look good. I fixed up the __init markings on some functions which were in the wrong place.

Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

(adding Arnd in CC) this is what I have done in the past but I have no strong preference.

Yes, they do.

Again whatever is more preferable to the maintainers. Just let me know so I can rearrange the DTS patchset.

Thank you,

Carlo Caione

I'd prefer not to send dts changes through the clk tree either. I looked for the dts changes on the list but I couldn't find them.

I've put these patches on a 'clk-meson8b' branch and merged it into clk-next. We won't rewrite clk-meson8b so you can use it for a stable baseline to send to arm-soc if needed.

Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project