pinctrl: mvebu: numerous fixes, cleanups and improvements
Subsystems (4)
cover pinctrl: mvebu: numerous fixes, cleanups and improvements
Hello,
This fairly long series of patches implement numerous fixes, cleanups and improvements to the description of the MPP pins on Armada 370, 375, 38x, 39x and XP.
The original motivation was a bug report mentioning some inconsistencies between the Armada 38x HW datasheet and the corresponding pinctrl driver. Even though I had already written some basic Python script to extract the MPP data from the datasheet, and do some of the code generation steps automatically, a good part of the process was still manual, which means: 1/ mistakes can be made, 2/ it's not easy to update with new versions of the datasheets that fix bugs in the MPP description.
Therefore, I improved my Python scripts, and now the MPP tables in the pinctrl drivers are automatically generated from the datasheet HW information. The script in question is quite ugly, as it takes into account some existing inconsistencies in the formatting of the different pinctrl drivers, and also different naming choices between Linux and the HW datasheet. But nonetheless, it has been very useful to bring all the pinctrl drivers in sync with the datasheet, and to detect inconsistencies between the pinctrl drivers.
This long series of patches is the result of this work, and can be separated in three parts:
* The "fixes", which are marked for stable because they fix some real potential problems. These are patches 1 to 9 included.
* The "cleanups", which are not doing anything really interesting except renaming things to progressively make drivers more consistent with each other and with the datasheets. These are patches 10 to 24 included.
* The "improvements", which are actually adding pin functions that were not supported earlier, or even a new SoC completely such as the Armada 395 (as part of the armada-39x driver). These are patches 25 to 34 included.
Some of the patches are breaking the DT backward compatibility, but most of them are doing that on pins that are highly unlikely to be used with a mainline kernel. The only real concern could be with patch 21 that renames the function "spi" on Armada XP to "spi0" to match the datasheet and to prepare for the addition of the "spi1" function. If that is considered to be a too serious breakage, then we can imagine leaving "spi" for the first SPI bus and use "spi1" for the second SPI bus. I can rework the patch series to adjust this if deemed necessary.
In some cases, I have decided to not make drivers match to not break the DT backward compatibility. For example, some drivers use uart0/uart1, while some others use ua0/ua1 (like in the Marvell datasheets), and I've left this inconsistency as is (my script copes with it).
In addition to the fixes to the MPP lists themselves, two patches are fixing the pinctrl_gpio_range[] definitions, which were wrong for Armada 38x and Armada 39x.
I wish you good luck when reviewing this. It was boring to do, so I guess it is going to be horribly boring to review :-)
Best regards,
Thomas
Thomas Petazzoni (34):
pinctrl: mvebu: armada-38x: fix PCIe functions
pinctrl: mvebu: armada-370: fix spi0 pin description
pinctrl: mvebu: armada-375: remove non-existing NAND re/we pins
pinctrl: mvebu: armada-xp: remove non-existing NAND pins
pinctrl: mvebu: armada-xp: remove non-existing VDD cpu_pd functions
pinctrl: mvebu: armada-xp: fix functions of MPP48
pinctrl: mvebu: armada-375: remove incorrect space in pin description
pinctrl: mvebu: armada-38x: fix incorrect total number of GPIOs
pinctrl: mvebu: armada-39x: fix incorrect total number of GPIOs
pinctrl: mvebu: armada-{375,38x,39x}: normalize naming of PTP subnames
pinctrl: mvebu: armada-{38x,39x,xp}: normalize naming of DRAM
functions
pinctrl: mvebu: armada-39x: normalize SATA present functionality
naming
pinctrl: mvebu: armada-39x: normalize SDIO pin naming
pinctrl: mvebu: armada-{370,375,38x,39x}: normalize dev pins
pinctrl: mvebu: armada-39x: align NAND pin naming
pinctrl: mvebu: armada-{370,375,38x,39x,xp}: normalize TDM pins
pinctrl: mvebu: armada-{370,375}: normalize PCIe pins
pinctrl: mvebu: armada-{370,375}: normalize audio pins
pinctrl: mvebu: armada-{370,xp}: normalize ethernet txclkout pins
pinctrl: mvebu: armada-xp: fix binding documentation of ge1 pins
pinctrl: mvebu: armada-370: align VDD cpu-pd pin naming with datasheet
pinctrl: mvebu: armada-370: align spi1 clock pin naming
pinctrl: mvebu: armada-xp: rename spi to spi0
pinctrl: mvebu: armada-39x: normalize ref clock naming
pinctrl: mvebu: armada-xp: add spi1 function
pinctrl: mvebu: armada-xp: add nand rb function
pinctrl: mvebu: armada-xp: add dram functions
pinctrl: mvebu: armada-38x: add sata functions
pinctrl: mvebu: armada-38x: add nand functions
pinctrl: mvebu: armada-38x: add ua1 functions
pinctrl: mvebu: armada-38x: add ptp functions
pinctrl: mvebu: armada-39x: add missing PCIe functions
pinctrl: mvebu: armada-39x: add missing SATA functions
pinctrl: mvebu: armada-39x: add support for Armada 395 variant
.../pinctrl/marvell,armada-370-pinctrl.txt | 18 +-- .../pinctrl/marvell,armada-375-pinctrl.txt | 34 +++--- .../pinctrl/marvell,armada-38x-pinctrl.txt | 66 +++++------ .../pinctrl/marvell,armada-39x-pinctrl.txt | 84 +++++++------ .../bindings/pinctrl/marvell,armada-xp-pinctrl.txt | 80 ++++++------- drivers/pinctrl/mvebu/pinctrl-armada-370.c | 22 ++-- drivers/pinctrl/mvebu/pinctrl-armada-375.c | 50 ++++---- drivers/pinctrl/mvebu/pinctrl-armada-38x.c | 120 ++++++++++--------- drivers/pinctrl/mvebu/pinctrl-armada-39x.c | 131 ++++++++++++--------- drivers/pinctrl/mvebu/pinctrl-armada-xp.c | 98 +++++++-------- 10 files changed, 363 insertions(+), 340 deletions(-)
Signature · 1 line
2.1.0
PATCH 1/34 pinctrl: mvebu: armada-38x: fix PCIe functions
A new revision of the Marvell Armada 38x hardware datasheet unveiled that the definition of some of the PCIe functions were not correct. This commit fixes the pinctrl driver accordingly.
Some PCIe functions simply do not exist, some of the PCIe functions in fact were corresponding to other functions, and some PCIe functions have been added.
Note: the seemingly unrelated removal of spi(cs2) on MPP47 is related:
this function is in fact implemented on MPP43, instead of a PCIe function.
--- .../pinctrl/marvell,armada-38x-pinctrl.txt | 38 ++++++++--------- drivers/pinctrl/mvebu/pinctrl-armada-38x.c | 49 +++++++++------------- 2 files changed, 39 insertions(+), 48 deletions(-)
Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt +19 -19
@@ -27,15 +27,15 @@ mpp8 8 gpio, ge0(txd1), dev(ad10) mpp9 9 gpio, ge0(txd2), dev(ad11) mpp10 10 gpio, ge0(txd3), dev(ad12) mpp11 11 gpio, ge0(txctl), dev(ad13) -mpp12 12 gpio, ge0(rxd0), pcie0(rstout), pcie1(rstout) [1], spi0(cs1), dev(ad14) -mpp13 13 gpio, ge0(rxd1), pcie0(clkreq), pcie1(clkreq) [1], spi0(cs2), dev(ad15) -mpp14 14 gpio, ge0(rxd2), ptp(clk), m(vtt_ctrl), spi0(cs3), dev(wen1) -mpp15 15 gpio, ge0(rxd3), ge(mdc slave), pcie0(rstout), spi0(mosi), pcie1(rstout) [1] -mpp16 16 gpio, ge0(rxctl), ge(mdio slave), m(decc_err), spi0(miso), pcie0(clkreq) +mpp12 12 gpio, ge0(rxd0), pcie0(rstout), spi0(cs1), dev(ad14), pcie3(clkreq) +mpp13 13 gpio, ge0(rxd1), pcie0(clkreq), pcie1(clkreq) [1], spi0(cs2), dev(ad15), pcie2(clkreq) +mpp14 14 gpio, ge0(rxd2), ptp(clk), m(vtt_ctrl), spi0(cs3), dev(wen1), pcie3(clkreq) +mpp15 15 gpio, ge0(rxd3), ge(mdc slave), pcie0(rstout), spi0(mosi) +mpp16 16 gpio, ge0(rxctl), ge(mdio slave), m(decc_err), spi0(miso), pcie0(clkreq), pcie1(clkreq) [1] mpp17 17 gpio, ge0(rxclk), ptp(clk), ua1(rxd), spi0(sck), sata1(prsnt) -mpp18 18 gpio, ge0(rxerr), ptp(trig_gen), ua1(txd), spi0(cs0), pcie1(rstout) [1] -mpp19 19 gpio, ge0(col), ptp(event_req), pcie0(clkreq), sata1(prsnt), ua0(cts) -mpp20 20 gpio, ge0(txclk), ptp(clk), pcie1(rstout) [1], sata0(prsnt), ua0(rts) +mpp18 18 gpio, ge0(rxerr), ptp(trig_gen), ua1(txd), spi0(cs0) +mpp19 19 gpio, ge0(col), ptp(event_req), ge0(txerr), sata1(prsnt), ua0(cts) +mpp20 20 gpio, ge0(txclk), ptp(clk), sata0(prsnt), ua0(rts) mpp21 21 gpio, spi0(cs1), ge1(rxd0), sata0(prsnt), sd0(cmd), dev(bootcs) mpp22 22 gpio, spi0(mosi), dev(ad0) mpp23 23 gpio, spi0(sck), dev(ad2)
@@ -58,23 +58,23 @@ mpp39 39 gpio, i2c1(sck), ge1(rxd2), ua0(cts), sd0(d1), dev(a2) mpp40 40 gpio, i2c1(sda), ge1(rxd3), ua0(rts), sd0(d2), dev(ad6) mpp41 41 gpio, ua1(rxd), ge1(rxctl), ua0(cts), spi1(cs3), dev(burst/last) mpp42 42 gpio, ua1(txd), ua0(rts), dev(ad7) -mpp43 43 gpio, pcie0(clkreq), m(vtt_ctrl), m(decc_err), pcie0(rstout), dev(clkout) -mpp44 44 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3(prsnt) [3], pcie0(rstout) -mpp45 45 gpio, ref(clk_out0), pcie0(rstout), pcie1(rstout) [1], pcie2(rstout), pcie3(rstout) -mpp46 46 gpio, ref(clk_out1), pcie0(rstout), pcie1(rstout) [1], pcie2(rstout), pcie3(rstout) -mpp47 47 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], spi1(cs2), sata3(prsnt) [2] -mpp48 48 gpio, sata0(prsnt), m(vtt_ctrl), tdm2c(pclk), audio(mclk), sd0(d4) -mpp49 49 gpio, sata2(prsnt) [2], sata3(prsnt) [2], tdm2c(fsync), audio(lrclk), sd0(d5) -mpp50 50 gpio, pcie0(rstout), pcie1(rstout) [1], tdm2c(drx), audio(extclk), sd0(cmd) +mpp43 43 gpio, pcie0(clkreq), m(vtt_ctrl), m(decc_err), spi1(cs2), dev(clkout) +mpp44 44 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3(prsnt) [3] +mpp45 45 gpio, ref(clk_out0), pcie0(rstout) +mpp46 46 gpio, ref(clk_out1), pcie0(rstout) +mpp47 47 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3(prsnt) [2] +mpp48 48 gpio, sata0(prsnt), m(vtt_ctrl), tdm2c(pclk), audio(mclk), sd0(d4), pcie0(clkreq) +mpp49 49 gpio, sata2(prsnt) [2], sata3(prsnt) [2], tdm2c(fsync), audio(lrclk), sd0(d5), pcie1(clkreq) +mpp50 50 gpio, pcie0(rstout), tdm2c(drx), audio(extclk), sd0(cmd) mpp51 51 gpio, tdm2c(dtx), audio(sdo), m(decc_err) -mpp52 52 gpio, pcie0(rstout), pcie1(rstout) [1], tdm2c(intn), audio(sdi), sd0(d6) +mpp52 52 gpio, pcie0(rstout), tdm2c(intn), audio(sdi), sd0(d6) mpp53 53 gpio, sata1(prsnt), sata0(prsnt), tdm2c(rstn), audio(bclk), sd0(d7) -mpp54 54 gpio, sata0(prsnt), sata1(prsnt), pcie0(rstout), pcie1(rstout) [1], sd0(d3) +mpp54 54 gpio, sata0(prsnt), sata1(prsnt), pcie0(rstout), ge0(txerr), sd0(d3) mpp55 55 gpio, ua1(cts), ge(mdio), pcie1(clkreq) [1], spi1(cs1), sd0(d0) mpp56 56 gpio, ua1(rts), ge(mdc), m(decc_err), spi1(mosi) mpp57 57 gpio, spi1(sck), sd0(clk) mpp58 58 gpio, pcie1(clkreq) [1], i2c1(sck), pcie2(clkreq), spi1(miso), sd0(d1) -mpp59 59 gpio, pcie0(rstout), i2c1(sda), pcie1(rstout) [1], spi1(cs0), sd0(d2) +mpp59 59 gpio, pcie0(rstout), i2c1(sda), spi1(cs0), sd0(d2) [1]: only available on 88F6820 and 88F6828 [2]: only available on 88F6828
drivers/pinctrl/mvebu/pinctrl-armada-38x.c +20 -29
151 lines not on this page · raw message
Signature · 1 line
2.1.0
PATCH 1/34 pinctrl: mvebu: armada-38x: fix PCIe functions
Quoted 8 lines · Thomas Petazzoni
A new revision of the Marvell Armada 38x hardware datasheet unveiled that the definition of some of the PCIe functions were not correct. This commit fixes the pinctrl driver accordingly.
Some PCIe functions simply do not exist, some of the PCIe functions in fact were corresponding to other functions, and some PCIe functions have been added.
Quoted 7 lines
Note: the seemingly unrelated removal of spi(cs2) on MPP47 is related:
this function is in fact implemented on MPP43, instead of a PCIe function.Signed-off-by Thomas Petazzoni <[email protected]>Cc <[email protected]> # v3.15+Fixes ca6d9a084b56f ("pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385")
Patch applied.
Yours,
Linus Walleij
PATCH 2/34 pinctrl: mvebu: armada-370: fix spi0 pin description
In reply to Thomas PetazzoniDue to a mistake, the CS0 and CS1 SPI0 functions were incorrectly named "spi0-1" instead of just "spi0". This commit fixes that.
This DT binding change does not affect any of the in-tree users.
--- .../devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt | 4 ++-- drivers/pinctrl/mvebu/pinctrl-armada-370.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-)
Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt +2 -2
@@ -92,5 +92,5 @@ mpp61 61 gpo, dev(wen1), uart1(txd), audio(rclk) mpp62 62 gpio, dev(a2), uart1(cts), tdm(drx), pcie(clkreq0), audio(mclk), uart0(cts) mpp63 63 gpo, spi0(sck), tclk -mpp64 64 gpio, spi0(miso), spi0-1(cs1) -mpp65 65 gpio, spi0(mosi), spi0-1(cs2) +mpp64 64 gpio, spi0(miso), spi0(cs1) +mpp65 65 gpio, spi0(mosi), spi0(cs2)
drivers/pinctrl/mvebu/pinctrl-armada-370.c +2 -2
@@ -370,11 +370,11 @@ static struct mvebu_mpp_mode mv88f6710_mpp_modes[] = {MPP_MODE (64 ,MPP_FUNCTION (0x0 ,"gpio" ,NULL ),MPP_FUNCTION (0x1 ,"spi0" ,"miso" ), -MPP_FUNCTION (0x2 ,"spi0-1" ,"cs1" )), +MPP_FUNCTION (0x2 ,"spi0" ,"cs1" )),MPP_MODE (65 ,MPP_FUNCTION (0x0 ,"gpio" ,NULL ),MPP_FUNCTION (0x1 ,"spi0" ,"mosi" ), - MPP_FUNCTION(0x2, "spi0-1", "cs2")), + MPP_FUNCTION(0x2, "spi0", "cs2")), };static struct mvebu_pinctrl_soc_info armada_370_pinctrl_info;
Signature · 1 line
2.1.0
PATCH 2/34 pinctrl: mvebu: armada-370: fix spi0 pin description
Quoted 8 lines · Thomas Petazzoni
Due to a mistake, the CS0 and CS1 SPI0 functions were incorrectly named "spi0-1" instead of just "spi0". This commit fixes that.
This DT binding change does not affect any of the in-tree users.
Signed-off-by Thomas Petazzoni <[email protected]>Cc <[email protected]> # v3.7+Fixes 5f597bb2be57 ("pinctrl: mvebu: add pinctrl driver for Armada 370")
Patch applied.
Yours,
Linus Walleij
PATCH 3/34 pinctrl: mvebu: armada-375: remove non-existing NAND re/we pins
In reply to Thomas PetazzoniAfter updating to a more recent version of the Armada 375, we realized that some of the pins documented as having a NAND-related functionality in fact did not have such functionality. This commit updates the pinctrl driver accordingly.
--- .../devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt | 4 ++-- drivers/pinctrl/mvebu/pinctrl-armada-375.c | 2 -- 2 files changed, 2 insertions(+), 4 deletions(-)
Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt +2 -2
@@ -22,8 +22,8 @@ mpp5 5 gpio, dev(ad7), spi0(cs2), spi1(cs2) mpp6 6 gpio, dev(ad0), led(p1), audio(rclk) mpp7 7 gpio, dev(ad1), ptp(clk), led(p2), audio(extclk) mpp8 8 gpio, dev (bootcs), spi0(cs0), spi1(cs0) -mpp9 9 gpio, nf(wen), spi0(sck), spi1(sck) -mpp10 10 gpio, nf(ren), dram(vttctrl), led(c1) +mpp9 9 gpio, spi0(sck), spi1(sck), nand(we) +mpp10 10 gpio, dram(vttctrl), led(c1), nand(re) mpp11 11 gpio, dev(a0), led(c2), audio(sdo) mpp12 12 gpio, dev(a1), audio(bclk) mpp13 13 gpio, dev(readyn), pcie0(rstoutn), pcie1(rstoutn)
drivers/pinctrl/mvebu/pinctrl-armada-375.c +0 -2
@@ -98,13 +98,11 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_FUNCTION(0x5, "nand", "ce")),MPP_MODE (9 ,MPP_FUNCTION (0x0 ,"gpio" ,NULL ), -MPP_FUNCTION (0x1 ,"nf" ,"wen" ),MPP_FUNCTION (0x2 ,"spi0" ,"sck" ),MPP_FUNCTION (0x3 ,"spi1" ,"sck" ),MPP_FUNCTION (0x5 ,"nand" ,"we" )), MPP_MODE(10, MPP_FUNCTION(0x0, "gpio", NULL), - MPP_FUNCTION(0x1, "nf", "ren"), MPP_FUNCTION(0x2, "dram", "vttctrl"), MPP_FUNCTION(0x3, "led", "c1"), MPP_FUNCTION(0x5, "nand", "re"),
Signature · 1 line
2.1.0
Andrew Lunn
maintainerPATCH 3/34 pinctrl: mvebu: armada-375: remove non-existing NAND re/we pins
Quoted 26 lines · Thomas Petazzoni
After updating to a more recent version of the Armada 375, we realized that some of the pins documented as having a NAND-related functionality in fact did not have such functionality. This commit updates the pinctrl driver accordingly.
Signed-off-by Thomas Petazzoni <[email protected]>Cc <[email protected]> # v3.15+Fixes ce3ed59dcddd ("pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 375")--- .../devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt | 4 ++-- drivers/pinctrl/mvebu/pinctrl-armada-375.c | 2 -- 2 files changed, 2 insertions(+), 4 deletions(-)Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt +2
-2@@ -22,8 +22,8 @@ mpp5 5 gpio, dev(ad7), spi0(cs2), spi1(cs2) mpp6 6 gpio, dev(ad0), led(p1), audio(rclk) mpp7 7 gpio, dev(ad1), ptp(clk), led(p2), audio(extclk) mpp8 8 gpio, dev (bootcs), spi0(cs0), spi1(cs0) -mpp9 9 gpio, nf(wen), spi0(sck), spi1(sck) -mpp10 10 gpio, nf(ren), dram(vttctrl), led(c1) +mpp9 9 gpio, spi0(sck), spi1(sck), nand(we) +mpp10 10 gpio, dram(vttctrl), led(c1), nand(re)
Quoted 1 line
From
armada-375.dtsi:
nand_pins: nand-pins {
marvell,pins = "mpp0", "mpp1", "mpp2",
"mpp3", "mpp4", "mpp5",
"mpp6", "mpp7", "mpp8",
"mpp9", "mpp10", "mpp11",
"mpp12", "mpp13";
marvell,function = "nand";
};Don't you also need to remove mpp9 and mpp10 from here? What does pinctrl do when you ask for pins which are not a member of the function?
Andrew
PATCH 3/34 pinctrl: mvebu: armada-375: remove non-existing NAND re/we pins
Dear Andrew Lunn,
Quoted 11 lines · Andrew Lunn
From
armada-375.dtsi:nand_pins: nand-pins { marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", "mpp4", "mpp5", "mpp6", "mpp7", "mpp8", "mpp9", "mpp10", "mpp11", "mpp12", "mpp13"; marvell,function = "nand"; };
Quoted 3 lines
Don't you also need to remove mpp9 and mpp10 from here? What does pinctrl do when you ask for pins which are not a member of the function?
In fact, no. Look at the patch:
MPP_MODE(9,
MPP_FUNCTION(0x0, "gpio", NULL),
- MPP_FUNCTION(0x1, "nf", "wen"),
MPP_FUNCTION(0x2, "spi0", "sck"), MPP_FUNCTION(0x3, "spi1", "sck"), MPP_FUNCTION(0x5, "nand", "we")),
MPP_MODE(10,
MPP_FUNCTION(0x0, "gpio", NULL),
- MPP_FUNCTION(0x1, "nf", "ren"),
MPP_FUNCTION(0x2, "dram", "vttctrl"), MPP_FUNCTION(0x3, "led", "c1"), MPP_FUNCTION(0x5, "nand", "re"),
See how both pins had a "nf" function (0x1) and a "nand" function (0x5). I didn't even notice that when doing the patch, so my commit log was slightly confusing.
The "nf" functions were incorrect. The "nand" functions were correct, and already used by armada-375.dtsi. I have just tested NAND on Armada 375 DB with all the pinctrl patches applied, and it works fine (created a UBI device, with a volume, etc.).
Best regards,
Thomas
Signature · 3 lines
Thomas Petazzoni, CTO, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com
PATCH 3/34 pinctrl: mvebu: armada-375: remove non-existing NAND re/we pins
In reply to Thomas PetazzoniQuoted 8 lines · Thomas Petazzoni
After updating to a more recent version of the Armada 375, we realized that some of the pins documented as having a NAND-related functionality in fact did not have such functionality. This commit updates the pinctrl driver accordingly.
Signed-off-by Thomas Petazzoni <[email protected]>Cc <[email protected]> # v3.15+Fixes ce3ed59dcddd ("pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 375")
Patch applied.
Yours,
Linus Walleij
PATCH 4/34 pinctrl: mvebu: armada-xp: remove non-existing NAND pins
In reply to Thomas PetazzoniAfter updating to a more recent version of the Armada XP datasheet, we realized that some of the pins documented as having a NAND-related functionality in fact did not have such functionality. This commit updates the pinctrl driver accordingly.
--- .../devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt | 4 ++-- drivers/pinctrl/mvebu/pinctrl-armada-xp.c | 2 -- 2 files changed, 2 insertions(+), 4 deletions(-)
Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt +2 -2
@@ -42,8 +42,8 @@ mpp20 20 gpio, ge0(rxd4), ge1(rxd2), lcd(d20), ptp(clk) mpp21 21 gpio, ge0(rxd5), ge1(rxd3), lcd(d21), mem(bat) mpp22 22 gpio, ge0(rxd6), ge1(rxctl), lcd(d22), sata0(prsnt) mpp23 23 gpio, ge0(rxd7), ge1(rxclk), lcd(d23), sata1(prsnt) -mpp24 24 gpio, lcd(hsync), sata1(prsnt), nf(bootcs-re), tdm(rst) -mpp25 25 gpio, lcd(vsync), sata0(prsnt), nf(bootcs-we), tdm(pclk) +mpp24 24 gpio, lcd(hsync), sata1(prsnt), tdm(rst) +mpp25 25 gpio, lcd(vsync), sata0(prsnt), tdm(pclk) mpp26 26 gpio, lcd(clk), tdm(fsync), vdd(cpu1-pd) mpp27 27 gpio, lcd(e), tdm(dtx), ptp(trig) mpp28 28 gpio, lcd(pwm), tdm(drx), ptp(evreq)
drivers/pinctrl/mvebu/pinctrl-armada-xp.c +0 -2
@@ -172,13 +172,11 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = {MPP_MODE (24 ,MPP_VAR_FUNCTION (0x0 ,"gpio" ,NULL ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x1 ,"sata1" ,"prsnt" ,V_MV78230_PLUS ), -MPP_VAR_FUNCTION (0x2 ,"nf" ,"bootcs-re" ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x3 ,"tdm" ,"rst" ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x4 ,"lcd" ,"hsync" ,V_MV78230_PLUS )),MPP_MODE (25 ,MPP_VAR_FUNCTION (0x0 ,"gpio" ,NULL ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x1 ,"sata0" ,"prsnt" ,V_MV78230_PLUS ), -MPP_VAR_FUNCTION (0x2 ,"nf" ,"bootcs-we" ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x3 ,"tdm" ,"pclk" ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x4 ,"lcd" ,"vsync" ,V_MV78230_PLUS )), MPP_MODE(26,
Signature · 1 line
2.1.0
PATCH 5/34 pinctrl: mvebu: armada-xp: remove non-existing VDD cpu_pd functions
In reply to Thomas PetazzoniThe latest version of the Armada XP datasheet no longer documents the VDD cpu_pd functions, which might indicate they are not working and/or not supported. This commit ensures the pinctrl driver matches the datasheet.
--- .../bindings/pinctrl/marvell,armada-xp-pinctrl.txt | 26 +++++++---------- drivers/pinctrl/mvebu/pinctrl-armada-xp.c | 33 +++++++--------------- 2 files changed, 20 insertions(+), 39 deletions(-)
Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt +10 -16
@@ -44,13 +44,13 @@ mpp22 22 gpio, ge0(rxd6), ge1(rxctl), lcd(d22), sata0(prsnt) mpp23 23 gpio, ge0(rxd7), ge1(rxclk), lcd(d23), sata1(prsnt) mpp24 24 gpio, lcd(hsync), sata1(prsnt), tdm(rst) mpp25 25 gpio, lcd(vsync), sata0(prsnt), tdm(pclk) -mpp26 26 gpio, lcd(clk), tdm(fsync), vdd(cpu1-pd) +mpp26 26 gpio, lcd(clk), tdm(fsync) mpp27 27 gpio, lcd(e), tdm(dtx), ptp(trig) mpp28 28 gpio, lcd(pwm), tdm(drx), ptp(evreq) -mpp29 29 gpio, lcd(ref-clk), tdm(int0), ptp(clk), vdd(cpu0-pd) +mpp29 29 gpio, lcd(ref-clk), tdm(int0), ptp(clk) mpp30 30 gpio, tdm(int1), sd0(clk) -mpp31 31 gpio, tdm(int2), sd0(cmd), vdd(cpu0-pd) -mpp32 32 gpio, tdm(int3), sd0(d0), vdd(cpu1-pd) +mpp31 31 gpio, tdm(int2), sd0(cmd) +mpp32 32 gpio, tdm(int3), sd0(d0) mpp33 33 gpio, tdm(int4), sd0(d1), mem(bat) mpp34 34 gpio, tdm(int5), sd0(d2), sata0(prsnt) mpp35 35 gpio, tdm(int6), sd0(d3), sata1(prsnt)
@@ -58,14 +58,11 @@ mpp36 36 gpio, spi(mosi) mpp37 37 gpio, spi(miso) mpp38 38 gpio, spi(sck) mpp39 39 gpio, spi(cs0) -mpp40 40 gpio, spi(cs1), uart2(cts), lcd(vga-hsync), vdd(cpu1-pd), - pcie(clkreq0) +mpp40 40 gpio, spi(cs1), uart2(cts), lcd(vga-hsync), pcie(clkreq0) mpp41 41 gpio, spi(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt), pcie(clkreq1) -mpp42 42 gpio, uart2(rxd), uart0(cts), tdm(int7), tdm-1(timer), - vdd(cpu0-pd) -mpp43 43 gpio, uart2(txd), uart0(rts), spi(cs3), pcie(rstout), - vdd(cpu2-3-pd){1} +mpp42 42 gpio, uart2(rxd), uart0(cts), tdm(int7), tdm-1(timer) +mpp43 43 gpio, uart2(txd), uart0(rts), spi(cs3), pcie(rstout) mpp44 44 gpio, uart2(cts), uart3(rxd), spi(cs4), pcie(clkreq2), mem(bat) mpp45 45 gpio, uart2(rts), uart3(txd), spi(cs5), sata1(prsnt)
@@ -84,9 +81,9 @@ mpp51 51 gpio, dev(ad16) mpp52 52 gpio, dev(ad17) mpp53 53 gpio, dev(ad18) mpp54 54 gpio, dev(ad19) -mpp55 55 gpio, dev(ad20), vdd(cpu0-pd) -mpp56 56 gpio, dev(ad21), vdd(cpu1-pd) -mpp57 57 gpio, dev(ad22), vdd(cpu2-3-pd){1} +mpp55 55 gpio, dev(ad20) +mpp56 56 gpio, dev(ad21) +mpp57 57 gpio, dev(ad22) mpp58 58 gpio, dev(ad23) mpp59 59 gpio, dev(ad24) mpp60 60 gpio, dev(ad25)
@@ -96,6 +93,3 @@ mpp63 63 gpio, dev(ad28) mpp64 64 gpio, dev(ad29) mpp65 65 gpio, dev(ad30) mpp66 66 gpio, dev(ad31) - -Notes: -* {1} vdd(cpu2-3-pd) only available on mv78460.
drivers/pinctrl/mvebu/pinctrl-armada-xp.c +10 -23
@@ -14,10 +14,7 @@* available: mv78230, mv78260 and mv78460. From a pin muxing * perspective, the mv78230 has 49 MPP pins. The mv78260 and mv78460 * both have 67 MPP pins (more GPIOs and address lines for the memory -* bus mainly). The only difference between the mv78260 and the -* mv78460 in terms of pin muxing is the addition of two functions on -* pins 43 and 56 to access the VDD of the CPU2 and 3 (mv78260 has two -* cores, mv78460 has four cores). +* bus mainly). */ #include <linux/err.h>
@@ -182,8 +179,7 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = {MPP_MODE (26 ,MPP_VAR_FUNCTION (0x0 ,"gpio" ,NULL ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x3 ,"tdm" ,"fsync" ,V_MV78230_PLUS ), -MPP_VAR_FUNCTION (0x4 ,"lcd" ,"clk" ,V_MV78230_PLUS ), -MPP_VAR_FUNCTION (0x5 ,"vdd" ,"cpu1-pd" ,V_MV78230_PLUS )), +MPP_VAR_FUNCTION (0x4 ,"lcd" ,"clk" ,V_MV78230_PLUS )), MPP_MODE(27, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "ptp", "trig", V_MV78230_PLUS),
@@ -198,8 +194,7 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "ptp", "clk", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x3, "tdm", "int0", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x4, "lcd", "ref-clk", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x5, "vdd", "cpu0-pd", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x4, "lcd", "ref-clk", V_MV78230_PLUS)), MPP_MODE(30, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "sd0", "clk", V_MV78230_PLUS),
@@ -207,13 +202,11 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = {MPP_MODE (31 ,MPP_VAR_FUNCTION (0x0 ,"gpio" ,NULL ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x1 ,"sd0" ,"cmd" ,V_MV78230_PLUS ), -MPP_VAR_FUNCTION (0x3 ,"tdm" ,"int2" ,V_MV78230_PLUS ), -MPP_VAR_FUNCTION (0x5 ,"vdd" ,"cpu0-pd" ,V_MV78230_PLUS )), +MPP_VAR_FUNCTION (0x3 ,"tdm" ,"int2" ,V_MV78230_PLUS )),MPP_MODE (32 ,MPP_VAR_FUNCTION (0x0 ,"gpio" ,NULL ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x1 ,"sd0" ,"d0" ,V_MV78230_PLUS ), -MPP_VAR_FUNCTION (0x3 ,"tdm" ,"int3" ,V_MV78230_PLUS ), -MPP_VAR_FUNCTION (0x5 ,"vdd" ,"cpu1-pd" ,V_MV78230_PLUS )), +MPP_VAR_FUNCTION (0x3 ,"tdm" ,"int3" ,V_MV78230_PLUS )), MPP_MODE(33, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "sd0", "d1", V_MV78230_PLUS),
@@ -245,7 +238,6 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = {MPP_VAR_FUNCTION (0x0 ,"gpio" ,NULL ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x1 ,"spi" ,"cs1" ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x2 ,"uart2" ,"cts" ,V_MV78230_PLUS ), -MPP_VAR_FUNCTION (0x3 ,"vdd" ,"cpu1-pd" ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x4 ,"lcd" ,"vga-hsync" ,V_MV78230_PLUS ), MPP_VAR_FUNCTION(0x5, "pcie", "clkreq0", V_MV78230_PLUS)), MPP_MODE(41,
@@ -260,15 +252,13 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x1, "uart2", "rxd", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart0", "cts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x3, "tdm", "int7", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x4, "tdm-1", "timer", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x5, "vdd", "cpu0-pd", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x4, "tdm-1", "timer", V_MV78230_PLUS)),MPP_MODE (43 ,MPP_VAR_FUNCTION (0x0 ,"gpio" ,NULL ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x1 ,"uart2" ,"txd" ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x2 ,"uart0" ,"rts" ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x3 ,"spi" ,"cs3" ,V_MV78230_PLUS ), -MPP_VAR_FUNCTION (0x4 ,"pcie" ,"rstout" ,V_MV78230_PLUS ), -MPP_VAR_FUNCTION (0x5 ,"vdd" ,"cpu2-3-pd" ,V_MV78460 )), +MPP_VAR_FUNCTION (0x4 ,"pcie" ,"rstout" ,V_MV78230_PLUS )), MPP_MODE(44, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "uart2", "cts", V_MV78230_PLUS),
@@ -319,16 +309,13 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x1, "dev", "ad19", V_MV78260_PLUS)),MPP_MODE (55 ,MPP_VAR_FUNCTION (0x0 ,"gpio" ,NULL ,V_MV78260_PLUS ), -MPP_VAR_FUNCTION (0x1 ,"dev" ,"ad20" ,V_MV78260_PLUS ), -MPP_VAR_FUNCTION (0x2 ,"vdd" ,"cpu0-pd" ,V_MV78260_PLUS )), +MPP_VAR_FUNCTION (0x1 ,"dev" ,"ad20" ,V_MV78260_PLUS )),MPP_MODE (56 ,MPP_VAR_FUNCTION (0x0 ,"gpio" ,NULL ,V_MV78260_PLUS ), -MPP_VAR_FUNCTION (0x1 ,"dev" ,"ad21" ,V_MV78260_PLUS ), -MPP_VAR_FUNCTION (0x2 ,"vdd" ,"cpu1-pd" ,V_MV78260_PLUS )), +MPP_VAR_FUNCTION (0x1 ,"dev" ,"ad21" ,V_MV78260_PLUS )),MPP_MODE (57 ,MPP_VAR_FUNCTION (0x0 ,"gpio" ,NULL ,V_MV78260_PLUS ), -MPP_VAR_FUNCTION (0x1 ,"dev" ,"ad22" ,V_MV78260_PLUS ), -MPP_VAR_FUNCTION (0x2 ,"vdd" ,"cpu2-3-pd" ,V_MV78460 )), +MPP_VAR_FUNCTION (0x1 ,"dev" ,"ad22" ,V_MV78260_PLUS )),MPP_MODE (58 ,MPP_VAR_FUNCTION (0x0 ,"gpio" ,NULL ,V_MV78260_PLUS ), MPP_VAR_FUNCTION(0x1, "dev", "ad23", V_MV78260_PLUS)),
Signature · 1 line
2.1.0
PATCH 5/34 pinctrl: mvebu: armada-xp: remove non-existing VDD cpu_pd functions
Quoted 8 lines · Thomas Petazzoni
The latest version of the Armada XP datasheet no longer documents the VDD
cpu_pdfunctions, which might indicate they are not working and/or not supported. This commit ensures the pinctrl driver matches the datasheet.Signed-off-by Thomas Petazzoni <[email protected]>Cc <[email protected]> # v3.7+Fixes 463e270f766a ("pinctrl: mvebu: add pinctrl driver for Armada XP")
Patch applied.
Yours,
Linus Walleij
PATCH 6/34 pinctrl: mvebu: armada-xp: fix functions of MPP48
In reply to Thomas PetazzoniThere was a mistake in the definition of the functions for MPP48 on Marvell Armada XP. The second function is dev(clkout), and not tclk.
--- Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt | 2 +- drivers/pinctrl/mvebu/pinctrl-armada-xp.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt +1 -1
@@ -69,7 +69,7 @@ mpp45 45 gpio, uart2(rts), uart3(txd), spi(cs5), sata1(prsnt) mpp46 46 gpio, uart3(rts), uart1(rts), spi(cs6), sata0(prsnt) mpp47 47 gpio, uart3(cts), uart1(cts), spi(cs7), pcie(clkreq3), ref(clkout) -mpp48 48 gpio, tclk, dev(burst/last) +mpp48 48 gpio, dev(clkout), dev(burst/last) * Marvell Armada XP (mv78260 and mv78460 only)
drivers/pinctrl/mvebu/pinctrl-armada-xp.c +1 -1
@@ -287,7 +287,7 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x5, "pcie", "clkreq3", V_MV78230_PLUS)),MPP_MODE (48 ,MPP_VAR_FUNCTION (0x0 ,"gpio" ,NULL ,V_MV78230_PLUS ), -MPP_VAR_FUNCTION (0x1 ,"tclk" ,NULL ,V_MV78230_PLUS ), +MPP_VAR_FUNCTION (0x1 ,"dev" ,"clkout" ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x2 ,"dev" ,"burst/last" ,V_MV78230_PLUS )), MPP_MODE(49, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
Signature · 1 line
2.1.0
PATCH 7/34 pinctrl: mvebu: armada-375: remove incorrect space in pin description
In reply to Thomas PetazzoniThere was an incorrect space in the definition of the function of one pin in the Armada 375 pinctrl driver, which this commit fixes.
--- drivers/pinctrl/mvebu/pinctrl-armada-375.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/pinctrl/mvebu/pinctrl-armada-375.c +1 -1
@@ -92,7 +92,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_FUNCTION(0x5, "nand", "io1")),MPP_MODE (8 ,MPP_FUNCTION (0x0 ,"gpio" ,NULL ), -MPP_FUNCTION (0x1 ,"dev " ,"bootcs" ), +MPP_FUNCTION (0x1 ,"dev" ,"bootcs" ),MPP_FUNCTION (0x2 ,"spi0" ,"cs0" ),MPP_FUNCTION (0x3 ,"spi1" ,"cs0" ), MPP_FUNCTION(0x5, "nand", "ce")),
Signature · 1 line
2.1.0
PATCH 8/34 pinctrl: mvebu: armada-38x: fix incorrect total number of GPIOs
In reply to Thomas PetazzoniThe pinctrl_gpio_range[] array described a first bank of 32 GPIOs and a second one of 27 GPIOs. However, since there is a total of 60 MPP pins that can be muxed as GPIOs, the second bank really has 28 GPIOs.
--- drivers/pinctrl/mvebu/pinctrl-armada-38x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/pinctrl/mvebu/pinctrl-armada-38x.c +1 -1
@@ -402,7 +402,7 @@ static struct mvebu_mpp_ctrl armada_38x_mpp_controls[] = {static struct pinctrl_gpio_range armada_38x_mpp_gpio_ranges[] = {MPP_GPIO_RANGE (0 ,0 ,0 ,32 ), -MPP_GPIO_RANGE (1 ,32 ,32 ,27 ), +MPP_GPIO_RANGE (1 ,32 ,32 ,28 ), };static int armada_38x_pinctrl_probe (struct platform_device *pdev)
Signature · 1 line
2.1.0
PATCH 8/34 pinctrl: mvebu: armada-38x: fix incorrect total number of GPIOs
Quoted 7 lines · Thomas Petazzoni
The pinctrl_gpio_range[] array described a first bank of 32 GPIOs and a second one of 27 GPIOs. However, since there is a total of 60 MPP pins that can be muxed as GPIOs, the second bank really has 28 GPIOs.
Signed-off-by Thomas Petazzoni <[email protected]>Cc <[email protected]> # v3.15+Fixes ca6d9a084b56f ("pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385")
Patch applied.
Yours,
Linus Walleij
PATCH 9/34 pinctrl: mvebu: armada-39x: fix incorrect total number of GPIOs
In reply to Thomas PetazzoniThe pinctrl_gpio_range[] array described a first bank of 32 GPIOs and a second one of 27 GPIOs. However, since there is a total of 60 MPP pins that can be muxed as GPIOs, the second bank really has 28 GPIOs.
--- drivers/pinctrl/mvebu/pinctrl-armada-39x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/pinctrl/mvebu/pinctrl-armada-39x.c +1 -1
@@ -380,7 +380,7 @@ static struct mvebu_mpp_ctrl armada_39x_mpp_controls[] = {static struct pinctrl_gpio_range armada_39x_mpp_gpio_ranges[] = {MPP_GPIO_RANGE (0 ,0 ,0 ,32 ), -MPP_GPIO_RANGE (1 ,32 ,32 ,27 ), +MPP_GPIO_RANGE (1 ,32 ,32 ,28 ), };static int armada_39x_pinctrl_probe (struct platform_device *pdev)
Signature · 1 line
2.1.0
PATCH 10/34 pinctrl: mvebu: armada-{375, 38x, 39x}: normalize naming of PTP subnames
In reply to Thomas PetazzoniThe subnames are purely informative, but it's nicer when they match accross SoCs. This commit adjusts the Armada 375, Armada 38x and Armada 39x MPP definitions so that the subnames of the PTP pins match the ones used on Armada XP and Kirkwood.
--- .../bindings/pinctrl/marvell,armada-375-pinctrl.txt | 10 +++++----- .../bindings/pinctrl/marvell,armada-38x-pinctrl.txt | 8 ++++---- .../bindings/pinctrl/marvell,armada-39x-pinctrl.txt | 2 +- drivers/pinctrl/mvebu/pinctrl-armada-375.c | 16 ++++++++-------- drivers/pinctrl/mvebu/pinctrl-armada-38x.c | 8 ++++---- drivers/pinctrl/mvebu/pinctrl-armada-39x.c | 2 +- 6 files changed, 23 insertions(+), 23 deletions(-)
Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt +5 -5
@@ -15,8 +15,8 @@ name pins functions ================================================================================ mpp0 0 gpio, dev(ad2), spi0(cs1), spi1(cs1) mpp1 1 gpio, dev(ad3), spi0(mosi), spi1(mosi) -mpp2 2 gpio, dev(ad4), ptp(eventreq), led(c0), audio(sdi) -mpp3 3 gpio, dev(ad5), ptp(triggen), led(p3), audio(mclk) +mpp2 2 gpio, dev(ad4), ptp(evreq), led(c0), audio(sdi) +mpp3 3 gpio, dev(ad5), ptp(trig), led(p3), audio(mclk) mpp4 4 gpio, dev(ad6), spi0(miso), spi1(miso) mpp5 5 gpio, dev(ad7), spi0(cs2), spi1(cs2) mpp6 6 gpio, dev(ad0), led(p1), audio(rclk)
@@ -45,7 +45,7 @@ mpp28 28 gpio, led(p3), ge1(txctl), sd(clk) mpp29 29 gpio, pcie1(clkreq), ge1(rxclk), sd(d3) mpp30 30 gpio, ge1(txd0), spi1(cs0) mpp31 31 gpio, ge1(txd1), spi1(mosi) -mpp32 32 gpio, ge1(txd2), spi1(sck), ptp(triggen) +mpp32 32 gpio, ge1(txd2), spi1(sck), ptp(trig) mpp33 33 gpio, ge1(txd3), spi1(miso) mpp34 34 gpio, ge1(txclkout), spi1(sck) mpp35 35 gpio, ge1(rxctl), spi1(cs1), spi0(cs2)
@@ -76,7 +76,7 @@ mpp59 59 gpio, led(c1) mpp60 60 gpio, uart1(txd), led(c2) mpp61 61 gpio, i2c1(sda), uart1(rxd), spi1(cs2), led(p0) mpp62 62 gpio, i2c1(sck), led(p1) -mpp63 63 gpio, ptp(triggen), led(p2) +mpp63 63 gpio, ptp(trig), led(p2) mpp64 64 gpio, dram(vttctrl), led(p3) mpp65 65 gpio, sata1(prsnt) -mpp66 66 gpio, ptp(eventreq), spi1(cs3) +mpp66 66 gpio, ptp(evreq), spi1(cs3)
Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt +4 -4
@@ -33,8 +33,8 @@ mpp14 14 gpio, ge0(rxd2), ptp(clk), m(vtt_ctrl), spi0(cs3), dev(we mpp15 15 gpio, ge0(rxd3), ge(mdc slave), pcie0(rstout), spi0(mosi) mpp16 16 gpio, ge0(rxctl), ge(mdio slave), m(decc_err), spi0(miso), pcie0(clkreq), pcie1(clkreq) [1] mpp17 17 gpio, ge0(rxclk), ptp(clk), ua1(rxd), spi0(sck), sata1(prsnt) -mpp18 18 gpio, ge0(rxerr), ptp(trig_gen), ua1(txd), spi0(cs0) -mpp19 19 gpio, ge0(col), ptp(event_req), ge0(txerr), sata1(prsnt), ua0(cts) +mpp18 18 gpio, ge0(rxerr), ptp(trig), ua1(txd), spi0(cs0) +mpp19 19 gpio, ge0(col), ptp(evreq), ge0(txerr), sata1(prsnt), ua0(cts) mpp20 20 gpio, ge0(txclk), ptp(clk), sata0(prsnt), ua0(rts) mpp21 21 gpio, spi0(cs1), ge1(rxd0), sata0(prsnt), sd0(cmd), dev(bootcs) mpp22 22 gpio, spi0(mosi), dev(ad0)
@@ -51,9 +51,9 @@ mpp32 32 gpio, ge1(txctl), dev(wen0) mpp33 33 gpio, m(decc_err), dev(ad3) mpp34 34 gpio, dev(ad1) mpp35 35 gpio, ref(clk_out1), dev(a1) -mpp36 36 gpio, ptp(trig_gen), dev(a0) +mpp36 36 gpio, ptp(trig), dev(a0) mpp37 37 gpio, ptp(clk), ge1(rxclk), sd0(d3), dev(ad8) -mpp38 38 gpio, ptp(event_req), ge1(rxd1), ref(clk_out0), sd0(d0), dev(ad4) +mpp38 38 gpio, ptp(evreq), ge1(rxd1), ref(clk_out0), sd0(d0), dev(ad4) mpp39 39 gpio, i2c1(sck), ge1(rxd2), ua0(cts), sd0(d1), dev(a2) mpp40 40 gpio, i2c1(sda), ge1(rxd3), ua0(rts), sd0(d2), dev(ad6) mpp41 41 gpio, ua1(rxd), ge1(rxctl), ua0(cts), spi1(cs3), dev(burst/last)
Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt +1 -1
@@ -24,7 +24,7 @@ mpp6 6 gpio, dev(cs3), xsmi(mdio) mpp7 7 gpio, dev(ad9), xsmi(mdc) mpp8 8 gpio, dev(ad10), ptp(trig) mpp9 9 gpio, dev(ad11), ptp(clk) -mpp10 10 gpio, dev(ad12), ptp(event) +mpp10 10 gpio, dev(ad12), ptp(evreq) mpp11 11 gpio, dev(ad13), led(clk) mpp12 12 gpio, pcie0(rstout), dev(ad14), led(stb) mpp13 13 gpio, dev(ad15), led(data)
drivers/pinctrl/mvebu/pinctrl-armada-375.c +8 -8
@@ -51,7 +51,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_MODE(2, MPP_FUNCTION(0x0, "gpio", NULL), MPP_FUNCTION(0x1, "dev", "ad4"), - MPP_FUNCTION(0x2, "ptp", "eventreq"), + MPP_FUNCTION(0x2, "ptp", "evreq"), MPP_FUNCTION(0x3, "led", "c0"), MPP_FUNCTION(0x4, "audio", "sdi"), MPP_FUNCTION(0x5, "nand", "io4"),
@@ -59,7 +59,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_MODE(3, MPP_FUNCTION(0x0, "gpio", NULL), MPP_FUNCTION(0x1, "dev", "ad5"), - MPP_FUNCTION(0x2, "ptp", "triggen"), + MPP_FUNCTION(0x2, "ptp", "trig"), MPP_FUNCTION(0x3, "led", "p3"), MPP_FUNCTION(0x4, "audio", "mclk"), MPP_FUNCTION(0x5, "nand", "io5"),
@@ -207,7 +207,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_FUNCTION(0x2, "ge1", "txd0"), MPP_FUNCTION(0x3, "spi1", "cs0"), MPP_FUNCTION(0x5, "led", "p3"), - MPP_FUNCTION(0x6, "ptp", "eventreq")), + MPP_FUNCTION(0x6, "ptp", "evreq")), MPP_MODE(31, MPP_FUNCTION(0x0, "gpio", NULL), MPP_FUNCTION(0x2, "ge1", "txd1"),
@@ -217,7 +217,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_FUNCTION(0x0, "gpio", NULL), MPP_FUNCTION(0x2, "ge1", "txd2"), MPP_FUNCTION(0x3, "spi1", "sck"), - MPP_FUNCTION(0x4, "ptp", "triggen"), + MPP_FUNCTION(0x4, "ptp", "trig"), MPP_FUNCTION(0x5, "led", "c0")), MPP_MODE(33, MPP_FUNCTION(0x0, "gpio", NULL),
@@ -290,7 +290,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_FUNCTION(0x1, "led", "p1"), MPP_FUNCTION(0x2, "ge0", "txd1"), MPP_FUNCTION(0x3, "ge1", "txd1"), - MPP_FUNCTION(0x5, "ptp", "triggen"), + MPP_FUNCTION(0x5, "ptp", "trig"), MPP_FUNCTION(0x6, "dev", "ale0")), MPP_MODE(48, MPP_FUNCTION(0x0, "gpio", NULL),
@@ -309,7 +309,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_FUNCTION(0x1, "led", "c0"), MPP_FUNCTION(0x2, "ge0", "rxd0"), MPP_FUNCTION(0x3, "ge1", "rxd0"), - MPP_FUNCTION(0x5, "ptp", "eventreq"), + MPP_FUNCTION(0x5, "ptp", "evreq"), MPP_FUNCTION(0x6, "dev", "ad12")), MPP_MODE(51, MPP_FUNCTION(0x0, "gpio", NULL),
@@ -377,7 +377,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_FUNCTION(0x6, "dev", "ad15")),MPP_MODE (63 ,MPP_FUNCTION (0x0 ,"gpio" ,NULL ), -MPP_FUNCTION (0x2 ,"ptp" ,"triggen" ), +MPP_FUNCTION (0x2 ,"ptp" ,"trig" ),MPP_FUNCTION (0x4 ,"led" ,"p2" ),MPP_FUNCTION (0x6 ,"dev" ,"burst" )), MPP_MODE(64,
@@ -389,7 +389,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_FUNCTION(0x1, "sata1", "prsnt")),MPP_MODE (66 ,MPP_FUNCTION (0x0 ,"gpio" ,NULL ), -MPP_FUNCTION (0x2 ,"ptp" ,"eventreq" ), +MPP_FUNCTION (0x2 ,"ptp" ,"evreq" ),MPP_FUNCTION (0x4 ,"spi1" ,"cs3" ),MPP_FUNCTION (0x5 ,"pcie0" ,"rstoutn" ), MPP_FUNCTION(0x6, "dev", "cs3")),
drivers/pinctrl/mvebu/pinctrl-armada-38x.c +4 -4
@@ -137,13 +137,13 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = {MPP_MODE (18 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6810_PLUS ),MPP_VAR_FUNCTION (1 ,"ge0" ,"rxerr" ,V_88F6810_PLUS ), -MPP_VAR_FUNCTION (2 ,"ptp" ,"trig_gen" ,V_88F6810_PLUS ), +MPP_VAR_FUNCTION (2 ,"ptp" ,"trig" ,V_88F6810_PLUS ),MPP_VAR_FUNCTION (3 ,"ua1" ,"txd" ,V_88F6810_PLUS ),MPP_VAR_FUNCTION (4 ,"spi0" ,"cs0" ,V_88F6810_PLUS )), MPP_MODE(19, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "ge0", "col", V_88F6810_PLUS), - MPP_VAR_FUNCTION(2, "ptp", "event_req", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "ptp", "evreq", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "ge0", "txerr", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "sata1", "prsnt", V_88F6810_PLUS), MPP_VAR_FUNCTION(5, "ua0", "cts", V_88F6810_PLUS),
@@ -231,7 +231,7 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(5, "dev", "a1", V_88F6810_PLUS)),MPP_MODE (36 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6810_PLUS ), -MPP_VAR_FUNCTION (1 ,"ptp" ,"trig_gen" ,V_88F6810_PLUS ), +MPP_VAR_FUNCTION (1 ,"ptp" ,"trig" ,V_88F6810_PLUS ),MPP_VAR_FUNCTION (5 ,"dev" ,"a0" ,V_88F6810_PLUS )), MPP_MODE(37, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
@@ -241,7 +241,7 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(5, "dev", "ad8", V_88F6810_PLUS)), MPP_MODE(38, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), - MPP_VAR_FUNCTION(1, "ptp", "event_req", V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "ptp", "evreq", V_88F6810_PLUS), MPP_VAR_FUNCTION(2, "ge1", "rxd1", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "ref", "clk_out0", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "sd0", "d0", V_88F6810_PLUS),
drivers/pinctrl/mvebu/pinctrl-armada-39x.c +1 -1
@@ -82,7 +82,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = {MPP_MODE (10 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (5 ,"dev" ,"ad12" ,V_88F6920_PLUS ), -MPP_VAR_FUNCTION (7 ,"ptp" ,"event" ,V_88F6920_PLUS )), +MPP_VAR_FUNCTION (7 ,"ptp" ,"evreq" ,V_88F6920_PLUS )), MPP_MODE(11, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(5, "dev", "ad13", V_88F6920_PLUS),
Signature · 1 line
2.1.0
PATCH 10/34 pinctrl: mvebu: armada-{375,38x,39x}: normalize naming of PTP subnames
Quoted 6 lines · Thomas Petazzoni
The subnames are purely informative, but it's nicer when they match accross SoCs. This commit adjusts the Armada 375, Armada 38x and Armada 39x MPP definitions so that the subnames of the PTP pins match the ones used on Armada XP and Kirkwood.
Signed-off-by Thomas Petazzoni <[email protected]>
Patch applied.
Yours,
Linus Walleij
PATCH 11/34 pinctrl: mvebu: armada-{38x, 39x, xp}: normalize naming of DRAM functions
In reply to Thomas PetazzoniThis commit makes the dram functions naming (both the name and subname) consistent accross SoC, by using:
dram(vttctrl)
dram(deccerr)
in all Marvell SoCs.
Due to the change to the name, it changes the DT binding, but these functions are not used by any in-tree Device Tree file, and are very unlikely to be used by anyone.
--- .../bindings/pinctrl/marvell,armada-38x-pinctrl.txt | 14 +++++++------- .../bindings/pinctrl/marvell,armada-39x-pinctrl.txt | 14 +++++++------- .../bindings/pinctrl/marvell,armada-xp-pinctrl.txt | 6 +++--- drivers/pinctrl/mvebu/pinctrl-armada-38x.c | 16 ++++++++-------- drivers/pinctrl/mvebu/pinctrl-armada-39x.c | 16 ++++++++-------- drivers/pinctrl/mvebu/pinctrl-armada-xp.c | 6 +++--- 6 files changed, 36 insertions(+), 36 deletions(-)
Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt +7 -7
@@ -29,9 +29,9 @@ mpp10 10 gpio, ge0(txd3), dev(ad12) mpp11 11 gpio, ge0(txctl), dev(ad13) mpp12 12 gpio, ge0(rxd0), pcie0(rstout), spi0(cs1), dev(ad14), pcie3(clkreq) mpp13 13 gpio, ge0(rxd1), pcie0(clkreq), pcie1(clkreq) [1], spi0(cs2), dev(ad15), pcie2(clkreq) -mpp14 14 gpio, ge0(rxd2), ptp(clk), m(vtt_ctrl), spi0(cs3), dev(wen1), pcie3(clkreq) +mpp14 14 gpio, ge0(rxd2), ptp(clk), dram(vttctrl), spi0(cs3), dev(wen1), pcie3(clkreq) mpp15 15 gpio, ge0(rxd3), ge(mdc slave), pcie0(rstout), spi0(mosi) -mpp16 16 gpio, ge0(rxctl), ge(mdio slave), m(decc_err), spi0(miso), pcie0(clkreq), pcie1(clkreq) [1] +mpp16 16 gpio, ge0(rxctl), ge(mdio slave), dram(deccerr), spi0(miso), pcie0(clkreq), pcie1(clkreq) [1] mpp17 17 gpio, ge0(rxclk), ptp(clk), ua1(rxd), spi0(sck), sata1(prsnt) mpp18 18 gpio, ge0(rxerr), ptp(trig), ua1(txd), spi0(cs0) mpp19 19 gpio, ge0(col), ptp(evreq), ge0(txerr), sata1(prsnt), ua0(cts)
@@ -48,7 +48,7 @@ mpp29 29 gpio, ge1(txd1), dev(ale0) mpp30 30 gpio, ge1(txd2), dev(oen) mpp31 31 gpio, ge1(txd3), dev(ale1) mpp32 32 gpio, ge1(txctl), dev(wen0) -mpp33 33 gpio, m(decc_err), dev(ad3) +mpp33 33 gpio, dram(deccerr), dev(ad3) mpp34 34 gpio, dev(ad1) mpp35 35 gpio, ref(clk_out1), dev(a1) mpp36 36 gpio, ptp(trig), dev(a0)
@@ -58,20 +58,20 @@ mpp39 39 gpio, i2c1(sck), ge1(rxd2), ua0(cts), sd0(d1), dev(a2) mpp40 40 gpio, i2c1(sda), ge1(rxd3), ua0(rts), sd0(d2), dev(ad6) mpp41 41 gpio, ua1(rxd), ge1(rxctl), ua0(cts), spi1(cs3), dev(burst/last) mpp42 42 gpio, ua1(txd), ua0(rts), dev(ad7) -mpp43 43 gpio, pcie0(clkreq), m(vtt_ctrl), m(decc_err), spi1(cs2), dev(clkout) +mpp43 43 gpio, pcie0(clkreq), dram(vttctrl), dram(deccerr), spi1(cs2), dev(clkout) mpp44 44 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3(prsnt) [3] mpp45 45 gpio, ref(clk_out0), pcie0(rstout) mpp46 46 gpio, ref(clk_out1), pcie0(rstout) mpp47 47 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3(prsnt) [2] -mpp48 48 gpio, sata0(prsnt), m(vtt_ctrl), tdm2c(pclk), audio(mclk), sd0(d4), pcie0(clkreq) +mpp48 48 gpio, sata0(prsnt), dram(vttctrl), tdm2c(pclk), audio(mclk), sd0(d4), pcie0(clkreq) mpp49 49 gpio, sata2(prsnt) [2], sata3(prsnt) [2], tdm2c(fsync), audio(lrclk), sd0(d5), pcie1(clkreq) mpp50 50 gpio, pcie0(rstout), tdm2c(drx), audio(extclk), sd0(cmd) -mpp51 51 gpio, tdm2c(dtx), audio(sdo), m(decc_err) +mpp51 51 gpio, tdm2c(dtx), audio(sdo), dram(deccerr) mpp52 52 gpio, pcie0(rstout), tdm2c(intn), audio(sdi), sd0(d6) mpp53 53 gpio, sata1(prsnt), sata0(prsnt), tdm2c(rstn), audio(bclk), sd0(d7) mpp54 54 gpio, sata0(prsnt), sata1(prsnt), pcie0(rstout), ge0(txerr), sd0(d3) mpp55 55 gpio, ua1(cts), ge(mdio), pcie1(clkreq) [1], spi1(cs1), sd0(d0) -mpp56 56 gpio, ua1(rts), ge(mdc), m(decc_err), spi1(mosi) +mpp56 56 gpio, ua1(rts), ge(mdc), dram(deccerr), spi1(mosi) mpp57 57 gpio, spi1(sck), sd0(clk) mpp58 58 gpio, pcie1(clkreq) [1], i2c1(sck), pcie2(clkreq), spi1(miso), sd0(d1) mpp59 59 gpio, pcie0(rstout), i2c1(sda), spi1(cs0), sd0(d2)
Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt +7 -7
@@ -28,9 +28,9 @@ mpp10 10 gpio, dev(ad12), ptp(evreq) mpp11 11 gpio, dev(ad13), led(clk) mpp12 12 gpio, pcie0(rstout), dev(ad14), led(stb) mpp13 13 gpio, dev(ad15), led(data) -mpp14 14 gpio, m(vtt), dev(wen1), ua1(txd) +mpp14 14 gpio, dram(vttctrl), dev(wen1), ua1(txd) mpp15 15 gpio, pcie0(rstout), spi0(mosi), i2c1(sck) -mpp16 16 gpio, m(decc), spi0(miso), i2c1(sda) +mpp16 16 gpio, dram(deccerr), spi0(miso), i2c1(sda) mpp17 17 gpio, ua1(rxd), spi0(sck), smi(mdio) mpp18 18 gpio, ua1(txd), spi0(cs0), i2c2(sck) mpp19 19 gpio, sata1(present) [1], ua0(cts), ua1(rxd), i2c2(sda)
@@ -47,7 +47,7 @@ mpp29 29 gpio, dev(ale0), ge(txd1) mpp30 30 gpio, dev(oen), ge(txd2) mpp31 31 gpio, dev(ale1), ge(txd3) mpp32 32 gpio, dev(wen0), ge(txctl) -mpp33 33 gpio, m(decc), dev(ad3) +mpp33 33 gpio, dram(deccerr), dev(ad3) mpp34 34 gpio, dev(ad1) mpp35 35 gpio, ref(clk), dev(a1) mpp36 36 gpio, dev(a0)
@@ -57,20 +57,20 @@ mpp39 39 gpio, i2c1(sck), ua0(cts), sd(d1), dev(a2), ge(rxd2) mpp40 40 gpio, i2c1(sda), ua0(rts), sd(d2), dev(ad6), ge(rxd3) mpp41 41 gpio, ua1(rxd), ua0(cts), spi1(cs3), dev(burstn), nd(rbn0), ge(rxctl) mpp42 42 gpio, ua1(txd), ua0(rts), dev(ad7) -mpp43 43 gpio, pcie0(clkreq), m(vtt), m(decc), spi1(cs2), dev(clkout), nd(rbn1) +mpp43 43 gpio, pcie0(clkreq), dram(vttctrl), dram(deccerr), spi1(cs2), dev(clkout), nd(rbn1) mpp44 44 gpio, sata0(present) [1], sata1(present) [1], led(clk) mpp45 45 gpio, ref(clk), pcie0(rstout), ua1(rxd) mpp46 46 gpio, ref(clk), pcie0(rstout), ua1(txd), led(stb) mpp47 47 gpio, sata0(present) [1], sata1(present) [1], led(data) -mpp48 48 gpio, sata0(present) [1], m(vtt), tdm(pclk) [1], audio(mclk) [1], sd(d4), pcie0(clkreq), ua1(txd) +mpp48 48 gpio, sata0(present) [1], dram(vttctrl), tdm(pclk) [1], audio(mclk) [1], sd(d4), pcie0(clkreq), ua1(txd) mpp49 49 gpio, tdm(fsync) [1], audio(lrclk) [1], sd(d5), ua2(rxd) mpp50 50 gpio, pcie0(rstout), tdm(drx) [1], audio(extclk) [1], sd(cmd), ua2(rxd) -mpp51 51 gpio, tdm(dtx) [1], audio(sdo) [1], m(decc), ua2(txd) +mpp51 51 gpio, tdm(dtx) [1], audio(sdo) [1], dram(deccerr), ua2(txd) mpp52 52 gpio, pcie0(rstout), tdm(intn) [1], audio(sdi) [1], sd(d6), i2c3(sck) mpp53 53 gpio, sata1(present) [1], sata0(present) [1], tdm(rstn) [1], audio(bclk) [1], sd(d7), i2c3(sda) mpp54 54 gpio, sata0(present) [1], sata1(present) [1], pcie0(rstout), sd(d3), ua3(txd) mpp55 55 gpio, ua1(cts), spi1(cs1), sd(d0), ua1(rxd), ua3(rxd) -mpp56 56 gpio, ua1(rts), m(decc), spi1(mosi), ua1(txd) +mpp56 56 gpio, ua1(rts), dram(deccerr), spi1(mosi), ua1(txd) mpp57 57 gpio, spi1(sck), sd(clk), ua1(txd) mpp58 58 gpio, i2c1(sck), pcie2(clkreq), spi1(miso), sd(d1), ua1(rxd) mpp59 59 gpio, pcie0(rstout), i2c1(sda), spi1(cs0), sd(d2)
Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt +3 -3
@@ -39,7 +39,7 @@ mpp17 17 gpio, ge0(col), ge1(txctl), lcd(d17) mpp18 18 gpio, ge0(rxerr), ge1(rxd0), lcd(d18), ptp(trig) mpp19 19 gpio, ge0(crs), ge1(rxd1), lcd(d19), ptp(evreq) mpp20 20 gpio, ge0(rxd4), ge1(rxd2), lcd(d20), ptp(clk) -mpp21 21 gpio, ge0(rxd5), ge1(rxd3), lcd(d21), mem(bat) +mpp21 21 gpio, ge0(rxd5), ge1(rxd3), lcd(d21), dram(bat) mpp22 22 gpio, ge0(rxd6), ge1(rxctl), lcd(d22), sata0(prsnt) mpp23 23 gpio, ge0(rxd7), ge1(rxclk), lcd(d23), sata1(prsnt) mpp24 24 gpio, lcd(hsync), sata1(prsnt), tdm(rst)
@@ -51,7 +51,7 @@ mpp29 29 gpio, lcd(ref-clk), tdm(int0), ptp(clk) mpp30 30 gpio, tdm(int1), sd0(clk) mpp31 31 gpio, tdm(int2), sd0(cmd) mpp32 32 gpio, tdm(int3), sd0(d0) -mpp33 33 gpio, tdm(int4), sd0(d1), mem(bat) +mpp33 33 gpio, tdm(int4), sd0(d1), dram(bat) mpp34 34 gpio, tdm(int5), sd0(d2), sata0(prsnt) mpp35 35 gpio, tdm(int6), sd0(d3), sata1(prsnt) mpp36 36 gpio, spi(mosi)
@@ -64,7 +64,7 @@ mpp41 41 gpio, spi(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt), mpp42 42 gpio, uart2(rxd), uart0(cts), tdm(int7), tdm-1(timer) mpp43 43 gpio, uart2(txd), uart0(rts), spi(cs3), pcie(rstout) mpp44 44 gpio, uart2(cts), uart3(rxd), spi(cs4), pcie(clkreq2), - mem(bat) + dram(bat) mpp45 45 gpio, uart2(rts), uart3(txd), spi(cs5), sata1(prsnt) mpp46 46 gpio, uart3(rts), uart1(rts), spi(cs6), sata0(prsnt) mpp47 47 gpio, uart3(cts), uart1(cts), spi(cs7), pcie(clkreq3),
drivers/pinctrl/mvebu/pinctrl-armada-38x.c +8 -8
@@ -109,7 +109,7 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = {MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6810_PLUS ),MPP_VAR_FUNCTION (1 ,"ge0" ,"rxd2" ,V_88F6810_PLUS ),MPP_VAR_FUNCTION (2 ,"ptp" ,"clk" ,V_88F6810_PLUS ), -MPP_VAR_FUNCTION (3 ,"m" ,"vtt_ctrl" ,V_88F6810_PLUS ), +MPP_VAR_FUNCTION (3 ,"dram" ,"vttctrl" ,V_88F6810_PLUS ),MPP_VAR_FUNCTION (4 ,"spi0" ,"cs3" ,V_88F6810_PLUS ),MPP_VAR_FUNCTION (5 ,"dev" ,"wen1" ,V_88F6810_PLUS ), MPP_VAR_FUNCTION(6, "pcie3", "clkreq", V_88F6810_PLUS)),
@@ -123,7 +123,7 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = {MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6810_PLUS ),MPP_VAR_FUNCTION (1 ,"ge0" ,"rxctl" ,V_88F6810_PLUS ),MPP_VAR_FUNCTION (2 ,"ge" ,"mdio slave" ,V_88F6810_PLUS ), -MPP_VAR_FUNCTION (3 ,"m" ,"decc_err" ,V_88F6810_PLUS ), +MPP_VAR_FUNCTION (3 ,"dram" ,"deccerr" ,V_88F6810_PLUS ),MPP_VAR_FUNCTION (4 ,"spi0" ,"miso" ,V_88F6810_PLUS ),MPP_VAR_FUNCTION (5 ,"pcie0" ,"clkreq" ,V_88F6810_PLUS ), MPP_VAR_FUNCTION(6, "pcie1", "clkreq", V_88F6820_PLUS)),
@@ -220,7 +220,7 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(5, "dev", "wen0", V_88F6810_PLUS)),MPP_MODE (33 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6810_PLUS ), -MPP_VAR_FUNCTION (1 ,"m" ,"decc_err" ,V_88F6810_PLUS ), +MPP_VAR_FUNCTION (1 ,"dram" ,"deccerr" ,V_88F6810_PLUS ),MPP_VAR_FUNCTION (5 ,"dev" ,"ad3" ,V_88F6810_PLUS )), MPP_MODE(34, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
@@ -275,8 +275,8 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = {MPP_MODE (43 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6810_PLUS ),MPP_VAR_FUNCTION (1 ,"pcie0" ,"clkreq" ,V_88F6810_PLUS ), -MPP_VAR_FUNCTION (2 ,"m" ,"vtt_ctrl" ,V_88F6810_PLUS ), -MPP_VAR_FUNCTION (3 ,"m" ,"decc_err" ,V_88F6810_PLUS ), +MPP_VAR_FUNCTION (2 ,"dram" ,"vttctrl" ,V_88F6810_PLUS ), +MPP_VAR_FUNCTION (3 ,"dram" ,"deccerr" ,V_88F6810_PLUS ),MPP_VAR_FUNCTION (4 ,"spi1" ,"cs2" ,V_88F6810_PLUS ),MPP_VAR_FUNCTION (5 ,"dev" ,"clkout" ,V_88F6810_PLUS )), MPP_MODE(44,
@@ -302,7 +302,7 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_MODE(48, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6810_PLUS), - MPP_VAR_FUNCTION(2, "m", "vtt_ctrl", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "dram", "vttctrl", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "tdm2c", "pclk", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "audio", "mclk", V_88F6810_PLUS), MPP_VAR_FUNCTION(5, "sd0", "d4", V_88F6810_PLUS),
@@ -325,7 +325,7 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "tdm2c", "dtx", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "audio", "sdo", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "m", "decc_err", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(5, "dram", "deccerr", V_88F6810_PLUS)), MPP_MODE(52, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6810_PLUS),
@@ -357,7 +357,7 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "ua1", "rts", V_88F6810_PLUS), MPP_VAR_FUNCTION(2, "ge", "mdc", V_88F6810_PLUS), - MPP_VAR_FUNCTION(3, "m", "decc_err", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "dram", "deccerr", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "spi1", "mosi", V_88F6810_PLUS)), MPP_MODE(57, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
drivers/pinctrl/mvebu/pinctrl-armada-39x.c +8 -8
@@ -98,7 +98,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(7, "led", "data", V_88F6920_PLUS)),MPP_MODE (14 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6920_PLUS ), -MPP_VAR_FUNCTION (3 ,"m" ,"vtt" ,V_88F6920_PLUS ), +MPP_VAR_FUNCTION (3 ,"dram" ,"vttctrl" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (5 ,"dev" ,"wen1" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (7 ,"ua1" ,"txd" ,V_88F6920_PLUS )), MPP_MODE(15,
@@ -108,7 +108,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(7, "i2c1", "sck", V_88F6920_PLUS)),MPP_MODE (16 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6920_PLUS ), -MPP_VAR_FUNCTION (3 ,"m" ,"decc" ,V_88F6920_PLUS ), +MPP_VAR_FUNCTION (3 ,"dram" ,"deccerr" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (4 ,"spi0" ,"miso" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (7 ,"i2c1" ,"sda" ,V_88F6920_PLUS )), MPP_MODE(17,
@@ -198,7 +198,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(8, "ge", "txctl", V_88F6920_PLUS)),MPP_MODE (33 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6920_PLUS ), -MPP_VAR_FUNCTION (1 ,"m" ,"decc" ,V_88F6920_PLUS ), +MPP_VAR_FUNCTION (1 ,"dram" ,"deccerr" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (5 ,"dev" ,"ad3" ,V_88F6920_PLUS )), MPP_MODE(34, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
@@ -251,8 +251,8 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = {MPP_MODE (43 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (1 ,"pcie0" ,"clkreq" ,V_88F6920_PLUS ), -MPP_VAR_FUNCTION (2 ,"m" ,"vtt" ,V_88F6920_PLUS ), -MPP_VAR_FUNCTION (3 ,"m" ,"decc" ,V_88F6920_PLUS ), +MPP_VAR_FUNCTION (2 ,"dram" ,"vttctrl" ,V_88F6920_PLUS ), +MPP_VAR_FUNCTION (3 ,"dram" ,"deccerr" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (4 ,"spi1" ,"cs2" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (5 ,"dev" ,"clkout" ,V_88F6920_PLUS ), MPP_VAR_FUNCTION(6, "nd", "rbn1", V_88F6920_PLUS)),
@@ -280,7 +280,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_MODE(48, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(1, "sata0", "present", V_88F6928), - MPP_VAR_FUNCTION(2, "m", "vtt", V_88F6920_PLUS), + MPP_VAR_FUNCTION(2, "dram", "vttctrl", V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "tdm", "pclk", V_88F6928), MPP_VAR_FUNCTION(4, "audio", "mclk", V_88F6928), MPP_VAR_FUNCTION(5, "sd", "d4", V_88F6920_PLUS),
@@ -303,7 +303,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "tdm", "dtx", V_88F6928), MPP_VAR_FUNCTION(4, "audio", "sdo", V_88F6928), - MPP_VAR_FUNCTION(5, "m", "decc", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "dram", "deccerr", V_88F6920_PLUS), MPP_VAR_FUNCTION(7, "ua2", "txd", V_88F6920_PLUS)), MPP_MODE(52, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
@@ -337,7 +337,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = {MPP_MODE (56 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (1 ,"ua1" ,"rts" ,V_88F6920_PLUS ), -MPP_VAR_FUNCTION (3 ,"m" ,"decc" ,V_88F6920_PLUS ), +MPP_VAR_FUNCTION (3 ,"dram" ,"deccerr" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (4 ,"spi1" ,"mosi" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (6 ,"ua1" ,"txd" ,V_88F6920_PLUS )), MPP_MODE(57,
drivers/pinctrl/mvebu/pinctrl-armada-xp.c +3 -3
@@ -152,7 +152,7 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "ge0", "rxd5", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "ge1", "rxd3", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x3, "mem", "bat", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x3, "dram", "bat", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "lcd", "d21", V_MV78230_PLUS)), MPP_MODE(22, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
@@ -211,7 +211,7 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "sd0", "d1", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x3, "tdm", "int4", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x4, "mem", "bat", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x4, "dram", "bat", V_MV78230_PLUS)), MPP_MODE(34, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "sd0", "d2", V_MV78230_PLUS),
@@ -264,7 +264,7 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x1, "uart2", "cts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart3", "rxd", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x3, "spi", "cs4", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x4, "mem", "bat", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x4, "dram", "bat", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x5, "pcie", "clkreq2", V_MV78230_PLUS)), MPP_MODE(45, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
Signature · 1 line
2.1.0
PATCH 11/34 pinctrl: mvebu: armada-{38x,39x,xp}: normalize naming of DRAM functions
Quoted 6 lines · Thomas Petazzoni
This commit makes the dram functions naming (both the name and subname) consistent accross SoC, by using:
dram(vttctrl)
dram(deccerr)
Quoted 7 lines
in all Marvell SoCs.
Due to the change to the name, it changes the DT binding, but these functions are not used by any in-tree Device Tree file, and are very unlikely to be used by anyone.
Signed-off-by Thomas Petazzoni <[email protected]>
Patch applied.
Yours,
Linus Walleij
PATCH 12/34 pinctrl: mvebu: armada-39x: normalize SATA present functionality naming
In reply to Thomas PetazzoniThis commit makes the naming of SATA related MPP functions consistent accross SoCs by adjusting the Armada 39x definition to use "prsnt" instead of "present".
Since only the subnames are changed, the DT binding is not modified at all.
--- .../pinctrl/marvell,armada-39x-pinctrl.txt | 16 +++++++-------- drivers/pinctrl/mvebu/pinctrl-armada-39x.c | 24 +++++++++++----------- 2 files changed, 20 insertions(+), 20 deletions(-)
Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt +8 -8
@@ -33,9 +33,9 @@ mpp15 15 gpio, pcie0(rstout), spi0(mosi), i2c1(sck) mpp16 16 gpio, dram(deccerr), spi0(miso), i2c1(sda) mpp17 17 gpio, ua1(rxd), spi0(sck), smi(mdio) mpp18 18 gpio, ua1(txd), spi0(cs0), i2c2(sck) -mpp19 19 gpio, sata1(present) [1], ua0(cts), ua1(rxd), i2c2(sda) -mpp20 20 gpio, sata0(present) [1], ua0(rts), ua1(txd), smi(mdc) -mpp21 21 gpio, spi0(cs1), sata0(present) [1], sd(cmd), dev(bootcs), ge(rxd0) +mpp19 19 gpio, sata1(prsnt) [1], ua0(cts), ua1(rxd), i2c2(sda) +mpp20 20 gpio, sata0(prsnt) [1], ua0(rts), ua1(txd), smi(mdc) +mpp21 21 gpio, spi0(cs1), sata0(prsnt) [1], sd(cmd), dev(bootcs), ge(rxd0) mpp22 22 gpio, spi0(mosi), dev(ad0) mpp23 23 gpio, spi0(sck), dev(ad2) mpp24 24 gpio, spi0(miso), ua0(cts), ua1(rxd), sd(d4), dev(readyn)
@@ -58,17 +58,17 @@ mpp40 40 gpio, i2c1(sda), ua0(rts), sd(d2), dev(ad6), ge(rxd3) mpp41 41 gpio, ua1(rxd), ua0(cts), spi1(cs3), dev(burstn), nd(rbn0), ge(rxctl) mpp42 42 gpio, ua1(txd), ua0(rts), dev(ad7) mpp43 43 gpio, pcie0(clkreq), dram(vttctrl), dram(deccerr), spi1(cs2), dev(clkout), nd(rbn1) -mpp44 44 gpio, sata0(present) [1], sata1(present) [1], led(clk) +mpp44 44 gpio, sata0(prsnt) [1], sata1(prsnt) [1], led(clk) mpp45 45 gpio, ref(clk), pcie0(rstout), ua1(rxd) mpp46 46 gpio, ref(clk), pcie0(rstout), ua1(txd), led(stb) -mpp47 47 gpio, sata0(present) [1], sata1(present) [1], led(data) -mpp48 48 gpio, sata0(present) [1], dram(vttctrl), tdm(pclk) [1], audio(mclk) [1], sd(d4), pcie0(clkreq), ua1(txd) +mpp47 47 gpio, sata0(prsnt) [1], sata1(prsnt) [1], led(data) +mpp48 48 gpio, sata0(prsnt) [1], dram(vttctrl), tdm(pclk) [1], audio(mclk) [1], sd(d4), pcie0(clkreq), ua1(txd) mpp49 49 gpio, tdm(fsync) [1], audio(lrclk) [1], sd(d5), ua2(rxd) mpp50 50 gpio, pcie0(rstout), tdm(drx) [1], audio(extclk) [1], sd(cmd), ua2(rxd) mpp51 51 gpio, tdm(dtx) [1], audio(sdo) [1], dram(deccerr), ua2(txd) mpp52 52 gpio, pcie0(rstout), tdm(intn) [1], audio(sdi) [1], sd(d6), i2c3(sck) -mpp53 53 gpio, sata1(present) [1], sata0(present) [1], tdm(rstn) [1], audio(bclk) [1], sd(d7), i2c3(sda) -mpp54 54 gpio, sata0(present) [1], sata1(present) [1], pcie0(rstout), sd(d3), ua3(txd) +mpp53 53 gpio, sata1(prsnt) [1], sata0(prsnt) [1], tdm(rstn) [1], audio(bclk) [1], sd(d7), i2c3(sda) +mpp54 54 gpio, sata0(prsnt) [1], sata1(prsnt) [1], pcie0(rstout), sd(d3), ua3(txd) mpp55 55 gpio, ua1(cts), spi1(cs1), sd(d0), ua1(rxd), ua3(rxd) mpp56 56 gpio, ua1(rts), dram(deccerr), spi1(mosi), ua1(txd) mpp57 57 gpio, spi1(sck), sd(clk), ua1(txd)
drivers/pinctrl/mvebu/pinctrl-armada-39x.c +12 -12
@@ -123,20 +123,20 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(7, "i2c2", "sck", V_88F6920_PLUS)),MPP_MODE (19 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6920_PLUS ), -MPP_VAR_FUNCTION (4 ,"sata1" ,"present" ,V_88F6928 ), +MPP_VAR_FUNCTION (4 ,"sata1" ,"prsnt" ,V_88F6928 ),MPP_VAR_FUNCTION (5 ,"ua0" ,"cts" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (6 ,"ua1" ,"rxd" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (7 ,"i2c2" ,"sda" ,V_88F6920_PLUS )),MPP_MODE (20 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6920_PLUS ), -MPP_VAR_FUNCTION (4 ,"sata0" ,"present" ,V_88F6928 ), +MPP_VAR_FUNCTION (4 ,"sata0" ,"prsnt" ,V_88F6928 ),MPP_VAR_FUNCTION (5 ,"ua0" ,"rts" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (6 ,"ua1" ,"txd" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (7 ,"smi" ,"mdc" ,V_88F6920_PLUS )),MPP_MODE (21 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (1 ,"spi0" ,"cs1" ,V_88F6920_PLUS ), -MPP_VAR_FUNCTION (3 ,"sata0" ,"present" ,V_88F6928 ), +MPP_VAR_FUNCTION (3 ,"sata0" ,"prsnt" ,V_88F6928 ),MPP_VAR_FUNCTION (4 ,"sd" ,"cmd" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (5 ,"dev" ,"bootcs" ,V_88F6920_PLUS ), MPP_VAR_FUNCTION(8, "ge", "rxd0", V_88F6920_PLUS)),
@@ -258,8 +258,8 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(6, "nd", "rbn1", V_88F6920_PLUS)),MPP_MODE (44 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6920_PLUS ), -MPP_VAR_FUNCTION (1 ,"sata0" ,"present" ,V_88F6928 ), -MPP_VAR_FUNCTION (2 ,"sata1" ,"present" ,V_88F6928 ), +MPP_VAR_FUNCTION (1 ,"sata0" ,"prsnt" ,V_88F6928 ), +MPP_VAR_FUNCTION (2 ,"sata1" ,"prsnt" ,V_88F6928 ),MPP_VAR_FUNCTION (7 ,"led" ,"clk" ,V_88F6920_PLUS )), MPP_MODE(45, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
@@ -274,12 +274,12 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(7, "led", "stb", V_88F6920_PLUS)),MPP_MODE (47 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6920_PLUS ), -MPP_VAR_FUNCTION (1 ,"sata0" ,"present" ,V_88F6928 ), -MPP_VAR_FUNCTION (2 ,"sata1" ,"present" ,V_88F6928 ), +MPP_VAR_FUNCTION (1 ,"sata0" ,"prsnt" ,V_88F6928 ), +MPP_VAR_FUNCTION (2 ,"sata1" ,"prsnt" ,V_88F6928 ),MPP_VAR_FUNCTION (7 ,"led" ,"data" ,V_88F6920_PLUS )), MPP_MODE(48, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), - MPP_VAR_FUNCTION(1, "sata0", "present", V_88F6928), + MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6928), MPP_VAR_FUNCTION(2, "dram", "vttctrl", V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "tdm", "pclk", V_88F6928), MPP_VAR_FUNCTION(4, "audio", "mclk", V_88F6928),
@@ -314,16 +314,16 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(7, "i2c3", "sck", V_88F6920_PLUS)),MPP_MODE (53 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6920_PLUS ), -MPP_VAR_FUNCTION (1 ,"sata1" ,"present" ,V_88F6928 ), -MPP_VAR_FUNCTION (2 ,"sata0" ,"present" ,V_88F6928 ), +MPP_VAR_FUNCTION (1 ,"sata1" ,"prsnt" ,V_88F6928 ), +MPP_VAR_FUNCTION (2 ,"sata0" ,"prsnt" ,V_88F6928 ),MPP_VAR_FUNCTION (3 ,"tdm" ,"rstn" ,V_88F6928 ),MPP_VAR_FUNCTION (4 ,"audio" ,"bclk" ,V_88F6928 ),MPP_VAR_FUNCTION (5 ,"sd" ,"d7" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (7 ,"i2c3" ,"sda" ,V_88F6920_PLUS )),MPP_MODE (54 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6920_PLUS ), -MPP_VAR_FUNCTION (1 ,"sata0" ,"present" ,V_88F6928 ), -MPP_VAR_FUNCTION (2 ,"sata1" ,"present" ,V_88F6928 ), +MPP_VAR_FUNCTION (1 ,"sata0" ,"prsnt" ,V_88F6928 ), +MPP_VAR_FUNCTION (2 ,"sata1" ,"prsnt" ,V_88F6928 ),MPP_VAR_FUNCTION (3 ,"pcie0" ,"rstout" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (5 ,"sd" ,"d3" ,V_88F6920_PLUS ), MPP_VAR_FUNCTION(7, "ua3", "txd", V_88F6920_PLUS)),
Signature · 1 line
2.1.0
PATCH 12/34 pinctrl: mvebu: armada-39x: normalize SATA present functionality naming
Quoted 8 lines · Thomas Petazzoni
This commit makes the naming of SATA related MPP functions consistent accross SoCs by adjusting the Armada 39x definition to use "prsnt" instead of "present".
Since only the subnames are changed, the DT binding is not modified at all.
Signed-off-by Thomas Petazzoni <[email protected]>
Patch applied.
Yours,
Linus Walleij
PATCH 13/34 pinctrl: mvebu: armada-39x: normalize SDIO pin naming
In reply to Thomas PetazzoniIn order to be consistent with the datasheet and some other SoCs, this commit renames the SDIO pins of the Armada 39x from "sd" to "sd0".
While this changes the DT binding, this is not a problem since Armada 39x is a brand new SoC which isn't used in production yet (so now is the right time to fix such things).
--- .../pinctrl/marvell,armada-39x-pinctrl.txt | 40 +++++++++++----------- drivers/pinctrl/mvebu/pinctrl-armada-39x.c | 40 +++++++++++----------- 2 files changed, 40 insertions(+), 40 deletions(-)
Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt +20 -20
@@ -35,14 +35,14 @@ mpp17 17 gpio, ua1(rxd), spi0(sck), smi(mdio) mpp18 18 gpio, ua1(txd), spi0(cs0), i2c2(sck) mpp19 19 gpio, sata1(prsnt) [1], ua0(cts), ua1(rxd), i2c2(sda) mpp20 20 gpio, sata0(prsnt) [1], ua0(rts), ua1(txd), smi(mdc) -mpp21 21 gpio, spi0(cs1), sata0(prsnt) [1], sd(cmd), dev(bootcs), ge(rxd0) +mpp21 21 gpio, spi0(cs1), sata0(prsnt) [1], sd0(cmd), dev(bootcs), ge(rxd0) mpp22 22 gpio, spi0(mosi), dev(ad0) mpp23 23 gpio, spi0(sck), dev(ad2) -mpp24 24 gpio, spi0(miso), ua0(cts), ua1(rxd), sd(d4), dev(readyn) -mpp25 25 gpio, spi0(cs0), ua0(rts), ua1(txd), sd(d5), dev(cs0) -mpp26 26 gpio, spi0(cs2), i2c1(sck), sd(d6), dev(cs1) -mpp27 27 gpio, spi0(cs3), i2c1(sda), sd(d7), dev(cs2), ge(txclkout) -mpp28 28 gpio, sd(clk), dev(ad5), ge(txd0) +mpp24 24 gpio, spi0(miso), ua0(cts), ua1(rxd), sd0(d4), dev(readyn) +mpp25 25 gpio, spi0(cs0), ua0(rts), ua1(txd), sd0(d5), dev(cs0) +mpp26 26 gpio, spi0(cs2), i2c1(sck), sd0(d6), dev(cs1) +mpp27 27 gpio, spi0(cs3), i2c1(sda), sd0(d7), dev(cs2), ge(txclkout) +mpp28 28 gpio, sd0(clk), dev(ad5), ge(txd0) mpp29 29 gpio, dev(ale0), ge(txd1) mpp30 30 gpio, dev(oen), ge(txd2) mpp31 31 gpio, dev(ale1), ge(txd3)
@@ -51,10 +51,10 @@ mpp33 33 gpio, dram(deccerr), dev(ad3) mpp34 34 gpio, dev(ad1) mpp35 35 gpio, ref(clk), dev(a1) mpp36 36 gpio, dev(a0) -mpp37 37 gpio, sd(d3), dev(ad8), ge(rxclk) -mpp38 38 gpio, ref(clk), sd(d0), dev(ad4), ge(rxd1) -mpp39 39 gpio, i2c1(sck), ua0(cts), sd(d1), dev(a2), ge(rxd2) -mpp40 40 gpio, i2c1(sda), ua0(rts), sd(d2), dev(ad6), ge(rxd3) +mpp37 37 gpio, sd0(d3), dev(ad8), ge(rxclk) +mpp38 38 gpio, ref(clk), sd0(d0), dev(ad4), ge(rxd1) +mpp39 39 gpio, i2c1(sck), ua0(cts), sd0(d1), dev(a2), ge(rxd2) +mpp40 40 gpio, i2c1(sda), ua0(rts), sd0(d2), dev(ad6), ge(rxd3) mpp41 41 gpio, ua1(rxd), ua0(cts), spi1(cs3), dev(burstn), nd(rbn0), ge(rxctl) mpp42 42 gpio, ua1(txd), ua0(rts), dev(ad7) mpp43 43 gpio, pcie0(clkreq), dram(vttctrl), dram(deccerr), spi1(cs2), dev(clkout), nd(rbn1)
@@ -62,17 +62,17 @@ mpp44 44 gpio, sata0(prsnt) [1], sata1(prsnt) [1], led(clk) mpp45 45 gpio, ref(clk), pcie0(rstout), ua1(rxd) mpp46 46 gpio, ref(clk), pcie0(rstout), ua1(txd), led(stb) mpp47 47 gpio, sata0(prsnt) [1], sata1(prsnt) [1], led(data) -mpp48 48 gpio, sata0(prsnt) [1], dram(vttctrl), tdm(pclk) [1], audio(mclk) [1], sd(d4), pcie0(clkreq), ua1(txd) -mpp49 49 gpio, tdm(fsync) [1], audio(lrclk) [1], sd(d5), ua2(rxd) -mpp50 50 gpio, pcie0(rstout), tdm(drx) [1], audio(extclk) [1], sd(cmd), ua2(rxd) +mpp48 48 gpio, sata0(prsnt) [1], dram(vttctrl), tdm(pclk) [1], audio(mclk) [1], sd0(d4), pcie0(clkreq), ua1(txd) +mpp49 49 gpio, tdm(fsync) [1], audio(lrclk) [1], sd0(d5), ua2(rxd) +mpp50 50 gpio, pcie0(rstout), tdm(drx) [1], audio(extclk) [1], sd0(cmd), ua2(rxd) mpp51 51 gpio, tdm(dtx) [1], audio(sdo) [1], dram(deccerr), ua2(txd) -mpp52 52 gpio, pcie0(rstout), tdm(intn) [1], audio(sdi) [1], sd(d6), i2c3(sck) -mpp53 53 gpio, sata1(prsnt) [1], sata0(prsnt) [1], tdm(rstn) [1], audio(bclk) [1], sd(d7), i2c3(sda) -mpp54 54 gpio, sata0(prsnt) [1], sata1(prsnt) [1], pcie0(rstout), sd(d3), ua3(txd) -mpp55 55 gpio, ua1(cts), spi1(cs1), sd(d0), ua1(rxd), ua3(rxd) +mpp52 52 gpio, pcie0(rstout), tdm(intn) [1], audio(sdi) [1], sd0(d6), i2c3(sck) +mpp53 53 gpio, sata1(prsnt) [1], sata0(prsnt) [1], tdm(rstn) [1], audio(bclk) [1], sd0(d7), i2c3(sda) +mpp54 54 gpio, sata0(prsnt) [1], sata1(prsnt) [1], pcie0(rstout), sd0(d3), ua3(txd) +mpp55 55 gpio, ua1(cts), spi1(cs1), sd0(d0), ua1(rxd), ua3(rxd) mpp56 56 gpio, ua1(rts), dram(deccerr), spi1(mosi), ua1(txd) -mpp57 57 gpio, spi1(sck), sd(clk), ua1(txd) -mpp58 58 gpio, i2c1(sck), pcie2(clkreq), spi1(miso), sd(d1), ua1(rxd) -mpp59 59 gpio, pcie0(rstout), i2c1(sda), spi1(cs0), sd(d2) +mpp57 57 gpio, spi1(sck), sd0(clk), ua1(txd) +mpp58 58 gpio, i2c1(sck), pcie2(clkreq), spi1(miso), sd0(d1), ua1(rxd) +mpp59 59 gpio, pcie0(rstout), i2c1(sda), spi1(cs0), sd0(d2) [1]: only available on 88F6928
drivers/pinctrl/mvebu/pinctrl-armada-39x.c +20 -20
@@ -137,7 +137,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = {MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (1 ,"spi0" ,"cs1" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (3 ,"sata0" ,"prsnt" ,V_88F6928 ), -MPP_VAR_FUNCTION (4 ,"sd" ,"cmd" ,V_88F6920_PLUS ), +MPP_VAR_FUNCTION (4 ,"sd0" ,"cmd" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (5 ,"dev" ,"bootcs" ,V_88F6920_PLUS ), MPP_VAR_FUNCTION(8, "ge", "rxd0", V_88F6920_PLUS)), MPP_MODE(22,
@@ -153,31 +153,31 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(1, "spi0", "miso", V_88F6920_PLUS), MPP_VAR_FUNCTION(2, "ua0", "cts", V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "ua1", "rxd", V_88F6920_PLUS), - MPP_VAR_FUNCTION(4, "sd", "d4", V_88F6920_PLUS), + MPP_VAR_FUNCTION(4, "sd0", "d4", V_88F6920_PLUS), MPP_VAR_FUNCTION(5, "dev", "readyn", V_88F6920_PLUS)),MPP_MODE (25 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (1 ,"spi0" ,"cs0" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (2 ,"ua0" ,"rts" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (3 ,"ua1" ,"txd" ,V_88F6920_PLUS ), -MPP_VAR_FUNCTION (4 ,"sd" ,"d5" ,V_88F6920_PLUS ), +MPP_VAR_FUNCTION (4 ,"sd0" ,"d5" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (5 ,"dev" ,"cs0" ,V_88F6920_PLUS )),MPP_MODE (26 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (1 ,"spi0" ,"cs2" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (3 ,"i2c1" ,"sck" ,V_88F6920_PLUS ), -MPP_VAR_FUNCTION (4 ,"sd" ,"d6" ,V_88F6920_PLUS ), +MPP_VAR_FUNCTION (4 ,"sd0" ,"d6" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (5 ,"dev" ,"cs1" ,V_88F6920_PLUS )),MPP_MODE (27 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (1 ,"spi0" ,"cs3" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (3 ,"i2c1" ,"sda" ,V_88F6920_PLUS ), -MPP_VAR_FUNCTION (4 ,"sd" ,"d7" ,V_88F6920_PLUS ), +MPP_VAR_FUNCTION (4 ,"sd0" ,"d7" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (5 ,"dev" ,"cs2" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (8 ,"ge" ,"txclkout" ,V_88F6920_PLUS )),MPP_MODE (28 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6920_PLUS ), -MPP_VAR_FUNCTION (4 ,"sd" ,"clk" ,V_88F6920_PLUS ), +MPP_VAR_FUNCTION (4 ,"sd0" ,"clk" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (5 ,"dev" ,"ad5" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (8 ,"ge" ,"txd0" ,V_88F6920_PLUS )), MPP_MODE(29,
@@ -212,27 +212,27 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(5, "dev", "a0", V_88F6920_PLUS)),MPP_MODE (37 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6920_PLUS ), -MPP_VAR_FUNCTION (4 ,"sd" ,"d3" ,V_88F6920_PLUS ), +MPP_VAR_FUNCTION (4 ,"sd0" ,"d3" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (5 ,"dev" ,"ad8" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (8 ,"ge" ,"rxclk" ,V_88F6920_PLUS )),MPP_MODE (38 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (3 ,"ref" ,"clk" ,V_88F6920_PLUS ), -MPP_VAR_FUNCTION (4 ,"sd" ,"d0" ,V_88F6920_PLUS ), +MPP_VAR_FUNCTION (4 ,"sd0" ,"d0" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (5 ,"dev" ,"ad4" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (8 ,"ge" ,"rxd1" ,V_88F6920_PLUS )),MPP_MODE (39 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (1 ,"i2c1" ,"sck" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (3 ,"ua0" ,"cts" ,V_88F6920_PLUS ), -MPP_VAR_FUNCTION (4 ,"sd" ,"d1" ,V_88F6920_PLUS ), +MPP_VAR_FUNCTION (4 ,"sd0" ,"d1" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (5 ,"dev" ,"a2" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (8 ,"ge" ,"rxd2" ,V_88F6920_PLUS )),MPP_MODE (40 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (1 ,"i2c1" ,"sda" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (3 ,"ua0" ,"rts" ,V_88F6920_PLUS ), -MPP_VAR_FUNCTION (4 ,"sd" ,"d2" ,V_88F6920_PLUS ), +MPP_VAR_FUNCTION (4 ,"sd0" ,"d2" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (5 ,"dev" ,"ad6" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (8 ,"ge" ,"rxd3" ,V_88F6920_PLUS )), MPP_MODE(41,
@@ -283,21 +283,21 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(2, "dram", "vttctrl", V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "tdm", "pclk", V_88F6928), MPP_VAR_FUNCTION(4, "audio", "mclk", V_88F6928), - MPP_VAR_FUNCTION(5, "sd", "d4", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "sd0", "d4", V_88F6920_PLUS), MPP_VAR_FUNCTION(6, "pcie0", "clkreq", V_88F6920_PLUS), MPP_VAR_FUNCTION(7, "ua1", "txd", V_88F6920_PLUS)),MPP_MODE (49 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (3 ,"tdm" ,"fsync" ,V_88F6928 ),MPP_VAR_FUNCTION (4 ,"audio" ,"lrclk" ,V_88F6928 ), -MPP_VAR_FUNCTION (5 ,"sd" ,"d5" ,V_88F6920_PLUS ), +MPP_VAR_FUNCTION (5 ,"sd0" ,"d5" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (7 ,"ua2" ,"rxd" ,V_88F6920_PLUS )),MPP_MODE (50 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (1 ,"pcie0" ,"rstout" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (3 ,"tdm" ,"drx" ,V_88F6928 ),MPP_VAR_FUNCTION (4 ,"audio" ,"extclk" ,V_88F6928 ), -MPP_VAR_FUNCTION (5 ,"sd" ,"cmd" ,V_88F6920_PLUS ), +MPP_VAR_FUNCTION (5 ,"sd0" ,"cmd" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (7 ,"ua2" ,"rxd" ,V_88F6920_PLUS )), MPP_MODE(51, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
@@ -310,7 +310,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "tdm", "intn", V_88F6928), MPP_VAR_FUNCTION(4, "audio", "sdi", V_88F6928), - MPP_VAR_FUNCTION(5, "sd", "d6", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "sd0", "d6", V_88F6920_PLUS), MPP_VAR_FUNCTION(7, "i2c3", "sck", V_88F6920_PLUS)), MPP_MODE(53, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
@@ -318,20 +318,20 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(2, "sata0", "prsnt", V_88F6928), MPP_VAR_FUNCTION(3, "tdm", "rstn", V_88F6928), MPP_VAR_FUNCTION(4, "audio", "bclk", V_88F6928), - MPP_VAR_FUNCTION(5, "sd", "d7", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "sd0", "d7", V_88F6920_PLUS), MPP_VAR_FUNCTION(7, "i2c3", "sda", V_88F6920_PLUS)),MPP_MODE (54 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (1 ,"sata0" ,"prsnt" ,V_88F6928 ),MPP_VAR_FUNCTION (2 ,"sata1" ,"prsnt" ,V_88F6928 ),MPP_VAR_FUNCTION (3 ,"pcie0" ,"rstout" ,V_88F6920_PLUS ), -MPP_VAR_FUNCTION (5 ,"sd" ,"d3" ,V_88F6920_PLUS ), +MPP_VAR_FUNCTION (5 ,"sd0" ,"d3" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (7 ,"ua3" ,"txd" ,V_88F6920_PLUS )),MPP_MODE (55 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (1 ,"ua1" ,"cts" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (4 ,"spi1" ,"cs1" ,V_88F6920_PLUS ), -MPP_VAR_FUNCTION (5 ,"sd" ,"d0" ,V_88F6920_PLUS ), +MPP_VAR_FUNCTION (5 ,"sd0" ,"d0" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (6 ,"ua1" ,"rxd" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (7 ,"ua3" ,"rxd" ,V_88F6920_PLUS )), MPP_MODE(56,
@@ -343,21 +343,21 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = {MPP_MODE (57 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (4 ,"spi1" ,"sck" ,V_88F6920_PLUS ), -MPP_VAR_FUNCTION (5 ,"sd" ,"clk" ,V_88F6920_PLUS ), +MPP_VAR_FUNCTION (5 ,"sd0" ,"clk" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (6 ,"ua1" ,"txd" ,V_88F6920_PLUS )),MPP_MODE (58 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (2 ,"i2c1" ,"sck" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (3 ,"pcie2" ,"clkreq" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (4 ,"spi1" ,"miso" ,V_88F6920_PLUS ), -MPP_VAR_FUNCTION (5 ,"sd" ,"d1" ,V_88F6920_PLUS ), +MPP_VAR_FUNCTION (5 ,"sd0" ,"d1" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (6 ,"ua1" ,"rxd" ,V_88F6920_PLUS )),MPP_MODE (59 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (1 ,"pcie0" ,"rstout" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (2 ,"i2c1" ,"sda" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (4 ,"spi1" ,"cs0" ,V_88F6920_PLUS ), - MPP_VAR_FUNCTION(5, "sd", "d2", V_88F6920_PLUS)), + MPP_VAR_FUNCTION(5, "sd0", "d2", V_88F6920_PLUS)), };static struct mvebu_pinctrl_soc_info armada_39x_pinctrl_info;
Signature · 1 line
2.1.0
PATCH 13/34 pinctrl: mvebu: armada-39x: normalize SDIO pin naming
Quoted 8 lines · Thomas Petazzoni
In order to be consistent with the datasheet and some other SoCs, this commit renames the SDIO pins of the Armada 39x from "sd" to "sd0".
While this changes the DT binding, this is not a problem since Armada 39x is a brand new SoC which isn't used in production yet (so now is the right time to fix such things).
Signed-off-by Thomas Petazzoni <[email protected]>
Patch applied.
Yours,
Linus Walleij
PATCH 14/34 pinctrl: mvebu: armada-{370, 375, 38x, 39x}: normalize dev pins
In reply to Thomas PetazzoniThis commit modifies the definition of the Device Bus interface pins to be consistent accross SoCs. Especially, it removes the 'n' indicators that we don't encode in the subnames of pins:
'dev(wen0)' becomes 'dev(we0)'
'dev(wen1)' becomes 'dev(we1)'
'dev(oen)' becomes 'dev(oe)'
etc.
In addition, it fixes the Armada 375 DT binding documentation, which forgot to document the 'dev' function for MPP46, MPP57 and MPP63.
Since only the subnames are changed, this commit does not affect DT compatibility.
--- .../devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt | 6 +++--- .../devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt | 8 ++++---- .../devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt | 6 +++--- .../devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt | 10 +++++----- drivers/pinctrl/mvebu/pinctrl-armada-370.c | 6 +++--- drivers/pinctrl/mvebu/pinctrl-armada-375.c | 8 ++++---- drivers/pinctrl/mvebu/pinctrl-armada-38x.c | 6 +++--- drivers/pinctrl/mvebu/pinctrl-armada-39x.c | 10 +++++----- 8 files changed, 30 insertions(+), 30 deletions(-)
Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt +3 -3
@@ -52,8 +52,8 @@ mpp30 30 gpio, ge0(rxd7), ge1(rxclk), i2c1(sck) mpp31 31 gpio, tclk, ge0(txerr) mpp32 32 gpio, spi0(cs0) mpp33 33 gpio, dev(bootcs), spi0(cs0) -mpp34 34 gpo, dev(wen0), spi0(mosi) -mpp35 35 gpo, dev(oen), spi0(sck) +mpp34 34 gpo, dev(we0), spi0(mosi) +mpp35 35 gpo, dev(oe), spi0(sck) mpp36 36 gpo, dev(a1), spi0(miso) mpp37 37 gpo, dev(a0), sata0(prsnt) mpp38 38 gpio, dev(ready), uart1(cts), uart0(cts)
@@ -88,7 +88,7 @@ mpp58 58 gpio, dev(cs0), uart1(rts), tdm(int), audio(extclk), mpp59 59 gpo, dev(ale0), uart1(rts), uart0(rts), audio(bclk) mpp60 60 gpio, dev(ale1), uart1(rxd), sata0(prsnt), pcie(rst-out), audio(sdi) -mpp61 61 gpo, dev(wen1), uart1(txd), audio(rclk) +mpp61 61 gpo, dev(we1), uart1(txd), audio(rclk) mpp62 62 gpio, dev(a2), uart1(cts), tdm(drx), pcie(clkreq0), audio(mclk), uart0(cts) mpp63 63 gpo, spi0(sck), tclk
Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt +4 -4
@@ -26,7 +26,7 @@ mpp9 9 gpio, spi0(sck), spi1(sck), nand(we) mpp10 10 gpio, dram(vttctrl), led(c1), nand(re) mpp11 11 gpio, dev(a0), led(c2), audio(sdo) mpp12 12 gpio, dev(a1), audio(bclk) -mpp13 13 gpio, dev(readyn), pcie0(rstoutn), pcie1(rstoutn) +mpp13 13 gpio, dev(ready), pcie0(rstoutn), pcie1(rstoutn) mpp14 14 gpio, i2c0(sda), uart1(txd) mpp15 15 gpio, i2c0(sck), uart1(rxd) mpp16 16 gpio, uart0(txd)
@@ -59,7 +59,7 @@ mpp42 42 gpio, spi1(cs2), led(c0) mpp43 43 gpio, sata0(prsnt), dram(vttctrl) mpp44 44 gpio, sata0(prsnt) mpp45 45 gpio, spi0(cs2), pcie0(rstoutn) -mpp46 46 gpio, led(p0), ge0(txd0), ge1(txd0) +mpp46 46 gpio, led(p0), ge0(txd0), ge1(txd0), dev(we1) mpp47 47 gpio, led(p1), ge0(txd1), ge1(txd1) mpp48 48 gpio, led(p2), ge0(txd2), ge1(txd2) mpp49 49 gpio, led(p3), ge0(txd3), ge1(txd3)
@@ -70,13 +70,13 @@ mpp53 53 gpio, pcie1(rstoutn), ge0(rxd3), ge1(rxd3) mpp54 54 gpio, pcie0(rstoutn), ge0(rxctl), ge1(rxctl) mpp55 55 gpio, ge0(rxclk), ge1(rxclk) mpp56 56 gpio, ge0(txclkout), ge1(txclkout) -mpp57 57 gpio, ge0(txctl), ge1(txctl) +mpp57 57 gpio, ge0(txctl), ge1(txctl), dev(we0) mpp58 58 gpio, led(c0) mpp59 59 gpio, led(c1) mpp60 60 gpio, uart1(txd), led(c2) mpp61 61 gpio, i2c1(sda), uart1(rxd), spi1(cs2), led(p0) mpp62 62 gpio, i2c1(sck), led(p1) -mpp63 63 gpio, ptp(trig), led(p2) +mpp63 63 gpio, ptp(trig), led(p2), dev(burst/last) mpp64 64 gpio, dram(vttctrl), led(p3) mpp65 65 gpio, sata1(prsnt) mpp66 66 gpio, ptp(evreq), spi1(cs3)
Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt +3 -3
@@ -29,7 +29,7 @@ mpp10 10 gpio, ge0(txd3), dev(ad12) mpp11 11 gpio, ge0(txctl), dev(ad13) mpp12 12 gpio, ge0(rxd0), pcie0(rstout), spi0(cs1), dev(ad14), pcie3(clkreq) mpp13 13 gpio, ge0(rxd1), pcie0(clkreq), pcie1(clkreq) [1], spi0(cs2), dev(ad15), pcie2(clkreq) -mpp14 14 gpio, ge0(rxd2), ptp(clk), dram(vttctrl), spi0(cs3), dev(wen1), pcie3(clkreq) +mpp14 14 gpio, ge0(rxd2), ptp(clk), dram(vttctrl), spi0(cs3), dev(we1), pcie3(clkreq) mpp15 15 gpio, ge0(rxd3), ge(mdc slave), pcie0(rstout), spi0(mosi) mpp16 16 gpio, ge0(rxctl), ge(mdio slave), dram(deccerr), spi0(miso), pcie0(clkreq), pcie1(clkreq) [1] mpp17 17 gpio, ge0(rxclk), ptp(clk), ua1(rxd), spi0(sck), sata1(prsnt)
@@ -45,9 +45,9 @@ mpp26 26 gpio, spi0(cs2), i2c1(sck), sd0(d6), dev(cs1) mpp27 27 gpio, spi0(cs3), ge1(txclkout), i2c1(sda), sd0(d7), dev(cs2) mpp28 28 gpio, ge1(txd0), sd0(clk), dev(ad5) mpp29 29 gpio, ge1(txd1), dev(ale0) -mpp30 30 gpio, ge1(txd2), dev(oen) +mpp30 30 gpio, ge1(txd2), dev(oe) mpp31 31 gpio, ge1(txd3), dev(ale1) -mpp32 32 gpio, ge1(txctl), dev(wen0) +mpp32 32 gpio, ge1(txctl), dev(we0) mpp33 33 gpio, dram(deccerr), dev(ad3) mpp34 34 gpio, dev(ad1) mpp35 35 gpio, ref(clk_out1), dev(a1)
Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt +5 -5
@@ -28,7 +28,7 @@ mpp10 10 gpio, dev(ad12), ptp(evreq) mpp11 11 gpio, dev(ad13), led(clk) mpp12 12 gpio, pcie0(rstout), dev(ad14), led(stb) mpp13 13 gpio, dev(ad15), led(data) -mpp14 14 gpio, dram(vttctrl), dev(wen1), ua1(txd) +mpp14 14 gpio, dram(vttctrl), dev(we1), ua1(txd) mpp15 15 gpio, pcie0(rstout), spi0(mosi), i2c1(sck) mpp16 16 gpio, dram(deccerr), spi0(miso), i2c1(sda) mpp17 17 gpio, ua1(rxd), spi0(sck), smi(mdio)
@@ -38,15 +38,15 @@ mpp20 20 gpio, sata0(prsnt) [1], ua0(rts), ua1(txd), smi(mdc) mpp21 21 gpio, spi0(cs1), sata0(prsnt) [1], sd0(cmd), dev(bootcs), ge(rxd0) mpp22 22 gpio, spi0(mosi), dev(ad0) mpp23 23 gpio, spi0(sck), dev(ad2) -mpp24 24 gpio, spi0(miso), ua0(cts), ua1(rxd), sd0(d4), dev(readyn) +mpp24 24 gpio, spi0(miso), ua0(cts), ua1(rxd), sd0(d4), dev(ready) mpp25 25 gpio, spi0(cs0), ua0(rts), ua1(txd), sd0(d5), dev(cs0) mpp26 26 gpio, spi0(cs2), i2c1(sck), sd0(d6), dev(cs1) mpp27 27 gpio, spi0(cs3), i2c1(sda), sd0(d7), dev(cs2), ge(txclkout) mpp28 28 gpio, sd0(clk), dev(ad5), ge(txd0) mpp29 29 gpio, dev(ale0), ge(txd1) -mpp30 30 gpio, dev(oen), ge(txd2) +mpp30 30 gpio, dev(oe), ge(txd2) mpp31 31 gpio, dev(ale1), ge(txd3) -mpp32 32 gpio, dev(wen0), ge(txctl) +mpp32 32 gpio, dev(we0), ge(txctl) mpp33 33 gpio, dram(deccerr), dev(ad3) mpp34 34 gpio, dev(ad1) mpp35 35 gpio, ref(clk), dev(a1)
@@ -55,7 +55,7 @@ mpp37 37 gpio, sd0(d3), dev(ad8), ge(rxclk) mpp38 38 gpio, ref(clk), sd0(d0), dev(ad4), ge(rxd1) mpp39 39 gpio, i2c1(sck), ua0(cts), sd0(d1), dev(a2), ge(rxd2) mpp40 40 gpio, i2c1(sda), ua0(rts), sd0(d2), dev(ad6), ge(rxd3) -mpp41 41 gpio, ua1(rxd), ua0(cts), spi1(cs3), dev(burstn), nd(rbn0), ge(rxctl) +mpp41 41 gpio, ua1(rxd), ua0(cts), spi1(cs3), dev(burst/last), nd(rbn0), ge(rxctl) mpp42 42 gpio, ua1(txd), ua0(rts), dev(ad7) mpp43 43 gpio, pcie0(clkreq), dram(vttctrl), dram(deccerr), spi1(cs2), dev(clkout), nd(rbn1) mpp44 44 gpio, sata0(prsnt) [1], sata1(prsnt) [1], led(clk)
drivers/pinctrl/mvebu/pinctrl-armada-370.c +3 -3
@@ -207,11 +207,11 @@ static struct mvebu_mpp_mode mv88f6710_mpp_modes[] = { MPP_FUNCTION(0x2, "spi0", "cs0")),MPP_MODE (34 ,MPP_FUNCTION (0x0 ,"gpo" ,NULL ), -MPP_FUNCTION (0x1 ,"dev" ,"wen0" ), +MPP_FUNCTION (0x1 ,"dev" ,"we0" ),MPP_FUNCTION (0x2 ,"spi0" ,"mosi" )),MPP_MODE (35 ,MPP_FUNCTION (0x0 ,"gpo" ,NULL ), -MPP_FUNCTION (0x1 ,"dev" ,"oen" ), +MPP_FUNCTION (0x1 ,"dev" ,"oe" ),MPP_FUNCTION (0x2 ,"spi0" ,"sck" )), MPP_MODE(36, MPP_FUNCTION(0x0, "gpo", NULL),
@@ -352,7 +352,7 @@ static struct mvebu_mpp_mode mv88f6710_mpp_modes[] = { MPP_FUNCTION(0x5, "audio", "sdi")),MPP_MODE (61 ,MPP_FUNCTION (0x0 ,"gpo" ,NULL ), -MPP_FUNCTION (0x1 ,"dev" ,"wen1" ), +MPP_FUNCTION (0x1 ,"dev" ,"we1" ),MPP_FUNCTION (0x2 ,"uart1" ,"txd" ),MPP_FUNCTION (0x5 ,"audio" ,"rclk" )), MPP_MODE(62,
drivers/pinctrl/mvebu/pinctrl-armada-375.c +4 -4
@@ -120,7 +120,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_FUNCTION(0x5, "nand", "ale")), MPP_MODE(13, MPP_FUNCTION(0x0, "gpio", NULL), - MPP_FUNCTION(0x1, "dev", "readyn"), + MPP_FUNCTION(0x1, "dev", "ready"), MPP_FUNCTION(0x2, "pcie0", "rstoutn"), MPP_FUNCTION(0x3, "pcie1", "rstoutn"), MPP_FUNCTION(0x5, "nand", "rb"),
@@ -284,7 +284,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_FUNCTION(0x1, "led", "p0"), MPP_FUNCTION(0x2, "ge0", "txd0"), MPP_FUNCTION(0x3, "ge1", "txd0"), - MPP_FUNCTION(0x6, "dev", "wen1")), + MPP_FUNCTION(0x6, "dev", "we1")), MPP_MODE(47, MPP_FUNCTION(0x0, "gpio", NULL), MPP_FUNCTION(0x1, "led", "p1"),
@@ -351,7 +351,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_FUNCTION(0x0, "gpio", NULL), MPP_FUNCTION(0x2, "ge0", "txctl"), MPP_FUNCTION(0x3, "ge1", "txctl"), - MPP_FUNCTION(0x6, "dev", "wen0")), + MPP_FUNCTION(0x6, "dev", "we0")),MPP_MODE (58 ,MPP_FUNCTION (0x0 ,"gpio" ,NULL ), MPP_FUNCTION(0x4, "led", "c0")),
@@ -379,7 +379,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_FUNCTION(0x0, "gpio", NULL), MPP_FUNCTION(0x2, "ptp", "trig"), MPP_FUNCTION(0x4, "led", "p2"), - MPP_FUNCTION(0x6, "dev", "burst")), + MPP_FUNCTION(0x6, "dev", "burst/last")), MPP_MODE(64, MPP_FUNCTION(0x0, "gpio", NULL), MPP_FUNCTION(0x2, "dram", "vttctrl"),
drivers/pinctrl/mvebu/pinctrl-armada-38x.c +3 -3
@@ -111,7 +111,7 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(2, "ptp", "clk", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "dram", "vttctrl", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "spi0", "cs3", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "dev", "wen1", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "dev", "we1", V_88F6810_PLUS), MPP_VAR_FUNCTION(6, "pcie3", "clkreq", V_88F6810_PLUS)), MPP_MODE(15, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
@@ -209,7 +209,7 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = {MPP_MODE (30 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6810_PLUS ),MPP_VAR_FUNCTION (2 ,"ge1" ,"txd2" ,V_88F6810_PLUS ), -MPP_VAR_FUNCTION (5 ,"dev" ,"oen" ,V_88F6810_PLUS )), +MPP_VAR_FUNCTION (5 ,"dev" ,"oe" ,V_88F6810_PLUS )), MPP_MODE(31, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(2, "ge1", "txd3", V_88F6810_PLUS),
@@ -217,7 +217,7 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = {MPP_MODE (32 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6810_PLUS ),MPP_VAR_FUNCTION (2 ,"ge1" ,"txctl" ,V_88F6810_PLUS ), -MPP_VAR_FUNCTION (5 ,"dev" ,"wen0" ,V_88F6810_PLUS )), +MPP_VAR_FUNCTION (5 ,"dev" ,"we0" ,V_88F6810_PLUS )), MPP_MODE(33, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "dram", "deccerr", V_88F6810_PLUS),
drivers/pinctrl/mvebu/pinctrl-armada-39x.c +5 -5
@@ -99,7 +99,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = {MPP_MODE (14 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (3 ,"dram" ,"vttctrl" ,V_88F6920_PLUS ), -MPP_VAR_FUNCTION (5 ,"dev" ,"wen1" ,V_88F6920_PLUS ), +MPP_VAR_FUNCTION (5 ,"dev" ,"we1" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (7 ,"ua1" ,"txd" ,V_88F6920_PLUS )), MPP_MODE(15, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
@@ -154,7 +154,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(2, "ua0", "cts", V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "ua1", "rxd", V_88F6920_PLUS), MPP_VAR_FUNCTION(4, "sd0", "d4", V_88F6920_PLUS), - MPP_VAR_FUNCTION(5, "dev", "readyn", V_88F6920_PLUS)), + MPP_VAR_FUNCTION(5, "dev", "ready", V_88F6920_PLUS)), MPP_MODE(25, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(1, "spi0", "cs0", V_88F6920_PLUS),
@@ -186,7 +186,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(8, "ge", "txd1", V_88F6920_PLUS)),MPP_MODE (30 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6920_PLUS ), -MPP_VAR_FUNCTION (5 ,"dev" ,"oen" ,V_88F6920_PLUS ), +MPP_VAR_FUNCTION (5 ,"dev" ,"oe" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (8 ,"ge" ,"txd2" ,V_88F6920_PLUS )), MPP_MODE(31, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
@@ -194,7 +194,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(8, "ge", "txd3", V_88F6920_PLUS)),MPP_MODE (32 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6920_PLUS ), -MPP_VAR_FUNCTION (5 ,"dev" ,"wen0" ,V_88F6920_PLUS ), +MPP_VAR_FUNCTION (5 ,"dev" ,"we0" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (8 ,"ge" ,"txctl" ,V_88F6920_PLUS )), MPP_MODE(33, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
@@ -240,7 +240,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = {MPP_VAR_FUNCTION (1 ,"ua1" ,"rxd" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (3 ,"ua0" ,"cts" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (4 ,"spi1" ,"cs3" ,V_88F6920_PLUS ), -MPP_VAR_FUNCTION (5 ,"dev" ,"burstn" ,V_88F6920_PLUS ), +MPP_VAR_FUNCTION (5 ,"dev" ,"burst/last" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (6 ,"nd" ,"rbn0" ,V_88F6920_PLUS ), MPP_VAR_FUNCTION(8, "ge", "rxctl", V_88F6920_PLUS)), MPP_MODE(42,
Signature · 1 line
2.1.0
PATCH 14/34 pinctrl: mvebu: armada-{370, 375, 38x, 39x}: normalize dev pins
Quoted 9 lines · Thomas Petazzoni
This commit modifies the definition of the Device Bus interface pins to be consistent accross SoCs. Especially, it removes the 'n' indicators that we don't encode in the subnames of pins:
'dev(wen0)' becomes 'dev(we0)' 'dev(wen1)' becomes 'dev(we1)' 'dev(oen)' becomes 'dev(oe)' etc.
Quoted 7 lines
In addition, it fixes the Armada 375 DT binding documentation, which forgot to document the 'dev' function for MPP46, MPP57 and MPP63.
Since only the subnames are changed, this commit does not affect DT compatibility.
Signed-off-by Thomas Petazzoni <[email protected]>
Patch applied.
Yours,
Linus Walleij
PATCH 15/34 pinctrl: mvebu: armada-39x: align NAND pin naming
In reply to Thomas PetazzoniAll SoCs use "nand" to designate NAND pins, only Armada 39x is using "nd", which is not consistent. This commit fixes that by renaming the corresponding functions.
It also changes the subnames from rbn0/rbn1 to rb0/rb1, to respect the convention used everywhere that we don't encode the 'n' part of signal names.
While this commit changes the main name of function, therefore potentially breaking the DT compatibility, this is not a problem since Armada 39x is a brand new SoC which isn't used in production yet.
--- .../devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt | 4 ++-- drivers/pinctrl/mvebu/pinctrl-armada-39x.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-)
Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt +2 -2
@@ -55,9 +55,9 @@ mpp37 37 gpio, sd0(d3), dev(ad8), ge(rxclk) mpp38 38 gpio, ref(clk), sd0(d0), dev(ad4), ge(rxd1) mpp39 39 gpio, i2c1(sck), ua0(cts), sd0(d1), dev(a2), ge(rxd2) mpp40 40 gpio, i2c1(sda), ua0(rts), sd0(d2), dev(ad6), ge(rxd3) -mpp41 41 gpio, ua1(rxd), ua0(cts), spi1(cs3), dev(burst/last), nd(rbn0), ge(rxctl) +mpp41 41 gpio, ua1(rxd), ua0(cts), spi1(cs3), dev(burst/last), nand(rb0), ge(rxctl) mpp42 42 gpio, ua1(txd), ua0(rts), dev(ad7) -mpp43 43 gpio, pcie0(clkreq), dram(vttctrl), dram(deccerr), spi1(cs2), dev(clkout), nd(rbn1) +mpp43 43 gpio, pcie0(clkreq), dram(vttctrl), dram(deccerr), spi1(cs2), dev(clkout), nand(rb1) mpp44 44 gpio, sata0(prsnt) [1], sata1(prsnt) [1], led(clk) mpp45 45 gpio, ref(clk), pcie0(rstout), ua1(rxd) mpp46 46 gpio, ref(clk), pcie0(rstout), ua1(txd), led(stb)
drivers/pinctrl/mvebu/pinctrl-armada-39x.c +2 -2
@@ -241,7 +241,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(3, "ua0", "cts", V_88F6920_PLUS), MPP_VAR_FUNCTION(4, "spi1", "cs3", V_88F6920_PLUS), MPP_VAR_FUNCTION(5, "dev", "burst/last", V_88F6920_PLUS), - MPP_VAR_FUNCTION(6, "nd", "rbn0", V_88F6920_PLUS), + MPP_VAR_FUNCTION(6, "nand", "rb0", V_88F6920_PLUS), MPP_VAR_FUNCTION(8, "ge", "rxctl", V_88F6920_PLUS)), MPP_MODE(42, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
@@ -255,7 +255,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(3, "dram", "deccerr", V_88F6920_PLUS), MPP_VAR_FUNCTION(4, "spi1", "cs2", V_88F6920_PLUS), MPP_VAR_FUNCTION(5, "dev", "clkout", V_88F6920_PLUS), - MPP_VAR_FUNCTION(6, "nd", "rbn1", V_88F6920_PLUS)), + MPP_VAR_FUNCTION(6, "nand", "rb1", V_88F6920_PLUS)), MPP_MODE(44, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6928),
Signature · 1 line
2.1.0
PATCH 15/34 pinctrl: mvebu: armada-39x: align NAND pin naming
Quoted 8 lines · Thomas Petazzoni
All SoCs use "nand" to designate NAND pins, only Armada 39x is using "nd", which is not consistent. This commit fixes that by renaming the corresponding functions.
It also changes the subnames from rbn0/rbn1 to rb0/rb1, to respect the convention used everywhere that we don't encode the 'n' part of signal names.
Quoted 5 lines
While this commit changes the main name of function, therefore potentially breaking the DT compatibility, this is not a problem since Armada 39x is a brand new SoC which isn't used in production yet.
Signed-off-by Thomas Petazzoni <[email protected]>
Patch applied.
Yours,
Linus Walleij
PATCH 15/34 pinctrl: mvebu: armada-39x: align NAND pin naming
In reply to Thomas PetazzoniQuoted 8 lines · Thomas Petazzoni
All SoCs use "nand" to designate NAND pins, only Armada 39x is using "nd", which is not consistent. This commit fixes that by renaming the corresponding functions.
It also changes the subnames from rbn0/rbn1 to rb0/rb1, to respect the convention used everywhere that we don't encode the 'n' part of signal names.
Quoted 5 lines
While this commit changes the main name of function, therefore potentially breaking the DT compatibility, this is not a problem since Armada 39x is a brand new SoC which isn't used in production yet.
Signed-off-by Thomas Petazzoni <[email protected]>
Patch applied.
Yours,
Linus Walleij
PATCH 16/34 pinctrl: mvebu: armada-{370, 375, 38x, 39x, xp}: normalize TDM pins
In reply to Thomas PetazzoniThis commit normalizes the naming of the TDM pins accross the different Marvell SoCs. Mainly it consists in:
* Removing the 'n' from signal names: 'intn' becomes 'int' and 'rstn' becomes 'rst'
* Renaming the main name 'tdm2c' to 'tdm' on Armada 38x.
* Change the main name 'tdm-1' to 'tdm' for one of the pins of the Armada XP
The last two changes affect DT compatibility, but since the TDM interface is nowhere near being supported in mainline, it should not be considered to be a serious problem at this point.
--- .../bindings/pinctrl/marvell,armada-370-pinctrl.txt | 2 +- .../bindings/pinctrl/marvell,armada-375-pinctrl.txt | 6 +++--- .../bindings/pinctrl/marvell,armada-38x-pinctrl.txt | 12 ++++++------ .../bindings/pinctrl/marvell,armada-39x-pinctrl.txt | 4 ++-- .../bindings/pinctrl/marvell,armada-xp-pinctrl.txt | 2 +- drivers/pinctrl/mvebu/pinctrl-armada-370.c | 2 +- drivers/pinctrl/mvebu/pinctrl-armada-375.c | 6 +++--- drivers/pinctrl/mvebu/pinctrl-armada-38x.c | 12 ++++++------ drivers/pinctrl/mvebu/pinctrl-armada-39x.c | 4 ++-- drivers/pinctrl/mvebu/pinctrl-armada-xp.c | 2 +- 10 files changed, 26 insertions(+), 26 deletions(-)
Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt +1 -1
@@ -20,7 +20,7 @@ mpp3 3 gpio, i2c0(sda), uart0(rxd) mpp4 4 gpio, cpu_pd(vdd) mpp5 5 gpo, ge0(txclko), uart1(txd), spi1(clk), audio(mclk) mpp6 6 gpio, ge0(txd0), sata0(prsnt), tdm(rst), audio(sdo) -mpp7 7 gpo, ge0(txd1), tdm(tdx), audio(lrclk) +mpp7 7 gpo, ge0(txd1), tdm(dtx), audio(lrclk) mpp8 8 gpio, ge0(txd2), uart0(rts), tdm(drx), audio(bclk) mpp9 9 gpo, ge0(txd3), uart1(txd), sd0(clk), audio(spdifo) mpp10 10 gpio, ge0(txctl), uart0(cts), tdm(fsync), audio(sdi)
Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt +3 -3
@@ -31,8 +31,8 @@ mpp14 14 gpio, i2c0(sda), uart1(txd) mpp15 15 gpio, i2c0(sck), uart1(rxd) mpp16 16 gpio, uart0(txd) mpp17 17 gpio, uart0(rxd) -mpp18 18 gpio, tdm(intn) -mpp19 19 gpio, tdm(rstn) +mpp18 18 gpio, tdm(int) +mpp19 19 gpio, tdm(rst) mpp20 20 gpio, tdm(pclk) mpp21 21 gpio, tdm(fsync) mpp22 22 gpio, tdm(drx)
@@ -50,7 +50,7 @@ mpp33 33 gpio, ge1(txd3), spi1(miso) mpp34 34 gpio, ge1(txclkout), spi1(sck) mpp35 35 gpio, ge1(rxctl), spi1(cs1), spi0(cs2) mpp36 36 gpio, pcie0(clkreq) -mpp37 37 gpio, pcie0(clkreq), tdm(intn), ge(mdc) +mpp37 37 gpio, pcie0(clkreq), tdm(int), ge(mdc) mpp38 38 gpio, pcie1(clkreq), ge(mdio) mpp39 39 gpio, ref(clkout) mpp40 40 gpio, uart1(txd)
Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt +6 -6
@@ -63,12 +63,12 @@ mpp44 44 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3 mpp45 45 gpio, ref(clk_out0), pcie0(rstout) mpp46 46 gpio, ref(clk_out1), pcie0(rstout) mpp47 47 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3(prsnt) [2] -mpp48 48 gpio, sata0(prsnt), dram(vttctrl), tdm2c(pclk), audio(mclk), sd0(d4), pcie0(clkreq) -mpp49 49 gpio, sata2(prsnt) [2], sata3(prsnt) [2], tdm2c(fsync), audio(lrclk), sd0(d5), pcie1(clkreq) -mpp50 50 gpio, pcie0(rstout), tdm2c(drx), audio(extclk), sd0(cmd) -mpp51 51 gpio, tdm2c(dtx), audio(sdo), dram(deccerr) -mpp52 52 gpio, pcie0(rstout), tdm2c(intn), audio(sdi), sd0(d6) -mpp53 53 gpio, sata1(prsnt), sata0(prsnt), tdm2c(rstn), audio(bclk), sd0(d7) +mpp48 48 gpio, sata0(prsnt), dram(vttctrl), tdm(pclk), audio(mclk), sd0(d4), pcie0(clkreq) +mpp49 49 gpio, sata2(prsnt) [2], sata3(prsnt) [2], tdm(fsync), audio(lrclk), sd0(d5), pcie1(clkreq) +mpp50 50 gpio, pcie0(rstout), tdm(drx), audio(extclk), sd0(cmd) +mpp51 51 gpio, tdm(dtx), audio(sdo), dram(deccerr) +mpp52 52 gpio, pcie0(rstout), tdm(int), audio(sdi), sd0(d6) +mpp53 53 gpio, sata1(prsnt), sata0(prsnt), tdm(rst), audio(bclk), sd0(d7) mpp54 54 gpio, sata0(prsnt), sata1(prsnt), pcie0(rstout), ge0(txerr), sd0(d3) mpp55 55 gpio, ua1(cts), ge(mdio), pcie1(clkreq) [1], spi1(cs1), sd0(d0) mpp56 56 gpio, ua1(rts), ge(mdc), dram(deccerr), spi1(mosi)
Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt +2 -2
@@ -66,8 +66,8 @@ mpp48 48 gpio, sata0(prsnt) [1], dram(vttctrl), tdm(pclk) [1], audio(mclk) [1], mpp49 49 gpio, tdm(fsync) [1], audio(lrclk) [1], sd0(d5), ua2(rxd) mpp50 50 gpio, pcie0(rstout), tdm(drx) [1], audio(extclk) [1], sd0(cmd), ua2(rxd) mpp51 51 gpio, tdm(dtx) [1], audio(sdo) [1], dram(deccerr), ua2(txd) -mpp52 52 gpio, pcie0(rstout), tdm(intn) [1], audio(sdi) [1], sd0(d6), i2c3(sck) -mpp53 53 gpio, sata1(prsnt) [1], sata0(prsnt) [1], tdm(rstn) [1], audio(bclk) [1], sd0(d7), i2c3(sda) +mpp52 52 gpio, pcie0(rstout), tdm(int) [1], audio(sdi) [1], sd0(d6), i2c3(sck) +mpp53 53 gpio, sata1(prsnt) [1], sata0(prsnt) [1], tdm(rst) [1], audio(bclk) [1], sd0(d7), i2c3(sda) mpp54 54 gpio, sata0(prsnt) [1], sata1(prsnt) [1], pcie0(rstout), sd0(d3), ua3(txd) mpp55 55 gpio, ua1(cts), spi1(cs1), sd0(d0), ua1(rxd), ua3(rxd) mpp56 56 gpio, ua1(rts), dram(deccerr), spi1(mosi), ua1(txd)
Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt +1 -1
@@ -61,7 +61,7 @@ mpp39 39 gpio, spi(cs0) mpp40 40 gpio, spi(cs1), uart2(cts), lcd(vga-hsync), pcie(clkreq0) mpp41 41 gpio, spi(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt), pcie(clkreq1) -mpp42 42 gpio, uart2(rxd), uart0(cts), tdm(int7), tdm-1(timer) +mpp42 42 gpio, uart2(rxd), uart0(cts), tdm(int7), tdm(timer) mpp43 43 gpio, uart2(txd), uart0(rts), spi(cs3), pcie(rstout) mpp44 44 gpio, uart2(cts), uart3(rxd), spi(cs4), pcie(clkreq2), dram(bat)
drivers/pinctrl/mvebu/pinctrl-armada-370.c +1 -1
@@ -68,7 +68,7 @@ static struct mvebu_mpp_mode mv88f6710_mpp_modes[] = {MPP_MODE (7 ,MPP_FUNCTION (0x0 ,"gpo" ,NULL ),MPP_FUNCTION (0x1 ,"ge0" ,"txd1" ), -MPP_FUNCTION (0x4 ,"tdm" ,"tdx" ), +MPP_FUNCTION (0x4 ,"tdm" ,"dtx" ),MPP_FUNCTION (0x5 ,"audio" ,"lrclk" )), MPP_MODE(8, MPP_FUNCTION(0x0, "gpio", NULL),
drivers/pinctrl/mvebu/pinctrl-armada-375.c +3 -3
@@ -141,10 +141,10 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_FUNCTION(0x2, "uart0", "rxd")),MPP_MODE (18 ,MPP_FUNCTION (0x0 ,"gpio" ,NULL ), -MPP_FUNCTION (0x2 ,"tdm" ,"intn" )), +MPP_FUNCTION (0x2 ,"tdm" ,"int" )),MPP_MODE (19 ,MPP_FUNCTION (0x0 ,"gpio" ,NULL ), -MPP_FUNCTION (0x2 ,"tdm" ,"rstn" )), +MPP_FUNCTION (0x2 ,"tdm" ,"rst" )),MPP_MODE (20 ,MPP_FUNCTION (0x0 ,"gpio" ,NULL ), MPP_FUNCTION(0x2, "tdm", "pclk")),
@@ -242,7 +242,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = {MPP_MODE (37 ,MPP_FUNCTION (0x0 ,"gpio" ,NULL ),MPP_FUNCTION (0x1 ,"pcie0" ,"clkreq" ), -MPP_FUNCTION (0x2 ,"tdm" ,"intn" ), +MPP_FUNCTION (0x2 ,"tdm" ,"int" ),MPP_FUNCTION (0x4 ,"ge" ,"mdc" )), MPP_MODE(38, MPP_FUNCTION(0x0, "gpio", NULL),
drivers/pinctrl/mvebu/pinctrl-armada-38x.c +6 -6
@@ -303,7 +303,7 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = {MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6810_PLUS ),MPP_VAR_FUNCTION (1 ,"sata0" ,"prsnt" ,V_88F6810_PLUS ),MPP_VAR_FUNCTION (2 ,"dram" ,"vttctrl" ,V_88F6810_PLUS ), -MPP_VAR_FUNCTION (3 ,"tdm2c" ,"pclk" ,V_88F6810_PLUS ), +MPP_VAR_FUNCTION (3 ,"tdm" ,"pclk" ,V_88F6810_PLUS ),MPP_VAR_FUNCTION (4 ,"audio" ,"mclk" ,V_88F6810_PLUS ),MPP_VAR_FUNCTION (5 ,"sd0" ,"d4" ,V_88F6810_PLUS ), MPP_VAR_FUNCTION(6, "pcie0", "clkreq", V_88F6810_PLUS)),
@@ -311,32 +311,32 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "sata2", "prsnt", V_88F6828), MPP_VAR_FUNCTION(2, "sata3", "prsnt", V_88F6828), - MPP_VAR_FUNCTION(3, "tdm2c", "fsync", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "tdm", "fsync", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "audio", "lrclk", V_88F6810_PLUS), MPP_VAR_FUNCTION(5, "sd0", "d5", V_88F6810_PLUS), MPP_VAR_FUNCTION(6, "pcie1", "clkreq", V_88F6820_PLUS)),MPP_MODE (50 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6810_PLUS ),MPP_VAR_FUNCTION (1 ,"pcie0" ,"rstout" ,V_88F6810_PLUS ), -MPP_VAR_FUNCTION (3 ,"tdm2c" ,"drx" ,V_88F6810_PLUS ), +MPP_VAR_FUNCTION (3 ,"tdm" ,"drx" ,V_88F6810_PLUS ),MPP_VAR_FUNCTION (4 ,"audio" ,"extclk" ,V_88F6810_PLUS ),MPP_VAR_FUNCTION (5 ,"sd0" ,"cmd" ,V_88F6810_PLUS )),MPP_MODE (51 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6810_PLUS ), -MPP_VAR_FUNCTION (3 ,"tdm2c" ,"dtx" ,V_88F6810_PLUS ), +MPP_VAR_FUNCTION (3 ,"tdm" ,"dtx" ,V_88F6810_PLUS ),MPP_VAR_FUNCTION (4 ,"audio" ,"sdo" ,V_88F6810_PLUS ),MPP_VAR_FUNCTION (5 ,"dram" ,"deccerr" ,V_88F6810_PLUS )),MPP_MODE (52 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6810_PLUS ),MPP_VAR_FUNCTION (1 ,"pcie0" ,"rstout" ,V_88F6810_PLUS ), -MPP_VAR_FUNCTION (3 ,"tdm2c" ,"intn" ,V_88F6810_PLUS ), +MPP_VAR_FUNCTION (3 ,"tdm" ,"int" ,V_88F6810_PLUS ),MPP_VAR_FUNCTION (4 ,"audio" ,"sdi" ,V_88F6810_PLUS ),MPP_VAR_FUNCTION (5 ,"sd0" ,"d6" ,V_88F6810_PLUS )),MPP_MODE (53 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6810_PLUS ),MPP_VAR_FUNCTION (1 ,"sata1" ,"prsnt" ,V_88F6810_PLUS ),MPP_VAR_FUNCTION (2 ,"sata0" ,"prsnt" ,V_88F6810_PLUS ), -MPP_VAR_FUNCTION (3 ,"tdm2c" ,"rstn" ,V_88F6810_PLUS ), +MPP_VAR_FUNCTION (3 ,"tdm" ,"rst" ,V_88F6810_PLUS ),MPP_VAR_FUNCTION (4 ,"audio" ,"bclk" ,V_88F6810_PLUS ),MPP_VAR_FUNCTION (5 ,"sd0" ,"d7" ,V_88F6810_PLUS )), MPP_MODE(54,
drivers/pinctrl/mvebu/pinctrl-armada-39x.c +2 -2
@@ -308,7 +308,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = {MPP_MODE (52 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (1 ,"pcie0" ,"rstout" ,V_88F6920_PLUS ), -MPP_VAR_FUNCTION (3 ,"tdm" ,"intn" ,V_88F6928 ), +MPP_VAR_FUNCTION (3 ,"tdm" ,"int" ,V_88F6928 ),MPP_VAR_FUNCTION (4 ,"audio" ,"sdi" ,V_88F6928 ),MPP_VAR_FUNCTION (5 ,"sd0" ,"d6" ,V_88F6920_PLUS ), MPP_VAR_FUNCTION(7, "i2c3", "sck", V_88F6920_PLUS)),
@@ -316,7 +316,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = {MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (1 ,"sata1" ,"prsnt" ,V_88F6928 ),MPP_VAR_FUNCTION (2 ,"sata0" ,"prsnt" ,V_88F6928 ), -MPP_VAR_FUNCTION (3 ,"tdm" ,"rstn" ,V_88F6928 ), +MPP_VAR_FUNCTION (3 ,"tdm" ,"rst" ,V_88F6928 ),MPP_VAR_FUNCTION (4 ,"audio" ,"bclk" ,V_88F6928 ),MPP_VAR_FUNCTION (5 ,"sd0" ,"d7" ,V_88F6920_PLUS ), MPP_VAR_FUNCTION(7, "i2c3", "sda", V_88F6920_PLUS)),
drivers/pinctrl/mvebu/pinctrl-armada-xp.c +1 -1
@@ -252,7 +252,7 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x1, "uart2", "rxd", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart0", "cts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x3, "tdm", "int7", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x4, "tdm-1", "timer", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x4, "tdm", "timer", V_MV78230_PLUS)), MPP_MODE(43, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "uart2", "txd", V_MV78230_PLUS),
Signature · 1 line
2.1.0
PATCH 16/34 pinctrl: mvebu: armada-{370,375,38x,39x,xp}: normalize TDM pins
Quoted 8 lines · Thomas Petazzoni
This commit normalizes the naming of the TDM pins accross the different Marvell SoCs. Mainly it consists in:
* Removing the 'n' from signal names: 'intn' becomes 'int' and 'rstn' becomes 'rst'
* Renaming the main name 'tdm2c' to 'tdm' on Armada 38x.
Quoted 8 lines
* Change the main name 'tdm-1' to 'tdm' for one of the pins of the Armada XP
The last two changes affect DT compatibility, but since the TDM interface is nowhere near being supported in mainline, it should not be considered to be a serious problem at this point.
Signed-off-by Thomas Petazzoni <[email protected]>
Patch applied.
Yours,
Linus Walleij
PATCH 17/34 pinctrl: mvebu: armada-{370,375}: normalize PCIe pins
In reply to Thomas PetazzoniThis commit normalizes the naming of PCIe pins to use 'rstout' instead of 'rstoutn' or 'rst-out'.
Since only the subnames are changed, DT compatibility is not affected.
--- .../bindings/pinctrl/marvell,armada-370-pinctrl.txt | 2 +- .../bindings/pinctrl/marvell,armada-375-pinctrl.txt | 8 ++++---- drivers/pinctrl/mvebu/pinctrl-armada-370.c | 2 +- drivers/pinctrl/mvebu/pinctrl-armada-375.c | 14 +++++++------- 4 files changed, 13 insertions(+), 13 deletions(-)
Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt +1 -1
@@ -86,7 +86,7 @@ mpp57 57 gpio, dev(cs3), uart1(rxd), tdm(fsync), sata0(prsnt), mpp58 58 gpio, dev(cs0), uart1(rts), tdm(int), audio(extclk), uart0(rts) mpp59 59 gpo, dev(ale0), uart1(rts), uart0(rts), audio(bclk) -mpp60 60 gpio, dev(ale1), uart1(rxd), sata0(prsnt), pcie(rst-out), +mpp60 60 gpio, dev(ale1), uart1(rxd), sata0(prsnt), pcie(rstout), audio(sdi) mpp61 61 gpo, dev(we1), uart1(txd), audio(rclk) mpp62 62 gpio, dev(a2), uart1(cts), tdm(drx), pcie(clkreq0),
Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt +4 -4
@@ -26,7 +26,7 @@ mpp9 9 gpio, spi0(sck), spi1(sck), nand(we) mpp10 10 gpio, dram(vttctrl), led(c1), nand(re) mpp11 11 gpio, dev(a0), led(c2), audio(sdo) mpp12 12 gpio, dev(a1), audio(bclk) -mpp13 13 gpio, dev(ready), pcie0(rstoutn), pcie1(rstoutn) +mpp13 13 gpio, dev(ready), pcie0(rstout), pcie1(rstout) mpp14 14 gpio, i2c0(sda), uart1(txd) mpp15 15 gpio, i2c0(sck), uart1(rxd) mpp16 16 gpio, uart0(txd)
@@ -58,7 +58,7 @@ mpp41 41 gpio, uart1(rxd) mpp42 42 gpio, spi1(cs2), led(c0) mpp43 43 gpio, sata0(prsnt), dram(vttctrl) mpp44 44 gpio, sata0(prsnt) -mpp45 45 gpio, spi0(cs2), pcie0(rstoutn) +mpp45 45 gpio, spi0(cs2), pcie0(rstout) mpp46 46 gpio, led(p0), ge0(txd0), ge1(txd0), dev(we1) mpp47 47 gpio, led(p1), ge0(txd1), ge1(txd1) mpp48 48 gpio, led(p2), ge0(txd2), ge1(txd2)
@@ -66,8 +66,8 @@ mpp49 49 gpio, led(p3), ge0(txd3), ge1(txd3) mpp50 50 gpio, led(c0), ge0(rxd0), ge1(rxd0) mpp51 51 gpio, led(c1), ge0(rxd1), ge1(rxd1) mpp52 52 gpio, led(c2), ge0(rxd2), ge1(rxd2) -mpp53 53 gpio, pcie1(rstoutn), ge0(rxd3), ge1(rxd3) -mpp54 54 gpio, pcie0(rstoutn), ge0(rxctl), ge1(rxctl) +mpp53 53 gpio, pcie1(rstout), ge0(rxd3), ge1(rxd3) +mpp54 54 gpio, pcie0(rstout), ge0(rxctl), ge1(rxctl) mpp55 55 gpio, ge0(rxclk), ge1(rxclk) mpp56 56 gpio, ge0(txclkout), ge1(txclkout) mpp57 57 gpio, ge0(txctl), ge1(txctl), dev(we0)
drivers/pinctrl/mvebu/pinctrl-armada-370.c +1 -1
@@ -348,7 +348,7 @@ static struct mvebu_mpp_mode mv88f6710_mpp_modes[] = { MPP_FUNCTION(0x1, "dev", "ale1"), MPP_FUNCTION(0x2, "uart1", "rxd"), MPP_FUNCTION(0x3, "sata0", "prsnt"), - MPP_FUNCTION(0x4, "pcie", "rst-out"), + MPP_FUNCTION(0x4, "pcie", "rstout"), MPP_FUNCTION(0x5, "audio", "sdi")), MPP_MODE(61, MPP_FUNCTION(0x0, "gpo", NULL),
drivers/pinctrl/mvebu/pinctrl-armada-375.c +7 -7
@@ -121,8 +121,8 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = {MPP_MODE (13 ,MPP_FUNCTION (0x0 ,"gpio" ,NULL ),MPP_FUNCTION (0x1 ,"dev" ,"ready" ), -MPP_FUNCTION (0x2 ,"pcie0" ,"rstoutn" ), -MPP_FUNCTION (0x3 ,"pcie1" ,"rstoutn" ), +MPP_FUNCTION (0x2 ,"pcie0" ,"rstout" ), +MPP_FUNCTION (0x3 ,"pcie1" ,"rstout" ),MPP_FUNCTION (0x5 ,"nand" ,"rb" ),MPP_FUNCTION (0x6 ,"spi1" ,"mosi" )), MPP_MODE(14,
@@ -201,7 +201,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_FUNCTION(0x2, "ge1", "rxclk"), MPP_FUNCTION(0x3, "sd", "d3"), MPP_FUNCTION(0x5, "spi0", "sck"), - MPP_FUNCTION(0x6, "pcie0", "rstoutn")), + MPP_FUNCTION(0x6, "pcie0", "rstout")), MPP_MODE(30, MPP_FUNCTION(0x0, "gpio", NULL), MPP_FUNCTION(0x2, "ge1", "txd0"),
@@ -276,7 +276,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = {MPP_MODE (45 ,MPP_FUNCTION (0x0 ,"gpio" ,NULL ),MPP_FUNCTION (0x2 ,"spi0" ,"cs2" ), -MPP_FUNCTION (0x4 ,"pcie0" ,"rstoutn" ), +MPP_FUNCTION (0x4 ,"pcie0" ,"rstout" ),MPP_FUNCTION (0x5 ,"led" ,"c2" ),MPP_FUNCTION (0x6 ,"spi1" ,"cs2" )), MPP_MODE(46,
@@ -326,14 +326,14 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_FUNCTION(0x6, "dev", "ad9")),MPP_MODE (53 ,MPP_FUNCTION (0x0 ,"gpio" ,NULL ), -MPP_FUNCTION (0x1 ,"pcie1" ,"rstoutn" ), +MPP_FUNCTION (0x1 ,"pcie1" ,"rstout" ),MPP_FUNCTION (0x2 ,"ge0" ,"rxd3" ),MPP_FUNCTION (0x3 ,"ge1" ,"rxd3" ),MPP_FUNCTION (0x5 ,"i2c0" ,"sck" ),MPP_FUNCTION (0x6 ,"dev" ,"ad10" )),MPP_MODE (54 ,MPP_FUNCTION (0x0 ,"gpio" ,NULL ), -MPP_FUNCTION (0x1 ,"pcie0" ,"rstoutn" ), +MPP_FUNCTION (0x1 ,"pcie0" ,"rstout" ),MPP_FUNCTION (0x2 ,"ge0" ,"rxctl" ),MPP_FUNCTION (0x3 ,"ge1" ,"rxctl" ), MPP_FUNCTION(0x6, "dev", "ad11")),
@@ -391,7 +391,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = {MPP_FUNCTION (0x0 ,"gpio" ,NULL ),MPP_FUNCTION (0x2 ,"ptp" ,"evreq" ),MPP_FUNCTION (0x4 ,"spi1" ,"cs3" ), -MPP_FUNCTION (0x5 ,"pcie0" ,"rstoutn" ), +MPP_FUNCTION (0x5 ,"pcie0" ,"rstout" ), MPP_FUNCTION(0x6, "dev", "cs3")), };
Signature · 1 line
2.1.0
PATCH 17/34 pinctrl: mvebu: armada-{370, 375}: normalize PCIe pins
Quoted 6 lines · Thomas Petazzoni
This commit normalizes the naming of PCIe pins to use 'rstout' instead of 'rstoutn' or 'rst-out'.
Since only the subnames are changed, DT compatibility is not affected.
Signed-off-by Thomas Petazzoni <[email protected]>
Patch applied.
Yours,
Linus Walleij
PATCH 18/34 pinctrl: mvebu: armada-{370,375}: normalize audio pins
In reply to Thomas PetazzoniThis commit aligns the naming of the audio 'lrclk' pin accross Marvell SoCs.
Since only the subname is changed, the DT backward compatibility is not affected.
--- .../devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt | 2 +- .../devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt | 2 +- drivers/pinctrl/mvebu/pinctrl-armada-370.c | 2 +- drivers/pinctrl/mvebu/pinctrl-armada-375.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-)
Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt +1 -1
@@ -88,7 +88,7 @@ mpp58 58 gpio, dev(cs0), uart1(rts), tdm(int), audio(extclk), mpp59 59 gpo, dev(ale0), uart1(rts), uart0(rts), audio(bclk) mpp60 60 gpio, dev(ale1), uart1(rxd), sata0(prsnt), pcie(rstout), audio(sdi) -mpp61 61 gpo, dev(we1), uart1(txd), audio(rclk) +mpp61 61 gpo, dev(we1), uart1(txd), audio(lrclk) mpp62 62 gpio, dev(a2), uart1(cts), tdm(drx), pcie(clkreq0), audio(mclk), uart0(cts) mpp63 63 gpo, spi0(sck), tclk
Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt +1 -1
@@ -19,7 +19,7 @@ mpp2 2 gpio, dev(ad4), ptp(evreq), led(c0), audio(sdi) mpp3 3 gpio, dev(ad5), ptp(trig), led(p3), audio(mclk) mpp4 4 gpio, dev(ad6), spi0(miso), spi1(miso) mpp5 5 gpio, dev(ad7), spi0(cs2), spi1(cs2) -mpp6 6 gpio, dev(ad0), led(p1), audio(rclk) +mpp6 6 gpio, dev(ad0), led(p1), audio(lrclk) mpp7 7 gpio, dev(ad1), ptp(clk), led(p2), audio(extclk) mpp8 8 gpio, dev (bootcs), spi0(cs0), spi1(cs0) mpp9 9 gpio, spi0(sck), spi1(sck), nand(we)
drivers/pinctrl/mvebu/pinctrl-armada-370.c +1 -1
@@ -354,7 +354,7 @@ static struct mvebu_mpp_mode mv88f6710_mpp_modes[] = { MPP_FUNCTION(0x0, "gpo", NULL), MPP_FUNCTION(0x1, "dev", "we1"), MPP_FUNCTION(0x2, "uart1", "txd"), - MPP_FUNCTION(0x5, "audio", "rclk")), + MPP_FUNCTION(0x5, "audio", "lrclk")), MPP_MODE(62, MPP_FUNCTION(0x0, "gpio", NULL), MPP_FUNCTION(0x1, "dev", "a2"),
drivers/pinctrl/mvebu/pinctrl-armada-375.c +1 -1
@@ -81,7 +81,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_FUNCTION(0x0, "gpio", NULL), MPP_FUNCTION(0x1, "dev", "ad0"), MPP_FUNCTION(0x3, "led", "p1"), - MPP_FUNCTION(0x4, "audio", "rclk"), + MPP_FUNCTION(0x4, "audio", "lrclk"), MPP_FUNCTION(0x5, "nand", "io0")), MPP_MODE(7, MPP_FUNCTION(0x0, "gpio", NULL),
Signature · 1 line
2.1.0
PATCH 18/34 pinctrl: mvebu: armada-{370, 375}: normalize audio pins
Quoted 7 lines · Thomas Petazzoni
This commit aligns the naming of the audio 'lrclk' pin accross Marvell SoCs.
Since only the subname is changed, the DT backward compatibility is not affected.
Signed-off-by Thomas Petazzoni <[email protected]>
Patch applied.
Yours,
Linus Walleij
PATCH 19/34 pinctrl: mvebu: armada-{370, xp}: normalize ethernet txclkout pins
In reply to Thomas PetazzoniThis commit normalizes the naming of the Ethernet txclkout pin to be the same accross Marvell SoCs. It is worth mentioning that the DT binding documentation of the Armada XP was wrong for MPP12: it said the function was ge1(txd0), while it is in fact ge1(txclkout). It is however not really a fix worth sending to stable since it does not change the behavior, and the driver itself was correct.
Since only the subnames are changed, DT backward compatibility is not affected.
--- .../devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt | 2 +- .../devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt | 4 ++-- drivers/pinctrl/mvebu/pinctrl-armada-370.c | 2 +- drivers/pinctrl/mvebu/pinctrl-armada-xp.c | 4 ++-- 4 files changed, 6 insertions(+), 6 deletions(-)
Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt +1 -1
@@ -18,7 +18,7 @@ mpp1 1 gpo, uart0(txd) mpp2 2 gpio, i2c0(sck), uart0(txd) mpp3 3 gpio, i2c0(sda), uart0(rxd) mpp4 4 gpio, cpu_pd(vdd) -mpp5 5 gpo, ge0(txclko), uart1(txd), spi1(clk), audio(mclk) +mpp5 5 gpo, ge0(txclkout), uart1(txd), spi1(clk), audio(mclk) mpp6 6 gpio, ge0(txd0), sata0(prsnt), tdm(rst), audio(sdo) mpp7 7 gpo, ge0(txd1), tdm(dtx), audio(lrclk) mpp8 8 gpio, ge0(txd2), uart0(rts), tdm(drx), audio(bclk)
Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt +2 -2
@@ -18,7 +18,7 @@ only for more detailed description in this document. name pins functions ================================================================================ -mpp0 0 gpio, ge0(txclko), lcd(d0) +mpp0 0 gpio, ge0(txclkout), lcd(d0) mpp1 1 gpio, ge0(txd0), lcd(d1) mpp2 2 gpio, ge0(txd1), lcd(d2) mpp3 3 gpio, ge0(txd2), lcd(d3)
@@ -30,7 +30,7 @@ mpp8 8 gpio, ge0(rxd2), lcd(d8) mpp9 9 gpio, ge0(rxd3), lcd(d9) mpp10 10 gpio, ge0(rxctl), lcd(d10) mpp11 11 gpio, ge0(rxclk), lcd(d11) -mpp12 12 gpio, ge0(txd4), ge1(txd0), lcd(d12) +mpp12 12 gpio, ge0(txd4), ge1(txclkout), lcd(d12) mpp13 13 gpio, ge0(txd5), ge1(txd1), lcd(d13) mpp14 14 gpio, ge0(txd6), ge1(txd2), lcd(d15) mpp15 15 gpio, ge0(txd7), ge1(txd3), lcd(d16)
drivers/pinctrl/mvebu/pinctrl-armada-370.c +1 -1
@@ -55,7 +55,7 @@ static struct mvebu_mpp_mode mv88f6710_mpp_modes[] = { MPP_FUNCTION(0x1, "cpu_pd", "vdd")),MPP_MODE (5 ,MPP_FUNCTION (0x0 ,"gpo" ,NULL ), -MPP_FUNCTION (0x1 ,"ge0" ,"txclko" ), +MPP_FUNCTION (0x1 ,"ge0" ,"txclkout" ),MPP_FUNCTION (0x2 ,"uart1" ,"txd" ),MPP_FUNCTION (0x4 ,"spi1" ,"clk" ), MPP_FUNCTION(0x5, "audio", "mclk")),
drivers/pinctrl/mvebu/pinctrl-armada-xp.c +2 -2
@@ -54,7 +54,7 @@ enum armada_xp_variant {static struct mvebu_mpp_mode armada_xp_mpp_modes[] = {MPP_MODE (0 ,MPP_VAR_FUNCTION (0x0 ,"gpio" ,NULL ,V_MV78230_PLUS ), -MPP_VAR_FUNCTION (0x1 ,"ge0" ,"txclko" ,V_MV78230_PLUS ), +MPP_VAR_FUNCTION (0x1 ,"ge0" ,"txclkout" ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x4 ,"lcd" ,"d0" ,V_MV78230_PLUS )), MPP_MODE(1, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
@@ -103,7 +103,7 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = {MPP_MODE (12 ,MPP_VAR_FUNCTION (0x0 ,"gpio" ,NULL ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x1 ,"ge0" ,"txd4" ,V_MV78230_PLUS ), -MPP_VAR_FUNCTION (0x2 ,"ge1" ,"clkout" ,V_MV78230_PLUS ), +MPP_VAR_FUNCTION (0x2 ,"ge1" ,"txclkout" ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x4 ,"lcd" ,"d12" ,V_MV78230_PLUS )), MPP_MODE(13, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
Signature · 1 line
2.1.0
PATCH 19/34 pinctrl: mvebu: armada-{370, xp}: normalize ethernet txclkout pins
Quoted 11 lines · Thomas Petazzoni
This commit normalizes the naming of the Ethernet txclkout pin to be the same accross Marvell SoCs. It is worth mentioning that the DT binding documentation of the Armada XP was wrong for MPP12: it said the function was ge1(txd0), while it is in fact ge1(txclkout). It is however not really a fix worth sending to stable since it does not change the behavior, and the driver itself was correct.
Since only the subnames are changed, DT backward compatibility is not affected.
Signed-off-by Thomas Petazzoni <[email protected]>
Patch applied.
Yours,
Linus Walleij
PATCH 20/34 pinctrl: mvebu: armada-xp: fix binding documentation of ge1 pins
In reply to Thomas PetazzoniThere was an off-by-one in the documentation of the ge1(txd[0-3]) pins, which is fixed by this commit. Since the driver was correct, and the subnames are anyway not used in the DT binding itself, there is no need to push this documentation fix for stable.
--- .../devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt +3 -3
@@ -31,9 +31,9 @@ mpp9 9 gpio, ge0(rxd3), lcd(d9) mpp10 10 gpio, ge0(rxctl), lcd(d10) mpp11 11 gpio, ge0(rxclk), lcd(d11) mpp12 12 gpio, ge0(txd4), ge1(txclkout), lcd(d12) -mpp13 13 gpio, ge0(txd5), ge1(txd1), lcd(d13) -mpp14 14 gpio, ge0(txd6), ge1(txd2), lcd(d15) -mpp15 15 gpio, ge0(txd7), ge1(txd3), lcd(d16) +mpp13 13 gpio, ge0(txd5), ge1(txd0), lcd(d13) +mpp14 14 gpio, ge0(txd6), ge1(txd1), lcd(d15) +mpp15 15 gpio, ge0(txd7), ge1(txd2), lcd(d16) mpp16 16 gpio, ge0(txd7), ge1(txd3), lcd(d16) mpp17 17 gpio, ge0(col), ge1(txctl), lcd(d17) mpp18 18 gpio, ge0(rxerr), ge1(rxd0), lcd(d18), ptp(trig)
Signature · 1 line
2.1.0
PATCH 20/34 pinctrl: mvebu: armada-xp: fix binding documentation of ge1 pins
Quoted 6 lines · Thomas Petazzoni
There was an off-by-one in the documentation of the
ge1(txd[0-3])pins, which is fixed by this commit. Since the driver was correct, and the subnames are anyway not used in the DT binding itself, there is no need to push this documentation fix for stable.Signed-off-by Thomas Petazzoni <[email protected]>
Patch applied.
Yours,
Linus Walleij
PATCH 21/34 pinctrl: mvebu: armada-370: align VDD cpu-pd pin naming with datasheet
In reply to Thomas PetazzoniFor consistency with the datasheet, this commit renames the VDD function of the MPP4 pin.
While this changes the DT compatibility, it is not considered to be a problem since this pin is unlikely to be used for anything but debugging purposes.
--- .../devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt | 2 +- drivers/pinctrl/mvebu/pinctrl-armada-370.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt +1 -1
@@ -17,7 +17,7 @@ mpp0 0 gpio, uart0(rxd) mpp1 1 gpo, uart0(txd) mpp2 2 gpio, i2c0(sck), uart0(txd) mpp3 3 gpio, i2c0(sda), uart0(rxd) -mpp4 4 gpio, cpu_pd(vdd) +mpp4 4 gpio, vdd(cpu-pd) mpp5 5 gpo, ge0(txclkout), uart1(txd), spi1(clk), audio(mclk) mpp6 6 gpio, ge0(txd0), sata0(prsnt), tdm(rst), audio(sdo) mpp7 7 gpo, ge0(txd1), tdm(dtx), audio(lrclk)
drivers/pinctrl/mvebu/pinctrl-armada-370.c +1 -1
@@ -52,7 +52,7 @@ static struct mvebu_mpp_mode mv88f6710_mpp_modes[] = { MPP_FUNCTION(0x2, "uart0", "rxd")),MPP_MODE (4 ,MPP_FUNCTION (0x0 ,"gpio" ,NULL ), -MPP_FUNCTION (0x1 ,"cpu_pd" ,"vdd" )), +MPP_FUNCTION (0x1 ,"vdd" ,"cpu-pd" )), MPP_MODE(5, MPP_FUNCTION(0x0, "gpo", NULL), MPP_FUNCTION(0x1, "ge0", "txclkout"),
Signature · 1 line
2.1.0
PATCH 21/34 pinctrl: mvebu: armada-370: align VDD cpu-pd pin naming with datasheet
Quoted 8 lines · Thomas Petazzoni
For consistency with the datasheet, this commit renames the VDD function of the MPP4 pin.
While this changes the DT compatibility, it is not considered to be a problem since this pin is unlikely to be used for anything but debugging purposes.
Signed-off-by Thomas Petazzoni <[email protected]>
Patch applied.
Yours,
Linus Walleij
PATCH 22/34 pinctrl: mvebu: armada-370: align spi1 clock pin naming
In reply to Thomas PetazzoniAcross all SoCs, even on Armada 370 for SPI0, the clock pin uses the 'sck' subname and not 'clk', so this commit adjusts the code and documentation accordingly.
Since this commit only changes the subname, DT backward compatibility is not affected.
--- .../devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt | 2 +- drivers/pinctrl/mvebu/pinctrl-armada-370.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt +1 -1
@@ -18,7 +18,7 @@ mpp1 1 gpo, uart0(txd) mpp2 2 gpio, i2c0(sck), uart0(txd) mpp3 3 gpio, i2c0(sda), uart0(rxd) mpp4 4 gpio, vdd(cpu-pd) -mpp5 5 gpo, ge0(txclkout), uart1(txd), spi1(clk), audio(mclk) +mpp5 5 gpo, ge0(txclkout), uart1(txd), spi1(sck), audio(mclk) mpp6 6 gpio, ge0(txd0), sata0(prsnt), tdm(rst), audio(sdo) mpp7 7 gpo, ge0(txd1), tdm(dtx), audio(lrclk) mpp8 8 gpio, ge0(txd2), uart0(rts), tdm(drx), audio(bclk)
drivers/pinctrl/mvebu/pinctrl-armada-370.c +1 -1
@@ -57,7 +57,7 @@ static struct mvebu_mpp_mode mv88f6710_mpp_modes[] = { MPP_FUNCTION(0x0, "gpo", NULL), MPP_FUNCTION(0x1, "ge0", "txclkout"), MPP_FUNCTION(0x2, "uart1", "txd"), - MPP_FUNCTION(0x4, "spi1", "clk"), + MPP_FUNCTION(0x4, "spi1", "sck"), MPP_FUNCTION(0x5, "audio", "mclk")), MPP_MODE(6, MPP_FUNCTION(0x0, "gpio", NULL),
Signature · 1 line
2.1.0
PATCH 22/34 pinctrl: mvebu: armada-370: align spi1 clock pin naming
Quoted 8 lines · Thomas Petazzoni
Across all SoCs, even on Armada 370 for SPI0, the clock pin uses the 'sck' subname and not 'clk', so this commit adjusts the code and documentation accordingly.
Since this commit only changes the subname, DT backward compatibility is not affected.
Signed-off-by Thomas Petazzoni <[email protected]>
Patch applied.
Yours,
Linus Walleij
PATCH 23/34 pinctrl: mvebu: armada-xp: rename spi to spi0
In reply to Thomas PetazzoniAfter updating to the latest Armada XP datasheet, we discovered that there is a second SPI bus accessible from the MPP pins, called 'spi1'.
In order to be consistent with other SoCs having two SPI busses, this commit renames the functions of the first SPI bus to 'spi0' instead of just 'spi'.
This commit obviously breaks the DT backward compatibility for the people using the "spi" function name in their Device Tree.
--- .../bindings/pinctrl/marvell,armada-xp-pinctrl.txt | 22 +++++++++++----------- drivers/pinctrl/mvebu/pinctrl-armada-xp.c | 22 +++++++++++----------- 2 files changed, 22 insertions(+), 22 deletions(-)
Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt +11 -11
@@ -54,20 +54,20 @@ mpp32 32 gpio, tdm(int3), sd0(d0) mpp33 33 gpio, tdm(int4), sd0(d1), dram(bat) mpp34 34 gpio, tdm(int5), sd0(d2), sata0(prsnt) mpp35 35 gpio, tdm(int6), sd0(d3), sata1(prsnt) -mpp36 36 gpio, spi(mosi) -mpp37 37 gpio, spi(miso) -mpp38 38 gpio, spi(sck) -mpp39 39 gpio, spi(cs0) -mpp40 40 gpio, spi(cs1), uart2(cts), lcd(vga-hsync), pcie(clkreq0) -mpp41 41 gpio, spi(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt), +mpp36 36 gpio, spi0(mosi) +mpp37 37 gpio, spi0(miso) +mpp38 38 gpio, spi0(sck) +mpp39 39 gpio, spi0(cs0) +mpp40 40 gpio, spi0(cs1), uart2(cts), lcd(vga-hsync), pcie(clkreq0) +mpp41 41 gpio, spi0(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt), pcie(clkreq1) mpp42 42 gpio, uart2(rxd), uart0(cts), tdm(int7), tdm(timer) -mpp43 43 gpio, uart2(txd), uart0(rts), spi(cs3), pcie(rstout) -mpp44 44 gpio, uart2(cts), uart3(rxd), spi(cs4), pcie(clkreq2), +mpp43 43 gpio, uart2(txd), uart0(rts), spi0(cs3), pcie(rstout) +mpp44 44 gpio, uart2(cts), uart3(rxd), spi0(cs4), pcie(clkreq2), dram(bat) -mpp45 45 gpio, uart2(rts), uart3(txd), spi(cs5), sata1(prsnt) -mpp46 46 gpio, uart3(rts), uart1(rts), spi(cs6), sata0(prsnt) -mpp47 47 gpio, uart3(cts), uart1(cts), spi(cs7), pcie(clkreq3), +mpp45 45 gpio, uart2(rts), uart3(txd), spi0(cs5), sata1(prsnt) +mpp46 46 gpio, uart3(rts), uart1(rts), spi0(cs6), sata0(prsnt) +mpp47 47 gpio, uart3(cts), uart1(cts), spi0(cs7), pcie(clkreq3), ref(clkout) mpp48 48 gpio, dev(clkout), dev(burst/last)
drivers/pinctrl/mvebu/pinctrl-armada-xp.c +11 -11
@@ -224,25 +224,25 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x3, "tdm", "int6", V_MV78230_PLUS)),MPP_MODE (36 ,MPP_VAR_FUNCTION (0x0 ,"gpio" ,NULL ,V_MV78230_PLUS ), -MPP_VAR_FUNCTION (0x1 ,"spi" ,"mosi" ,V_MV78230_PLUS )), +MPP_VAR_FUNCTION (0x1 ,"spi0" ,"mosi" ,V_MV78230_PLUS )),MPP_MODE (37 ,MPP_VAR_FUNCTION (0x0 ,"gpio" ,NULL ,V_MV78230_PLUS ), -MPP_VAR_FUNCTION (0x1 ,"spi" ,"miso" ,V_MV78230_PLUS )), +MPP_VAR_FUNCTION (0x1 ,"spi0" ,"miso" ,V_MV78230_PLUS )),MPP_MODE (38 ,MPP_VAR_FUNCTION (0x0 ,"gpio" ,NULL ,V_MV78230_PLUS ), -MPP_VAR_FUNCTION (0x1 ,"spi" ,"sck" ,V_MV78230_PLUS )), +MPP_VAR_FUNCTION (0x1 ,"spi0" ,"sck" ,V_MV78230_PLUS )),MPP_MODE (39 ,MPP_VAR_FUNCTION (0x0 ,"gpio" ,NULL ,V_MV78230_PLUS ), -MPP_VAR_FUNCTION (0x1 ,"spi" ,"cs0" ,V_MV78230_PLUS )), +MPP_VAR_FUNCTION (0x1 ,"spi0" ,"cs0" ,V_MV78230_PLUS )),MPP_MODE (40 ,MPP_VAR_FUNCTION (0x0 ,"gpio" ,NULL ,V_MV78230_PLUS ), -MPP_VAR_FUNCTION (0x1 ,"spi" ,"cs1" ,V_MV78230_PLUS ), +MPP_VAR_FUNCTION (0x1 ,"spi0" ,"cs1" ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x2 ,"uart2" ,"cts" ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x4 ,"lcd" ,"vga-hsync" ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x5 ,"pcie" ,"clkreq0" ,V_MV78230_PLUS )), MPP_MODE(41, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x1, "spi", "cs2", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x1, "spi0", "cs2", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart2", "rts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x3, "sata1", "prsnt", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "lcd", "vga-vsync", V_MV78230_PLUS),
@@ -257,32 +257,32 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "uart2", "txd", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart0", "rts", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x3, "spi", "cs3", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x3, "spi0", "cs3", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "pcie", "rstout", V_MV78230_PLUS)),MPP_MODE (44 ,MPP_VAR_FUNCTION (0x0 ,"gpio" ,NULL ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x1 ,"uart2" ,"cts" ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x2 ,"uart3" ,"rxd" ,V_MV78230_PLUS ), -MPP_VAR_FUNCTION (0x3 ,"spi" ,"cs4" ,V_MV78230_PLUS ), +MPP_VAR_FUNCTION (0x3 ,"spi0" ,"cs4" ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x4 ,"dram" ,"bat" ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x5 ,"pcie" ,"clkreq2" ,V_MV78230_PLUS )),MPP_MODE (45 ,MPP_VAR_FUNCTION (0x0 ,"gpio" ,NULL ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x1 ,"uart2" ,"rts" ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x2 ,"uart3" ,"txd" ,V_MV78230_PLUS ), -MPP_VAR_FUNCTION (0x3 ,"spi" ,"cs5" ,V_MV78230_PLUS ), +MPP_VAR_FUNCTION (0x3 ,"spi0" ,"cs5" ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x4 ,"sata1" ,"prsnt" ,V_MV78230_PLUS )),MPP_MODE (46 ,MPP_VAR_FUNCTION (0x0 ,"gpio" ,NULL ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x1 ,"uart3" ,"rts" ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x2 ,"uart1" ,"rts" ,V_MV78230_PLUS ), -MPP_VAR_FUNCTION (0x3 ,"spi" ,"cs6" ,V_MV78230_PLUS ), +MPP_VAR_FUNCTION (0x3 ,"spi0" ,"cs6" ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x4 ,"sata0" ,"prsnt" ,V_MV78230_PLUS )),MPP_MODE (47 ,MPP_VAR_FUNCTION (0x0 ,"gpio" ,NULL ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x1 ,"uart3" ,"cts" ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x2 ,"uart1" ,"cts" ,V_MV78230_PLUS ), -MPP_VAR_FUNCTION (0x3 ,"spi" ,"cs7" ,V_MV78230_PLUS ), +MPP_VAR_FUNCTION (0x3 ,"spi0" ,"cs7" ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x4 ,"ref" ,"clkout" ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x5 ,"pcie" ,"clkreq3" ,V_MV78230_PLUS )), MPP_MODE(48,
Signature · 1 line
2.1.0
Andrew Lunn
maintainerPATCH 23/34 pinctrl: mvebu: armada-xp: rename spi to spi0
Quoted 9 lines · Thomas Petazzoni
After updating to the latest Armada XP datasheet, we discovered that there is a second SPI bus accessible from the MPP pins, called 'spi1'.
In order to be consistent with other SoCs having two SPI busses, this commit renames the functions of the first SPI bus to 'spi0' instead of just 'spi'.
This commit obviously breaks the DT backward compatibility for the people using the "spi" function name in their Device Tree.
Hi Thomas
Should this patch also contain a change to armada-xp.dtsi:
spi0_pins: spi0-pins {
marvell,pins = "mpp36", "mpp37",
"mpp38", "mpp39";
marvell,function = "spi";
};
AndrewPATCH 23/34 pinctrl: mvebu: armada-xp: rename spi to spi0
Quoted 1 line · Andrew Lunn
Should this patch also contain a change to
armada-xp.dtsi:
I prefer to not carry dt patches in the pinctrl tree.
That part of the kernel should one day go into a separate git so it is OK to patch it separately through ARM SoC.
Yours,
Linus Walleij
PATCH 23/34 pinctrl: mvebu: armada-xp: rename spi to spi0
In reply to Thomas PetazzoniQuoted 11 lines · Thomas Petazzoni
After updating to the latest Armada XP datasheet, we discovered that there is a second SPI bus accessible from the MPP pins, called 'spi1'.
In order to be consistent with other SoCs having two SPI busses, this commit renames the functions of the first SPI bus to 'spi0' instead of just 'spi'.
This commit obviously breaks the DT backward compatibility for the people using the "spi" function name in their Device Tree.
Signed-off-by Thomas Petazzoni <[email protected]>
Patch applied.
Yours,
Linus Walleij
PATCH 24/34 pinctrl: mvebu: armada-39x: normalize ref clock naming
In reply to Thomas PetazzoniThis commit normalizes the subnames of the reference clock MPP pins in the Armada 39x pinctrl driver to match with the name used on other SoCs.
Since only the subnames are changed, DT backward compatibility is not affected.
--- drivers/pinctrl/mvebu/pinctrl-armada-39x.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
drivers/pinctrl/mvebu/pinctrl-armada-39x.c +4 -4
@@ -205,7 +205,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(5, "dev", "ad1", V_88F6920_PLUS)),MPP_MODE (35 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6920_PLUS ), -MPP_VAR_FUNCTION (1 ,"ref" ,"clk" ,V_88F6920_PLUS ), +MPP_VAR_FUNCTION (1 ,"ref" ,"clk_out1" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (5 ,"dev" ,"a1" ,V_88F6920_PLUS )), MPP_MODE(36, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
@@ -217,7 +217,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(8, "ge", "rxclk", V_88F6920_PLUS)),MPP_MODE (38 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6920_PLUS ), -MPP_VAR_FUNCTION (3 ,"ref" ,"clk" ,V_88F6920_PLUS ), +MPP_VAR_FUNCTION (3 ,"ref" ,"clk_out0" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (4 ,"sd0" ,"d0" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (5 ,"dev" ,"ad4" ,V_88F6920_PLUS ), MPP_VAR_FUNCTION(8, "ge", "rxd1", V_88F6920_PLUS)),
@@ -263,12 +263,12 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(7, "led", "clk", V_88F6920_PLUS)),MPP_MODE (45 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6920_PLUS ), -MPP_VAR_FUNCTION (1 ,"ref" ,"clk" ,V_88F6920_PLUS ), +MPP_VAR_FUNCTION (1 ,"ref" ,"clk_out0" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (2 ,"pcie0" ,"rstout" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (6 ,"ua1" ,"rxd" ,V_88F6920_PLUS )),MPP_MODE (46 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6920_PLUS ), -MPP_VAR_FUNCTION (1 ,"ref" ,"clk" ,V_88F6920_PLUS ), +MPP_VAR_FUNCTION (1 ,"ref" ,"clk_out1" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (2 ,"pcie0" ,"rstout" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (6 ,"ua1" ,"txd" ,V_88F6920_PLUS ), MPP_VAR_FUNCTION(7, "led", "stb", V_88F6920_PLUS)),
Signature · 1 line
2.1.0
PATCH 24/34 pinctrl: mvebu: armada-39x: normalize ref clock naming
Quoted 8 lines · Thomas Petazzoni
This commit normalizes the subnames of the reference clock MPP pins in the Armada 39x pinctrl driver to match with the name used on other SoCs.
Since only the subnames are changed, DT backward compatibility is not affected.
Signed-off-by Thomas Petazzoni <[email protected]>
Patch applied.
Yours,
Linus Walleij
PATCH 25/34 pinctrl: mvebu: armada-xp: add spi1 function
In reply to Thomas PetazzoniThe latest Armada XP datasheet documents that some of the MPP pins can be used to access the second SPI bus, labelled 'spi1'. This commit adds the corresponding pins in the pinctrl driver and its DT binding documentation.
--- .../bindings/pinctrl/marvell,armada-xp-pinctrl.txt | 26 +++++++++++++--------- drivers/pinctrl/mvebu/pinctrl-armada-xp.c | 25 +++++++++++++++------ 2 files changed, 33 insertions(+), 18 deletions(-)
Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt +15 -11
@@ -31,11 +31,11 @@ mpp9 9 gpio, ge0(rxd3), lcd(d9) mpp10 10 gpio, ge0(rxctl), lcd(d10) mpp11 11 gpio, ge0(rxclk), lcd(d11) mpp12 12 gpio, ge0(txd4), ge1(txclkout), lcd(d12) -mpp13 13 gpio, ge0(txd5), ge1(txd0), lcd(d13) -mpp14 14 gpio, ge0(txd6), ge1(txd1), lcd(d15) +mpp13 13 gpio, ge0(txd5), ge1(txd0), spi1(mosi), lcd(d13) +mpp14 14 gpio, ge0(txd6), ge1(txd1), spi1(sck), lcd(d15) mpp15 15 gpio, ge0(txd7), ge1(txd2), lcd(d16) -mpp16 16 gpio, ge0(txd7), ge1(txd3), lcd(d16) -mpp17 17 gpio, ge0(col), ge1(txctl), lcd(d17) +mpp16 16 gpio, ge0(txd7), ge1(txd3), spi1(cs0), lcd(d16) +mpp17 17 gpio, ge0(col), ge1(txctl), spi1(miso), lcd(d17) mpp18 18 gpio, ge0(rxerr), ge1(rxd0), lcd(d18), ptp(trig) mpp19 19 gpio, ge0(crs), ge1(rxd1), lcd(d19), ptp(evreq) mpp20 20 gpio, ge0(rxd4), ge1(rxd2), lcd(d20), ptp(clk)
@@ -58,17 +58,21 @@ mpp36 36 gpio, spi0(mosi) mpp37 37 gpio, spi0(miso) mpp38 38 gpio, spi0(sck) mpp39 39 gpio, spi0(cs0) -mpp40 40 gpio, spi0(cs1), uart2(cts), lcd(vga-hsync), pcie(clkreq0) +mpp40 40 gpio, spi0(cs1), uart2(cts), lcd(vga-hsync), pcie(clkreq0), + spi1(cs1) mpp41 41 gpio, spi0(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt), - pcie(clkreq1) + pcie(clkreq1), spi1(cs2) mpp42 42 gpio, uart2(rxd), uart0(cts), tdm(int7), tdm(timer) -mpp43 43 gpio, uart2(txd), uart0(rts), spi0(cs3), pcie(rstout) +mpp43 43 gpio, uart2(txd), uart0(rts), spi0(cs3), pcie(rstout), + spi1(cs3) mpp44 44 gpio, uart2(cts), uart3(rxd), spi0(cs4), pcie(clkreq2), - dram(bat) -mpp45 45 gpio, uart2(rts), uart3(txd), spi0(cs5), sata1(prsnt) -mpp46 46 gpio, uart3(rts), uart1(rts), spi0(cs6), sata0(prsnt) + dram(bat), spi1(cs4) +mpp45 45 gpio, uart2(rts), uart3(txd), spi0(cs5), sata1(prsnt), + spi1(cs5) +mpp46 46 gpio, uart3(rts), uart1(rts), spi0(cs6), sata0(prsnt), + spi1(cs6) mpp47 47 gpio, uart3(cts), uart1(cts), spi0(cs7), pcie(clkreq3), - ref(clkout) + ref(clkout), spi1(cs7) mpp48 48 gpio, dev(clkout), dev(burst/last) * Marvell Armada XP (mv78260 and mv78460 only)
drivers/pinctrl/mvebu/pinctrl-armada-xp.c +18 -7
@@ -109,11 +109,13 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "ge0", "txd5", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "ge1", "txd0", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x3, "spi1", "mosi", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "lcd", "d13", V_MV78230_PLUS)),MPP_MODE (14 ,MPP_VAR_FUNCTION (0x0 ,"gpio" ,NULL ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x1 ,"ge0" ,"txd6" ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x2 ,"ge1" ,"txd1" ,V_MV78230_PLUS ), +MPP_VAR_FUNCTION (0x3 ,"spi1" ,"sck" ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x4 ,"lcd" ,"d14" ,V_MV78230_PLUS )), MPP_MODE(15, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
@@ -124,11 +126,13 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "ge0", "txclk", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "ge1", "txd3", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x3, "spi1", "cs0", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "lcd", "d16", V_MV78230_PLUS)),MPP_MODE (17 ,MPP_VAR_FUNCTION (0x0 ,"gpio" ,NULL ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x1 ,"ge0" ,"col" ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x2 ,"ge1" ,"txctl" ,V_MV78230_PLUS ), +MPP_VAR_FUNCTION (0x3 ,"spi1" ,"miso" ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x4 ,"lcd" ,"d17" ,V_MV78230_PLUS )), MPP_MODE(18, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
@@ -239,14 +243,16 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x1, "spi0", "cs1", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart2", "cts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "lcd", "vga-hsync", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x5, "pcie", "clkreq0", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x5, "pcie", "clkreq0", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x6, "spi1", "cs1", V_MV78230_PLUS)),MPP_MODE (41 ,MPP_VAR_FUNCTION (0x0 ,"gpio" ,NULL ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x1 ,"spi0" ,"cs2" ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x2 ,"uart2" ,"rts" ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x3 ,"sata1" ,"prsnt" ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x4 ,"lcd" ,"vga-vsync" ,V_MV78230_PLUS ), -MPP_VAR_FUNCTION (0x5 ,"pcie" ,"clkreq1" ,V_MV78230_PLUS )), +MPP_VAR_FUNCTION (0x5 ,"pcie" ,"clkreq1" ,V_MV78230_PLUS ), +MPP_VAR_FUNCTION (0x6 ,"spi1" ,"cs2" ,V_MV78230_PLUS )), MPP_MODE(42, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "uart2", "rxd", V_MV78230_PLUS),
@@ -258,33 +264,38 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x1, "uart2", "txd", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart0", "rts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x3, "spi0", "cs3", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x4, "pcie", "rstout", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x4, "pcie", "rstout", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x6, "spi1", "cs3", V_MV78230_PLUS)),MPP_MODE (44 ,MPP_VAR_FUNCTION (0x0 ,"gpio" ,NULL ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x1 ,"uart2" ,"cts" ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x2 ,"uart3" ,"rxd" ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x3 ,"spi0" ,"cs4" ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x4 ,"dram" ,"bat" ,V_MV78230_PLUS ), -MPP_VAR_FUNCTION (0x5 ,"pcie" ,"clkreq2" ,V_MV78230_PLUS )), +MPP_VAR_FUNCTION (0x5 ,"pcie" ,"clkreq2" ,V_MV78230_PLUS ), +MPP_VAR_FUNCTION (0x6 ,"spi1" ,"cs4" ,V_MV78230_PLUS )),MPP_MODE (45 ,MPP_VAR_FUNCTION (0x0 ,"gpio" ,NULL ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x1 ,"uart2" ,"rts" ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x2 ,"uart3" ,"txd" ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x3 ,"spi0" ,"cs5" ,V_MV78230_PLUS ), -MPP_VAR_FUNCTION (0x4 ,"sata1" ,"prsnt" ,V_MV78230_PLUS )), +MPP_VAR_FUNCTION (0x4 ,"sata1" ,"prsnt" ,V_MV78230_PLUS ), +MPP_VAR_FUNCTION (0x6 ,"spi1" ,"cs5" ,V_MV78230_PLUS )),MPP_MODE (46 ,MPP_VAR_FUNCTION (0x0 ,"gpio" ,NULL ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x1 ,"uart3" ,"rts" ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x2 ,"uart1" ,"rts" ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x3 ,"spi0" ,"cs6" ,V_MV78230_PLUS ), -MPP_VAR_FUNCTION (0x4 ,"sata0" ,"prsnt" ,V_MV78230_PLUS )), +MPP_VAR_FUNCTION (0x4 ,"sata0" ,"prsnt" ,V_MV78230_PLUS ), +MPP_VAR_FUNCTION (0x6 ,"spi1" ,"cs6" ,V_MV78230_PLUS )),MPP_MODE (47 ,MPP_VAR_FUNCTION (0x0 ,"gpio" ,NULL ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x1 ,"uart3" ,"cts" ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x2 ,"uart1" ,"cts" ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x3 ,"spi0" ,"cs7" ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x4 ,"ref" ,"clkout" ,V_MV78230_PLUS ), -MPP_VAR_FUNCTION (0x5 ,"pcie" ,"clkreq3" ,V_MV78230_PLUS )), +MPP_VAR_FUNCTION (0x5 ,"pcie" ,"clkreq3" ,V_MV78230_PLUS ), +MPP_VAR_FUNCTION (0x6 ,"spi1" ,"cs7" ,V_MV78230_PLUS )), MPP_MODE(48, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "dev", "clkout", V_MV78230_PLUS),
Signature · 1 line
2.1.0
PATCH 25/34 pinctrl: mvebu: armada-xp: add spi1 function
Quoted 6 lines · Thomas Petazzoni
The latest Armada XP datasheet documents that some of the MPP pins can be used to access the second SPI bus, labelled 'spi1'. This commit adds the corresponding pins in the pinctrl driver and its DT binding documentation.
Signed-off-by Thomas Petazzoni <[email protected]>
Patch applied.
Yours,
Linus Walleij
PATCH 26/34 pinctrl: mvebu: armada-xp: add nand rb function
In reply to Thomas PetazzoniThe latest version of the Armada XP datasheet documents a new NAND-related MPP function on MPP48, for which this commit adds support.
--- .../devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt | 2 +- drivers/pinctrl/mvebu/pinctrl-armada-xp.c | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-)
Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt +1 -1
@@ -73,7 +73,7 @@ mpp46 46 gpio, uart3(rts), uart1(rts), spi0(cs6), sata0(prsnt), spi1(cs6) mpp47 47 gpio, uart3(cts), uart1(cts), spi0(cs7), pcie(clkreq3), ref(clkout), spi1(cs7) -mpp48 48 gpio, dev(clkout), dev(burst/last) +mpp48 48 gpio, dev(clkout), dev(burst/last), nand(rb) * Marvell Armada XP (mv78260 and mv78460 only)
drivers/pinctrl/mvebu/pinctrl-armada-xp.c +2 -1
@@ -299,7 +299,8 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = {MPP_MODE (48 ,MPP_VAR_FUNCTION (0x0 ,"gpio" ,NULL ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x1 ,"dev" ,"clkout" ,V_MV78230_PLUS ), -MPP_VAR_FUNCTION (0x2 ,"dev" ,"burst/last" ,V_MV78230_PLUS )), +MPP_VAR_FUNCTION (0x2 ,"dev" ,"burst/last" ,V_MV78230_PLUS ), +MPP_VAR_FUNCTION (0x3 ,"nand" ,"rb" ,V_MV78230_PLUS )),MPP_MODE (49 ,MPP_VAR_FUNCTION (0x0 ,"gpio" ,NULL ,V_MV78260_PLUS ), MPP_VAR_FUNCTION(0x1, "dev", "we3", V_MV78260_PLUS)),
Signature · 1 line
2.1.0
PATCH 26/34 pinctrl: mvebu: armada-xp: add nand rb function
Quoted 5 lines · Thomas Petazzoni
The latest version of the Armada XP datasheet documents a new NAND-related MPP function on MPP48, for which this commit adds support.
Signed-off-by Thomas Petazzoni <[email protected]>
Patch applied.
Yours,
Linus Walleij
PATCH 27/34 pinctrl: mvebu: armada-xp: add dram functions
In reply to Thomas PetazzoniThe latest Armada XP datasheet documents several new DRAM related functions on various MPPs. This commit adds the description of these new functions in the Armada XP pinctrl driver and its DT binding documentation.
--- .../devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt | 6 +++--- drivers/pinctrl/mvebu/pinctrl-armada-xp.c | 7 +++++-- 2 files changed, 8 insertions(+), 5 deletions(-)
Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt +3 -3
@@ -51,8 +51,8 @@ mpp29 29 gpio, lcd(ref-clk), tdm(int0), ptp(clk) mpp30 30 gpio, tdm(int1), sd0(clk) mpp31 31 gpio, tdm(int2), sd0(cmd) mpp32 32 gpio, tdm(int3), sd0(d0) -mpp33 33 gpio, tdm(int4), sd0(d1), dram(bat) -mpp34 34 gpio, tdm(int5), sd0(d2), sata0(prsnt) +mpp33 33 gpio, tdm(int4), sd0(d1), dram(bat), dram(vttctrl) +mpp34 34 gpio, tdm(int5), sd0(d2), sata0(prsnt), dram(deccerr) mpp35 35 gpio, tdm(int6), sd0(d3), sata1(prsnt) mpp36 36 gpio, spi0(mosi) mpp37 37 gpio, spi0(miso)
@@ -68,7 +68,7 @@ mpp43 43 gpio, uart2(txd), uart0(rts), spi0(cs3), pcie(rstout), mpp44 44 gpio, uart2(cts), uart3(rxd), spi0(cs4), pcie(clkreq2), dram(bat), spi1(cs4) mpp45 45 gpio, uart2(rts), uart3(txd), spi0(cs5), sata1(prsnt), - spi1(cs5) + spi1(cs5), dram(vttctrl) mpp46 46 gpio, uart3(rts), uart1(rts), spi0(cs6), sata0(prsnt), spi1(cs6) mpp47 47 gpio, uart3(cts), uart1(cts), spi0(cs7), pcie(clkreq3),
drivers/pinctrl/mvebu/pinctrl-armada-xp.c +5 -2
@@ -215,12 +215,14 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "sd0", "d1", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x3, "tdm", "int4", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x4, "dram", "bat", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x4, "dram", "bat", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x5, "dram", "vttctrl", V_MV78230_PLUS)),MPP_MODE (34 ,MPP_VAR_FUNCTION (0x0 ,"gpio" ,NULL ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x1 ,"sd0" ,"d2" ,V_MV78230_PLUS ),MPP_VAR_FUNCTION (0x2 ,"sata0" ,"prsnt" ,V_MV78230_PLUS ), -MPP_VAR_FUNCTION (0x3 ,"tdm" ,"int5" ,V_MV78230_PLUS )), +MPP_VAR_FUNCTION (0x3 ,"tdm" ,"int5" ,V_MV78230_PLUS ), +MPP_VAR_FUNCTION (0x4 ,"dram" ,"deccerr" ,V_MV78230_PLUS )), MPP_MODE(35, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "sd0", "d3", V_MV78230_PLUS),
@@ -280,6 +282,7 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x2, "uart3", "txd", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x3, "spi0", "cs5", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "sata1", "prsnt", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x5, "dram", "vttctrl", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x6, "spi1", "cs5", V_MV78230_PLUS)), MPP_MODE(46, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
Signature · 1 line
2.1.0
PATCH 27/34 pinctrl: mvebu: armada-xp: add dram functions
Quoted 6 lines · Thomas Petazzoni
The latest Armada XP datasheet documents several new DRAM related functions on various MPPs. This commit adds the description of these new functions in the Armada XP pinctrl driver and its DT binding documentation.
Signed-off-by Thomas Petazzoni <[email protected]>
Patch applied.
Yours,
Linus Walleij
PATCH 28/34 pinctrl: mvebu: armada-38x: add sata functions
In reply to Thomas PetazzoniThe latest version of the Armada 38x datasheet documents several new SATA related functions on various MPP pins. This commit adds the description of these new functions to the Armada 38x pinctrl driver as well as to its DT binding documentation.
--- .../devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt | 4 ++-- drivers/pinctrl/mvebu/pinctrl-armada-38x.c | 6 ++++-- 2 files changed, 6 insertions(+), 4 deletions(-)
Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt +2 -2
@@ -32,11 +32,11 @@ mpp13 13 gpio, ge0(rxd1), pcie0(clkreq), pcie1(clkreq) [1], spi0(c mpp14 14 gpio, ge0(rxd2), ptp(clk), dram(vttctrl), spi0(cs3), dev(we1), pcie3(clkreq) mpp15 15 gpio, ge0(rxd3), ge(mdc slave), pcie0(rstout), spi0(mosi) mpp16 16 gpio, ge0(rxctl), ge(mdio slave), dram(deccerr), spi0(miso), pcie0(clkreq), pcie1(clkreq) [1] -mpp17 17 gpio, ge0(rxclk), ptp(clk), ua1(rxd), spi0(sck), sata1(prsnt) +mpp17 17 gpio, ge0(rxclk), ptp(clk), ua1(rxd), spi0(sck), sata1(prsnt), sata0(prsnt) mpp18 18 gpio, ge0(rxerr), ptp(trig), ua1(txd), spi0(cs0) mpp19 19 gpio, ge0(col), ptp(evreq), ge0(txerr), sata1(prsnt), ua0(cts) mpp20 20 gpio, ge0(txclk), ptp(clk), sata0(prsnt), ua0(rts) -mpp21 21 gpio, spi0(cs1), ge1(rxd0), sata0(prsnt), sd0(cmd), dev(bootcs) +mpp21 21 gpio, spi0(cs1), ge1(rxd0), sata0(prsnt), sd0(cmd), dev(bootcs), sata1(prsnt) mpp22 22 gpio, spi0(mosi), dev(ad0) mpp23 23 gpio, spi0(sck), dev(ad2) mpp24 24 gpio, spi0(miso), ua0(cts), ua1(rxd), sd0(d4), dev(ready)
drivers/pinctrl/mvebu/pinctrl-armada-38x.c +4 -2
@@ -133,7 +133,8 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(2, "ptp", "clk", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "ua1", "rxd", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "spi0", "sck", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "sata1", "prsnt", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(5, "sata1", "prsnt", V_88F6810_PLUS), + MPP_VAR_FUNCTION(6, "sata0", "prsnt", V_88F6810_PLUS)), MPP_MODE(18, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "ge0", "rxerr", V_88F6810_PLUS),
@@ -161,7 +162,8 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(2, "ge1", "rxd0", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "sata0", "prsnt", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "sd0", "cmd", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "dev", "bootcs", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(5, "dev", "bootcs", V_88F6810_PLUS), + MPP_VAR_FUNCTION(6, "sata1", "prsnt", V_88F6810_PLUS)), MPP_MODE(22, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "spi0", "mosi", V_88F6810_PLUS),
Signature · 1 line
2.1.0
PATCH 28/34 pinctrl: mvebu: armada-38x: add sata functions
Quoted 6 lines · Thomas Petazzoni
The latest version of the Armada 38x datasheet documents several new SATA related functions on various MPP pins. This commit adds the description of these new functions to the Armada 38x pinctrl driver as well as to its DT binding documentation.
Signed-off-by Thomas Petazzoni <[email protected]>
Patch applied.
Yours,
Linus Walleij
PATCH 29/34 pinctrl: mvebu: armada-38x: add nand functions
In reply to Thomas PetazzoniThe latest version of the Armada 38x datasheet documents several new NAND related functions on various MPP pins. This commit adds the description of these new functions to the Armada 38x pinctrl driver as well as to its DT binding documentation.
--- .../devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt | 4 ++-- drivers/pinctrl/mvebu/pinctrl-armada-38x.c | 6 ++++-- 2 files changed, 6 insertions(+), 4 deletions(-)
Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt +2 -2
@@ -56,9 +56,9 @@ mpp37 37 gpio, ptp(clk), ge1(rxclk), sd0(d3), dev(ad8) mpp38 38 gpio, ptp(evreq), ge1(rxd1), ref(clk_out0), sd0(d0), dev(ad4) mpp39 39 gpio, i2c1(sck), ge1(rxd2), ua0(cts), sd0(d1), dev(a2) mpp40 40 gpio, i2c1(sda), ge1(rxd3), ua0(rts), sd0(d2), dev(ad6) -mpp41 41 gpio, ua1(rxd), ge1(rxctl), ua0(cts), spi1(cs3), dev(burst/last) +mpp41 41 gpio, ua1(rxd), ge1(rxctl), ua0(cts), spi1(cs3), dev(burst/last), nand(rb0) mpp42 42 gpio, ua1(txd), ua0(rts), dev(ad7) -mpp43 43 gpio, pcie0(clkreq), dram(vttctrl), dram(deccerr), spi1(cs2), dev(clkout) +mpp43 43 gpio, pcie0(clkreq), dram(vttctrl), dram(deccerr), spi1(cs2), dev(clkout), nand(rb1) mpp44 44 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3(prsnt) [3] mpp45 45 gpio, ref(clk_out0), pcie0(rstout) mpp46 46 gpio, ref(clk_out1), pcie0(rstout)
drivers/pinctrl/mvebu/pinctrl-armada-38x.c +4 -2
@@ -268,7 +268,8 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(2, "ge1", "rxctl", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "ua0", "cts", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "spi1", "cs3", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "dev", "burst/last", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(5, "dev", "burst/last", V_88F6810_PLUS), + MPP_VAR_FUNCTION(6, "nand", "rb0", V_88F6810_PLUS)), MPP_MODE(42, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "ua1", "txd", V_88F6810_PLUS),
@@ -280,7 +281,8 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(2, "dram", "vttctrl", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "dram", "deccerr", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "spi1", "cs2", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "dev", "clkout", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(5, "dev", "clkout", V_88F6810_PLUS), + MPP_VAR_FUNCTION(6, "nand", "rb1", V_88F6810_PLUS)), MPP_MODE(44, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6810_PLUS),
Signature · 1 line
2.1.0
PATCH 29/34 pinctrl: mvebu: armada-38x: add nand functions
Quoted 6 lines · Thomas Petazzoni
The latest version of the Armada 38x datasheet documents several new NAND related functions on various MPP pins. This commit adds the description of these new functions to the Armada 38x pinctrl driver as well as to its DT binding documentation.
Signed-off-by Thomas Petazzoni <[email protected]>
Patch applied.
Yours,
Linus Walleij
PATCH 30/34 pinctrl: mvebu: armada-38x: add ua1 functions
In reply to Thomas PetazzoniThe latest version of the Armada 38x datasheet documents several new UART1 related functions on various MPP pins. This commit adds the description of these new functions to the Armada 38x pinctrl driver as well as to its DT binding documentation.
--- .../bindings/pinctrl/marvell,armada-38x-pinctrl.txt | 12 ++++++------ drivers/pinctrl/mvebu/pinctrl-armada-38x.c | 18 ++++++++++++------ 2 files changed, 18 insertions(+), 12 deletions(-)
Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt +6 -6
@@ -60,8 +60,8 @@ mpp41 41 gpio, ua1(rxd), ge1(rxctl), ua0(cts), spi1(cs3), dev(burs mpp42 42 gpio, ua1(txd), ua0(rts), dev(ad7) mpp43 43 gpio, pcie0(clkreq), dram(vttctrl), dram(deccerr), spi1(cs2), dev(clkout), nand(rb1) mpp44 44 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3(prsnt) [3] -mpp45 45 gpio, ref(clk_out0), pcie0(rstout) -mpp46 46 gpio, ref(clk_out1), pcie0(rstout) +mpp45 45 gpio, ref(clk_out0), pcie0(rstout), ua1(rxd) +mpp46 46 gpio, ref(clk_out1), pcie0(rstout), ua1(txd) mpp47 47 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3(prsnt) [2] mpp48 48 gpio, sata0(prsnt), dram(vttctrl), tdm(pclk), audio(mclk), sd0(d4), pcie0(clkreq) mpp49 49 gpio, sata2(prsnt) [2], sata3(prsnt) [2], tdm(fsync), audio(lrclk), sd0(d5), pcie1(clkreq)
@@ -70,10 +70,10 @@ mpp51 51 gpio, tdm(dtx), audio(sdo), dram(deccerr) mpp52 52 gpio, pcie0(rstout), tdm(int), audio(sdi), sd0(d6) mpp53 53 gpio, sata1(prsnt), sata0(prsnt), tdm(rst), audio(bclk), sd0(d7) mpp54 54 gpio, sata0(prsnt), sata1(prsnt), pcie0(rstout), ge0(txerr), sd0(d3) -mpp55 55 gpio, ua1(cts), ge(mdio), pcie1(clkreq) [1], spi1(cs1), sd0(d0) -mpp56 56 gpio, ua1(rts), ge(mdc), dram(deccerr), spi1(mosi) -mpp57 57 gpio, spi1(sck), sd0(clk) -mpp58 58 gpio, pcie1(clkreq) [1], i2c1(sck), pcie2(clkreq), spi1(miso), sd0(d1) +mpp55 55 gpio, ua1(cts), ge(mdio), pcie1(clkreq) [1], spi1(cs1), sd0(d0), ua1(rxd) +mpp56 56 gpio, ua1(rts), ge(mdc), dram(deccerr), spi1(mosi), ua1(txd) +mpp57 57 gpio, spi1(sck), sd0(clk), ua1(txd) +mpp58 58 gpio, pcie1(clkreq) [1], i2c1(sck), pcie2(clkreq), spi1(miso), sd0(d1), ua1(rxd) mpp59 59 gpio, pcie0(rstout), i2c1(sda), spi1(cs0), sd0(d2) [1]: only available on 88F6820 and 88F6828
drivers/pinctrl/mvebu/pinctrl-armada-38x.c +12 -6
@@ -292,11 +292,13 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = {MPP_MODE (45 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6810_PLUS ),MPP_VAR_FUNCTION (1 ,"ref" ,"clk_out0" ,V_88F6810_PLUS ), -MPP_VAR_FUNCTION (2 ,"pcie0" ,"rstout" ,V_88F6810_PLUS )), +MPP_VAR_FUNCTION (2 ,"pcie0" ,"rstout" ,V_88F6810_PLUS ), +MPP_VAR_FUNCTION (6 ,"ua1" ,"rxd" ,V_88F6810_PLUS )),MPP_MODE (46 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6810_PLUS ),MPP_VAR_FUNCTION (1 ,"ref" ,"clk_out1" ,V_88F6810_PLUS ), -MPP_VAR_FUNCTION (2 ,"pcie0" ,"rstout" ,V_88F6810_PLUS )), +MPP_VAR_FUNCTION (2 ,"pcie0" ,"rstout" ,V_88F6810_PLUS ), +MPP_VAR_FUNCTION (6 ,"ua1" ,"txd" ,V_88F6810_PLUS )), MPP_MODE(47, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6810_PLUS),
@@ -356,24 +358,28 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(2, "ge", "mdio", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "pcie1", "clkreq", V_88F6820_PLUS), MPP_VAR_FUNCTION(4, "spi1", "cs1", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "sd0", "d0", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(5, "sd0", "d0", V_88F6810_PLUS), + MPP_VAR_FUNCTION(6, "ua1", "rxd", V_88F6810_PLUS)),MPP_MODE (56 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6810_PLUS ),MPP_VAR_FUNCTION (1 ,"ua1" ,"rts" ,V_88F6810_PLUS ),MPP_VAR_FUNCTION (2 ,"ge" ,"mdc" ,V_88F6810_PLUS ),MPP_VAR_FUNCTION (3 ,"dram" ,"deccerr" ,V_88F6810_PLUS ), -MPP_VAR_FUNCTION (4 ,"spi1" ,"mosi" ,V_88F6810_PLUS )), +MPP_VAR_FUNCTION (4 ,"spi1" ,"mosi" ,V_88F6810_PLUS ), +MPP_VAR_FUNCTION (6 ,"ua1" ,"txd" ,V_88F6810_PLUS )),MPP_MODE (57 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6810_PLUS ),MPP_VAR_FUNCTION (4 ,"spi1" ,"sck" ,V_88F6810_PLUS ), -MPP_VAR_FUNCTION (5 ,"sd0" ,"clk" ,V_88F6810_PLUS )), +MPP_VAR_FUNCTION (5 ,"sd0" ,"clk" ,V_88F6810_PLUS ), +MPP_VAR_FUNCTION (6 ,"ua1" ,"txd" ,V_88F6810_PLUS )),MPP_MODE (58 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6810_PLUS ),MPP_VAR_FUNCTION (1 ,"pcie1" ,"clkreq" ,V_88F6820_PLUS ),MPP_VAR_FUNCTION (2 ,"i2c1" ,"sck" ,V_88F6810_PLUS ),MPP_VAR_FUNCTION (3 ,"pcie2" ,"clkreq" ,V_88F6810_PLUS ),MPP_VAR_FUNCTION (4 ,"spi1" ,"miso" ,V_88F6810_PLUS ), -MPP_VAR_FUNCTION (5 ,"sd0" ,"d1" ,V_88F6810_PLUS )), +MPP_VAR_FUNCTION (5 ,"sd0" ,"d1" ,V_88F6810_PLUS ), +MPP_VAR_FUNCTION (6 ,"ua1" ,"rxd" ,V_88F6810_PLUS )), MPP_MODE(59, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6810_PLUS),
Signature · 1 line
2.1.0
PATCH 30/34 pinctrl: mvebu: armada-38x: add ua1 functions
Quoted 6 lines · Thomas Petazzoni
The latest version of the Armada 38x datasheet documents several new UART1 related functions on various MPP pins. This commit adds the description of these new functions to the Armada 38x pinctrl driver as well as to its DT binding documentation.
Signed-off-by Thomas Petazzoni <[email protected]>
Patch applied.
Yours,
Linus Walleij
PATCH 31/34 pinctrl: mvebu: armada-38x: add ptp functions
In reply to Thomas PetazzoniThe latest version of the Armada 38x datasheet documents several new PTP related functions on various MPP pins. This commit adds the description of these new functions to the Armada 38x pinctrl driver as well as to its DT binding documentation.
--- .../devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt | 6 +++--- drivers/pinctrl/mvebu/pinctrl-armada-38x.c | 9 ++++++--- 2 files changed, 9 insertions(+), 6 deletions(-)
Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt +3 -3
@@ -66,9 +66,9 @@ mpp47 47 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3 mpp48 48 gpio, sata0(prsnt), dram(vttctrl), tdm(pclk), audio(mclk), sd0(d4), pcie0(clkreq) mpp49 49 gpio, sata2(prsnt) [2], sata3(prsnt) [2], tdm(fsync), audio(lrclk), sd0(d5), pcie1(clkreq) mpp50 50 gpio, pcie0(rstout), tdm(drx), audio(extclk), sd0(cmd) -mpp51 51 gpio, tdm(dtx), audio(sdo), dram(deccerr) -mpp52 52 gpio, pcie0(rstout), tdm(int), audio(sdi), sd0(d6) -mpp53 53 gpio, sata1(prsnt), sata0(prsnt), tdm(rst), audio(bclk), sd0(d7) +mpp51 51 gpio, tdm(dtx), audio(sdo), dram(deccerr), ptp(trig) +mpp52 52 gpio, pcie0(rstout), tdm(int), audio(sdi), sd0(d6), ptp(clk) +mpp53 53 gpio, sata1(prsnt), sata0(prsnt), tdm(rst), audio(bclk), sd0(d7), ptp(evreq) mpp54 54 gpio, sata0(prsnt), sata1(prsnt), pcie0(rstout), ge0(txerr), sd0(d3) mpp55 55 gpio, ua1(cts), ge(mdio), pcie1(clkreq) [1], spi1(cs1), sd0(d0), ua1(rxd) mpp56 56 gpio, ua1(rts), ge(mdc), dram(deccerr), spi1(mosi), ua1(txd)
drivers/pinctrl/mvebu/pinctrl-armada-38x.c +6 -3
@@ -331,20 +331,23 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "tdm", "dtx", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "audio", "sdo", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "dram", "deccerr", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(5, "dram", "deccerr", V_88F6810_PLUS), + MPP_VAR_FUNCTION(6, "ptp", "trig", V_88F6810_PLUS)),MPP_MODE (52 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6810_PLUS ),MPP_VAR_FUNCTION (1 ,"pcie0" ,"rstout" ,V_88F6810_PLUS ),MPP_VAR_FUNCTION (3 ,"tdm" ,"int" ,V_88F6810_PLUS ),MPP_VAR_FUNCTION (4 ,"audio" ,"sdi" ,V_88F6810_PLUS ), -MPP_VAR_FUNCTION (5 ,"sd0" ,"d6" ,V_88F6810_PLUS )), +MPP_VAR_FUNCTION (5 ,"sd0" ,"d6" ,V_88F6810_PLUS ), +MPP_VAR_FUNCTION (6 ,"ptp" ,"clk" ,V_88F6810_PLUS )),MPP_MODE (53 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6810_PLUS ),MPP_VAR_FUNCTION (1 ,"sata1" ,"prsnt" ,V_88F6810_PLUS ),MPP_VAR_FUNCTION (2 ,"sata0" ,"prsnt" ,V_88F6810_PLUS ),MPP_VAR_FUNCTION (3 ,"tdm" ,"rst" ,V_88F6810_PLUS ),MPP_VAR_FUNCTION (4 ,"audio" ,"bclk" ,V_88F6810_PLUS ), -MPP_VAR_FUNCTION (5 ,"sd0" ,"d7" ,V_88F6810_PLUS )), +MPP_VAR_FUNCTION (5 ,"sd0" ,"d7" ,V_88F6810_PLUS ), +MPP_VAR_FUNCTION (6 ,"ptp" ,"evreq" ,V_88F6810_PLUS )), MPP_MODE(54, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6810_PLUS),
Signature · 1 line
2.1.0
PATCH 31/34 pinctrl: mvebu: armada-38x: add ptp functions
Quoted 6 lines · Thomas Petazzoni
The latest version of the Armada 38x datasheet documents several new PTP related functions on various MPP pins. This commit adds the description of these new functions to the Armada 38x pinctrl driver as well as to its DT binding documentation.
Signed-off-by Thomas Petazzoni <[email protected]>
Patch applied.
Yours,
Linus Walleij
PATCH 32/34 pinctrl: mvebu: armada-39x: add missing PCIe functions
In reply to Thomas PetazzoniThe latest version of the Armada 39x datasheet documents several new PCIe related functions on various MPP pins. This commit adds the description of these new functions to the Armada 39x pinctrl driver as well as to its DT binding documentation.
--- .../devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt | 4 ++-- drivers/pinctrl/mvebu/pinctrl-armada-39x.c | 2 ++ 2 files changed, 4 insertions(+), 2 deletions(-)
Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt +2 -2
@@ -27,10 +27,10 @@ mpp9 9 gpio, dev(ad11), ptp(clk) mpp10 10 gpio, dev(ad12), ptp(evreq) mpp11 11 gpio, dev(ad13), led(clk) mpp12 12 gpio, pcie0(rstout), dev(ad14), led(stb) -mpp13 13 gpio, dev(ad15), led(data) +mpp13 13 gpio, dev(ad15), pcie2(clkreq), led(data) mpp14 14 gpio, dram(vttctrl), dev(we1), ua1(txd) mpp15 15 gpio, pcie0(rstout), spi0(mosi), i2c1(sck) -mpp16 16 gpio, dram(deccerr), spi0(miso), i2c1(sda) +mpp16 16 gpio, dram(deccerr), spi0(miso), pcie0(clkreq), i2c1(sda) mpp17 17 gpio, ua1(rxd), spi0(sck), smi(mdio) mpp18 18 gpio, ua1(txd), spi0(cs0), i2c2(sck) mpp19 19 gpio, sata1(prsnt) [1], ua0(cts), ua1(rxd), i2c2(sda)
drivers/pinctrl/mvebu/pinctrl-armada-39x.c +2 -0
@@ -95,6 +95,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = {MPP_MODE (13 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (5 ,"dev" ,"ad15" ,V_88F6920_PLUS ), +MPP_VAR_FUNCTION (6 ,"pcie2" ,"clkreq" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (7 ,"led" ,"data" ,V_88F6920_PLUS )), MPP_MODE(14, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
@@ -110,6 +111,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "dram", "deccerr", V_88F6920_PLUS), MPP_VAR_FUNCTION(4, "spi0", "miso", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "pcie0", "clkreq", V_88F6920_PLUS), MPP_VAR_FUNCTION(7, "i2c1", "sda", V_88F6920_PLUS)), MPP_MODE(17, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
Signature · 1 line
2.1.0
PATCH 32/34 pinctrl: mvebu: armada-39x: add missing PCIe functions
Quoted 6 lines · Thomas Petazzoni
The latest version of the Armada 39x datasheet documents several new PCIe related functions on various MPP pins. This commit adds the description of these new functions to the Armada 39x pinctrl driver as well as to its DT binding documentation.
Signed-off-by Thomas Petazzoni <[email protected]>
Patch applied.
Yours,
Linus Walleij
PATCH 33/34 pinctrl: mvebu: armada-39x: add missing SATA functions
In reply to Thomas PetazzoniThe latest version of the Armada 39x datasheet documents several new SATA related functions on various MPP pins. This commit adds the description of these new functions to the Armada 39x pinctrl driver as well as to its DT binding documentation.
--- .../bindings/pinctrl/marvell,armada-39x-pinctrl.txt | 14 +++++++++----- drivers/pinctrl/mvebu/pinctrl-armada-39x.c | 9 +++++++++ 2 files changed, 18 insertions(+), 5 deletions(-)
Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt +9 -5
@@ -31,11 +31,12 @@ mpp13 13 gpio, dev(ad15), pcie2(clkreq), led(data) mpp14 14 gpio, dram(vttctrl), dev(we1), ua1(txd) mpp15 15 gpio, pcie0(rstout), spi0(mosi), i2c1(sck) mpp16 16 gpio, dram(deccerr), spi0(miso), pcie0(clkreq), i2c1(sda) -mpp17 17 gpio, ua1(rxd), spi0(sck), smi(mdio) +mpp17 17 gpio, ua1(rxd), spi0(sck), sata1(prsnt) [1], sata0(prsnt) [1], smi(mdio) mpp18 18 gpio, ua1(txd), spi0(cs0), i2c2(sck) mpp19 19 gpio, sata1(prsnt) [1], ua0(cts), ua1(rxd), i2c2(sda) mpp20 20 gpio, sata0(prsnt) [1], ua0(rts), ua1(txd), smi(mdc) -mpp21 21 gpio, spi0(cs1), sata0(prsnt) [1], sd0(cmd), dev(bootcs), ge(rxd0) +mpp21 21 gpio, spi0(cs1), sata0(prsnt) [1], sd0(cmd), dev(bootcs), + sata1(prsnt) [1], ge(rxd0) mpp22 22 gpio, spi0(mosi), dev(ad0) mpp23 23 gpio, spi0(sck), dev(ad2) mpp24 24 gpio, spi0(miso), ua0(cts), ua1(rxd), sd0(d4), dev(ready)
@@ -58,12 +59,15 @@ mpp40 40 gpio, i2c1(sda), ua0(rts), sd0(d2), dev(ad6), ge(rxd3) mpp41 41 gpio, ua1(rxd), ua0(cts), spi1(cs3), dev(burst/last), nand(rb0), ge(rxctl) mpp42 42 gpio, ua1(txd), ua0(rts), dev(ad7) mpp43 43 gpio, pcie0(clkreq), dram(vttctrl), dram(deccerr), spi1(cs2), dev(clkout), nand(rb1) -mpp44 44 gpio, sata0(prsnt) [1], sata1(prsnt) [1], led(clk) +mpp44 44 gpio, sata0(prsnt) [1], sata1(prsnt) [1], sata2(prsnt) [1], + sata3(prsnt) [1], led(clk) mpp45 45 gpio, ref(clk), pcie0(rstout), ua1(rxd) mpp46 46 gpio, ref(clk), pcie0(rstout), ua1(txd), led(stb) -mpp47 47 gpio, sata0(prsnt) [1], sata1(prsnt) [1], led(data) +mpp47 47 gpio, sata0(prsnt) [1], sata1(prsnt) [1], sata2(prsnt) [1], + sata3(prsnt) [1], led(data) mpp48 48 gpio, sata0(prsnt) [1], dram(vttctrl), tdm(pclk) [1], audio(mclk) [1], sd0(d4), pcie0(clkreq), ua1(txd) -mpp49 49 gpio, tdm(fsync) [1], audio(lrclk) [1], sd0(d5), ua2(rxd) +mpp49 49 gpio, sata2(prsnt) [1], sata3(prsnt) [1], tdm(fsync) [1], + audio(lrclk) [1], sd0(d5), ua2(rxd) mpp50 50 gpio, pcie0(rstout), tdm(drx) [1], audio(extclk) [1], sd0(cmd), ua2(rxd) mpp51 51 gpio, tdm(dtx) [1], audio(sdo) [1], dram(deccerr), ua2(txd) mpp52 52 gpio, pcie0(rstout), tdm(int) [1], audio(sdi) [1], sd0(d6), i2c3(sck)
drivers/pinctrl/mvebu/pinctrl-armada-39x.c +9 -0
@@ -117,6 +117,8 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "ua1", "rxd", V_88F6920_PLUS), MPP_VAR_FUNCTION(4, "spi0", "sck", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "sata1", "prsnt", V_88F6928), + MPP_VAR_FUNCTION(6, "sata0", "prsnt", V_88F6928), MPP_VAR_FUNCTION(7, "smi", "mdio", V_88F6920_PLUS)), MPP_MODE(18, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
@@ -141,6 +143,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(3, "sata0", "prsnt", V_88F6928), MPP_VAR_FUNCTION(4, "sd0", "cmd", V_88F6920_PLUS), MPP_VAR_FUNCTION(5, "dev", "bootcs", V_88F6920_PLUS), + MPP_VAR_FUNCTION(6, "sata1", "prsnt", V_88F6928), MPP_VAR_FUNCTION(8, "ge", "rxd0", V_88F6920_PLUS)), MPP_MODE(22, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
@@ -262,6 +265,8 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6928), MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6928), + MPP_VAR_FUNCTION(3, "sata2", "prsnt", V_88F6928), + MPP_VAR_FUNCTION(4, "sata3", "prsnt", V_88F6928), MPP_VAR_FUNCTION(7, "led", "clk", V_88F6920_PLUS)), MPP_MODE(45, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
@@ -278,6 +283,8 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6928), MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6928), + MPP_VAR_FUNCTION(3, "sata2", "prsnt", V_88F6928), + MPP_VAR_FUNCTION(5, "sata3", "prsnt", V_88F6928), MPP_VAR_FUNCTION(7, "led", "data", V_88F6920_PLUS)), MPP_MODE(48, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
@@ -290,6 +297,8 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(7, "ua1", "txd", V_88F6920_PLUS)), MPP_MODE(49, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(1, "sata2", "prsnt", V_88F6928), + MPP_VAR_FUNCTION(2, "sata3", "prsnt", V_88F6928), MPP_VAR_FUNCTION(3, "tdm", "fsync", V_88F6928), MPP_VAR_FUNCTION(4, "audio", "lrclk", V_88F6928), MPP_VAR_FUNCTION(5, "sd0", "d5", V_88F6920_PLUS),
Signature · 1 line
2.1.0
PATCH 33/34 pinctrl: mvebu: armada-39x: add missing SATA functions
Quoted 6 lines · Thomas Petazzoni
The latest version of the Armada 39x datasheet documents several new SATA related functions on various MPP pins. This commit adds the description of these new functions to the Armada 39x pinctrl driver as well as to its DT binding documentation.
Signed-off-by Thomas Petazzoni <[email protected]>
Patch applied.
Yours,
Linus Walleij
PATCH 34/34 pinctrl: mvebu: armada-39x: add support for Armada 395 variant
In reply to Thomas PetazzoniThe Armada 39x SoC family has grown a new variant, the Armada 395, which sits between the Armada 390 and Armada 398 in terms of features. This commit adds support for this additional variant to the Armada 39x pinctrl driver.
--- .../pinctrl/marvell,armada-39x-pinctrl.txt | 30 ++++++++-------- drivers/pinctrl/mvebu/pinctrl-armada-39x.c | 40 +++++++++++++--------- 2 files changed, 39 insertions(+), 31 deletions(-)
Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt +16 -14
@@ -4,8 +4,9 @@ Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding part and usage. Required properties: -- compatible: "marvell,88f6920-pinctrl", "marvell,88f6928-pinctrl" - depending on the specific variant of the SoC being used. +- compatible: "marvell,88f6920-pinctrl", "marvell,88f6925-pinctrl" or + "marvell,88f6928-pinctrl" depending on the specific variant of the + SoC being used. - reg: register specifier of MPP registers Available mpp pins/groups and functions:
@@ -59,19 +60,19 @@ mpp40 40 gpio, i2c1(sda), ua0(rts), sd0(d2), dev(ad6), ge(rxd3) mpp41 41 gpio, ua1(rxd), ua0(cts), spi1(cs3), dev(burst/last), nand(rb0), ge(rxctl) mpp42 42 gpio, ua1(txd), ua0(rts), dev(ad7) mpp43 43 gpio, pcie0(clkreq), dram(vttctrl), dram(deccerr), spi1(cs2), dev(clkout), nand(rb1) -mpp44 44 gpio, sata0(prsnt) [1], sata1(prsnt) [1], sata2(prsnt) [1], - sata3(prsnt) [1], led(clk) +mpp44 44 gpio, sata0(prsnt) [1], sata1(prsnt) [1], sata2(prsnt) [2], + sata3(prsnt) [2], led(clk) mpp45 45 gpio, ref(clk), pcie0(rstout), ua1(rxd) mpp46 46 gpio, ref(clk), pcie0(rstout), ua1(txd), led(stb) -mpp47 47 gpio, sata0(prsnt) [1], sata1(prsnt) [1], sata2(prsnt) [1], - sata3(prsnt) [1], led(data) -mpp48 48 gpio, sata0(prsnt) [1], dram(vttctrl), tdm(pclk) [1], audio(mclk) [1], sd0(d4), pcie0(clkreq), ua1(txd) -mpp49 49 gpio, sata2(prsnt) [1], sata3(prsnt) [1], tdm(fsync) [1], - audio(lrclk) [1], sd0(d5), ua2(rxd) -mpp50 50 gpio, pcie0(rstout), tdm(drx) [1], audio(extclk) [1], sd0(cmd), ua2(rxd) -mpp51 51 gpio, tdm(dtx) [1], audio(sdo) [1], dram(deccerr), ua2(txd) -mpp52 52 gpio, pcie0(rstout), tdm(int) [1], audio(sdi) [1], sd0(d6), i2c3(sck) -mpp53 53 gpio, sata1(prsnt) [1], sata0(prsnt) [1], tdm(rst) [1], audio(bclk) [1], sd0(d7), i2c3(sda) +mpp47 47 gpio, sata0(prsnt) [1], sata1(prsnt) [1], sata2(prsnt) [2], + sata3(prsnt) [2], led(data) +mpp48 48 gpio, sata0(prsnt) [1], dram(vttctrl), tdm(pclk) [2], audio(mclk) [2], sd0(d4), pcie0(clkreq), ua1(txd) +mpp49 49 gpio, sata2(prsnt) [2], sata3(prsnt) [2], tdm(fsync) [2], + audio(lrclk) [2], sd0(d5), ua2(rxd) +mpp50 50 gpio, pcie0(rstout), tdm(drx) [2], audio(extclk) [2], sd0(cmd), ua2(rxd) +mpp51 51 gpio, tdm(dtx) [2], audio(sdo) [2], dram(deccerr), ua2(txd) +mpp52 52 gpio, pcie0(rstout), tdm(int) [2], audio(sdi) [2], sd0(d6), i2c3(sck) +mpp53 53 gpio, sata1(prsnt) [1], sata0(prsnt) [1], tdm(rst) [2], audio(bclk) [2], sd0(d7), i2c3(sda) mpp54 54 gpio, sata0(prsnt) [1], sata1(prsnt) [1], pcie0(rstout), sd0(d3), ua3(txd) mpp55 55 gpio, ua1(cts), spi1(cs1), sd0(d0), ua1(rxd), ua3(rxd) mpp56 56 gpio, ua1(rts), dram(deccerr), spi1(mosi), ua1(txd)
@@ -79,4 +80,5 @@ mpp57 57 gpio, spi1(sck), sd0(clk), ua1(txd) mpp58 58 gpio, i2c1(sck), pcie2(clkreq), spi1(miso), sd0(d1), ua1(rxd) mpp59 59 gpio, pcie0(rstout), i2c1(sda), spi1(cs0), sd0(d2) -[1]: only available on 88F6928 +[1]: only available on 88F6925/88F6928 +[2]: only available on 88F6928
drivers/pinctrl/mvebu/pinctrl-armada-39x.c +23 -17
@@ -36,8 +36,10 @@ static int armada_39x_mpp_ctrl_set(unsigned pid, unsigned long config)enum {V_88F6920 =BIT (0 ), -V_88F6928 =BIT (1 ), -V_88F6920_PLUS = (V_88F6920 |V_88F6928 ), +V_88F6925 =BIT (1 ), +V_88F6928 =BIT (2 ), +V_88F6920_PLUS = (V_88F6920 |V_88F6925 |V_88F6928 ), +V_88F6925_PLUS = (V_88F6925 |V_88F6928 ), };static struct mvebu_mpp_mode armada_39x_mpp_modes[] = {
@@ -117,8 +119,8 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "ua1", "rxd", V_88F6920_PLUS), MPP_VAR_FUNCTION(4, "spi0", "sck", V_88F6920_PLUS), - MPP_VAR_FUNCTION(5, "sata1", "prsnt", V_88F6928), - MPP_VAR_FUNCTION(6, "sata0", "prsnt", V_88F6928), + MPP_VAR_FUNCTION(5, "sata1", "prsnt", V_88F6925_PLUS), + MPP_VAR_FUNCTION(6, "sata0", "prsnt", V_88F6925_PLUS), MPP_VAR_FUNCTION(7, "smi", "mdio", V_88F6920_PLUS)), MPP_MODE(18, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
@@ -127,23 +129,23 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(7, "i2c2", "sck", V_88F6920_PLUS)),MPP_MODE (19 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6920_PLUS ), -MPP_VAR_FUNCTION (4 ,"sata1" ,"prsnt" ,V_88F6928 ), +MPP_VAR_FUNCTION (4 ,"sata1" ,"prsnt" ,V_88F6925_PLUS ),MPP_VAR_FUNCTION (5 ,"ua0" ,"cts" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (6 ,"ua1" ,"rxd" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (7 ,"i2c2" ,"sda" ,V_88F6920_PLUS )),MPP_MODE (20 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6920_PLUS ), -MPP_VAR_FUNCTION (4 ,"sata0" ,"prsnt" ,V_88F6928 ), +MPP_VAR_FUNCTION (4 ,"sata0" ,"prsnt" ,V_88F6925_PLUS ),MPP_VAR_FUNCTION (5 ,"ua0" ,"rts" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (6 ,"ua1" ,"txd" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (7 ,"smi" ,"mdc" ,V_88F6920_PLUS )),MPP_MODE (21 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (1 ,"spi0" ,"cs1" ,V_88F6920_PLUS ), -MPP_VAR_FUNCTION (3 ,"sata0" ,"prsnt" ,V_88F6928 ), +MPP_VAR_FUNCTION (3 ,"sata0" ,"prsnt" ,V_88F6925_PLUS ),MPP_VAR_FUNCTION (4 ,"sd0" ,"cmd" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (5 ,"dev" ,"bootcs" ,V_88F6920_PLUS ), -MPP_VAR_FUNCTION (6 ,"sata1" ,"prsnt" ,V_88F6928 ), +MPP_VAR_FUNCTION (6 ,"sata1" ,"prsnt" ,V_88F6925_PLUS ),MPP_VAR_FUNCTION (8 ,"ge" ,"rxd0" ,V_88F6920_PLUS )), MPP_MODE(22, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
@@ -263,8 +265,8 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(6, "nand", "rb1", V_88F6920_PLUS)),MPP_MODE (44 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6920_PLUS ), -MPP_VAR_FUNCTION (1 ,"sata0" ,"prsnt" ,V_88F6928 ), -MPP_VAR_FUNCTION (2 ,"sata1" ,"prsnt" ,V_88F6928 ), +MPP_VAR_FUNCTION (1 ,"sata0" ,"prsnt" ,V_88F6925_PLUS ), +MPP_VAR_FUNCTION (2 ,"sata1" ,"prsnt" ,V_88F6925_PLUS ),MPP_VAR_FUNCTION (3 ,"sata2" ,"prsnt" ,V_88F6928 ),MPP_VAR_FUNCTION (4 ,"sata3" ,"prsnt" ,V_88F6928 ), MPP_VAR_FUNCTION(7, "led", "clk", V_88F6920_PLUS)),
@@ -281,14 +283,14 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(7, "led", "stb", V_88F6920_PLUS)),MPP_MODE (47 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6920_PLUS ), -MPP_VAR_FUNCTION (1 ,"sata0" ,"prsnt" ,V_88F6928 ), -MPP_VAR_FUNCTION (2 ,"sata1" ,"prsnt" ,V_88F6928 ), +MPP_VAR_FUNCTION (1 ,"sata0" ,"prsnt" ,V_88F6925_PLUS ), +MPP_VAR_FUNCTION (2 ,"sata1" ,"prsnt" ,V_88F6925_PLUS ),MPP_VAR_FUNCTION (3 ,"sata2" ,"prsnt" ,V_88F6928 ),MPP_VAR_FUNCTION (5 ,"sata3" ,"prsnt" ,V_88F6928 ),MPP_VAR_FUNCTION (7 ,"led" ,"data" ,V_88F6920_PLUS )), MPP_MODE(48, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), - MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6928), + MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6925_PLUS), MPP_VAR_FUNCTION(2, "dram", "vttctrl", V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "tdm", "pclk", V_88F6928), MPP_VAR_FUNCTION(4, "audio", "mclk", V_88F6928),
@@ -325,16 +327,16 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(7, "i2c3", "sck", V_88F6920_PLUS)),MPP_MODE (53 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6920_PLUS ), -MPP_VAR_FUNCTION (1 ,"sata1" ,"prsnt" ,V_88F6928 ), -MPP_VAR_FUNCTION (2 ,"sata0" ,"prsnt" ,V_88F6928 ), +MPP_VAR_FUNCTION (1 ,"sata1" ,"prsnt" ,V_88F6925_PLUS ), +MPP_VAR_FUNCTION (2 ,"sata0" ,"prsnt" ,V_88F6925_PLUS ),MPP_VAR_FUNCTION (3 ,"tdm" ,"rst" ,V_88F6928 ),MPP_VAR_FUNCTION (4 ,"audio" ,"bclk" ,V_88F6928 ),MPP_VAR_FUNCTION (5 ,"sd0" ,"d7" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (7 ,"i2c3" ,"sda" ,V_88F6920_PLUS )),MPP_MODE (54 ,MPP_VAR_FUNCTION (0 ,"gpio" ,NULL ,V_88F6920_PLUS ), -MPP_VAR_FUNCTION (1 ,"sata0" ,"prsnt" ,V_88F6928 ), -MPP_VAR_FUNCTION (2 ,"sata1" ,"prsnt" ,V_88F6928 ), +MPP_VAR_FUNCTION (1 ,"sata0" ,"prsnt" ,V_88F6925_PLUS ), +MPP_VAR_FUNCTION (2 ,"sata1" ,"prsnt" ,V_88F6925_PLUS ),MPP_VAR_FUNCTION (3 ,"pcie0" ,"rstout" ,V_88F6920_PLUS ),MPP_VAR_FUNCTION (5 ,"sd0" ,"d3" ,V_88F6920_PLUS ), MPP_VAR_FUNCTION(7, "ua3", "txd", V_88F6920_PLUS)),
@@ -379,6 +381,10 @@ static const struct of_device_id armada_39x_pinctrl_of_match[] = { .data = (void *) V_88F6920, }, { + .compatible = "marvell,mv88f6925-pinctrl", + .data = (void *) V_88F6925, + }, + { .compatible = "marvell,mv88f6928-pinctrl", .data = (void *) V_88F6928, },
Signature · 1 line
2.1.0
PATCH 34/34 pinctrl: mvebu: armada-39x: add support for Armada 395 variant
Quoted 6 lines · Thomas Petazzoni
The Armada 39x SoC family has grown a new variant, the Armada 395, which sits between the Armada 390 and Armada 398 in terms of features. This commit adds support for this additional variant to the Armada 39x pinctrl driver.
Signed-off-by Thomas Petazzoni <[email protected]>
Patch applied.
Yours,
Linus Walleij
Andrew Lunn
maintainercover pinctrl: mvebu: numerous fixes, cleanups and improvements
In reply to Thomas PetazzoniQuoted 5 lines · Thomas Petazzoni
Hello,
This fairly long series of patches implement numerous fixes, cleanups and improvements to the description of the MPP pins on Armada 370, 375, 38x, 39x and XP.
...
Quoted 2 lines
I wish you good luck when reviewing this. It was boring to do, so I guess it is going to be horribly boring to review :-)
Not so far :-)
So i mailed two specific comments, but i think there might be a generic problem. You appear to be modifying pinctrl without making corresponding changes to .dtsi files? Or have i just missed them? I would of expected the .dtsi file changes to be in the same patch, or there are going to be bisect issues.
Andrew
cover pinctrl: mvebu: numerous fixes, cleanups and improvements
Andrew,
Quoted 4 lines · Andrew Lunn
Quoted 2 lines
I wish you good luck when reviewing this. It was boring to do, so I guess it is going to be horribly boring to review :-)
Not so far :-)
Great :-)
Quoted 5 lines
So i mailed two specific comments, but i think there might be a generic problem. You appear to be modifying pinctrl without making corresponding changes to .dtsi files? Or have i just missed them? I would of expected the .dtsi file changes to be in the same patch, or there are going to be bisect issues.
In fact, for most of the changes there should be zero impact on the .dtsi or .dts files. Most of the changes are about the subnames (which don't appear in DT) or adding new functions.
However, you indeed pointed two cases I missed. So I guess I'll have to review the entire series to double check what is the impact on the DT. But before doing that, it'd be great to have your point of on the patches that actually break the DT backward compatibility. If there are to be rejected anyway, I'd rather not spend more time on them.
Thanks a lot!
Thomas
Signature · 3 lines
Thomas Petazzoni, CTO, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com
Andrew Lunn
maintainercover pinctrl: mvebu: numerous fixes, cleanups and improvements
Quoted 3 lines · Thomas Petazzoni
But before doing that, it'd be great to have your point of on the patches that actually break the DT backward compatibility. If there are to be rejected anyway, I'd rather not spend more time on them.
Hi Thomas
I read a presentation recently, "Device Tree as a stable ABI: a fairy tale?" :-)
But we should at least try. So what is actually involved in keeping backwards compatibility?
The two patches i pointed out have two different situations.
What does pinctrl do when you ask for a pin which is not a member of the function? If it silently ignores it, not a problem. But i expect it actually throws an error. I could be wrong here, but it looks like it is the mvebu code which checks if a pin is a member of a function. So it might be possible to set the value of the val in the mvebu_mpp_ctrl_setting to 0xff for the removed NAND pins, and when we see such a value, print a warning about outdated DT, and "succeed" rather than return an error.
For spi -> spi0 it seems messier. So i would leave it as spi with a comment, and add spi1.
I do see value in having consistent names and matching the datasheet were possible. So if we can find reasonable compromises, i think these patches are useful.
Andrew
cover pinctrl: mvebu: numerous fixes, cleanups and improvements
Hello,
Quoted 2 lines · Andrew Lunn
I read a presentation recently, "Device Tree as a stable ABI: a fairy tale?" :-)
Reminds me of something :)
Quoted 5 lines
But we should at least try. So what is actually involved in keeping backwards compatibility?
The two patches i pointed out have two different situations.
Quoted 8 lines
What does pinctrl do when you ask for a pin which is not a member of the function? If it silently ignores it, not a problem. But i expect it actually throws an error. I could be wrong here, but it looks like it is the mvebu code which checks if a pin is a member of a function. So it might be possible to set the value of the val in the
mvebu_mpp_ctrl_settingto0xfffor the removed NAND pins, and when we see such a value, print a warning about outdated DT, and "succeed" rather than return an error.
This can only work if the function number is not actually used. For example, in the very first patch "pinctrl: mvebu: armada-38x: fix PCIe functions" :
- MPP_VAR_FUNCTION(4, "pcie1", "rstout", V_88F6820_PLUS),
+ MPP_VAR_FUNCTION(4, "ge0", "txerr", V_88F6810_PLUS),
So the function 4 used to be pcie1, which you would like to still be supported, but it's now actually used for ge0.
To be honest, I actually prefer that people updating their kernel and using an old DT get an error about pin muxing, rather than having the driver silently ignore and have people never update their Device Tree.
It's also about long term maintainability. Do we want to keep old crap around forever in all device drivers?
Quoted 2 lines
For spi -> spi0 it seems messier. So i would leave it as spi with a comment, and add spi1.
I'm fine with that.
What about tdm2c -> tdm renaming on Armada 38x, and tdm-1 -> tdm for one single TDM pin on Armada XP ?
I think we're hitting the limits of the DT backward compatibility: our description of the hardware had some bugs. What do we do? Continue to support bugs?
Thomas
Signature · 3 lines
Thomas Petazzoni, CTO, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com
Andrew Lunn
maintainercover pinctrl: mvebu: numerous fixes, cleanups and improvements
Quoted 16 lines
Quoted 8 lines
What does pinctrl do when you ask for a pin which is not a member of the function? If it silently ignores it, not a problem. But i expect it actually throws an error. I could be wrong here, but it looks like it is the mvebu code which checks if a pin is a member of a function. So it might be possible to set the value of the val in the
mvebu_mpp_ctrl_settingto0xfffor the removed NAND pins, and when we see such a value, print a warning about outdated DT, and "succeed" rather than return an error.This can only work if the function number is not actually used. For example, in the very first patch "pinctrl: mvebu: armada-38x: fix PCIe functions" :
(quoted diff) +1
-1- MPP_VAR_FUNCTION(4, "pcie1", "rstout", V_88F6820_PLUS), + MPP_VAR_FUNCTION(4, "ge0", "txerr", V_88F6810_PLUS),
Quoted 2 lines
So the function 4 used to be pcie1, which you would like to still be supported, but it's now actually used for ge0.
Isn't 4 a function of the hardware? So this never worked. It is a bug. So the DT file must also have a bug if this actually affects anybody. So i would say, no backwards compatibility is required here.
Quoted 3 lines
To be honest, I actually prefer that people updating their kernel and using an old DT get an error about pin muxing, rather than having the driver silently ignore and have people never update their Device Tree.
I also think many people will be keeping there DT file in step with the kernel. Both get read from /boot by u-boot, or are appended to the kernel, etc. I doubt there are many Marvell systems which a chunk of FLASH dedicated to holding the DT blob.
Quoted 10 lines
It's also about long term maintainability. Do we want to keep old crap around forever in all device drivers?
Quoted 2 lines
For spi -> spi0 it seems messier. So i would leave it as spi with a comment, and add spi1.
I'm fine with that.
What about tdm2c -> tdm renaming on Armada 38x, and tdm-1 -> tdm for one single TDM pin on Armada XP ?
Is there an in-kernel use of TDM? I don't think so. So i would just change them.
Quoted 3 lines
I think we're hitting the limits of the DT backward compatibility: our description of the hardware had some bugs. What do we do? Continue to support bugs?
For true bugs, i say no, we fix it. Renames for which there is no in-kernel user, just do it. But where there are in-kernel users, which are not Marvell development boards, we should at least see if there is a simple and not too ugly way to keep backwards compatibility, and issue a strong warning it is time to upgrade.
Andrew
cover pinctrl: mvebu: numerous fixes, cleanups and improvements
Dear Andrew Lunn,
Quoted 11 lines · Andrew Lunn
Quoted 9 lines
This can only work if the function number is not actually used. For example, in the very first patch "pinctrl: mvebu: armada-38x: fix PCIe functions" :
(quoted diff) +1
-1- MPP_VAR_FUNCTION(4, "pcie1", "rstout", V_88F6820_PLUS), + MPP_VAR_FUNCTION(4, "ge0", "txerr", V_88F6810_PLUS),So the function 4 used to be pcie1, which you would like to still be supported, but it's now actually used for ge0.
Isn't 4 a function of the hardware?
I don't understand your question here. Of course '4' is hardware-related.
Quoted 3 lines
So this never worked. It is a
bug. So the DT file must also have a bug if this actually affects anybody. So i would say, no backwards compatibility is required here.
How is this different from the NAND case you highlighted for patch 03/34 ? If you have a .dts or .dtsi that does:
marvell,pins = "mpp12"; marvell,function = "pcie1";
then this will now generate an error, because there is no longer a "pcie1" function on mpp12. Just like with PATCH 03/34 there is no longer a "nf" function on pins mpp9 and mpp10.
Quoted 8 lines
Quoted 3 lines
To be honest, I actually prefer that people updating their kernel and using an old DT get an error about pin muxing, rather than having the driver silently ignore and have people never update their Device Tree.
I also think many people will be keeping there DT file in step with the kernel. Both get read from /boot by u-boot, or are appended to the kernel, etc. I doubt there are many Marvell systems which a chunk of FLASH dedicated to holding the DT blob.
Agreed.
Quoted 6 lines
Quoted 6 lines
It's also about long term maintainability. Do we want to keep old crap around forever in all device drivers?
Quoted 2 lines
For spi -> spi0 it seems messier. So i would leave it as spi with a comment, and add spi1.
Quoted 7 lines
Quoted 4 lines
I'm fine with that.
What about tdm2c -> tdm renaming on Armada 38x, and tdm-1 -> tdm for one single TDM pin on Armada XP ?
Is there an in-kernel use of TDM? I don't think so. So i would just change them.
No, there is no in-kernel use of TDM in the mainline kernel.
Quoted 5 lines
For true bugs, i say no, we fix it. Renames for which there is no in-kernel user, just do it. But where there are in-kernel users, which are not Marvell development boards, we should at least see if there is a simple and not too ugly way to keep backwards compatibility, and issue a strong warning it is time to upgrade.
So, what do you propose to do precisely? Here are the patches that are removing/changing the main name of certain MPP functions:
* [PATCH 01/34] pinctrl: mvebu: armada-38x: fix PCIe functions
* [PATCH 02/34] pinctrl: mvebu: armada-370: fix spi0 pin description
* [PATCH 03/34] pinctrl: mvebu: armada-375: remove non-existing NAND re/we pins
* [PATCH 04/34] pinctrl: mvebu: armada-xp: remove non-existing NAND pins
* [PATCH 05/34] pinctrl: mvebu: armada-xp: remove non-existing VDD cpu_pd functions
* [PATCH 06/34] pinctrl: mvebu: armada-xp: fix functions of MPP48
* [PATCH 07/34] pinctrl: mvebu: armada-375: remove incorrect space in pin description
* [PATCH 11/34] pinctrl: mvebu: armada-{38x,39x,xp}: normalize naming of DRAM functions
* [PATCH 13/34] pinctrl: mvebu: armada-39x: normalize SDIO pin naming
* [PATCH 15/34] pinctrl: mvebu: armada-39x: align NAND pin naming
* [PATCH 16/34] pinctrl: mvebu: armada-{370,375,38x,39x,xp}: normalize TDM pins
* [PATCH 21/34] pinctrl: mvebu: armada-370: align VDD cpu-pd pin naming with datasheet
* [PATCH 23/34] pinctrl: mvebu: armada-xp: rename spi to spi0
What do we do for each of them?
Thanks,
Thomas
Signature · 3 lines
Thomas Petazzoni, CTO, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com
cover pinctrl: mvebu: numerous fixes, cleanups and improvements
In reply to Thomas PetazzoniQuoted 3 lines · Thomas Petazzoni
This fairly long series of patches implement numerous fixes, cleanups and improvements to the description of the MPP pins on Armada 370, 375, 38x, 39x and XP.
I have simply applied all of them, I trust you.
If updates to existing device trees in the kernel are needed please funnel these through ARM SoC.
I do not subscribe to the "device tree bindings etched in stone" philosophy for devices not yet widely deployed so I would recommend to disregard it.
Yours,
Linus Walleij
cover pinctrl: mvebu: numerous fixes, cleanups and improvements
Hi Linus,
Quoted 8 lines · Linus Walleij
Quoted 3 lines · Thomas Petazzoni
This fairly long series of patches implement numerous fixes, cleanups and improvements to the description of the MPP pins on Armada 370, 375, 38x, 39x and XP.
I have simply applied all of them, I trust you.
Does it means that it will be part of 4.2 ?
Thanks,
Gregory
Quoted 10 lines
If updates to existing device trees in the kernel are needed please funnel these through ARM SoC.
I do not subscribe to the "device tree bindings etched in stone" philosophy for devices not yet widely deployed so I would recommend to disregard it.
Yours,
Linus Walleij
Signature · 4 lines
Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
cover pinctrl: mvebu: numerous fixes, cleanups and improvements
Quoted 6 lines · Gregory CLEMENT
Hi Linus,
Quoted 3 lines · Linus Walleij
On Tue, Jun 9, 2015 at 6:46 PM, Thomas Petazzoni
<[email protected]> wrote:
Quoted 7 lines
Quoted 5 lines
Quoted 3 lines
This fairly long series of patches implement numerous fixes, cleanups and improvements to the description of the MPP pins on Armada 370, 375, 38x, 39x and XP.
I have simply applied all of them, I trust you.
Does it means that it will be part of 4.2 ?
Yes. They are already in Torvalds' tree by the way :)
Yours,
Linus Walleij