imx: mx6 cast return type of is_soc_rev to int

PATCH New Peng Fan 3 participants 21 messages Jun 10, 2015

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Arm (32-bit) Arm i.MX and Layerscape

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Peng Fan

author

2015-06-10 08:06 UTC #0 lore raw

PATCH 1/8 imx: mx6 cast return type of is_soc_rev to int

is_soc_rev should be casted to signed int, otherwise may incur errors when detecting cpu types, since we use such pieces of code:
"
if (is_soc_rev(CHIP_REV_1_0) > 0) ......
if (is_soc_rev(CHIP_REV_2_0) >= 0) ......
"

Signed-off-by Peng Fan <[email protected]>

---
 arch/arm/include/asm/arch-mx6/sys_proto.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

arch/arm/include/asm/arch-mx6/sys_proto.h +1 -1

index c583291..9c827c9 100644
@@ -12,7 +12,7 @@
 #include "../arch-imx/cpu.h"
 
 #define soc_rev() (get_cpu_rev() & 0xFF)
-#define is_soc_rev(rev)        (soc_rev() - rev)
+#define is_soc_rev(rev)        (int)(soc_rev() - rev)
 
 u32 get_nr_cpus(void);
 u32 get_cpu_rev(void);

Signature · 1 line

1.8.4

Peng Fan

author

2015-06-10 08:06 UTC #1 lore raw

PATCH 2/8 imx: mx6: Add MX6DQP CPU rev type

Add new cpu type for i.MX6DQP and providing a dynamical detecting function.

Signed-off-by Peng Fan <[email protected]>

Signed-off-by Ye.Li <[email protected]>

---
 arch/arm/cpu/armv7/mx6/soc.c              | 4 +++-
 arch/arm/include/asm/arch-mx6/imx-regs.h  | 1 +
 arch/arm/include/asm/arch-mx6/sys_proto.h | 6 ++++++
 3 files changed, 10 insertions(+), 1 deletion(-)

arch/arm/cpu/armv7/mx6/soc.c +3 -1

index b21bd03..29de624 100644
@@ -62,6 +62,7 @@ u32 get_cpu_rev(void)
 	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 	u32 reg = readl(&anatop->digprog_sololite);
 	u32 type = ((reg >> 16) & 0xff);
+	u32 major;
 
 	if (type != MXC_CPU_MX6SL) {
 		reg = readl(&anatop->digprog);

@@ -79,8 +80,9 @@ u32 get_cpu_rev(void)
 		}
 
 	}
+	major = ((reg >> 8) & 0xff);
 	reg &= 0xff;		/* mx6 silicon revision */
-	return (type << 12) | (reg + 0x10);
+	return (type << 12) | (reg + (0x10 * (major + 1)));
 }
 
 /*

arch/arm/include/asm/arch-mx6/imx-regs.h +1 -0

index 0d38d45..35a324c 100644
@@ -312,6 +312,7 @@
 #define CHIP_REV_1_0                 0x10
 #define CHIP_REV_1_2                 0x12
 #define CHIP_REV_1_5                 0x15
+#define CHIP_REV_2_0                 0x20
 #ifndef CONFIG_MX6SX
 #define IRAM_SIZE                    0x00040000
 #else

arch/arm/include/asm/arch-mx6/sys_proto.h +6 -0

index 9c827c9..c1d9c6d 100644
@@ -2,6 +2,8 @@
  * (C) Copyright 2009
  * Stefano Babic, DENX Software Engineering, [email protected].
  *
+ * (C) Copyright 2009-2015 Freescale Semiconductor, Inc.
+ *
  * SPDX-License-Identifier:	GPL-2.0+
  */

@@ -30,6 +32,10 @@ const char *get_imx_type(u32 imxtype);
 unsigned imx_ddr_size(void);
 void set_chipselect_size(int const);
 
+#define is_mx6dqp() ((is_cpu_type(MXC_CPU_MX6Q) || \
+		     is_cpu_type(MXC_CPU_MX6D)) && \
+		     (is_soc_rev(CHIP_REV_2_0) >= 0))
+
 /*
  * Initializes on-chip ethernet controllers.
  * to override, implement board_eth_init()

Signature · 1 line

1.8.4

Stefano Babic

2015-06-10 09:19 UTC #2 lore raw

PATCH 2/8 imx: mx6: Add MX6DQP CPU rev type

Hi Peng,

Quoted 51 lines · Peng Fan

Add new cpu type for i.MX6DQP and providing a dynamical detecting function.

Signed-off-by Peng Fan <[email protected]>

Signed-off-by Ye.Li <[email protected]>

---
 arch/arm/cpu/armv7/mx6/soc.c              | 4 +++-
 arch/arm/include/asm/arch-mx6/imx-regs.h  | 1 +
 arch/arm/include/asm/arch-mx6/sys_proto.h | 6 ++++++
 3 files changed, 10 insertions(+), 1 deletion(-)

arch/arm/cpu/armv7/mx6/soc.c +3 -1

index b21bd03..29de624 100644
@@ -62,6 +62,7 @@ u32 get_cpu_rev(void)
 	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 	u32 reg = readl(&anatop->digprog_sololite);
 	u32 type = ((reg >> 16) & 0xff);
+	u32 major;
 
 	if (type != MXC_CPU_MX6SL) {
 		reg = readl(&anatop->digprog);

@@ -79,8 +80,9 @@ u32 get_cpu_rev(void)
 		}
 
 	}
+	major = ((reg >> 8) & 0xff);
 	reg &= 0xff;		/* mx6 silicon revision */
-	return (type << 12) | (reg + 0x10);
+	return (type << 12) | (reg + (0x10 * (major + 1)));
 }
 
 /*

arch/arm/include/asm/arch-mx6/imx-regs.h +1 -0

index 0d38d45..35a324c 100644
@@ -312,6 +312,7 @@
 #define CHIP_REV_1_0                 0x10
 #define CHIP_REV_1_2                 0x12
 #define CHIP_REV_1_5                 0x15
+#define CHIP_REV_2_0                 0x20
 #ifndef CONFIG_MX6SX
 #define IRAM_SIZE                    0x00040000
 #else

arch/arm/include/asm/arch-mx6/sys_proto.h +0 -0

index 9c827c9..c1d9c6d 100644

arch/arm/include/asm/arch-mx6/sys_proto.h line 9

Quoted 8 lines

arch/arm/include/asm/arch-mx6/sys_proto.h +2 -0

@@ -2,6 +2,8 @@
  * (C) Copyright 2009
  * Stefano Babic, DENX Software Engineering, sbabic at denx.de.
  *
+ * (C) Copyright 2009-2015 Freescale Semiconductor, Inc.
+ *
  * SPDX-License-Identifier:	GPL-2.0+
  */

mmhhh..we have already discussed this topic, Copyright should not be changed by small changes in a file.

arch/arm/include/asm/arch-mx6/sys_proto.h const char *get_imx_type(u32 imxtype); · line 38

Quoted 8 lines

arch/arm/include/asm/arch-mx6/sys_proto.h +4 -0

@@ -30,6 +32,10 @@ const char *get_imx_type(u32 imxtype);
 unsigned imx_ddr_size(void);
 void set_chipselect_size(int const);
 
+#define is_mx6dqp() ((is_cpu_type(MXC_CPU_MX6Q) || \
+		     is_cpu_type(MXC_CPU_MX6D)) && \
+		     (is_soc_rev(CHIP_REV_2_0) >= 0))
+

As "insider" you could better explain me: it looks like there will be not a Quad/Dual with an increased chip revision. The new chip revision for i.MX6 is really the QP (P=perfect, as I see some workaround can be removed !)

Is it correct ? Else this conflicts if a 6Q with a revision > 2 will be released.

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Peng Fan

2015-06-10 10:01 UTC #3 lore raw

PATCH 2/8 imx: mx6: Add MX6DQP CPU rev type

Hi Stefano,

Quoted 57 lines · Stefano Babic

Hi Peng,

Quoted 54 lines · Peng Fan

Add new cpu type for i.MX6DQP and providing a dynamical detecting function.

Signed-off-by Peng Fan <[email protected]>

Signed-off-by Ye.Li <[email protected]>

---
 arch/arm/cpu/armv7/mx6/soc.c              | 4 +++-
 arch/arm/include/asm/arch-mx6/imx-regs.h  | 1 +
 arch/arm/include/asm/arch-mx6/sys_proto.h | 6 ++++++
 3 files changed, 10 insertions(+), 1 deletion(-)

arch/arm/cpu/armv7/mx6/soc.c +3 -1

index b21bd03..29de624 100644
@@ -62,6 +62,7 @@ u32 get_cpu_rev(void)
 	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 	u32 reg = readl(&anatop->digprog_sololite);
 	u32 type = ((reg >> 16) & 0xff);
+	u32 major;
 
 	if (type != MXC_CPU_MX6SL) {
 		reg = readl(&anatop->digprog);

@@ -79,8 +80,9 @@ u32 get_cpu_rev(void)
 		}
 
 	}
+	major = ((reg >> 8) & 0xff);
 	reg &= 0xff;		/* mx6 silicon revision */
-	return (type << 12) | (reg + 0x10);
+	return (type << 12) | (reg + (0x10 * (major + 1)));
 }
 
 /*

arch/arm/include/asm/arch-mx6/imx-regs.h +1 -0

index 0d38d45..35a324c 100644
@@ -312,6 +312,7 @@
 #define CHIP_REV_1_0                 0x10
 #define CHIP_REV_1_2                 0x12
 #define CHIP_REV_1_5                 0x15
+#define CHIP_REV_2_0                 0x20
 #ifndef CONFIG_MX6SX
 #define IRAM_SIZE                    0x00040000
 #else

arch/arm/include/asm/arch-mx6/sys_proto.h +0 -0

index 9c827c9..c1d9c6d 100644
@@ -2,6 +2,8 @@
  * (C) Copyright 2009
  * Stefano Babic, DENX Software Engineering, sbabic at denx.de.
  *

Quoted 8 lines

arch/arm/include/asm/arch-mx6/sys_proto.h line 9
Quoted 5 lines
arch/arm/include/asm/arch-mx6/sys_proto.h +2 -0
+ * (C) Copyright 2009-2015 Freescale Semiconductor, Inc.
+ *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
mmhhh..we have already discussed this topic, Copyright should not be changed by small changes in a file.

oh. I missed to remove this. Thanks for correcting me.

Quoted 15 lines

arch/arm/include/asm/arch-mx6/sys_proto.h const char *get_imx_type(u32 imxtype); · line 38
Quoted 9 lines
arch/arm/include/asm/arch-mx6/sys_proto.h +4 -0
@@ -30,6 +32,10 @@ const char *get_imx_type(u32 imxtype);
 unsigned imx_ddr_size(void);
 void set_chipselect_size(int const);
 
+#define is_mx6dqp() ((is_cpu_type(MXC_CPU_MX6Q) || \
+		     is_cpu_type(MXC_CPU_MX6D)) && \
+		     (is_soc_rev(CHIP_REV_2_0) >= 0))
+
As "insider" you could better explain me: it looks like there will be not a Quad/Dual with an increased chip revision. The new chip revision for i.MX6 is really the QP (P=perfect, as I see some workaround can be removed !)

Quoted 2 lines

Is it correct ? Else this conflicts if a 6Q with a revision > 2 will be released.

P mean plus. It is from 6Q, since ic did not give new chip id for id, we use revision.

Quoted 4 lines

Best regards,
Stefano Babic

Regards,
Peng.

Quoted 6 lines

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Stefano Babic

2015-06-10 10:09 UTC #4 lore raw

PATCH 2/8 imx: mx6: Add MX6DQP CPU rev type

Hi Peng,

Quoted 10 lines · Peng Fan

Quoted 10 lines
arch/arm/include/asm/arch-mx6/sys_proto.h const char *get_imx_type(u32 imxtype); · line 38
Quoted 4 lines
arch/arm/include/asm/arch-mx6/sys_proto.h +4 -0
+#define is_mx6dqp() ((is_cpu_type(MXC_CPU_MX6Q) || \
+		     is_cpu_type(MXC_CPU_MX6D)) && \
+		     (is_soc_rev(CHIP_REV_2_0) >= 0))
+
As "insider" you could better explain me: it looks like there will be not a Quad/Dual with an increased chip revision. The new chip revision for i.MX6 is really the QP (P=perfect, as I see some workaround can be removed !)

Quoted 3 lines

Quoted 2 lines
Is it correct ? Else this conflicts if a 6Q with a revision > 2 will be released.
P mean plus.

I know, it was only a joke ;-). There is not "perfect" SOC.

Quoted 2 lines

It is from 6Q, since ic did not give new chip id for id, we use revision.

This is ok now until a 6Q with revision 2 or greater will be released. Then there is a conflict and u-boot cannot identify a 6QP from a 6Q. But it is still ok if Freescale will *never* plan to release a newer 6Q. Is it ?

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Peng Fan

author

2015-06-10 08:06 UTC #5 lore raw

PATCH 3/8 imx: mx6: L2cache: Enable the double line fill for i.MX6DQP

In reply to Peng Fan

From: "Ye.Li" <[email protected]>

Since i.MX6DQP has fixed the L2 cache issue, enable the double line fill feature to provide better performance.

Signed-off-by Ye.Li <[email protected]>

Signed-off-by Peng Fan <[email protected]>

---
 arch/arm/cpu/armv7/mx6/soc.c | 3 +++
 1 file changed, 3 insertions(+)

arch/arm/cpu/armv7/mx6/soc.c +3 -0

index 29de624..e3474e7 100644
@@ -645,6 +645,9 @@ void v7_outer_cache_enable(void)
 
 #ifndef CONFIG_MX6Q
 	val |= 0x40800000;
+#else
+	if (is_mx6dqp())
+		val |= 0x40800000;
 #endif
 	writel(val, &pl310->pl310_prefetch_ctrl);

Signature · 1 line

1.8.4

Peng Fan

author

2015-06-10 08:06 UTC #6 lore raw

PATCH 4/8 imx: mx6: ccm: Change the clock settings for i.MX6QP

In reply to Peng Fan

Since i.MX6QP changes some CCM registers, so modify the clocks settings to follow the hardware changes.

A new CONFIG_MX6QP is introduced here and is used for the CCM difference. At default CONFIG_MX6Q is enabled along with the CONFIG_MX6QP.

Signed-off-by Ye.Li <[email protected]>

Signed-off-by Peng Fan <[email protected]>

---
 arch/arm/cpu/armv7/mx6/clock.c           | 13 +++++---
 arch/arm/cpu/armv7/mx6/soc.c             |  5 ++-
 arch/arm/include/asm/arch-mx6/crm_regs.h | 55 ++++++++++++++++++++++++--------
 include/configs/mx6_common.h             |  3 ++
 4 files changed, 57 insertions(+), 19 deletions(-)

arch/arm/cpu/armv7/mx6/clock.c +9 -4

index ae99945..36cd5a8 100644
@@ -323,7 +323,7 @@ static u32 get_ipg_per_clk(void)
 	u32 reg, perclk_podf;
 
 	reg = __raw_readl(&imx_ccm->cscmr1);
-#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
+#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6QP))
 	if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
 		return MXC_HCLK; /* OSC 24Mhz */
 #endif

@@ -337,7 +337,7 @@ static u32 get_uart_clk(void)
 	u32 reg, uart_podf;
 	u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
 	reg = __raw_readl(&imx_ccm->cscdr1);
-#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
+#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6QP))
 	if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
 		freq = MXC_HCLK;
 #endif

@@ -352,8 +352,13 @@ static u32 get_cspi_clk(void)
 	u32 reg, cspi_podf;
 
 	reg = __raw_readl(&imx_ccm->cscdr2);
-	reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK;
-	cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
+	cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK)
+		>> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
+
+#if defined(CONFIG_MX6QP)
+	if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
+		return MXC_HCLK / (cspi_podf + 1);
+#endif
 
 	return	decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
 }

arch/arm/cpu/armv7/mx6/soc.c +4 -1

index e3474e7..5eea9d9 100644
@@ -335,9 +335,12 @@ static void set_ahb_rate(u32 val)
 static void clear_mmdc_ch_mask(void)
 {
 	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	u32 reg;
+	reg = readl(&mxc_ccm->ccdr);
 
 	/* Clear MMDC channel mask */
-	writel(0, &mxc_ccm->ccdr);
+	reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
+	writel(reg, &mxc_ccm->ccdr);
 }
 
 static void init_bandgap(void)

arch/arm/include/asm/arch-mx6/crm_regs.h +41 ~~-14~~

120 lines not on this page · raw message

include/configs/mx6_common.h +3 -0

index 50370e1..b5de280 100644
@@ -30,6 +30,9 @@
 
 #define CONFIG_MP
 #define CONFIG_MXC_GPT_HCLK
+#ifdef CONFIG_MX6QP
+#define CONFIG_MX6Q
+#endif
 
 #define CONFIG_SYS_NO_FLASH

Signature · 1 line

1.8.4

Stefano Babic

2015-06-10 09:23 UTC #7 lore raw

PATCH 4/8 imx: mx6: ccm: Change the clock settings for i.MX6QP

Hi Peng,

Quoted 20 lines · Peng Fan

Since i.MX6QP changes some CCM registers, so modify the clocks settings to follow the hardware changes.
A new CONFIG_MX6QP is introduced here and is used for the CCM difference. At default CONFIG_MX6Q is enabled along with the CONFIG_MX6QP.
Signed-off-by Ye.Li <[email protected]>
Signed-off-by Peng Fan <[email protected]>
---
 arch/arm/cpu/armv7/mx6/clock.c           | 13 +++++---
 arch/arm/cpu/armv7/mx6/soc.c             |  5 ++-
 arch/arm/include/asm/arch-mx6/crm_regs.h | 55 ++++++++++++++++++++++++--------
 include/configs/mx6_common.h             |  3 ++
 4 files changed, 57 insertions(+), 19 deletions(-)
arch/arm/cpu/armv7/mx6/clock.c +0 -0
index ae99945..36cd5a8 100644

arch/arm/cpu/armv7/mx6/clock.c static u32 get_ipg_per_clk(void) · line 328

Quoted 7 lines

arch/arm/cpu/armv7/mx6/clock.c +1 -1

@@ -323,7 +323,7 @@ static u32 get_ipg_per_clk(void)
 	u32 reg, perclk_podf;
 
 	reg = __raw_readl(&imx_ccm->cscmr1);
-#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
+#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6QP))
 	if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
 		return MXC_HCLK; /* OSC 24Mhz */

I have a general issue. We already manage to have support for multiple variants of MX6 (at least, dual/quad/solo) with a single image. We get it dropping nasty #ifdef in case of quad/dual. I assume there are only slight changes in layout for the 6QP. Cannot we manage these changes at runtime instead of introducing a compiler switch ?

Quoted 183 lines

arch/arm/cpu/armv7/mx6/clock.c +8 -3

 #endif

@@ -337,7 +337,7 @@ static u32 get_uart_clk(void)
 	u32 reg, uart_podf;
 	u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
 	reg = __raw_readl(&imx_ccm->cscdr1);
-#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
+#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6QP))
 	if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
 		freq = MXC_HCLK;
 #endif

@@ -352,8 +352,13 @@ static u32 get_cspi_clk(void)
 	u32 reg, cspi_podf;
 
 	reg = __raw_readl(&imx_ccm->cscdr2);
-	reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK;
-	cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
+	cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK)
+		>> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
+
+#if defined(CONFIG_MX6QP)
+	if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
+		return MXC_HCLK / (cspi_podf + 1);
+#endif
 
 	return	decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
 }

arch/arm/cpu/armv7/mx6/soc.c +4 -1

index e3474e7..5eea9d9 100644
@@ -335,9 +335,12 @@ static void set_ahb_rate(u32 val)
 static void clear_mmdc_ch_mask(void)
 {
 	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	u32 reg;
+	reg = readl(&mxc_ccm->ccdr);
 
 	/* Clear MMDC channel mask */
-	writel(0, &mxc_ccm->ccdr);
+	reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
+	writel(reg, &mxc_ccm->ccdr);
 }
 
 static void init_bandgap(void)

arch/arm/include/asm/arch-mx6/crm_regs.h +41 ~~-14~~

index 887d048..576dabe 100644
@@ -113,7 +113,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCR_WB_COUNT_MASK			0x7
 #define MXC_CCM_CCR_WB_COUNT_OFFSET			(1 << 16)
 #define MXC_CCM_CCR_COSC_EN				(1 << 12)
-#ifdef CONFIG_MX6SX
+#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6QP))
 #define MXC_CCM_CCR_OSCNT_MASK				0x7F
 #else
 #define MXC_CCM_CCR_OSCNT_MASK				0xFF

@@ -123,6 +123,9 @@ struct mxc_ccm_reg {
 /* Define the bits in register CCDR */
 #define MXC_CCM_CCDR_MMDC_CH1_HS_MASK			(1 << 16)
 #define MXC_CCM_CCDR_MMDC_CH0_HS_MASK			(1 << 17)
+#ifdef CONFIG_MX6QP
+#define MXC_CCM_CCDR_MMDC_CH1_AXI_ROOT_CG	(1 << 18)
+#endif
 
 /* Define the bits in register CSR */
 #define MXC_CCM_CSR_COSC_READY				(1 << 5)

@@ -196,7 +199,11 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK		(0x3 << 4)
 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET		4
 #ifndef CONFIG_MX6SX
+#ifdef CONFIG_MX6QP
+#define MXC_CCM_CBCMR_PRE_CLK_SEL			(1 << 1)
+#else
 #define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL			(1 << 1)
+#endif
 #define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL			(1 << 0)
 #endif

@@ -229,7 +236,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK		(0x7 << 7)
 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET		7
 #endif
-#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
+#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6QP))
 #define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK			(1 << 6)
 #define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET		6
 #endif

@@ -244,15 +251,12 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET		19
 #define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV			(1 << 11)
 #define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV			(1 << 10)
-#ifdef CONFIG_MX6SX
+#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6QP))
 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK			(0x3 << 8)
 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET		8
+#endif
 #define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK		(0x3F << 2)
 #define MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET		2
-#else
-#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK			(0x3F << 2)
-#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET		2
-#endif
 
 /* Define the bits in register CSCDR1 */
 #ifndef CONFIG_MX6SX

@@ -273,15 +277,10 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET		6
 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK		(0x3 << 6)
 #endif
-#ifdef CONFIG_MX6SL
-#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK		0x1F
-#define MXC_CCM_CSCDR1_UART_CLK_SEL			(1 << 6)
-#else
-#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK		0x3F
-#ifdef CONFIG_MX6SX
+#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6QP))
 #define MXC_CCM_CSCDR1_UART_CLK_SEL			(1 << 6)
 #endif
-#endif
+#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK		0x3F
 #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET		0
 
 /* Define the bits in register CS1CDR */

@@ -316,10 +315,17 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK		(0x7 << 18)
 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET		18
 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v)			(((v) & 0x7) << 18)
+
+#ifdef CONFIG_MX6QP
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK		(0x7 << 15)
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET		15
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v)			(((v) & 0x7) << 15)
+#else
 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK		(0x3 << 16)
 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET		16
 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v)			(((v) & 0x3) << 16)
 #endif
+#endif
 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK		(0x7 << 12)
 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET		12
 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK		(0x7 << 9)

@@ -384,6 +390,11 @@ struct mxc_ccm_reg {
 /* Define the bits in register CSCDR2 */
 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK		(0x3F << 19)
 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET		19
+#ifdef CONFIG_MX6QP
+#define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK		(0x1 << 18)
+#define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_OFFSET		18
+#endif
+
 /* All IPU2_DI1 are LCDIF1 on MX6SX */
 #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK	(0x7 << 15)
 #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET	15

@@ -758,6 +769,22 @@ struct mxc_ccm_reg {
 #else
 #define MXC_CCM_CCGR6_VDOAXICLK_OFFSET		12
 #define MXC_CCM_CCGR6_VDOAXICLK_MASK		(3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
+#ifdef CONFIG_MX6QP
+#define MXC_CCM_CCGR6_VPUCLK_OFFSET	14
+#define MXC_CCM_CCGR6_VPUCLK_MASK	(3 << MXC_CCM_CCGR6_VPUCLK_OFFSET)
+#define MXC_CCM_CCGR6_PRE_CLK0_OFFSET	16
+#define MXC_CCM_CCGR6_PRE_CLK0_MASK	(3 << MXC_CCM_CCGR6_PRE_CLK0_OFFSET)
+#define MXC_CCM_CCGR6_PRE_CLK1_OFFSET	18
+#define MXC_CCM_CCGR6_PRE_CLK1_MASK	(3 << MXC_CCM_CCGR6_PRE_CLK1_OFFSET)
+#define MXC_CCM_CCGR6_PRE_CLK2_OFFSET	20
+#define MXC_CCM_CCGR6_PRE_CLK2_MASK	(3 << MXC_CCM_CCGR6_PRE_CLK2_OFFSET)
+#define MXC_CCM_CCGR6_PRE_CLK3_OFFSET	22
+#define MXC_CCM_CCGR6_PRE_CLK3_MASK	(3 << MXC_CCM_CCGR6_PRE_CLK3_OFFSET)
+#define MXC_CCM_CCGR6_PRG_CLK0_OFFSET	24
+#define MXC_CCM_CCGR6_PRG_CLK0_MASK	(3 << MXC_CCM_CCGR6_PRG_CLK0_OFFSET)
+#define MXC_CCM_CCGR6_PRG_CLK1_OFFSET	26
+#define MXC_CCM_CCGR6_PRG_CLK1_MASK	(3 << MXC_CCM_CCGR6_PRG_CLK1_OFFSET)
+#endif
 #endif
 
 #define BM_ANADIG_PLL_SYS_LOCK 0x80000000

include/configs/mx6_common.h +0 -0

index 50370e1..b5de280 100644

include/configs/mx6_common.h line 38

Quoted 9 lines

include/configs/mx6_common.h +3 -0

@@ -30,6 +30,9 @@
 
 #define CONFIG_MP
 #define CONFIG_MXC_GPT_HCLK
+#ifdef CONFIG_MX6QP
+#define CONFIG_MX6Q
+#endif
 
 #define CONFIG_SYS_NO_FLASH

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Peng Fan

2015-06-10 10:03 UTC #8 lore raw

PATCH 4/8 imx: mx6: ccm: Change the clock settings for i.MX6QP

Hi Stefano,

Quoted 25 lines · Stefano Babic

Hi Peng,
Quoted 22 lines · Peng Fan
Since i.MX6QP changes some CCM registers, so modify the clocks settings to follow the hardware changes.
A new CONFIG_MX6QP is introduced here and is used for the CCM difference. At default CONFIG_MX6Q is enabled along with the CONFIG_MX6QP.
Signed-off-by Ye.Li <[email protected]>
Signed-off-by Peng Fan <[email protected]>
---
 arch/arm/cpu/armv7/mx6/clock.c           | 13 +++++---
 arch/arm/cpu/armv7/mx6/soc.c             |  5 ++-
 arch/arm/include/asm/arch-mx6/crm_regs.h | 55 ++++++++++++++++++++++++--------
 include/configs/mx6_common.h             |  3 ++
 4 files changed, 57 insertions(+), 19 deletions(-)
arch/arm/cpu/armv7/mx6/clock.c +0 -0
index ae99945..36cd5a8 100644
@@ -323,7 +323,7 @@ static u32 get_ipg_per_clk(void)
 	u32 reg, perclk_podf;
 

Quoted 11 lines

arch/arm/cpu/armv7/mx6/clock.c static u32 get_ipg_per_clk(void) · line 328
Quoted 5 lines
arch/arm/cpu/armv7/mx6/clock.c +1 -1
 	reg = __raw_readl(&imx_ccm->cscmr1);
-#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
+#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6QP))
 	if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
 		return MXC_HCLK; /* OSC 24Mhz */
I have a general issue. We already manage to have support for multiple variants of MX6 (at least, dual/quad/solo) with a single image. We get it dropping nasty #ifdef in case of quad/dual. I assume there are only slight changes in layout for the 6QP. Cannot we manage these changes at runtime instead of introducing a compiler switch ?

Yeah, better do runtime check. Will fix this in v2.

Quoted 190 lines

arch/arm/cpu/armv7/mx6/clock.c +8 -3

 #endif

@@ -337,7 +337,7 @@ static u32 get_uart_clk(void)
 	u32 reg, uart_podf;
 	u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
 	reg = __raw_readl(&imx_ccm->cscdr1);
-#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
+#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6QP))
 	if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
 		freq = MXC_HCLK;
 #endif

@@ -352,8 +352,13 @@ static u32 get_cspi_clk(void)
 	u32 reg, cspi_podf;
 
 	reg = __raw_readl(&imx_ccm->cscdr2);
-	reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK;
-	cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
+	cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK)
+		>> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
+
+#if defined(CONFIG_MX6QP)
+	if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
+		return MXC_HCLK / (cspi_podf + 1);
+#endif
 
 	return	decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
 }

arch/arm/cpu/armv7/mx6/soc.c +4 -1

index e3474e7..5eea9d9 100644
@@ -335,9 +335,12 @@ static void set_ahb_rate(u32 val)
 static void clear_mmdc_ch_mask(void)
 {
 	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	u32 reg;
+	reg = readl(&mxc_ccm->ccdr);
 
 	/* Clear MMDC channel mask */
-	writel(0, &mxc_ccm->ccdr);
+	reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
+	writel(reg, &mxc_ccm->ccdr);
 }
 
 static void init_bandgap(void)

arch/arm/include/asm/arch-mx6/crm_regs.h +41 ~~-14~~

index 887d048..576dabe 100644
@@ -113,7 +113,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCR_WB_COUNT_MASK			0x7
 #define MXC_CCM_CCR_WB_COUNT_OFFSET			(1 << 16)
 #define MXC_CCM_CCR_COSC_EN				(1 << 12)
-#ifdef CONFIG_MX6SX
+#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6QP))
 #define MXC_CCM_CCR_OSCNT_MASK				0x7F
 #else
 #define MXC_CCM_CCR_OSCNT_MASK				0xFF

@@ -123,6 +123,9 @@ struct mxc_ccm_reg {
 /* Define the bits in register CCDR */
 #define MXC_CCM_CCDR_MMDC_CH1_HS_MASK			(1 << 16)
 #define MXC_CCM_CCDR_MMDC_CH0_HS_MASK			(1 << 17)
+#ifdef CONFIG_MX6QP
+#define MXC_CCM_CCDR_MMDC_CH1_AXI_ROOT_CG	(1 << 18)
+#endif
 
 /* Define the bits in register CSR */
 #define MXC_CCM_CSR_COSC_READY				(1 << 5)

@@ -196,7 +199,11 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK		(0x3 << 4)
 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET		4
 #ifndef CONFIG_MX6SX
+#ifdef CONFIG_MX6QP
+#define MXC_CCM_CBCMR_PRE_CLK_SEL			(1 << 1)
+#else
 #define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL			(1 << 1)
+#endif
 #define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL			(1 << 0)
 #endif

@@ -229,7 +236,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK		(0x7 << 7)
 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET		7
 #endif
-#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
+#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6QP))
 #define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK			(1 << 6)
 #define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET		6
 #endif

@@ -244,15 +251,12 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET		19
 #define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV			(1 << 11)
 #define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV			(1 << 10)
-#ifdef CONFIG_MX6SX
+#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6QP))
 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK			(0x3 << 8)
 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET		8
+#endif
 #define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK		(0x3F << 2)
 #define MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET		2
-#else
-#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK			(0x3F << 2)
-#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET		2
-#endif
 
 /* Define the bits in register CSCDR1 */
 #ifndef CONFIG_MX6SX

@@ -273,15 +277,10 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET		6
 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK		(0x3 << 6)
 #endif
-#ifdef CONFIG_MX6SL
-#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK		0x1F
-#define MXC_CCM_CSCDR1_UART_CLK_SEL			(1 << 6)
-#else
-#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK		0x3F
-#ifdef CONFIG_MX6SX
+#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6QP))
 #define MXC_CCM_CSCDR1_UART_CLK_SEL			(1 << 6)
 #endif
-#endif
+#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK		0x3F
 #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET		0
 
 /* Define the bits in register CS1CDR */

@@ -316,10 +315,17 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK		(0x7 << 18)
 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET		18
 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v)			(((v) & 0x7) << 18)
+
+#ifdef CONFIG_MX6QP
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK		(0x7 << 15)
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET		15
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v)			(((v) & 0x7) << 15)
+#else
 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK		(0x3 << 16)
 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET		16
 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v)			(((v) & 0x3) << 16)
 #endif
+#endif
 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK		(0x7 << 12)
 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET		12
 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK		(0x7 << 9)

@@ -384,6 +390,11 @@ struct mxc_ccm_reg {
 /* Define the bits in register CSCDR2 */
 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK		(0x3F << 19)
 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET		19
+#ifdef CONFIG_MX6QP
+#define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK		(0x1 << 18)
+#define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_OFFSET		18
+#endif
+
 /* All IPU2_DI1 are LCDIF1 on MX6SX */
 #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK	(0x7 << 15)
 #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET	15

@@ -758,6 +769,22 @@ struct mxc_ccm_reg {
 #else
 #define MXC_CCM_CCGR6_VDOAXICLK_OFFSET		12
 #define MXC_CCM_CCGR6_VDOAXICLK_MASK		(3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
+#ifdef CONFIG_MX6QP
+#define MXC_CCM_CCGR6_VPUCLK_OFFSET	14
+#define MXC_CCM_CCGR6_VPUCLK_MASK	(3 << MXC_CCM_CCGR6_VPUCLK_OFFSET)
+#define MXC_CCM_CCGR6_PRE_CLK0_OFFSET	16
+#define MXC_CCM_CCGR6_PRE_CLK0_MASK	(3 << MXC_CCM_CCGR6_PRE_CLK0_OFFSET)
+#define MXC_CCM_CCGR6_PRE_CLK1_OFFSET	18
+#define MXC_CCM_CCGR6_PRE_CLK1_MASK	(3 << MXC_CCM_CCGR6_PRE_CLK1_OFFSET)
+#define MXC_CCM_CCGR6_PRE_CLK2_OFFSET	20
+#define MXC_CCM_CCGR6_PRE_CLK2_MASK	(3 << MXC_CCM_CCGR6_PRE_CLK2_OFFSET)
+#define MXC_CCM_CCGR6_PRE_CLK3_OFFSET	22
+#define MXC_CCM_CCGR6_PRE_CLK3_MASK	(3 << MXC_CCM_CCGR6_PRE_CLK3_OFFSET)
+#define MXC_CCM_CCGR6_PRG_CLK0_OFFSET	24
+#define MXC_CCM_CCGR6_PRG_CLK0_MASK	(3 << MXC_CCM_CCGR6_PRG_CLK0_OFFSET)
+#define MXC_CCM_CCGR6_PRG_CLK1_OFFSET	26
+#define MXC_CCM_CCGR6_PRG_CLK1_MASK	(3 << MXC_CCM_CCGR6_PRG_CLK1_OFFSET)
+#endif
 #endif
 
 #define BM_ANADIG_PLL_SYS_LOCK 0x80000000

include/configs/mx6_common.h +3 -0

index 50370e1..b5de280 100644
@@ -30,6 +30,9 @@
 
 #define CONFIG_MP
 #define CONFIG_MXC_GPT_HCLK
+#ifdef CONFIG_MX6QP
+#define CONFIG_MX6Q
+#endif

Quoted 13 lines

include/configs/mx6_common.h line 38

Quoted 3 lines

include/configs/mx6_common.h +0 -0
 #define CONFIG_SYS_NO_FLASH
 

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Regards,
Peng

Peng Fan

author

2015-06-10 08:06 UTC #9 lore raw

PATCH 5/8 imx: mx6: hab : Remove the cache issue workaroud in hab for i.MX6QP

In reply to Peng Fan

From: "Ye.Li" <[email protected]>

Since the i.MX6QP has fixed the issue in boot ROM, so remove the workaround for i.MX6QP.

Signed-off-by Ye.Li <[email protected]>

Signed-off-by Peng Fan <[email protected]>

---
 arch/arm/cpu/armv7/mx6/hab.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

arch/arm/cpu/armv7/mx6/hab.c +2 -1

index 8dee595..bf7dbf0 100644
@@ -252,7 +252,8 @@ uint32_t authenticate_image(uint32_t ddr_start, uint32_t image_size)
 					 * do cache flushes. don't think any
 					 * exist, so we ignore them.
 					 */
-					writel(1, MX6DQ_PU_IROM_MMU_EN_VAR);
+					if (!is_mx6dqp())
+						writel(1, MX6DQ_PU_IROM_MMU_EN_VAR);
 				} else if (is_cpu_type(MXC_CPU_MX6DL) ||
 					   is_cpu_type(MXC_CPU_MX6SOLO)) {
 					writel(1, MX6DLS_PU_IROM_MMU_EN_VAR);

Signature · 1 line

1.8.4

Peng Fan

author

2015-06-10 08:06 UTC #10 lore raw

PATCH 6/8 imx: mx6qp: Enable PRG clock for IPU

In reply to Peng Fan

From: "Ye.Li" <[email protected]>

The i.MX6QP has a PRG module, need to enable its clock for using IPU.

Signed-off-by Peng Fan <[email protected]>

Signed-off-by Brown Oliver <[email protected]>

Signed-off-by Ye.Li <[email protected]>

---
 arch/arm/cpu/armv7/mx6/clock.c | 6 ++++++
 1 file changed, 6 insertions(+)

arch/arm/cpu/armv7/mx6/clock.c +6 -0

index 36cd5a8..ae1b4cc 100644
@@ -861,6 +861,12 @@ void enable_ipu_clock(void)
 	reg = readl(&mxc_ccm->CCGR3);
 	reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
 	writel(reg, &mxc_ccm->CCGR3);
+
+#ifdef CONFIG_MX6QP
+	reg = readl(&mxc_ccm->CCGR6);
+	reg |= MXC_CCM_CCGR6_PRG_CLK0_MASK;
+	writel(reg, &mxc_ccm->CCGR6);
+#endif
 }
 #endif
 /***************************************************/

Signature · 1 line

1.8.4

Stefano Babic

2015-06-10 09:24 UTC #11 lore raw

PATCH 6/8 imx: mx6qp: Enable PRG clock for IPU

Quoted 17 lines · Peng Fan

From: "Ye.Li" <[email protected]>
The i.MX6QP has a PRG module, need to enable its clock for using IPU.
Signed-off-by Peng Fan <[email protected]>
Signed-off-by Brown Oliver <[email protected]>
Signed-off-by Ye.Li <[email protected]>
---
 arch/arm/cpu/armv7/mx6/clock.c | 6 ++++++
 1 file changed, 6 insertions(+)
arch/arm/cpu/armv7/mx6/clock.c +0 -0
index 36cd5a8..ae1b4cc 100644

arch/arm/cpu/armv7/mx6/clock.c void enable_ipu_clock(void) · line 868

Quoted 8 lines

arch/arm/cpu/armv7/mx6/clock.c +5 -0

@@ -861,6 +861,12 @@ void enable_ipu_clock(void)
 	reg = readl(&mxc_ccm->CCGR3);
 	reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
 	writel(reg, &mxc_ccm->CCGR3);
+
+#ifdef CONFIG_MX6QP
+	reg = readl(&mxc_ccm->CCGR6);
+	reg |= MXC_CCM_CCGR6_PRG_CLK0_MASK;
+	writel(reg, &mxc_ccm->CCGR6);

This is easy to replace with runtime detection.

arch/arm/cpu/armv7/mx6/clock.c void enable_ipu_clock(void) · line 872

Quoted 5 lines

arch/arm/cpu/armv7/mx6/clock.c +1 -0

+#endif
 }
 #endif
 /***************************************************/

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Peng Fan

2015-06-10 10:04 UTC #12 lore raw

PATCH 6/8 imx: mx6qp: Enable PRG clock for IPU

Quoted 13 lines · Stefano Babic

Quoted 12 lines · Peng Fan
From: "Ye.Li" <[email protected]>
The i.MX6QP has a PRG module, need to enable its clock for using IPU.
Signed-off-by Peng Fan <[email protected]>
Signed-off-by Brown Oliver <[email protected]>
Signed-off-by Ye.Li <[email protected]>
---
 arch/arm/cpu/armv7/mx6/clock.c | 6 ++++++
 1 file changed, 6 insertions(+)

Quoted 15 lines

arch/arm/cpu/armv7/mx6/clock.c void enable_ipu_clock(void) · line 868
Quoted 13 lines
arch/arm/cpu/armv7/mx6/clock.c +5 -0
index 36cd5a8..ae1b4cc 100644
@@ -861,6 +861,12 @@ void enable_ipu_clock(void)
 	reg = readl(&mxc_ccm->CCGR3);
 	reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
 	writel(reg, &mxc_ccm->CCGR3);
+
+#ifdef CONFIG_MX6QP
+	reg = readl(&mxc_ccm->CCGR6);
+	reg |= MXC_CCM_CCGR6_PRG_CLK0_MASK;
+	writel(reg, &mxc_ccm->CCGR6);
This is easy to replace with runtime detection.

Will fix in v2.

Quoted 16 lines

arch/arm/cpu/armv7/mx6/clock.c void enable_ipu_clock(void) · line 872

Quoted 6 lines

arch/arm/cpu/armv7/mx6/clock.c +1 -0

+#endif
 }
 #endif
 /***************************************************/

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Regards,
Peng

Peng Fan

author

2015-06-10 08:06 UTC #13 lore raw

PATCH 7/8 imx: mx6qpsabreauto: Add MX6QP SABREAUTO CPU3 board support

In reply to Peng Fan

1. Add DDR script for mx6qpsabreauto board.
2. On CPU3 board, enet RGMII tx clock is from internal PLL. Set the GPR5[9] and init the enet pll output to 125Mhz.
3. On CPU3 board, SW1ABC=VDDSOC_IN, SW2=VDDARM_IN.

Build target: mx6qpsabreauto_config

U-Boot 2015.07-rc2-00008-g594f506 (Jun 10 2015 - 16:01:36 +0800)

Boot Log:

CPU:   Freescale i.MX6Q rev2.0 996 MHz (running at 792 MHz)
CPU:   Automotive temperature grade (-40C to 125C) at 36C
Reset cause: POR
Board: MX6Q-Sabreauto revA
I2C:   ready
DRAM:  2 GiB
PMIC:  PFUZE100 ID=0x10
Flash: 32 MiB
NAND:  4096 MiB
MMC:   FSL_SDHC: 0

*** Warning - bad CRC, using default environment

No panel detected: default to HDMI
Display: HDMI (1024x768)
In:    serial
Out:   serial
Err:   serial
Net:   FEC [PRIME]
Error: FEC address not set.

Hit any key to stop autoboot: 0

Signed-off-by Robin Gong <[email protected]>

Signed-off-by Ye.Li <[email protected]>

Signed-off-by Peng Fan <[email protected]>

---
 board/freescale/mx6qsabreauto/mx6qp.cfg       | 158 ++++++++++++++++++++++++++
 board/freescale/mx6qsabreauto/mx6qsabreauto.c |  32 +++++-
 configs/mx6qpsabreauto_defconfig              |   5 +
 include/configs/mx6qsabreauto.h               |   5 +-
 4 files changed, 194 insertions(+), 6 deletions(-)
 create mode 100644 board/freescale/mx6qsabreauto/mx6qp.cfg
 create mode 100644 configs/mx6qpsabreauto_defconfig

board/freescale/mx6qsabreauto/mx6qp.cfg new file +158 -0

new file mode 100644
index 0000000..5d55bcc
@@ -0,0 +1,158 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+/* image version */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of spi, sd, eimnor, nand, sata:
+ * spinor: flash_offset: 0x0400
+ * nand:   flash_offset: 0x0400
+ * sata:   flash_offset: 0x0400
+ * sd/mmc: flash_offset: 0x0400
+ * eimnor: flash_offset: 0x1000
+ */
+
+#if defined(CONFIG_SYS_BOOT_EIMNOR)
+BOOT_FROM	nor
+#else /* others has the same flash_offset as sd */
+BOOT_FROM	sd
+#endif
+
+#ifdef CONFIG_USE_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx6qsabreauto/plugin.bin 0x00907000
+#else
+
+#ifdef CONFIG_SECURE_BOOT
+CSF 0x2000
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+DATA 4 0x020e0798 0x000C0000
+DATA 4 0x020e0758 0x00000000
+DATA 4 0x020e0588 0x00000030
+DATA 4 0x020e0594 0x00000030
+DATA 4 0x020e056c 0x00000030
+DATA 4 0x020e0578 0x00000030
+DATA 4 0x020e074c 0x00000030
+DATA 4 0x020e057c 0x00000030
+DATA 4 0x020e058c 0x00000000
+DATA 4 0x020e059c 0x00000030
+DATA 4 0x020e05a0 0x00000030
+DATA 4 0x020e078c 0x00000030
+DATA 4 0x020e0750 0x00020000
+DATA 4 0x020e05a8 0x00000030
+DATA 4 0x020e05b0 0x00000030
+DATA 4 0x020e0524 0x00000030
+DATA 4 0x020e051c 0x00000030
+DATA 4 0x020e0518 0x00000030
+DATA 4 0x020e050c 0x00000030
+DATA 4 0x020e05b8 0x00000030
+DATA 4 0x020e05c0 0x00000030
+DATA 4 0x020e0774 0x00020000
+DATA 4 0x020e0784 0x00000030
+DATA 4 0x020e0788 0x00000030
+DATA 4 0x020e0794 0x00000030
+DATA 4 0x020e079c 0x00000030
+DATA 4 0x020e07a0 0x00000030
+DATA 4 0x020e07a4 0x00000030
+DATA 4 0x020e07a8 0x00000030
+DATA 4 0x020e0748 0x00000030
+DATA 4 0x020e05ac 0x00000030
+DATA 4 0x020e05b4 0x00000030
+DATA 4 0x020e0528 0x00000030
+DATA 4 0x020e0520 0x00000030
+DATA 4 0x020e0514 0x00000030
+DATA 4 0x020e0510 0x00000030
+DATA 4 0x020e05bc 0x00000030
+DATA 4 0x020e05c4 0x00000030
+DATA 4 0x021b0800 0xa1390003
+DATA 4 0x021b080c 0x001b001e
+DATA 4 0x021b0810 0x002e0029
+DATA 4 0x021b480c 0x001b002a
+DATA 4 0x021b4810 0x0019002c
+DATA 4 0x021b083c 0x43240334
+DATA 4 0x021b0840 0x0324031a
+DATA 4 0x021b483c 0x43340344
+DATA 4 0x021b4840 0x03280276
+DATA 4 0x021b0848 0x44383A3E
+DATA 4 0x021b4848 0x3C3C3846
+DATA 4 0x021b0850 0x2e303230
+DATA 4 0x021b4850 0x38283E34
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+DATA 4 0x021b481c 0x33333333
+DATA 4 0x021b4820 0x33333333
+DATA 4 0x021b4824 0x33333333
+DATA 4 0x021b4828 0x33333333
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b48b8 0x00000800
+DATA 4 0x021b0004 0x00020036
+DATA 4 0x021b0008 0x09444040
+DATA 4 0x021b000c 0x898E7955
+DATA 4 0x021b0010 0xFF328F64
+DATA 4 0x021b0014 0x01FF00DB
+DATA 4 0x021b0018 0x00001740
+DATA 4 0x021b001c 0x00008000
+
+DATA 4 0x021b002c 0x000026d2
+DATA 4 0x021b0030 0x008E1023
+DATA 4 0x021b0040 0x00000047
+DATA 4 0x021b0400 0x12420000
+DATA 4 0x021b0000 0x841A0000
+DATA 4 0x00bb0008 0x00000004
+DATA 4 0x00bb000c 0x2891E41A
+DATA 4 0x00bb0038 0x00000564
+DATA 4 0x00bb0014 0x00000040
+DATA 4 0x00bb0028 0x00000020
+DATA 4 0x00bb002c 0x00000020
+DATA 4 0x021b001c 0x04088032
+DATA 4 0x021b001c 0x00008033
+DATA 4 0x021b001c 0x00048031
+DATA 4 0x021b001c 0x09408030
+DATA 4 0x021b001c 0x04008040
+DATA 4 0x021b0020 0x00005800
+DATA 4 0x021b0818 0x00011117
+DATA 4 0x021b4818 0x00011117
+DATA 4 0x021b0004 0x00025576
+DATA 4 0x021b0404 0x00011006
+DATA 4 0x021b001c 0x00000000
+/* set the default clock gate to save power */
+DATA 4, 0x020c4068, 0x00C03F3F
+DATA 4, 0x020c406c, 0x0030FC03
+DATA 4, 0x020c4070, 0x0FFFC000
+DATA 4, 0x020c4074, 0x3FF00000
+DATA 4, 0x020c4078, 0xFFFFF300
+DATA 4, 0x020c407c, 0x0F0000F3
+DATA 4, 0x020c4080, 0x00000FFF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, 0x020e0010, 0xF00000CF
+/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
+DATA 4, 0x020e0018, 0x77177717
+DATA 4, 0x020e001c, 0x77177717
+#endif

board/freescale/mx6qsabreauto/mx6qsabreauto.c +27 -5

index b76e4eb..83e34c6 100644
@@ -354,9 +354,27 @@ int board_phy_config(struct phy_device *phydev)
 	return 0;
 }
 
+static int setup_fec(void)
+{
+	int ret;
+
+#ifdef CONFIG_MX6QP
+	imx_iomux_set_gpr_register(5, 9, 1, 1);
+#else
+	imx_iomux_set_gpr_register(1, 21, 1, 1);
+#endif
+
+	ret = enable_fec_anatop_clock(ENET_125MHZ);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
 int board_eth_init(bd_t *bis)
 {
 	setup_iomux_enet();
+	setup_fec();
 
 	return cpu_eth_init(bis);
 }

@@ -495,17 +513,21 @@ int board_spi_cs_gpio(unsigned bus, unsigned cs)
 int power_init_board(void)
 {
 	struct pmic *p;
-	unsigned int ret;
+	unsigned int value;
 
 	p = pfuze_common_init(I2C_PMIC);
 	if (!p)
 		return -ENODEV;
 
-	ret = pfuze_mode_init(p, APS_PFM);
-	if (ret < 0)
-		return ret;
+	if (is_mx6dqp()) {
+		/* set SW2 staby volatage 0.975V*/
+		pmic_reg_read(p, PFUZE100_SW2STBY, &value);
+		value &= ~0x3f;
+		value |= 0x17;
+		pmic_reg_write(p, PFUZE100_SW2STBY, value);
+	}
 
-	return 0;
+	return pfuze_mode_init(p, APS_PFM);
 }
 
 #ifdef CONFIG_CMD_BMODE

configs/mx6qpsabreauto_defconfig new file +5 -0

new file mode 100644
index 0000000..e0b717a
@@ -0,0 +1,5 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MX6QSABREAUTO=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg,MX6QP"
+CONFIG_CMD_SETEXPR=y
+CONFIG_CMD_NET=y

include/configs/mx6qsabreauto.h +4 -1

index 2260344..6ac64e6 100644
@@ -12,7 +12,10 @@
 #define CONFIG_MACH_TYPE	3529
 #define CONFIG_MXC_UART_BASE	UART4_BASE
 #define CONFIG_CONSOLE_DEV		"ttymxc3"
-#if defined CONFIG_MX6Q
+
+#if defined CONFIG_MX6QP
+#define CONFIG_DEFAULT_FDT_FILE	"imx6qp-sabreauto.dtb"
+#elif defined CONFIG_MX6Q
 #define CONFIG_DEFAULT_FDT_FILE	"imx6q-sabreauto.dtb"
 #elif defined CONFIG_MX6DL
 #define CONFIG_DEFAULT_FDT_FILE	"imx6dl-sabreauto.dtb"

Signature · 1 line

1.8.4

Stefano Babic

2015-06-10 09:40 UTC #14 lore raw

PATCH 7/8 imx: mx6qpsabreauto: Add MX6QP SABREAUTO CPU3 board support

Hi Peng,

Quoted 67 lines · Peng Fan

1. Add DDR script for mx6qpsabreauto board.
2. On CPU3 board, enet RGMII tx clock is from internal PLL. Set the GPR5[9] and init the enet pll output to 125Mhz.
3. On CPU3 board, SW1ABC=VDDSOC_IN, SW2=VDDARM_IN.
Build target: mx6qpsabreauto_config
U-Boot 2015.07-rc2-00008-g594f506 (Jun 10 2015 - 16:01:36 +0800)
Boot Log:
CPU:   Freescale i.MX6Q rev2.0 996 MHz (running at 792 MHz)
CPU:   Automotive temperature grade (-40C to 125C) at 36C
Reset cause: POR
Board: MX6Q-Sabreauto revA
I2C:   ready
DRAM:  2 GiB
PMIC:  PFUZE100 ID=0x10
Flash: 32 MiB
NAND:  4096 MiB
MMC:   FSL_SDHC: 0
*** Warning - bad CRC, using default environment
No panel detected: default to HDMI
Display: HDMI (1024x768)
In:    serial
Out:   serial
Err:   serial
Net:   FEC [PRIME]
Error: FEC address not set.
Hit any key to stop autoboot: 0
Signed-off-by Robin Gong <[email protected]>
Signed-off-by Ye.Li <[email protected]>
Signed-off-by Peng Fan <[email protected]>
---
 board/freescale/mx6qsabreauto/mx6qp.cfg       | 158 ++++++++++++++++++++++++++
 board/freescale/mx6qsabreauto/mx6qsabreauto.c |  32 +++++-
 configs/mx6qpsabreauto_defconfig              |   5 +
 include/configs/mx6qsabreauto.h               |   5 +-
 4 files changed, 194 insertions(+), 6 deletions(-)
 create mode 100644 board/freescale/mx6qsabreauto/mx6qp.cfg
 create mode 100644 configs/mx6qpsabreauto_defconfig
board/freescale/mx6qsabreauto/mx6qp.cfg new file +17 -0
new file mode 100644
index 0000000..5d55bcc
@@ -0,0 +1,158 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+/* image version */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+IMAGE_VERSION 2
+

board/freescale/mx6qsabreauto/mx6qp.cfg line 27

Quoted 10 lines

board/freescale/mx6qsabreauto/mx6qp.cfg new file +10 -0

+/*
+ * Boot Device : one of spi, sd, eimnor, nand, sata:
+ * spinor: flash_offset: 0x0400
+ * nand:   flash_offset: 0x0400
+ * sata:   flash_offset: 0x0400
+ * sd/mmc: flash_offset: 0x0400
+ * eimnor: flash_offset: 0x1000
+ */
+
+#if defined(CONFIG_SYS_BOOT_EIMNOR)

?????

Not defined in U-Boot mainline.

board/freescale/mx6qsabreauto/mx6qp.cfg line 35

Quoted 8 lines

board/freescale/mx6qsabreauto/mx6qp.cfg new file +8 -0

+BOOT_FROM	nor
+#else /* others has the same flash_offset as sd */
+BOOT_FROM	sd
+#endif
+
+#ifdef CONFIG_USE_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx6qsabreauto/plugin.bin 0x00907000

Ditto,

Quoted 20 lines

board/freescale/mx6qsabreauto/mx6qp.cfg new file +20 -0

+#else
+
+#ifdef CONFIG_SECURE_BOOT
+CSF 0x2000
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+DATA 4 0x020e0798 0x000C0000
+DATA 4 0x020e0758 0x00000000
+DATA 4 0x020e0588 0x00000030

board/freescale/mx6qsabreauto/mx6qp.cfg line 65

Quoted 10 lines

board/freescale/mx6qsabreauto/mx6qp.cfg new file +10 -0

+DATA 4 0x020e0594 0x00000030
+DATA 4 0x020e056c 0x00000030
+DATA 4 0x020e0578 0x00000030
+DATA 4 0x020e074c 0x00000030
+DATA 4 0x020e057c 0x00000030
+DATA 4 0x020e058c 0x00000000
+DATA 4 0x020e059c 0x00000030
+DATA 4 0x020e05a0 0x00000030
+DATA 4 0x020e078c 0x00000030
+DATA 4 0x020e0750 0x00020000

Until here, the same as mx6qsabreauto

board/freescale/mx6qsabreauto/mx6qp.cfg line 73

Quoted 8 lines

board/freescale/mx6qsabreauto/mx6qp.cfg new file +8 -0

+DATA 4 0x020e05a8 0x00000030
+DATA 4 0x020e05b0 0x00000030
+DATA 4 0x020e0524 0x00000030
+DATA 4 0x020e051c 0x00000030
+DATA 4 0x020e0518 0x00000030
+DATA 4 0x020e050c 0x00000030
+DATA 4 0x020e05b8 0x00000030
+DATA 4 0x020e05c0 0x00000030

Here is 40 ohm (reset value, do you need to set it ?) instead of 48 ohm as on 6qauto. Anyway, is there some chance to add SPL support for this board ? DDR setup can be then managed inside SPL code dropping this part and a single image for sabreauto6q and sabreauto6qp could be possible.

Of course, I will not block the patchset if this is not planned, but maybe you can consider it. In any case, some factorizing must be done instead of duplicating the cfg code.

Quoted 41 lines

board/freescale/mx6qsabreauto/mx6qp.cfg new file +38 -0

+DATA 4 0x020e0774 0x00020000
+DATA 4 0x020e0784 0x00000030
+DATA 4 0x020e0788 0x00000030
+DATA 4 0x020e0794 0x00000030
+DATA 4 0x020e079c 0x00000030
+DATA 4 0x020e07a0 0x00000030
+DATA 4 0x020e07a4 0x00000030
+DATA 4 0x020e07a8 0x00000030
+DATA 4 0x020e0748 0x00000030
+DATA 4 0x020e05ac 0x00000030
+DATA 4 0x020e05b4 0x00000030
+DATA 4 0x020e0528 0x00000030
+DATA 4 0x020e0520 0x00000030
+DATA 4 0x020e0514 0x00000030
+DATA 4 0x020e0510 0x00000030
+DATA 4 0x020e05bc 0x00000030
+DATA 4 0x020e05c4 0x00000030
+DATA 4 0x021b0800 0xa1390003
+DATA 4 0x021b080c 0x001b001e
+DATA 4 0x021b0810 0x002e0029
+DATA 4 0x021b480c 0x001b002a
+DATA 4 0x021b4810 0x0019002c
+DATA 4 0x021b083c 0x43240334
+DATA 4 0x021b0840 0x0324031a
+DATA 4 0x021b483c 0x43340344
+DATA 4 0x021b4840 0x03280276
+DATA 4 0x021b0848 0x44383A3E
+DATA 4 0x021b4848 0x3C3C3846
+DATA 4 0x021b0850 0x2e303230
+DATA 4 0x021b4850 0x38283E34
 
 
 
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+DATA 4 0x021b481c 0x33333333
+DATA 4 0x021b4820 0x33333333
+DATA 4 0x021b4824 0x33333333
+DATA 4 0x021b4828 0x33333333

board/freescale/mx6qsabreauto/mx6qp.cfg line 121

Quoted 10 lines

board/freescale/mx6qsabreauto/mx6qp.cfg new file +10 -0

+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b48b8 0x00000800
+DATA 4 0x021b0004 0x00020036
+DATA 4 0x021b0008 0x09444040
+DATA 4 0x021b000c 0x898E7955
+DATA 4 0x021b0010 0xFF328F64
+DATA 4 0x021b0014 0x01FF00DB
+DATA 4 0x021b0018 0x00001740
+DATA 4 0x021b001c 0x00008000
+

This is also common.

Quoted 46 lines

board/freescale/mx6qsabreauto/mx6qp.cfg new file +37 -0

+DATA 4 0x021b002c 0x000026d2
+DATA 4 0x021b0030 0x008E1023
+DATA 4 0x021b0040 0x00000047
+DATA 4 0x021b0400 0x12420000
+DATA 4 0x021b0000 0x841A0000
+DATA 4 0x00bb0008 0x00000004
+DATA 4 0x00bb000c 0x2891E41A
+DATA 4 0x00bb0038 0x00000564
+DATA 4 0x00bb0014 0x00000040
+DATA 4 0x00bb0028 0x00000020
+DATA 4 0x00bb002c 0x00000020
+DATA 4 0x021b001c 0x04088032
+DATA 4 0x021b001c 0x00008033
+DATA 4 0x021b001c 0x00048031
+DATA 4 0x021b001c 0x09408030
+DATA 4 0x021b001c 0x04008040
+DATA 4 0x021b0020 0x00005800
+DATA 4 0x021b0818 0x00011117
+DATA 4 0x021b4818 0x00011117
+DATA 4 0x021b0004 0x00025576
+DATA 4 0x021b0404 0x00011006
+DATA 4 0x021b001c 0x00000000
+/* set the default clock gate to save power */
+DATA 4, 0x020c4068, 0x00C03F3F
+DATA 4, 0x020c406c, 0x0030FC03
+DATA 4, 0x020c4070, 0x0FFFC000
+DATA 4, 0x020c4074, 0x3FF00000
+DATA 4, 0x020c4078, 0xFFFFF300
+DATA 4, 0x020c407c, 0x0F0000F3
+DATA 4, 0x020c4080, 0x00000FFF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, 0x020e0010, 0xF00000CF
+/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
+DATA 4, 0x020e0018, 0x77177717
+DATA 4, 0x020e001c, 0x77177717
+#endif

board/freescale/mx6qsabreauto/mx6qsabreauto.c +0 -0

index b76e4eb..83e34c6 100644

board/freescale/mx6qsabreauto/mx6qsabreauto.c int board_phy_config(struct phy_device *phydev) · line 361

Quoted 8 lines

board/freescale/mx6qsabreauto/mx6qsabreauto.c +5 -0

@@ -354,9 +354,27 @@ int board_phy_config(struct phy_device *phydev)
 	return 0;
 }
 
+static int setup_fec(void)
+{
+	int ret;
+
+#ifdef CONFIG_MX6QP

runtime detection

board/freescale/mx6qsabreauto/mx6qsabreauto.c int board_phy_config(struct phy_device *phydev) · line 364

Quoted 3 lines

board/freescale/mx6qsabreauto/mx6qsabreauto.c +3 -0

+	imx_iomux_set_gpr_register(5, 9, 1, 1);
+#else
+	imx_iomux_set_gpr_register(1, 21, 1, 1);

For not-6qp board you change it. Can you explain why and add comments about what you are doing (see comment at lines 563 and following regarding otg).

Quoted 61 lines

board/freescale/mx6qsabreauto/mx6qsabreauto.c +19 -5

+#endif
+
+	ret = enable_fec_anatop_clock(ENET_125MHZ);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
 int board_eth_init(bd_t *bis)
 {
 	setup_iomux_enet();
+	setup_fec();
 
 	return cpu_eth_init(bis);
 }

@@ -495,17 +513,21 @@ int board_spi_cs_gpio(unsigned bus, unsigned cs)
 int power_init_board(void)
 {
 	struct pmic *p;
-	unsigned int ret;
+	unsigned int value;
 
 	p = pfuze_common_init(I2C_PMIC);
 	if (!p)
 		return -ENODEV;
 
-	ret = pfuze_mode_init(p, APS_PFM);
-	if (ret < 0)
-		return ret;
+	if (is_mx6dqp()) {
+		/* set SW2 staby volatage 0.975V*/
+		pmic_reg_read(p, PFUZE100_SW2STBY, &value);
+		value &= ~0x3f;
+		value |= 0x17;
+		pmic_reg_write(p, PFUZE100_SW2STBY, value);
+	}
 
-	return 0;
+	return pfuze_mode_init(p, APS_PFM);
 }
 
 #ifdef CONFIG_CMD_BMODE

configs/mx6qpsabreauto_defconfig new file +5 -0

new file mode 100644
index 0000000..e0b717a
@@ -0,0 +1,5 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MX6QSABREAUTO=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg,MX6QP"
+CONFIG_CMD_SETEXPR=y
+CONFIG_CMD_NET=y

include/configs/mx6qsabreauto.h +0 -0

index 2260344..6ac64e6 100644
@@ -12,7 +12,10 @@
 #define CONFIG_MACH_TYPE	3529

include/configs/mx6qsabreauto.h line 21

Quoted 10 lines

include/configs/mx6qsabreauto.h +4 -1

 #define CONFIG_MXC_UART_BASE	UART4_BASE
 #define CONFIG_CONSOLE_DEV		"ttymxc3"
-#if defined CONFIG_MX6Q
+
+#if defined CONFIG_MX6QP
+#define CONFIG_DEFAULT_FDT_FILE	"imx6qp-sabreauto.dtb"
+#elif defined CONFIG_MX6Q
 #define CONFIG_DEFAULT_FDT_FILE	"imx6q-sabreauto.dtb"
 #elif defined CONFIG_MX6DL
 #define CONFIG_DEFAULT_FDT_FILE	"imx6dl-sabreauto.dtb"

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Peng Fan

2015-06-10 10:17 UTC #15 lore raw

PATCH 7/8 imx: mx6qpsabreauto: Add MX6QP SABREAUTO CPU3 board support

Hi, Stefano

Quoted 75 lines · Stefano Babic

Hi Peng,

Quoted 72 lines · Peng Fan

Build target: mx6qpsabreauto_config

U-Boot 2015.07-rc2-00008-g594f506 (Jun 10 2015 - 16:01:36 +0800)

Boot Log:

CPU:   Freescale i.MX6Q rev2.0 996 MHz (running at 792 MHz)
CPU:   Automotive temperature grade (-40C to 125C) at 36C
Reset cause: POR
Board: MX6Q-Sabreauto revA
I2C:   ready
DRAM:  2 GiB
PMIC:  PFUZE100 ID=0x10
Flash: 32 MiB
NAND:  4096 MiB
MMC:   FSL_SDHC: 0

*** Warning - bad CRC, using default environment

No panel detected: default to HDMI
Display: HDMI (1024x768)
In:    serial
Out:   serial
Err:   serial
Net:   FEC [PRIME]
Error: FEC address not set.

Hit any key to stop autoboot: 0

Signed-off-by Robin Gong <[email protected]>

Signed-off-by Ye.Li <[email protected]>

Signed-off-by Peng Fan <[email protected]>

---
 board/freescale/mx6qsabreauto/mx6qp.cfg       | 158 ++++++++++++++++++++++++++
 board/freescale/mx6qsabreauto/mx6qsabreauto.c |  32 +++++-
 configs/mx6qpsabreauto_defconfig              |   5 +
 include/configs/mx6qsabreauto.h               |   5 +-
 4 files changed, 194 insertions(+), 6 deletions(-)
 create mode 100644 board/freescale/mx6qsabreauto/mx6qp.cfg
 create mode 100644 configs/mx6qpsabreauto_defconfig

board/freescale/mx6qsabreauto/mx6qp.cfg new file +22 -0

new file mode 100644
index 0000000..5d55bcc
@@ -0,0 +1,158 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+/* image version */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of spi, sd, eimnor, nand, sata:
+ * spinor: flash_offset: 0x0400
+ * nand:   flash_offset: 0x0400
+ * sata:   flash_offset: 0x0400

Quoted 8 lines

board/freescale/mx6qsabreauto/mx6qp.cfg line 27
Quoted 5 lines
board/freescale/mx6qsabreauto/mx6qp.cfg new file +5 -0
+ * sd/mmc: flash_offset: 0x0400
+ * eimnor: flash_offset: 0x1000
+ */
+
+#if defined(CONFIG_SYS_BOOT_EIMNOR)
?????

Will remove this in v2.

Quoted 13 lines

Not defined in U-Boot mainline.
board/freescale/mx6qsabreauto/mx6qp.cfg line 35
Quoted 8 lines
board/freescale/mx6qsabreauto/mx6qp.cfg new file +8 -0
+BOOT_FROM	nor
+#else /* others has the same flash_offset as sd */
+BOOT_FROM	sd
+#endif
+
+#ifdef CONFIG_USE_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx6qsabreauto/plugin.bin 0x00907000
Ditto,

Will remove this in v2.

Quoted 35 lines

Quoted 21 lines

board/freescale/mx6qsabreauto/mx6qp.cfg new file +20 -0

+#else
+
+#ifdef CONFIG_SECURE_BOOT
+CSF 0x2000
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+DATA 4 0x020e0798 0x000C0000
+DATA 4 0x020e0758 0x00000000
+DATA 4 0x020e0588 0x00000030

board/freescale/mx6qsabreauto/mx6qp.cfg line 65

Quoted 10 lines

board/freescale/mx6qsabreauto/mx6qp.cfg new file +10 -0

+DATA 4 0x020e0594 0x00000030
+DATA 4 0x020e056c 0x00000030
+DATA 4 0x020e0578 0x00000030
+DATA 4 0x020e074c 0x00000030
+DATA 4 0x020e057c 0x00000030
+DATA 4 0x020e058c 0x00000000
+DATA 4 0x020e059c 0x00000030
+DATA 4 0x020e05a0 0x00000030
+DATA 4 0x020e078c 0x00000030
+DATA 4 0x020e0750 0x00020000

Until here, the same as mx6qsabreauto

Quoted 14 lines

board/freescale/mx6qsabreauto/mx6qp.cfg line 73
Quoted 8 lines
board/freescale/mx6qsabreauto/mx6qp.cfg new file +8 -0
+DATA 4 0x020e05a8 0x00000030
+DATA 4 0x020e05b0 0x00000030
+DATA 4 0x020e0524 0x00000030
+DATA 4 0x020e051c 0x00000030
+DATA 4 0x020e0518 0x00000030
+DATA 4 0x020e050c 0x00000030
+DATA 4 0x020e05b8 0x00000030
+DATA 4 0x020e05c0 0x00000030
Here is 40 ohm (reset value, do you need to set it ?) instead of 48 ohm as on 6qauto. Anyway, is there some chance to add SPL support for this board ? DDR setup can be then managed inside SPL code dropping this part and a single image for sabreauto6q and sabreauto6qp could be possible.

We get the script from IC team, so there maybe many duplicated configuration. I get your concern that SPL can give many benifits.
Current, we do not have plan to add SPL support.

Quoted 3 lines

Of course, I will not block the patchset if this is not planned, but maybe you can consider it. In any case, some factorizing must be done instead of duplicating the cfg code.

Using SPL, we can remove duplicated ddr cfg, but using cfg file, not that easy. I'll try.

Quoted 104 lines

Quoted 42 lines

board/freescale/mx6qsabreauto/mx6qp.cfg new file +38 -0

+DATA 4 0x020e0774 0x00020000
+DATA 4 0x020e0784 0x00000030
+DATA 4 0x020e0788 0x00000030
+DATA 4 0x020e0794 0x00000030
+DATA 4 0x020e079c 0x00000030
+DATA 4 0x020e07a0 0x00000030
+DATA 4 0x020e07a4 0x00000030
+DATA 4 0x020e07a8 0x00000030
+DATA 4 0x020e0748 0x00000030
+DATA 4 0x020e05ac 0x00000030
+DATA 4 0x020e05b4 0x00000030
+DATA 4 0x020e0528 0x00000030
+DATA 4 0x020e0520 0x00000030
+DATA 4 0x020e0514 0x00000030
+DATA 4 0x020e0510 0x00000030
+DATA 4 0x020e05bc 0x00000030
+DATA 4 0x020e05c4 0x00000030
+DATA 4 0x021b0800 0xa1390003
+DATA 4 0x021b080c 0x001b001e
+DATA 4 0x021b0810 0x002e0029
+DATA 4 0x021b480c 0x001b002a
+DATA 4 0x021b4810 0x0019002c
+DATA 4 0x021b083c 0x43240334
+DATA 4 0x021b0840 0x0324031a
+DATA 4 0x021b483c 0x43340344
+DATA 4 0x021b4840 0x03280276
+DATA 4 0x021b0848 0x44383A3E
+DATA 4 0x021b4848 0x3C3C3846
+DATA 4 0x021b0850 0x2e303230
+DATA 4 0x021b4850 0x38283E34
 
 
 
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+DATA 4 0x021b481c 0x33333333
+DATA 4 0x021b4820 0x33333333
+DATA 4 0x021b4824 0x33333333
+DATA 4 0x021b4828 0x33333333

board/freescale/mx6qsabreauto/mx6qp.cfg line 121

Quoted 10 lines

board/freescale/mx6qsabreauto/mx6qp.cfg new file +10 -0

+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b48b8 0x00000800
+DATA 4 0x021b0004 0x00020036
+DATA 4 0x021b0008 0x09444040
+DATA 4 0x021b000c 0x898E7955
+DATA 4 0x021b0010 0xFF328F64
+DATA 4 0x021b0014 0x01FF00DB
+DATA 4 0x021b0018 0x00001740
+DATA 4 0x021b001c 0x00008000
+

This is also common.

Quoted 49 lines

board/freescale/mx6qsabreauto/mx6qp.cfg new file +37 -0

+DATA 4 0x021b002c 0x000026d2
+DATA 4 0x021b0030 0x008E1023
+DATA 4 0x021b0040 0x00000047
+DATA 4 0x021b0400 0x12420000
+DATA 4 0x021b0000 0x841A0000
+DATA 4 0x00bb0008 0x00000004
+DATA 4 0x00bb000c 0x2891E41A
+DATA 4 0x00bb0038 0x00000564
+DATA 4 0x00bb0014 0x00000040
+DATA 4 0x00bb0028 0x00000020
+DATA 4 0x00bb002c 0x00000020
+DATA 4 0x021b001c 0x04088032
+DATA 4 0x021b001c 0x00008033
+DATA 4 0x021b001c 0x00048031
+DATA 4 0x021b001c 0x09408030
+DATA 4 0x021b001c 0x04008040
+DATA 4 0x021b0020 0x00005800
+DATA 4 0x021b0818 0x00011117
+DATA 4 0x021b4818 0x00011117
+DATA 4 0x021b0004 0x00025576
+DATA 4 0x021b0404 0x00011006
+DATA 4 0x021b001c 0x00000000
+/* set the default clock gate to save power */
+DATA 4, 0x020c4068, 0x00C03F3F
+DATA 4, 0x020c406c, 0x0030FC03
+DATA 4, 0x020c4070, 0x0FFFC000
+DATA 4, 0x020c4074, 0x3FF00000
+DATA 4, 0x020c4078, 0xFFFFF300
+DATA 4, 0x020c407c, 0x0F0000F3
+DATA 4, 0x020c4080, 0x00000FFF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, 0x020e0010, 0xF00000CF
+/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
+DATA 4, 0x020e0018, 0x77177717
+DATA 4, 0x020e001c, 0x77177717
+#endif

board/freescale/mx6qsabreauto/mx6qsabreauto.c +0 -0

index b76e4eb..83e34c6 100644
@@ -354,9 +354,27 @@ int board_phy_config(struct phy_device *phydev)
 	return 0;
 }

Quoted 7 lines

board/freescale/mx6qsabreauto/mx6qsabreauto.c int board_phy_config(struct phy_device *phydev) · line 361
Quoted 5 lines
board/freescale/mx6qsabreauto/mx6qsabreauto.c +5 -0
+static int setup_fec(void)
+{
+	int ret;
+
+#ifdef CONFIG_MX6QP
runtime detection

Will fix it in v2.

Quoted 8 lines

board/freescale/mx6qsabreauto/mx6qsabreauto.c int board_phy_config(struct phy_device *phydev) · line 364
Quoted 4 lines
board/freescale/mx6qsabreauto/mx6qsabreauto.c +3 -0
+	imx_iomux_set_gpr_register(5, 9, 1, 1);
+#else
+	imx_iomux_set_gpr_register(1, 21, 1, 1);
For not-6qp board you change it. Can you explain why and add comments about what you are doing (see comment at lines 563 and following regarding otg).

Will fix it in v2.

Quoted 67 lines

board/freescale/mx6qsabreauto/mx6qsabreauto.c +19 -5

+#endif
+
+	ret = enable_fec_anatop_clock(ENET_125MHZ);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
 int board_eth_init(bd_t *bis)
 {
 	setup_iomux_enet();
+	setup_fec();
 
 	return cpu_eth_init(bis);
 }

@@ -495,17 +513,21 @@ int board_spi_cs_gpio(unsigned bus, unsigned cs)
 int power_init_board(void)
 {
 	struct pmic *p;
-	unsigned int ret;
+	unsigned int value;
 
 	p = pfuze_common_init(I2C_PMIC);
 	if (!p)
 		return -ENODEV;
 
-	ret = pfuze_mode_init(p, APS_PFM);
-	if (ret < 0)
-		return ret;
+	if (is_mx6dqp()) {
+		/* set SW2 staby volatage 0.975V*/
+		pmic_reg_read(p, PFUZE100_SW2STBY, &value);
+		value &= ~0x3f;
+		value |= 0x17;
+		pmic_reg_write(p, PFUZE100_SW2STBY, value);
+	}
 
-	return 0;
+	return pfuze_mode_init(p, APS_PFM);
 }
 
 #ifdef CONFIG_CMD_BMODE

configs/mx6qpsabreauto_defconfig new file +5 -0

new file mode 100644
index 0000000..e0b717a
@@ -0,0 +1,5 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MX6QSABREAUTO=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg,MX6QP"
+CONFIG_CMD_SETEXPR=y
+CONFIG_CMD_NET=y

include/configs/mx6qsabreauto.h +3 -1

index 2260344..6ac64e6 100644
@@ -12,7 +12,10 @@
 #define CONFIG_MACH_TYPE	3529
 #define CONFIG_MXC_UART_BASE	UART4_BASE
 #define CONFIG_CONSOLE_DEV		"ttymxc3"
-#if defined CONFIG_MX6Q
+
+#if defined CONFIG_MX6QP
+#define CONFIG_DEFAULT_FDT_FILE	"imx6qp-sabreauto.dtb"

Quoted 15 lines

include/configs/mx6qsabreauto.h line 21

Quoted 5 lines

include/configs/mx6qsabreauto.h +1 -0

+#elif defined CONFIG_MX6Q
 #define CONFIG_DEFAULT_FDT_FILE	"imx6q-sabreauto.dtb"
 #elif defined CONFIG_MX6DL
 #define CONFIG_DEFAULT_FDT_FILE	"imx6dl-sabreauto.dtb"

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Regards,
Peng.

Peng Fan

author

2015-06-10 08:06 UTC #16 lore raw

PATCH 8/8 imx: mx6qp: Adjust AQos settings for peripherals

In reply to Peng Fan

From: "Ye.Li" <[email protected]>

To resolve USB camera bandwidth issue, the patch sets recommended AQoS setting from IC team value for peripheral and only on imx6qp.

The address is: 0xbb0608, the value is: 0x80000201

Signed-off-by Ye.Li <[email protected]>

Signed-off-by Peng Fan <[email protected]>

---
 arch/arm/cpu/armv7/mx6/soc.c | 3 +++
 1 file changed, 3 insertions(+)

arch/arm/cpu/armv7/mx6/soc.c +3 -0

index 5eea9d9..0de71d56 100644
@@ -424,6 +424,9 @@ int arch_cpu_init(void)
 
 	init_src();
 
+	if (is_mx6dqp())
+		writel(0x80000201, 0xbb0608);
+
 	return 0;
 }

Signature · 1 line

1.8.4

Stefano Babic

2015-06-10 09:44 UTC #17 lore raw

PATCH 8/8 imx: mx6qp: Adjust AQos settings for peripherals

Hi Peng,

Quoted 7 lines · Peng Fan

From: "Ye.Li" <[email protected]>
To resolve USB camera bandwidth issue, the patch sets recommended AQoS setting from IC team value for peripheral and only on imx6qp.
The address is: 0xbb0608, the value is: 0x80000201

I understand that, if you fight against this issue, the comment can be clear and maybe redundant. Please add comments in code describing the issue, and extend the commit log to better explain the issue and the solution.

Quoted 12 lines

Signed-off-by Ye.Li <[email protected]>
Signed-off-by Peng Fan <[email protected]>
---
 arch/arm/cpu/armv7/mx6/soc.c | 3 +++
 1 file changed, 3 insertions(+)
arch/arm/cpu/armv7/mx6/soc.c +0 -0
index 5eea9d9..0de71d56 100644

arch/arm/cpu/armv7/mx6/soc.c int arch_cpu_init(void) · line 432

Quoted 9 lines

arch/arm/cpu/armv7/mx6/soc.c +3 -0

@@ -424,6 +424,9 @@ int arch_cpu_init(void)
 
 	init_src();
 
+	if (is_mx6dqp())
+		writel(0x80000201, 0xbb0608);
+
 	return 0;
 }

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Peng Fan

2015-06-10 10:18 UTC #18 lore raw

PATCH 8/8 imx: mx6qp: Adjust AQos settings for peripherals

Hi Stefano,

Quoted 8 lines · Stefano Babic

Hi Peng,
Quoted 5 lines · Peng Fan
From: "Ye.Li" <[email protected]>
To resolve USB camera bandwidth issue, the patch sets recommended AQoS setting from IC team value for peripheral and only on imx6qp.

Quoted 7 lines

Quoted 2 lines
The address is: 0xbb0608, the value is: 0x80000201
I understand that, if you fight against this issue, the comment can be clear and maybe redundant. Please add comments in code describing the issue, and extend the commit log to better explain the issue and the solution.

ok. Will add more info.

Quoted 15 lines

Quoted 15 lines
Signed-off-by Ye.Li <[email protected]>
Signed-off-by Peng Fan <[email protected]>
---
 arch/arm/cpu/armv7/mx6/soc.c | 3 +++
 1 file changed, 3 insertions(+)
arch/arm/cpu/armv7/mx6/soc.c +0 -0
index 5eea9d9..0de71d56 100644
@@ -424,6 +424,9 @@ int arch_cpu_init(void)
 
 	init_src();
 

Quoted 17 lines

arch/arm/cpu/armv7/mx6/soc.c int arch_cpu_init(void) · line 432

Quoted 7 lines

arch/arm/cpu/armv7/mx6/soc.c +3 -0

+	if (is_mx6dqp())
+		writel(0x80000201, 0xbb0608);
+
 	return 0;
 }

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Regards,
Peng.

Stefano Babic

2015-06-10 08:20 UTC #19 lore raw

PATCH 1/8 imx: mx6 cast return type of is_soc_rev to int

In reply to Peng Fan

Hi Peng,

Quoted 8 lines · Peng Fan

is_soc_rev should be casted to signed int, otherwise may incur errors when detecting cpu types, since we use such pieces of code:
"
if (is_soc_rev(CHIP_REV_1_0) > 0) ......
if (is_soc_rev(CHIP_REV_2_0) >= 0) ......
"

We are mishandling the function. From the name, is_soc_rev() should really return a boolean value. We should call so_rev() instead of is_soc_rev() when we compare versions.

Quoted 11 lines

Signed-off-by Peng Fan <[email protected]>
---
 arch/arm/include/asm/arch-mx6/sys_proto.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm/include/asm/arch-mx6/sys_proto.h +0 -0
index c583291..9c827c9 100644

arch/arm/include/asm/arch-mx6/sys_proto.h line 18

Quoted 8 lines

arch/arm/include/asm/arch-mx6/sys_proto.h +1 -1

@@ -12,7 +12,7 @@
 #include "../arch-imx/cpu.h"
 
 #define soc_rev() (get_cpu_rev() & 0xFF)
-#define is_soc_rev(rev)        (soc_rev() - rev)
+#define is_soc_rev(rev)        (int)(soc_rev() - rev)
 
 u32 get_nr_cpus(void);
 u32 get_cpu_rev(void);

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Peng Fan

2015-06-10 08:42 UTC #20 lore raw

PATCH 1/8 imx: mx6 cast return type of is_soc_rev to int

Hi Stefano,

Quoted 12 lines · Stefano Babic

Hi Peng,
Quoted 8 lines · Peng Fan
is_soc_rev should be casted to signed int, otherwise may incur errors when detecting cpu types, since we use such pieces of code:
"
if (is_soc_rev(CHIP_REV_1_0) > 0) ......
if (is_soc_rev(CHIP_REV_2_0) >= 0) ......
"

Quoted 3 lines

We are mishandling the function. From the name, is_soc_rev() should really return a boolean value. We should call so_rev() instead of is_soc_rev() when we compare versions.

ok. Will address patch 2/8 using soc_rev() and discard this patch. Wait for more comments to patch from 2/8 - 8/8, then send out v2.

Quoted 17 lines

Signed-off-by Peng Fan <[email protected]>

---
 arch/arm/include/asm/arch-mx6/sys_proto.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

arch/arm/include/asm/arch-mx6/sys_proto.h +1 -1

index c583291..9c827c9 100644
@@ -12,7 +12,7 @@
 #include "../arch-imx/cpu.h"
 
 #define soc_rev() (get_cpu_rev() & 0xFF)
-#define is_soc_rev(rev)        (soc_rev() - rev)
+#define is_soc_rev(rev)        (int)(soc_rev() - rev)

Quoted 6 lines

arch/arm/include/asm/arch-mx6/sys_proto.h line 18
Quoted 3 lines
arch/arm/include/asm/arch-mx6/sys_proto.h +0 -0
 u32 get_nr_cpus(void);
 u32 get_cpu_rev(void);
Best regards,
Stefano Babic

Regards,
Peng.

Quoted 7 lines

Signature · 6 lines

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