arm64: dts: add device tree for ARM SMM-A53x2 on LogicTile Express 20MG

Add a DTS file for the MP2 Cortex-A53 Soft Macrocell Model implemented on a LogicTile Express 20MG (V2F-1XV7) daughterboard. This is based on the version that's currently available from the ARM DTS repository [1].

[1] git://linux-arm.org/arm-dts.git

Signed-off-by Kristina Martsenko <[email protected]>

---
 MAINTAINERS                                        |   1 +
 arch/arm64/boot/dts/arm/Makefile                   |   1 +
 .../boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts      | 196 +++++++++++++++++++++
 3 files changed, 198 insertions(+)
 create mode 100644 arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts

MAINTAINERS +0 -0

index 9180f46..1fb07e0 100644

arch/arm64/boot/dts/arm/Makefile +1 -0

index c5c98b9..bb3c072 100644
@@ -1,6 +1,7 @@
 dtb-$(CONFIG_ARCH_VEXPRESS) += foundation-v8.dtb
 dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb juno-r1.dtb
 dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb
+dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb
 
 always		:= $(dtb-y)
 subdir-y	:= $(dts-dirs)

arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts new file +5 -0

new file mode 100644
index 0000000..bbe28aa
@@ -0,0 +1,196 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * LogicTile Express 20MG
+ * V2F-1XV7

arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts new file +169 -0

+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	model = "V2F-1XV7 Cortex-A53x2 SMM";
+	arm,hbi = <0x247>;
+	arm,vexpress,site = <0xf>;
+	compatible = "arm,vexpress,v2f-1xv7,ca53x2", "arm,vexpress,v2f-1xv7", "arm,vexpress";
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	chosen {
+		stdout-path = "serial0:38400n8";
+	};
+
+	aliases {
+		serial0 = &v2m_serial0;
+		serial1 = &v2m_serial1;
+		serial2 = &v2m_serial2;
+		serial3 = &v2m_serial3;
+		i2c0 = &v2m_i2c_dvi;
+		i2c1 = &v2m_i2c_pcie;
+	};
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		cpu at 0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53", "arm,armv8";
+			reg = <0 0>;
+			next-level-cache = <&L2_0>;
+		};
+
+		cpu at 1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53", "arm,armv8";
+			reg = <0 1>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0x0 0x8000fff8>;
+			next-level-cache = <&L2_0>;
+		};
+
+		L2_0: l2-cache0 {
+			compatible = "cache";
+		};
+	};
+
+	memory at 80000000 {
+		device_type = "memory";
+		reg = <0 0x80000000 0 0x80000000>; /* 2GB @ 2GB */
+	};
+
+	gic: interrupt-controller at 2c001000 {
+		compatible = "arm,gic-400";
+		#interrupt-cells = <3>;
+		#address-cells = <0>;
+		interrupt-controller;
+		reg = <0 0x2c001000 0 0x1000>,
+		      <0 0x2c002000 0 0x2000>,
+		      <0 0x2c004000 0 0x2000>,
+		      <0 0x2c006000 0 0x2000>;
+		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+
+	pmu {
+		compatible = "arm,armv8-pmuv3";
+		interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	dcc {
+		compatible = "arm,vexpress,config-bus";
+		arm,vexpress,config-bridge = <&v2m_sysreg>;
+
+		smbclk: osc at 4 {
+			/* SMC clock */
+			compatible = "arm,vexpress-osc";
+			arm,vexpress-sysreg,func = <1 4>;
+			freq-range = <40000000 40000000>;
+			#clock-cells = <0>;
+			clock-output-names = "smclk";
+		};
+
+		volt at 0 {
+			/* VIO to expansion board above */
+			compatible = "arm,vexpress-volt";
+			arm,vexpress-sysreg,func = <2 0>;
+			regulator-name = "VIO_UP";
+			regulator-min-microvolt = <800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-always-on;
+		};
+
+		volt at 1 {
+			/* 12V from power connector J6 */
+			compatible = "arm,vexpress-volt";
+			arm,vexpress-sysreg,func = <2 1>;
+			regulator-name = "12";
+			regulator-always-on;
+		};
+
+		temp at 0 {
+			/* FPGA temperature */
+			compatible = "arm,vexpress-temp";
+			arm,vexpress-sysreg,func = <4 0>;
+			label = "FPGA";
+		};
+	};
+
+	smb {
+		compatible = "simple-bus";
+
+		#address-cells = <2>;
+		#size-cells = <1>;
+		ranges = <0 0 0 0x08000000 0x04000000>,
+			 <1 0 0 0x14000000 0x04000000>,
+			 <2 0 0 0x18000000 0x04000000>,
+			 <3 0 0 0x1c000000 0x04000000>,
+			 <4 0 0 0x0c000000 0x04000000>,
+			 <5 0 0 0x10000000 0x04000000>;
+
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 63>;
+		interrupt-map = <0 0  0 &gic GIC_SPI  0 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0  1 &gic GIC_SPI  1 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0  2 &gic GIC_SPI  2 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0  3 &gic GIC_SPI  3 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0  4 &gic GIC_SPI  4 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0  5 &gic GIC_SPI  5 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0  6 &gic GIC_SPI  6 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0  7 &gic GIC_SPI  7 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0  8 &gic GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0  9 &gic GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0 14 &gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0 16 &gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0 17 &gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0 18 &gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0 19 &gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0 20 &gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0 21 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0 22 &gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0 23 &gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0 24 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0 25 &gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0 26 &gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0 27 &gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0 28 &gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0 29 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0 30 &gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0 31 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0 32 &gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0 33 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0 34 &gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,

arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts new file +2 -0

+	};
+};

Signature · 1 line

2.1.4

Hi Kristina,

Quoted 5 lines · Kristina Martsenko

Add a DTS file for the MP2 Cortex-A53 Soft Macrocell Model implemented on a LogicTile Express 20MG (V2F-1XV7) daughterboard. This is based on the version that's currently available from the ARM DTS repository [1].

[1] git://linux-arm.org/arm-dts.git

I thought the plan was to keep new DTs in this repository, not to add them into the kernel. Has this changed?

Quoted 14 lines

Signed-off-by Kristina Martsenko <[email protected]>

---
 MAINTAINERS                                        |   1 +
 arch/arm64/boot/dts/arm/Makefile                   |   1 +
 .../boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts      | 196 +++++++++++++++++++++
 3 files changed, 198 insertions(+)
 create mode 100644 arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts

MAINTAINERS +0 -0

index 9180f46..1fb07e0 100644

MAINTAINERS M: Lorenzo Pieralisi <[email protected]> · line 1619

Quoted 7 lines

MAINTAINERS +1 -0

@@ -1613,6 +1613,7 @@ M:	Lorenzo Pieralisi <[email protected]>
 L:	linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
 S:	Maintained
 F:	arch/arm/boot/dts/vexpress*
+F:	arch/arm64/boot/dts/arm/vexpress*
 F:	arch/arm/mach-vexpress/
 F:	*/*/vexpress*
 F:	*/*/*/vexpress*

You might want to Cc Lorenzo on this patch if you add him as maintainer :)

Quoted 28 lines

arch/arm64/boot/dts/arm/Makefile +1 -0

index c5c98b9..bb3c072 100644
@@ -1,6 +1,7 @@
 dtb-$(CONFIG_ARCH_VEXPRESS) += foundation-v8.dtb
 dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb juno-r1.dtb
 dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb
+dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb
 
 always		:= $(dtb-y)
 subdir-y	:= $(dts-dirs)

arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts new file +10 -0

new file mode 100644
index 0000000..bbe28aa
@@ -0,0 +1,196 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * LogicTile Express 20MG
+ * V2F-1XV7
+ *
+ * Cortex-A53 (2 cores) Soft Macrocell Model
+ *
+ * HBI-0247C
+ */

arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts line 15

Quoted 5 lines

arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts new file +5 -0

+
+/dts-v1/;
+
+/* In use by spinning secondaries */
+/memreserve/ 0x80000000 0x00010000;

Where does the kernel get loaded to? If 0x80000000 is the start of memory and the kernel is loaded at 0x80000 offset as usual, then that memory is protected anyway.

Quoted 64 lines · Liviu Dudau

Hi Kristina,

Quoted 5 lines · Kristina Martsenko

Add a DTS file for the MP2 Cortex-A53 Soft Macrocell Model implemented on a LogicTile Express 20MG (V2F-1XV7) daughterboard. This is based on the version that's currently available from the ARM DTS repository [1].

[1] git://linux-arm.org/arm-dts.git

I thought the plan was to keep new DTs in this repository, not to add them into the kernel. Has this changed?

Quoted 14 lines

Signed-off-by Kristina Martsenko <[email protected]>

---
 MAINTAINERS                                        |   1 +
 arch/arm64/boot/dts/arm/Makefile                   |   1 +
 .../boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts      | 196 +++++++++++++++++++++
 3 files changed, 198 insertions(+)
 create mode 100644 arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts

MAINTAINERS +0 -0

index 9180f46..1fb07e0 100644

MAINTAINERS M: Lorenzo Pieralisi <[email protected]> · line 1619

Quoted 7 lines

MAINTAINERS +1 -0

@@ -1613,6 +1613,7 @@ M:	Lorenzo Pieralisi <[email protected]>
 L:	linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
 S:	Maintained
 F:	arch/arm/boot/dts/vexpress*
+F:	arch/arm64/boot/dts/arm/vexpress*
 F:	arch/arm/mach-vexpress/
 F:	*/*/vexpress*
 F:	*/*/*/vexpress*

You might want to Cc Lorenzo on this patch if you add him as maintainer :)

Quoted 28 lines

arch/arm64/boot/dts/arm/Makefile +1 -0

index c5c98b9..bb3c072 100644
@@ -1,6 +1,7 @@
 dtb-$(CONFIG_ARCH_VEXPRESS) += foundation-v8.dtb
 dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb juno-r1.dtb
 dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb
+dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb
 
 always		:= $(dtb-y)
 subdir-y	:= $(dts-dirs)

arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts new file +10 -0

new file mode 100644
index 0000000..bbe28aa
@@ -0,0 +1,196 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * LogicTile Express 20MG
+ * V2F-1XV7
+ *
+ * Cortex-A53 (2 cores) Soft Macrocell Model
+ *
+ * HBI-0247C
+ */

Quoted 8 lines

arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts line 15

Quoted 5 lines

arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts new file +5 -0

+
+/dts-v1/;
+
+/* In use by spinning secondaries */
+/memreserve/ 0x80000000 0x00010000;

Where does the kernel get loaded to? If 0x80000000 is the start of memory and the kernel is loaded at 0x80000 offset as usual, then that memory is protected anyway.

That's simply not true. The kernel may use _any_ memory which is described to it and not explicitly reserved.

We only reserve the kernel's static image (see arm64_memblock_init), which does not cover that region. We can easily map that memory and allocate it to something.

While we used to place page tables in the end of that region, we only reserved the page tables, and it was problematic because you had no idea how much of that memory the kernel might use.

Regardless, DTs should not rely on Linux implementation details like magic implicit reservations.

Mark.

Quoted 17 lines

Quoted 5 lines

arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts line 15

Quoted 2 lines

arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts new file +2 -0

+/* In use by spinning secondaries */
+/memreserve/ 0x80000000 0x00010000;

Where does the kernel get loaded to? If 0x80000000 is the start of memory and the kernel is loaded at 0x80000 offset as usual, then that memory is protected anyway.

That's simply not true. The kernel may use _any_ memory which is described to it and not explicitly reserved.

We only reserve the kernel's static image (see arm64_memblock_init), which does not cover that region. We can easily map that memory and allocate it to something.

While we used to place page tables in the end of that region, we only reserved the page tables, and it was problematic because you had no idea how much of that memory the kernel might use.

Quoted 2 lines

Regardless, DTs should not rely on Linux implementation details like magic implicit reservations.

Things might have changed since v3.18 but I remember having a hell of a time trying to access memory that was at the bottom of address space before the kernel start image.

But I agree that things should be explicitly stated in the DT.

Question for Kristina now: why spin method and not PSCI for this CoreTile?

Ideally we'd avoid placing the enable-method in the DTS at all, but I believe the boot monitor isn't smart enough to fix that up.

Quoted 2 lines · Mark Rutland

Ideally we'd avoid placing the enable-method in the DTS at all, but I believe the boot monitor isn't smart enough to fix that up.

You would be surprised how intelligent these animals can be :-P

8<--------------

    case CPU:
        err = safdt_insert_prop(safdt, "enable-method",
                                "spin-table", 11);
        if (err)
            break;
        addr = fdt_uint64(parser->cpu_release_addr);
        err = safdt_insert_prop(safdt, "cpu-release-addr", &addr, 8);

8<---------------

Hi Kristina,

Quoted 5 lines · Kristina Martsenko

Add a DTS file for the MP2 Cortex-A53 Soft Macrocell Model implemented on a LogicTile Express 20MG (V2F-1XV7) daughterboard. This is based on the version that's currently available from the ARM DTS repository [1].

[1] git://linux-arm.org/arm-dts.git

Review

Quoted 2 lines

(quoted diff) +2 -0

+
+		/include/ "../../../../arm/boot/dts/vexpress-v2m-rs1.dtsi"

Patch looks OK to me even if I'm not too keen on including DTSi files from a "different" arch directory.

Hi Kristina,

Quoted 5 lines · Kristina Martsenko

Add a DTS file for the MP2 Cortex-A53 Soft Macrocell Model implemented on a LogicTile Express 20MG (V2F-1XV7) daughterboard. This is based on the version that's currently available from the ARM DTS repository [1].

[1] git://linux-arm.org/arm-dts.git

I thought the plan was to keep new DTs in this repository, not to add them into the kernel. Has this changed?