ARM: mm: enable L1 prefetch on Cortex-A9
PATCH 1/1 ARM: mm: enable L1 prefetch on Cortex-A9
The Cortex-A9 has a L1 prefetch capability documented at
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388e/Chdejhgd.html:
The Cortex-A9 data cache implements an automatic prefetcher that monitors cache misses done by the processor. This unit can monitor and prefetch two independent data streams. It can be activated in software using a CP15 Auxiliary Control Register bit. See Auxiliary Control Register.
This commit enables this L1 prefetch feature unconditionally on all Cortex-A9 by setting bit 2 in the Auxiliary Control CP15 register. Note that since this bit only exists on Cortex-A9 but not on Cortex-A5 or Cortex-R7, we separate the handling of Cortex-A9 from the one of those two other cores.
--- arch/arm/mm/proc-v7.S | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)
arch/arm/mm/proc-v7.S +4 -1
@@ -257,8 +257,11 @@ ENDPROC(cpu_pj4b_do_resume) * It is assumed that: * - cache type register is implemented */ -__v7_ca5mp_setup: __v7_ca9mp_setup: + mov r10, #(1 << 0) @ Cache/TLB ops broadcasting + orr r10, r10, #(1 << 2) @ L1 prefetch + b 1f +__v7_ca5mp_setup: __v7_cr7mp_setup: mov r10, #(1 << 0) @ Cache/TLB ops broadcasting b 1f
Signature · 1 line
2.1.0
PATCH 1/1 ARM: mm: enable L1 prefetch on Cortex-A9
Quoted 9 lines · Thomas Petazzoni
The Cortex-A9 has a L1 prefetch capability documented at
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388e/Chdejhgd.html:The Cortex-A9 data cache implements an automatic prefetcher that monitors cache misses done by the processor. This unit can monitor and prefetch two independent data streams. It can be activated in software using a CP15 Auxiliary Control Register bit. See Auxiliary Control Register.
Quoted 5 lines
This commit enables this L1 prefetch feature unconditionally on all Cortex-A9 by setting bit 2 in the Auxiliary Control CP15 register. Note that since this bit only exists on Cortex-A9 but not on Cortex-A5 or Cortex-R7, we separate the handling of Cortex-A9 from the one of those two other cores.
Have you observed or measured any performance improvements or changes using this change?
Besta regards
Dirk
Quoted 22 lines
Signed-off-by Thomas Petazzoni <[email protected]>--- arch/arm/mm/proc-v7.S | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)arch/arm/mm/proc-v7.S +4
-1@@ -257,8 +257,11 @@ ENDPROC(cpu_pj4b_do_resume) * It is assumed that: * - cache type register is implemented */ -__v7_ca5mp_setup: __v7_ca9mp_setup: + mov r10, #(1 << 0) @ Cache/TLB ops broadcasting + orr r10, r10, #(1 << 2) @ L1 prefetch + b 1f +__v7_ca5mp_setup: __v7_cr7mp_setup: mov r10, #(1 << 0) @ Cache/TLB ops broadcasting b 1f
PATCH 1/1 ARM: mm: enable L1 prefetch on Cortex-A9
Dear Dirk Behme,
Quoted 8 lines · Dirk Behme
Quoted 5 lines
This commit enables this L1 prefetch feature unconditionally on all Cortex-A9 by setting bit 2 in the Auxiliary Control CP15 register. Note that since this bit only exists on Cortex-A9 but not on Cortex-A5 or Cortex-R7, we separate the handling of Cortex-A9 from the one of those two other cores.
Have you observed or measured any performance improvements or changes using this change?
No, I haven't done any measurement myself, I merely wanted to propagate some of the optimizations that were implemented in the Marvell BSP and open the discussion around enabling the L1 prefetching feature of the A9.
Best regards,
Thomas
Signature · 3 lines
Thomas Petazzoni, CTO, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com
PATCH 1/1 ARM: mm: enable L1 prefetch on Cortex-A9
In reply to Thomas PetazzoniQuoted 9 lines · Thomas Petazzoni
The Cortex-A9 has a L1 prefetch capability documented at
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388e/Chdejhgd.html:The Cortex-A9 data cache implements an automatic prefetcher that monitors cache misses done by the processor. This unit can monitor and prefetch two independent data streams. It can be activated in software using a CP15 Auxiliary Control Register bit. See Auxiliary Control Register.
Quoted 7 lines
This commit enables this L1 prefetch feature unconditionally on all Cortex-A9 by setting bit 2 in the Auxiliary Control CP15 register. Note that since this bit only exists on Cortex-A9 but not on Cortex-A5 or Cortex-R7, we separate the handling of Cortex-A9 from the one of those two other cores.
Signed-off-by Thomas Petazzoni <[email protected]>
I'd prefer not to take this until after the next merge window, because I don't want to deal with conflicts that this may cause with other branches in my tree.
We're at -rc8 now, only a week away from -final, now is not really the time to be taking new code into git trees anyway.
Signature · 2 lines
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PATCH 1/1 ARM: mm: enable L1 prefetch on Cortex-A9
Russell,
Quoted 6 lines · Russell King - ARM Linux
I'd prefer not to take this until after the next merge window, because I don't want to deal with conflicts that this may cause with other branches in my tree.
We're at -rc8 now, only a week away from -final, now is not really the time to be taking new code into git trees anyway.
I should have mentioned that explicitly, but I clearly didn't expect this patch to be taken for the upcoming 4.2 merge window as it's way too late. Targeting 4.3 is perfectly fine.
However, can you consider my "ARM: smp_scu: enable coherent speculative linefills", which has been sent almost three months ago:
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/332106.html
Thanks,
Thomas
Signature · 3 lines
Thomas Petazzoni, CTO, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com
PATCH 1/1 ARM: mm: enable L1 prefetch on Cortex-A9
Quoted 11 lines · Thomas Petazzoni
Russell,
Quoted 6 lines · Russell King - ARM Linux
I'd prefer not to take this until after the next merge window, because I don't want to deal with conflicts that this may cause with other branches in my tree.
We're at -rc8 now, only a week away from -final, now is not really the time to be taking new code into git trees anyway.
Quoted 8 lines
I should have mentioned that explicitly, but I clearly didn't expect this patch to be taken for the upcoming 4.2 merge window as it's way too late. Targeting 4.3 is perfectly fine.
However, can you consider my "ARM:
smp_scu: enable coherent speculative linefills", which has been sent almost three months ago:http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/332106.html
I looked at that, and decided I didn't have enough information to know whether that's a good idea to apply or not for all the different variants we have out there. It's something that needs to be merged early in the cycle to give it enough time to be (hopefully) tested by people.
A lot of these "enable optimisation X" patches need to go through that treatment.
Signature · 2 lines
FTTC broadband for 0.8mile line: currently at 10.5Mbps down 400kbps up according to speedtest.net.
PATCH 1/1 ARM: mm: enable L1 prefetch on Cortex-A9
Hello,
Quoted 5 lines · Russell King - ARM Linux
Quoted 4 lines
However, can you consider my "ARM:
smp_scu: enable coherent speculative linefills", which has been sent almost three months ago:http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/332106.html
Quoted 7 lines
I looked at that, and decided I didn't have enough information to know whether that's a good idea to apply or not for all the different variants we have out there. It's something that needs to be merged early in the cycle to give it enough time to be (hopefully) tested by people.
A lot of these "enable optimisation X" patches need to go through that treatment.
Makes perfect sense. Can we get these "enable optimization X" patches merged early enough in the 4.3 cycle, i.e right after 4.2-rc1 is released?
Thanks a lot,
Thomas
Signature · 3 lines
Thomas Petazzoni, CTO, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com
PATCH 1/1 ARM: mm: enable L1 prefetch on Cortex-A9
In reply to Thomas PetazzoniQuoted 9 lines · Thomas Petazzoni
The Cortex-A9 has a L1 prefetch capability documented at
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388e/Chdejhgd.html:The Cortex-A9 data cache implements an automatic prefetcher that monitors cache misses done by the processor. This unit can monitor and prefetch two independent data streams. It can be activated in software using a CP15 Auxiliary Control Register bit. See Auxiliary Control Register.
Quoted 5 lines
This commit enables this L1 prefetch feature unconditionally on all Cortex-A9 by setting bit 2 in the Auxiliary Control CP15 register. Note that since this bit only exists on Cortex-A9 but not on Cortex-A5 or Cortex-R7, we separate the handling of Cortex-A9 from the one of those two other cores.
Does this work in non-secure mode? Perhaps it is just ignored. If so, it deserves a comment along the lines of "This bit should be set by the bootloader and setting it has no effect in non-secure mode."
Rob
Quoted 30 lines
Signed-off-by Thomas Petazzoni <[email protected]>--- arch/arm/mm/proc-v7.S | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)arch/arm/mm/proc-v7.S +4
-2@@ -257,8 +257,11 @@ ENDPROC(cpu_pj4b_do_resume) * It is assumed that: * - cache type register is implemented */ -__v7_ca5mp_setup: __v7_ca9mp_setup: + mov r10, #(1 << 0) @ Cache/TLB ops broadcasting + orr r10, r10, #(1 << 2) @ L1 prefetch + b 1f +__v7_ca5mp_setup: __v7_cr7mp_setup: mov r10, #(1 << 0) @ Cache/TLB ops broadcasting b 1f --2.1.0
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PATCH 1/1 ARM: mm: enable L1 prefetch on Cortex-A9
Dear Rob Herring,
Quoted 9 lines · Rob Herring
Quoted 5 lines
This commit enables this L1 prefetch feature unconditionally on all Cortex-A9 by setting bit 2 in the Auxiliary Control CP15 register. Note that since this bit only exists on Cortex-A9 but not on Cortex-A5 or Cortex-R7, we separate the handling of Cortex-A9 from the one of those two other cores.
Does this work in non-secure mode? Perhaps it is just ignored. If so, it deserves a comment along the lines of "This bit should be set by the bootloader and setting it has no effect in non-secure mode."
According to
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388i/CIHCHFCG.html,
bit 0 (which was already set by the code before my patch) and bit 2 don't have any difference in terms of secure/non-secure access.
The CP15 register as a whole is RO in non-secure if NSACR.NS_SMP = 0. If NSACR.NS_SMP = 1, all bits are write-ignored in non-secure, except the SMP bit (bit 6).
So I assume that if this piece of code is currently setting bit 0, we can assume that setting bit 2 in the same place is also OK. However, setting bit 0 or 2 is probably going to raise an undefined instruction exception in non-secure when NSACR.NS_SMP = 0, but that is not a behavior introduced by my patch.
Thanks for the review!
Thomas
Signature · 3 lines
Thomas Petazzoni, CTO, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com