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MIPS: Add platform specific secondary core init

PATCH In review Tony Wu 2 participants 2 messages Jun 18, 2015 MIPS

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Tony Wu

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PATCH 1/1 MIPS: Add platform specific secondary core init

Define plat_smp_init_secondary() API, and move platform specific secondary core initialization to each platform.

Signed-off-by Tony Wu <[email protected]>
Cc James Hogan <[email protected]>
Cc Paul Burton <[email protected]>
Cc [email protected]
---
 arch/mips/include/asm/smp-ops.h  |    1 +
 arch/mips/kernel/smp-cmp.c       |    8 ++------
 arch/mips/kernel/smp-cps.c       |    4 ++--
 arch/mips/kernel/smp-mt.c        |   12 ++----------
 arch/mips/mti-malta/malta-init.c |   13 +++++++++++++
 5 files changed, 20 insertions(+), 18 deletions(-)
arch/mips/include/asm/smp-ops.h +1 -0
index 6ba1fb8..53ce7e1 100644
@@ -36,6 +36,7 @@ struct plat_smp_ops {
 };
 
 extern void register_smp_ops(struct plat_smp_ops *ops);
+extern void plat_smp_init_secondary(void)
 
 static inline void plat_smp_setup(void)
 {
arch/mips/kernel/smp-cmp.c +2 -6
index d5e0f94..e8c0258 100644
@@ -43,17 +43,13 @@ static void cmp_init_secondary(void)
 {
 	struct cpuinfo_mips *c __maybe_unused = &current_cpu_data;
 
-	/* Assume GIC is present */
-	change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP4 |
-				 STATUSF_IP5 | STATUSF_IP6 | STATUSF_IP7);
-
-	/* Enable per-cpu interrupts: platform specific */
-
 #ifdef CONFIG_MIPS_MT_SMP
 	if (cpu_has_mipsmt)
 		c->vpe_id = (read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) &
 			TCBIND_CURVPE;
 #endif
+	/* Call platform specific init secondary */
+	plat_smp_init_secondary();
 }
 
 static void cmp_smp_finish(void)
arch/mips/kernel/smp-cps.c +2 -2
index 4251d39..5570bc8 100644
@@ -279,8 +279,8 @@ static void cps_init_secondary(void)
 	if (cpu_has_mipsmt)
 		dmt();
 
-	change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP4 |
-				 STATUSF_IP5 | STATUSF_IP6 | STATUSF_IP7);
+	/* Call platform specific init secondary */
+	plat_smp_init_secondary();
 }
 
 static void cps_smp_finish(void)
arch/mips/kernel/smp-mt.c +2 -10
index 86311a1..3d1e32a 100644
@@ -158,16 +158,8 @@ static void vsmp_send_ipi_mask(const struct cpumask *mask, unsigned int action)
 
 static void vsmp_init_secondary(void)
 {
-#ifdef CONFIG_MIPS_GIC
-	/* This is Malta specific: IPI,performance and timer interrupts */
-	if (gic_present)
-		change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 |
-					 STATUSF_IP4 | STATUSF_IP5 |
-					 STATUSF_IP6 | STATUSF_IP7);
-	else
-#endif
-		change_c0_status(ST0_IM, STATUSF_IP0 | STATUSF_IP1 |
-					 STATUSF_IP6 | STATUSF_IP7);
+	/* Call platform specific init secondary */
+	plat_smp_init_secondary();
 }
 
 static void vsmp_smp_finish(void)
arch/mips/mti-malta/malta-init.c +13 -0
index cec3e18..3385ad9 100644
@@ -116,6 +116,19 @@ phys_addr_t mips_cpc_default_phys_base(void)
 	return CPC_BASE_ADDR;
 }
 
+void plat_smp_init_secondary(void)
+{
+#ifdef CONFIG_MIPS_GIC
+	if (gic_present)
+		change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 |
+					 STATUSF_IP4 | STATUSF_IP5 |
+					 STATUSF_IP6 | STATUSF_IP7);
+	else
+#endif
+		change_c0_status(ST0_IM, STATUSF_IP0 | STATUSF_IP1 |
+					 STATUSF_IP6 | STATUSF_IP7);
+}
+
 void __init prom_init(void)
 {
 	mips_display_message("LINUX");
Signature · 1 line
1.7.5
#1 lore raw
Quoted 2 lines · Tony Wu

Define plat_smp_init_secondary() API, and move platform specific secondary core initialization to each platform.

I really can't see that this code being platform specific. Why would a platform care about the c0_status register when a secondary boot is initialised?

That comment about Malta in smp-mt.c is misleading.

Qais

Quoted 111 lines
Signed-off-by Tony Wu <[email protected]>
Cc James Hogan <[email protected]>
Cc Paul Burton <[email protected]>
Cc [email protected]
---
  arch/mips/include/asm/smp-ops.h  |    1 +
  arch/mips/kernel/smp-cmp.c       |    8 ++------
  arch/mips/kernel/smp-cps.c       |    4 ++--
  arch/mips/kernel/smp-mt.c        |   12 ++----------
  arch/mips/mti-malta/malta-init.c |   13 +++++++++++++
  5 files changed, 20 insertions(+), 18 deletions(-)
arch/mips/include/asm/smp-ops.h +1 -0
index 6ba1fb8..53ce7e1 100644
@@ -36,6 +36,7 @@ struct plat_smp_ops {
  };
 
  extern void register_smp_ops(struct plat_smp_ops *ops);
+extern void plat_smp_init_secondary(void)
 
  static inline void plat_smp_setup(void)
  {
arch/mips/kernel/smp-cmp.c +2 -6
index d5e0f94..e8c0258 100644
@@ -43,17 +43,13 @@ static void cmp_init_secondary(void)
  {
  	struct cpuinfo_mips *c __maybe_unused = &current_cpu_data;
 
-	/* Assume GIC is present */
-	change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP4 |
-				 STATUSF_IP5 | STATUSF_IP6 | STATUSF_IP7);
-
-	/* Enable per-cpu interrupts: platform specific */
-
  #ifdef CONFIG_MIPS_MT_SMP
  	if (cpu_has_mipsmt)
  		c->vpe_id = (read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) &
  			TCBIND_CURVPE;
  #endif
+	/* Call platform specific init secondary */
+	plat_smp_init_secondary();
  }
 
  static void cmp_smp_finish(void)
arch/mips/kernel/smp-cps.c +2 -2
index 4251d39..5570bc8 100644
@@ -279,8 +279,8 @@ static void cps_init_secondary(void)
  	if (cpu_has_mipsmt)
  		dmt();
 
-	change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP4 |
-				 STATUSF_IP5 | STATUSF_IP6 | STATUSF_IP7);
+	/* Call platform specific init secondary */
+	plat_smp_init_secondary();
  }
 
  static void cps_smp_finish(void)
arch/mips/kernel/smp-mt.c +2 -10
index 86311a1..3d1e32a 100644
@@ -158,16 +158,8 @@ static void vsmp_send_ipi_mask(const struct cpumask *mask, unsigned int action)
 
  static void vsmp_init_secondary(void)
  {
-#ifdef CONFIG_MIPS_GIC
-	/* This is Malta specific: IPI,performance and timer interrupts */
-	if (gic_present)
-		change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 |
-					 STATUSF_IP4 | STATUSF_IP5 |
-					 STATUSF_IP6 | STATUSF_IP7);
-	else
-#endif
-		change_c0_status(ST0_IM, STATUSF_IP0 | STATUSF_IP1 |
-					 STATUSF_IP6 | STATUSF_IP7);
+	/* Call platform specific init secondary */
+	plat_smp_init_secondary();
  }
 
  static void vsmp_smp_finish(void)
arch/mips/mti-malta/malta-init.c +13 -0
index cec3e18..3385ad9 100644
@@ -116,6 +116,19 @@ phys_addr_t mips_cpc_default_phys_base(void)
  	return CPC_BASE_ADDR;
  }
 
+void plat_smp_init_secondary(void)
+{
+#ifdef CONFIG_MIPS_GIC
+	if (gic_present)
+		change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 |
+					 STATUSF_IP4 | STATUSF_IP5 |
+					 STATUSF_IP6 | STATUSF_IP7);
+	else
+#endif
+		change_c0_status(ST0_IM, STATUSF_IP0 | STATUSF_IP1 |
+					 STATUSF_IP6 | STATUSF_IP7);
+}
+
  void __init prom_init(void)
  {
  	mips_display_message("LINUX");