Support for Microchip pic32mx7 and pic32mz microcontrollers

Signed-off-by Serge Vakulenko <[email protected]>

---
 hw/mips/cputimer.c        | 13 +++++++------
 hw/mips/mips_fulong2e.c   |  2 +-
 hw/mips/mips_jazz.c       |  2 +-
 hw/mips/mips_malta.c      |  4 ++--
 hw/mips/mips_mipssim.c    |  2 +-
 hw/mips/mips_r4k.c        |  2 +-
 include/hw/mips/cpudevs.h |  2 +-
 target-mips/cpu.h         |  1 +
 8 files changed, 15 insertions(+), 13 deletions(-)

hw/mips/cputimer.c +6 -6

index 577c9ae..4f02a9f 100644
@@ -50,8 +50,8 @@ static void cpu_mips_timer_update(CPUMIPSState *env)
 
     now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
     wait = env->CP0_Compare - env->CP0_Count -
-	    (uint32_t)muldiv64(now, TIMER_FREQ, get_ticks_per_sec());
-    next = now + muldiv64(wait, get_ticks_per_sec(), TIMER_FREQ);
+        (uint32_t)muldiv64(now, env->count_freq, get_ticks_per_sec());
+    next = now + muldiv64(wait, get_ticks_per_sec(), env->count_freq);
     timer_mod(env->timer, next);
 }
 

@@ -80,7 +80,7 @@ uint32_t cpu_mips_get_count (CPUMIPSState *env)
         }
 
         return env->CP0_Count +
-            (uint32_t)muldiv64(now, TIMER_FREQ, get_ticks_per_sec());
+            (uint32_t)muldiv64(now, env->count_freq, get_ticks_per_sec());
     }
 }
 

@@ -97,7 +97,7 @@ void cpu_mips_store_count (CPUMIPSState *env, uint32_t count)
         /* Store new count register */
         env->CP0_Count =
             count - (uint32_t)muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
-                                       TIMER_FREQ, get_ticks_per_sec());
+                                       env->count_freq, get_ticks_per_sec());
         /* Update timer timer */
         cpu_mips_timer_update(env);
     }

@@ -122,7 +122,7 @@ void cpu_mips_stop_count(CPUMIPSState *env)
 {
     /* Store the current value */
     env->CP0_Count += (uint32_t)muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
-                                         TIMER_FREQ, get_ticks_per_sec());
+                                         env->count_freq, get_ticks_per_sec());
 }
 
 static void mips_timer_cb (void *opaque)

@@ -145,7 +145,7 @@ static void mips_timer_cb (void *opaque)
     env->CP0_Count--;
 }
 
-void cpu_mips_clock_init (CPUMIPSState *env)
+void cpu_mips_clock_init(CPUMIPSState *env, unsigned count_freq)
 {
     /*
      * If we're in KVM mode, don't create the periodic timer, that is handled in

hw/mips/mips_fulong2e.c +1 -1

index dea941a..5decc30 100644
@@ -343,7 +343,7 @@ static void mips_fulong2e_init(MachineState *machine)
 
     /* Init internal devices */
     cpu_mips_irq_init_cpu(env);
-    cpu_mips_clock_init(env);
+    cpu_mips_clock_init(env, 100*1000*1000);
 
     /* North bridge, Bonito --> IP2 */
     pci_bus = bonito_init((qemu_irq *)&(env->irq[2]));

hw/mips/mips_jazz.c +1 -1

index 9d60633..02629fa 100644
@@ -210,7 +210,7 @@ static void mips_jazz_init(MachineState *machine,
 
     /* Init CPU internal devices */
     cpu_mips_irq_init_cpu(env);
-    cpu_mips_clock_init(env);
+    cpu_mips_clock_init(env, 100*1000*1000);
 
     /* Chipset */
     rc4030 = rc4030_init(&dmas, &rc4030_dma_mr);

hw/mips/mips_malta.c +2 -2

index 3082e75..0393017 100644
@@ -988,7 +988,7 @@ void mips_malta_init(MachineState *machine)
 
         /* Init internal devices */
         cpu_mips_irq_init_cpu(env);
-        cpu_mips_clock_init(env);
+        cpu_mips_clock_init(env, 100*1000*1000);
         qemu_register_reset(main_cpu_reset, cpu);
     }
     cpu = MIPS_CPU(first_cpu);

@@ -1144,7 +1144,7 @@ void mips_malta_init(MachineState *machine)
 
     /* Init internal devices */
     cpu_mips_irq_init_cpu(env);
-    cpu_mips_clock_init(env);
+    cpu_mips_clock_init(env, 100*1000*1000);
 
     /*
      * We have a circular dependency problem: pci_bus depends on isa_irq,

hw/mips/mips_mipssim.c +1 -1

index 61f74a6..940ca58 100644
@@ -213,7 +213,7 @@ mips_mipssim_init(MachineState *machine)
 
     /* Init CPU internal devices. */
     cpu_mips_irq_init_cpu(env);
-    cpu_mips_clock_init(env);
+    cpu_mips_clock_init(env, 100*1000*1000);
 
     /* Register 64 KB of ISA IO space at 0x1fd00000. */
     memory_region_init_alias(isa, NULL, "isa_mmio",

hw/mips/mips_r4k.c +1 -1

index f4dcacd..5f0b766 100644
@@ -266,7 +266,7 @@ void mips_r4k_init(MachineState *machine)
 
     /* Init CPU internal devices */
     cpu_mips_irq_init_cpu(env);
-    cpu_mips_clock_init(env);
+    cpu_mips_clock_init(env, 100*1000*1000);
 
     /* ISA bus: IO space at 0x14000000, mem space at 0x10000000 */
     memory_region_init_alias(isa_io, NULL, "isa-io",

include/hw/mips/cpudevs.h +1 -1

index b2626f2..4d4e62a 100644
@@ -12,6 +12,6 @@ uint64_t cpu_mips_kvm_um_phys_to_kseg0(void *opaque, uint64_t addr);
 void cpu_mips_irq_init_cpu(CPUMIPSState *env);
 
 /* mips_timer.c */
-void cpu_mips_clock_init(CPUMIPSState *);
+void cpu_mips_clock_init(CPUMIPSState *, unsigned count_freq);
 
 #endif

target-mips/cpu.h +1 -0

index 474a0e3..c476166 100644
@@ -595,6 +595,7 @@ struct CPUMIPSState {
     const mips_def_t *cpu_model;
     void *irq[8];
     QEMUTimer *timer; /* Internal timer */
+    unsigned count_freq; /* rate of Count register */
 };
 
 #include "cpu-qom.h"

Signature · 1 line

1.9.1

hw/mips/cputimer.c void cpu_mips_clock_init (CPUMIPSState *env) · line 158

Quoted 7 lines · Serge Vakulenko

hw/mips/cputimer.c +1 -0

@@ -153,5 +153,6 @@ void cpu_mips_clock_init (CPUMIPSState *env)
      */
     if (!kvm_enabled()) {
         env->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &mips_timer_cb, env);
+        env->count_freq = count_freq;
     }
 }

So it means the value passed as an argument to this function is ignored in the KVM case. I guess we want to be able to tell the kernel about the request frequency.

Otherwise it looks fine.

--
Aurelien Jarno GPG: 4096R/1DDD8C9B
[email protected] http://www.aurel32.net

Quoted 12 lines · Aurelien Jarno

hw/mips/cputimer.c void cpu_mips_clock_init (CPUMIPSState *env) · line 158

Quoted 7 lines · Serge Vakulenko

hw/mips/cputimer.c +1 -0

@@ -153,5 +153,6 @@ void cpu_mips_clock_init (CPUMIPSState *env)
      */
     if (!kvm_enabled()) {
         env->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &mips_timer_cb, env);
+        env->count_freq = count_freq;
     }
 }

So it means the value passed as an argument to this function is ignored in the KVM case. I guess we want to be able to tell the kernel about the request frequency.

Sound like a new feature request for MIPS KVM developers. I cannot find any such possibility in the current KVM API.

My patch changes nothing for existing platforms like Malta, Fulong or MIPSsim. Everything continues to work as it is. Only for pic32mx7 cpu the clock rate is decreased to 40MHz. I'm not sure anybody could ever run KVM on this processor. :)

Signed-off-by Serge Vakulenko <[email protected]>

---
 hw/mips/cputimer.c | 18 +++++-------------
 1 file changed, 5 insertions(+), 13 deletions(-)

hw/mips/cputimer.c +2 -9

index 4f02a9f..94a29df 100644
@@ -25,21 +25,13 @@
 #include "qemu/timer.h"
 #include "sysemu/kvm.h"
 
-#define TIMER_FREQ	100 * 1000 * 1000
-
-/* XXX: do not use a global */
+/* Generate a random TLB index.
+ * Skip wired entries. */
 uint32_t cpu_mips_get_random (CPUMIPSState *env)
 {
-    static uint32_t lfsr = 1;
-    static uint32_t prev_idx = 0;
-    uint32_t idx;
-    /* Don't return same value twice, so get another value */
-    do {
-        lfsr = (lfsr >> 1) ^ (-(lfsr & 1u) & 0xd0000001u);

Secondly, I don't think calling random() is the correct thing to do. It's an expensive function that is not thread safe. Quoting the specification:

"Within the required constraints of the upper and lower bounds, the manner in which the processor selects values for the Random register is implementation-dependent."

So it's fine if we use a PRNG like the current code, but I agree we might want to improve it if it has some issues. We want to keep its value reproducible though so that the icount mode works as expected.

Quoted 8 lines · Aurelien Jarno

Secondly, I don't think calling random() is the correct thing to do. It's an expensive function that is not thread safe. Quoting the specification:

"Within the required constraints of the upper and lower bounds, the manner in which the processor selects values for the Random register is implementation-dependent."

Quoted 3 lines

So it's fine if we use a PRNG like the current code, but I agree we might want to improve it if it has some issues. We want to keep its value reproducible though so that the icount mode works as expected.

Implementations often implement CP0.Random as a free-running counter that
decrements between the bounds set as each instruction executes.

Maciej

Quoted 35 lines · Serge Vakulenko

Signed-off-by Serge Vakulenko <[email protected]>

---
 hw/mips/cputimer.c | 18 +++++-------------
 1 file changed, 5 insertions(+), 13 deletions(-)

hw/mips/cputimer.c +5 -13

index 4f02a9f..94a29df 100644
@@ -25,21 +25,13 @@
 #include "qemu/timer.h"
 #include "sysemu/kvm.h"
 
-#define TIMER_FREQ   100 * 1000 * 1000
-
-/* XXX: do not use a global */
+/* Generate a random TLB index.
+ * Skip wired entries. */
 uint32_t cpu_mips_get_random (CPUMIPSState *env)
 {
-    static uint32_t lfsr = 1;
-    static uint32_t prev_idx = 0;
-    uint32_t idx;
-    /* Don't return same value twice, so get another value */
-    do {
-        lfsr = (lfsr >> 1) ^ (-(lfsr & 1u) & 0xd0000001u);
-        idx = lfsr % (env->tlb->nb_tlb - env->CP0_Wired) + env->CP0_Wired;
-    } while (idx == prev_idx);
-    prev_idx = idx;
-    return idx;
+    env->CP0_Random = env->CP0_Wired +
+        random() % (env->tlb->nb_tlb - env->CP0_Wired);
+    return env->CP0_Random;
 }
 

hw/mips/cputimer.c line 37

Quoted 1 line

hw/mips/cputimer.c +0 -0

 /* MIPS R4K timer */

Can you please give us more details about what issue you are trying to fix there? Especially I don't understand about the "skip wired entries" part. It seems the original code handles the wired entries correctly, and at least your patch doesn't seem to change anything regarded that part.

Secondly, I don't think calling random() is the correct thing to do. It's an expensive function that is not thread safe. Quoting the specification:

"Within the required constraints of the upper and lower bounds, the manner in which the processor selects values for the Random register is implementation-dependent."

So it's fine if we use a PRNG like the current code, but I agree we might want to improve it if it has some issues. We want to keep its value reproducible though so that the icount mode works as expected.

--
Aurelien Jarno GPG: 4096R/1DDD8C9B
[email protected] http://www.aurel32.net

Quoted 36 lines · Aurelien Jarno

Quoted 35 lines · Serge Vakulenko

Signed-off-by Serge Vakulenko <[email protected]>

---
 hw/mips/cputimer.c | 18 +++++-------------
 1 file changed, 5 insertions(+), 13 deletions(-)

hw/mips/cputimer.c +5 -13

index 4f02a9f..94a29df 100644
@@ -25,21 +25,13 @@
 #include "qemu/timer.h"
 #include "sysemu/kvm.h"
 
-#define TIMER_FREQ   100 * 1000 * 1000
-
-/* XXX: do not use a global */
+/* Generate a random TLB index.
+ * Skip wired entries. */
 uint32_t cpu_mips_get_random (CPUMIPSState *env)
 {
-    static uint32_t lfsr = 1;
-    static uint32_t prev_idx = 0;
-    uint32_t idx;
-    /* Don't return same value twice, so get another value */
-    do {
-        lfsr = (lfsr >> 1) ^ (-(lfsr & 1u) & 0xd0000001u);
-        idx = lfsr % (env->tlb->nb_tlb - env->CP0_Wired) + env->CP0_Wired;
-    } while (idx == prev_idx);
-    prev_idx = idx;
-    return idx;
+    env->CP0_Random = env->CP0_Wired +
+        random() % (env->tlb->nb_tlb - env->CP0_Wired);
+    return env->CP0_Random;
 }
 

Quoted 7 lines

hw/mips/cputimer.c line 37

Quoted 1 line

hw/mips/cputimer.c +0 -0

 /* MIPS R4K timer */

Can you please give us more details about what issue you are trying to fix there? Especially I don't understand about the "skip wired entries" part. It seems the original code handles the wired entries correctly, and at least your patch doesn't seem to change anything regarded that part.

The original code looks fine by itself. But when you try to run in for nb_tlb=16 and CP0_Wired=1, you get a sequence:

15, 6, 7, 2, 7, 2, 7, 2, 7, 2, 7, 2, 7, 2, 7, 2, 7, 2, 7, 2, 7, 2, 7, 2, 7, 2, 7, 2...

This is what happens when 4.4bsd kernel starts on pic32mz processor. It makes the VM subsystem a bit crazy. Later the sequence becomes better, but I think it makes sense to improve it somehow.

Signed-off-by Serge Vakulenko <[email protected]>

---
 hw/mips/cputimer.c | 18 +++++-------------
 1 file changed, 5 insertions(+), 13 deletions(-)

hw/mips/cputimer.c +0 -0

index 4f02a9f..94a29df 100644

Quoted 13 lines · On Tue, 30 Jun 2015 21:12:31 -0700 Serge Vakulenko <[email protected]>…

Signed-off-by Serge Vakulenko <[email protected]>

---
 hw/mips/cputimer.c | 18 +++++-------------
 1 file changed, 5 insertions(+), 13 deletions(-)

hw/mips/cputimer.c +0 -0

index 4f02a9f..94a29df 100644
@@ -25,21 +25,13 @@
 #include "qemu/timer.h"
 #include "sysemu/kvm.h"
 

hw/mips/cputimer.c line 29

Quoted 2 lines

hw/mips/cputimer.c +0 -2

-#define TIMER_FREQ   100 * 1000 * 1000
-

This is a part of the 'Speed of MIPS CPU timer made configurable per platform.' patch.

--
Best regards,
Antony Pavlov

Signed-off-by Serge Vakulenko <[email protected]>

---
 hw/mips/cputimer.c   | 17 +++++++++++++++--
 hw/mips/mips_int.c   | 12 ++++++++++--
 target-mips/cpu.h    |  9 ++++++++-
 target-mips/helper.c | 20 ++++++++++++++------
 4 files changed, 47 insertions(+), 11 deletions(-)

hw/mips/cputimer.c +15 -2

index 94a29df..849d62c 100644
@@ -54,7 +54,13 @@ static void cpu_mips_timer_expire(CPUMIPSState *env)
     if (env->insn_flags & ISA_MIPS32R2) {
         env->CP0_Cause |= 1 << CP0Ca_TI;
     }
-    qemu_irq_raise(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
+    if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
+        /* External interrupt controller mode. */
+        env->eic_timer_irq(env, 1);
+    } else {
+        /* Legacy or vectored interrupt mode. */
+        qemu_irq_raise(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
+    }
 }
 
 uint32_t cpu_mips_get_count (CPUMIPSState *env)

@@ -102,7 +108,14 @@ void cpu_mips_store_compare (CPUMIPSState *env, uint32_t value)
         cpu_mips_timer_update(env);
     if (env->insn_flags & ISA_MIPS32R2)
         env->CP0_Cause &= ~(1 << CP0Ca_TI);
-    qemu_irq_lower(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
+
+    if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
+        /* External interrupt controller mode. */
+        env->eic_timer_irq(env, 0);
+    } else {
+        /* Legacy or vectored interrupt mode. */
+        qemu_irq_lower(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
+    }
 }
 
 void cpu_mips_start_count(CPUMIPSState *env)

hw/mips/mips_int.c +0 -0

index d740046..3452866 100644

hw/mips/mips_int.c +5 -0

+        }
+    } else {
+        /* Legacy or vectored interrupt mode. */
+        qemu_set_irq(env->irq[irq], level);
+    }
 }

target-mips/cpu.h +0 -0

index c476166..ab830ee 100644

target-mips/cpu.h +0 -0

     } else {
         /* A MIPS configured with compatibility or VInt (Vectored Interrupts)

target-mips/helper.c +14 -2

index 8e3204a..7e25998 100644
@@ -574,23 +574,31 @@ void mips_cpu_do_interrupt(CPUState *cs)
             unsigned int vector;
             unsigned int pending = (env->CP0_Cause & CP0Ca_IP_mask) >> 8;
 
-            pending &= env->CP0_Status >> 8;
             /* Compute the Vector Spacing.  */
             spacing = (env->CP0_IntCtl >> CP0IntCtl_VS) & ((1 << 6) - 1);
             spacing <<= 5;
 
-            if (env->CP0_Config3 & (1 << CP0C3_VInt)) {
+            if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
+                /* For VEIC mode, the external interrupt controller feeds the
+                 * vector through the CP0Cause IP lines. */
+                vector = pending;
+
+                /* Architecturally, this is chip-specific behavior.
+                 * TODO: some processors, like PIC32MZ,
+                 * provide vector in a different way.
+                 * Some processors, like PIC32, have a separate
+                 * bit INTCON.MVEC to explicitly enable vectored mode,
+                 * disabled by default. */
+                spacing = 0;
+            } else {
                 /* For VInt mode, the MIPS computes the vector internally.  */
+                pending &= env->CP0_Status >> 8;
                 for (vector = 7; vector > 0; vector--) {

target-mips/helper.c +0 -0

             offset = 0x200 + vector * spacing;
         }

Signature · 1 line

1.9.1

Quoted 51 lines · Serge Vakulenko

Signed-off-by Serge Vakulenko <[email protected]>

---
 hw/mips/cputimer.c   | 17 +++++++++++++++--
 hw/mips/mips_int.c   | 12 ++++++++++--
 target-mips/cpu.h    |  9 ++++++++-
 target-mips/helper.c | 20 ++++++++++++++------
 4 files changed, 47 insertions(+), 11 deletions(-)

hw/mips/cputimer.c +15 -2

index 94a29df..849d62c 100644
@@ -54,7 +54,13 @@ static void cpu_mips_timer_expire(CPUMIPSState *env)
     if (env->insn_flags & ISA_MIPS32R2) {
         env->CP0_Cause |= 1 << CP0Ca_TI;
     }
-    qemu_irq_raise(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
+    if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
+        /* External interrupt controller mode. */
+        env->eic_timer_irq(env, 1);
+    } else {
+        /* Legacy or vectored interrupt mode. */
+        qemu_irq_raise(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
+    }
 }
 
 uint32_t cpu_mips_get_count (CPUMIPSState *env)

@@ -102,7 +108,14 @@ void cpu_mips_store_compare (CPUMIPSState *env, uint32_t value)
         cpu_mips_timer_update(env);
     if (env->insn_flags & ISA_MIPS32R2)
         env->CP0_Cause &= ~(1 << CP0Ca_TI);
-    qemu_irq_lower(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
+
+    if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
+        /* External interrupt controller mode. */
+        env->eic_timer_irq(env, 0);
+    } else {
+        /* Legacy or vectored interrupt mode. */
+        qemu_irq_lower(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
+    }
 }
 
 void cpu_mips_start_count(CPUMIPSState *env)

hw/mips/mips_int.c +0 -0

index d740046..3452866 100644
@@ -32,7 +32,7 @@ static void cpu_mips_irq_request(void *opaque, int irq, int level)
     CPUMIPSState *env = &cpu->env;
     CPUState *cs = CPU(cpu);
 

hw/mips/mips_int.c static void cpu_mips_irq_request(void *opaque, int irq, int level) · line 36

Quoted 3 lines

hw/mips/mips_int.c +1 -1

-    if (irq < 0 || irq > 7)
+    if (irq < 0 || irq > 7 || (env->CP0_Config3 & (1 << CP0C3_VEIC)))
         return;

In which case you go through these code path? The internal interrupt controller should not be used with an external one, so this should not be reached. Actually machines with an external interrupt controller should not even call cpu_mips_irq_init_cpu().

Quoted 5 lines

hw/mips/mips_int.c +0 -0

     if (level) {

@@ -74,5 +74,13 @@ void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level)
         return;
     }
 

hw/mips/mips_int.c void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level) · line 80

Quoted 5 lines

hw/mips/mips_int.c +4 -1

-    qemu_set_irq(env->irq[irq], level);
+    if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
+        /* External interrupt controller mode. */
+        if (level > 0) {
+            env->eic_soft_irq(env, irq);

It means software interrupts can be asserted, but not deasserted with an external vector interrupt. I don't think that is correct.

Quoted 16 lines

hw/mips/mips_int.c +5 -0

+        }
+    } else {
+        /* Legacy or vectored interrupt mode. */
+        qemu_set_irq(env->irq[irq], level);
+    }
 }

target-mips/cpu.h +2 -0

index c476166..ab830ee 100644
@@ -596,6 +596,11 @@ struct CPUMIPSState {
     void *irq[8];
     QEMUTimer *timer; /* Internal timer */
     unsigned count_freq; /* rate of Count register */
+
+    /* Fields for external interrupt controller. */

target-mips/cpu.h struct CPUMIPSState { · line 603

Quoted 3 lines

target-mips/cpu.h +3 -0

+    void *eic_context;
+    void (*eic_timer_irq)(CPUMIPSState *env, int raise);
+    void (*eic_soft_irq)(CPUMIPSState *env, int num);

I don't think this is the way to go. You should just define variable like eic_timer_irq and eic_soft_irq similar to the irq[8] field above, and allocate them with qemu_allocate_irqs(). That way you can pass the context of the external interrupt controller.

target-mips/cpu.h static inline int cpu_mips_hw_interrupts_pending(CPUMIPSState *env) · line 675

Quoted 12 lines

target-mips/cpu.h +3 -1

 };
 
 #include "cpu-qom.h"

@@ -664,7 +669,9 @@ static inline int cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
     if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
         /* A MIPS configured with a vectorizing external interrupt controller
            will feed a vector into the Cause pending lines. The core treats
-           the status lines as a vector level, not as indiviual masks.  */
+           the status lines as a vector level, not as individual masks.  */
+        pending >>= CP0Ca_IP + 2;
+        status >>= CP0Ca_IP + 2;
         r = pending > status;

I don't think it's needed. As the pending and status field have been masked above, we don't need to shift them to do the comparison.

Quoted 38 lines

target-mips/cpu.h +0 -0

     } else {
         /* A MIPS configured with compatibility or VInt (Vectored Interrupts)

target-mips/helper.c +14 -3

index 8e3204a..7e25998 100644
@@ -574,23 +574,31 @@ void mips_cpu_do_interrupt(CPUState *cs)
             unsigned int vector;
             unsigned int pending = (env->CP0_Cause & CP0Ca_IP_mask) >> 8;
 
-            pending &= env->CP0_Status >> 8;
             /* Compute the Vector Spacing.  */
             spacing = (env->CP0_IntCtl >> CP0IntCtl_VS) & ((1 << 6) - 1);
             spacing <<= 5;
 
-            if (env->CP0_Config3 & (1 << CP0C3_VInt)) {
+            if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
+                /* For VEIC mode, the external interrupt controller feeds the
+                 * vector through the CP0Cause IP lines. */
+                vector = pending;
+
+                /* Architecturally, this is chip-specific behavior.
+                 * TODO: some processors, like PIC32MZ,
+                 * provide vector in a different way.
+                 * Some processors, like PIC32, have a separate
+                 * bit INTCON.MVEC to explicitly enable vectored mode,
+                 * disabled by default. */
+                spacing = 0;
+            } else {
                 /* For VInt mode, the MIPS computes the vector internally.  */
+                pending &= env->CP0_Status >> 8;
                 for (vector = 7; vector > 0; vector--) {
                     if (pending & (1 << vector)) {
                         /* Found it.  */
                         break;
                     }
                 }
-            } else {

target-mips/helper.c void mips_cpu_do_interrupt(CPUState *cs) · line 602

Quoted 4 lines

target-mips/helper.c +0 -3

-                /* For VEIC mode, the external interrupt controller feeds the
-                   vector through the CP0Cause IP lines.  */
-                vector = pending;
             }

The changes looks correct, but I do wonder why you swap the test on CP0_Config3. It would be less changes to just move the pending masking with CP0_Status inside the VInt mode.

Quoted 7 lines

target-mips/helper.c +0 -1

             offset = 0x200 + vector * spacing;
         }
--

1.9.1

--
Aurelien Jarno GPG: 4096R/1DDD8C9B
[email protected] http://www.aurel32.net

Quoted 17 lines · Aurelien Jarno

target-mips/cpu.h static inline int cpu_mips_hw_interrupts_pending(CPUMIPSState *env) · line 675

Quoted 13 lines · Serge Vakulenko

target-mips/cpu.h +3 -1

index c476166..ab830ee 100644
@@ -664,7 +669,9 @@ static inline int cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
     if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
         /* A MIPS configured with a vectorizing external interrupt controller
            will feed a vector into the Cause pending lines. The core treats
-           the status lines as a vector level, not as indiviual masks.  */
+           the status lines as a vector level, not as individual masks.  */
+        pending >>= CP0Ca_IP + 2;
+        status >>= CP0Ca_IP + 2;
         r = pending > status;

I don't think it's needed. As the pending and status field have been masked above, we don't need to shift them to do the comparison.

Quoted 3 lines

--
Aurelien Jarno GPG: 4096R/1DDD8C9B
[email protected] http://www.aurel32.net

Quoted 18 lines · Serge Vakulenko

Quoted 17 lines · Aurelien Jarno

target-mips/cpu.h static inline int cpu_mips_hw_interrupts_pending(CPUMIPSState *env) · line 675

Quoted 13 lines · Serge Vakulenko

target-mips/cpu.h +3 -1

index c476166..ab830ee 100644
@@ -664,7 +669,9 @@ static inline int cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
     if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
         /* A MIPS configured with a vectorizing external interrupt controller
            will feed a vector into the Cause pending lines. The core treats
-           the status lines as a vector level, not as indiviual masks.  */
+           the status lines as a vector level, not as individual masks.  */
+        pending >>= CP0Ca_IP + 2;
+        status >>= CP0Ca_IP + 2;
         r = pending > status;

I don't think it's needed. As the pending and status field have been masked above, we don't need to shift them to do the comparison.

This is not true. The values still need to be shifted to get rid of soft interrupt bits, otherwise the comparison becomes incorrect.

Quoted 38 lines

Quoted 38 lines

     } else {
         /* A MIPS configured with compatibility or VInt (Vectored Interrupts)

target-mips/helper.c +14 -3

index 8e3204a..7e25998 100644
@@ -574,23 +574,31 @@ void mips_cpu_do_interrupt(CPUState *cs)
             unsigned int vector;
             unsigned int pending = (env->CP0_Cause & CP0Ca_IP_mask) >> 8;
 
-            pending &= env->CP0_Status >> 8;
             /* Compute the Vector Spacing.  */
             spacing = (env->CP0_IntCtl >> CP0IntCtl_VS) & ((1 << 6) - 1);
             spacing <<= 5;
 
-            if (env->CP0_Config3 & (1 << CP0C3_VInt)) {
+            if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
+                /* For VEIC mode, the external interrupt controller feeds the
+                 * vector through the CP0Cause IP lines. */
+                vector = pending;
+
+                /* Architecturally, this is chip-specific behavior.
+                 * TODO: some processors, like PIC32MZ,
+                 * provide vector in a different way.
+                 * Some processors, like PIC32, have a separate
+                 * bit INTCON.MVEC to explicitly enable vectored mode,
+                 * disabled by default. */
+                spacing = 0;
+            } else {
                 /* For VInt mode, the MIPS computes the vector internally.  */
+                pending &= env->CP0_Status >> 8;
                 for (vector = 7; vector > 0; vector--) {
                     if (pending & (1 << vector)) {
                         /* Found it.  */
                         break;
                     }
                 }
-            } else {

Quoted 8 lines

target-mips/helper.c void mips_cpu_do_interrupt(CPUState *cs) · line 602

Quoted 4 lines

target-mips/helper.c +0 -3

-                /* For VEIC mode, the external interrupt controller feeds the
-                   vector through the CP0Cause IP lines.  */
-                vector = pending;
             }

The changes looks correct, but I do wonder why you swap the test on CP0_Config3. It would be less changes to just move the pending masking with CP0_Status inside the VInt mode.

According to MIPS PRA spec (MD00090), VInt bit becomes do-not-care when Config3.VEIC is enabled. So it makes little sense to rely on it's value here. And it makes it easier to understand this way. EIC and VInt modes are quite different: better not to mix them up.

Signed-off-by Serge Vakulenko <[email protected]>

---
 target-mips/cpu.h            |  2 ++
 target-mips/translate_init.c | 46 ++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 48 insertions(+)

target-mips/cpu.h +0 -0

index ab830ee..9f5890c 100644

target-mips/cpu.h +0 -0

     /* XXX: Maybe make LLAddr per-TC? */
     uint64_t lladdr;
     target_ulong llval;

target-mips/translate_init.c +21 -0

index ddfaff8..430a547 100644
@@ -232,6 +232,52 @@ static const mips_def_t mips_defs[] =
         .mmu_type = MMU_TYPE_FMT,
     },
     {
+        /* Configuration for Microchip PIC32MX microcontroller. */
+        .name = "M4K",
+        .CP0_PRid = 0x00018765,
+        .CP0_Config0 = MIPS_CONFIG0 | (2 << CP0C0_K23) | (2 << CP0C0_KU) |
+                       (1 << CP0C0_SB) | (1 << CP0C0_BM) |
+                       (1 << CP0C0_AR) | (MMU_TYPE_FMT << CP0C0_MT),
+        .CP0_Config1 = (1U << CP0C1_M) | (1 << CP0C1_CA) | (1 << CP0C1_EP),
+        .CP0_Config2 = MIPS_CONFIG2,
+        .CP0_Config3 = (1 << CP0C3_VEIC) | (1 << CP0C3_VInt),
+        .CP0_LLAddr_rw_bitmask = 0,
+        .CP0_LLAddr_shift = 4,
+        .SYNCI_Step = 32,
+        .CCRes = 2,
+        .CP0_Status_rw_bitmask = 0x1258FF17,
+        .SEGBITS = 32,
+        .PABITS = 32,
+        .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
+        .mmu_type = MMU_TYPE_FMT,
+    },
+    {
+        /* Configuration for Microchip PIC32MZ microcontroller. */

target-mips/translate_init.c static const mips_def_t mips_defs[] = · line 237

Quoted 11 lines

target-mips/translate_init.c +3 -0

index ddfaff8..430a547 100644
@@ -232,6 +232,52 @@ static const mips_def_t mips_defs[] =
         .mmu_type = MMU_TYPE_FMT,
     },
     {
+        /* Configuration for Microchip PIC32MX microcontroller. */
+        .name = "M4K",
+        .CP0_PRid = 0x00018765,

target-mips/translate_init.c static const mips_def_t mips_defs[] = · line 257

Quoted 4 lines

target-mips/translate_init.c +4 -0

+    {
+        /* Configuration for Microchip PIC32MZ microcontroller. */
+        .name = "microAptivP",
+        .CP0_PRid = 0x00019e28,

Otherwise it looks ok, though I haven't look at the PIC32 manual to check the values.

Quoted 11 lines · Aurelien Jarno

target-mips/translate_init.c static const mips_def_t mips_defs[] = · line 237

Quoted 11 lines

target-mips/translate_init.c +3 -0

index ddfaff8..430a547 100644
@@ -232,6 +232,52 @@ static const mips_def_t mips_defs[] =
         .mmu_type = MMU_TYPE_FMT,
     },
     {
+        /* Configuration for Microchip PIC32MX microcontroller. */
+        .name = "M4K",
+        .CP0_PRid = 0x00018765,

Hmm, does it make sense to set the Revision field here? We keep it at 0
for other templates, so why not 0x00018700?

Also I suggest to move the template earlier on so that entries remain
sorted by PRId, at least within the same vendor. So this would go between "4KEmR1" and "4KEc" (the M4K is an MTI RTL, quite an old one actually).

Quoted 4 lines

target-mips/translate_init.c static const mips_def_t mips_defs[] = · line 257

Quoted 4 lines

target-mips/translate_init.c +4 -0

+    {
+        /* Configuration for Microchip PIC32MZ microcontroller. */
+        .name = "microAptivP",
+        .CP0_PRid = 0x00019e28,

Same question here, why not 0x00019e00? Also why not "microAptivUP" as
documentation calls it (vs "microAptivUC")?

And again, it looks to me like the entry better followed "M14Kc".

Quoted 2 lines

Otherwise it looks ok, though I haven't look at the PIC32 manual to check the values.

I haven't checked if the bit patterns for configuration registers are
sane either. These RTLs are configurable, so (within some limits) real hardware will have different values anyway.

Maciej

Quoted 6 lines · Serge Vakulenko

Signed-off-by Serge Vakulenko <[email protected]>

---
 target-mips/cpu.h            |  2 ++
 target-mips/translate_init.c | 46 ++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 48 insertions(+)

target-mips/cpu.h struct CPUMIPSState { · line 397

Quoted 9 lines

target-mips/cpu.h +1 -0

index ab830ee..9f5890c 100644
@@ -394,6 +394,7 @@ struct CPUMIPSState {
 #define CP0C0_M    31
 #define CP0C0_K23  28
 #define CP0C0_KU   25
+#define CP0C0_SB   21

Bits in the range 16:24 are implementation specific, so I do wonder if we want to have this bit there. At least we should mark it as implementation specific.

target-mips/cpu.h struct CPUMIPSState { · line 483

Quoted 8 lines

target-mips/cpu.h +1 -0

 #define CP0C0_MDU  20
 #define CP0C0_MM   17
 #define CP0C0_BM   16

@@ -479,6 +480,7 @@ struct CPUMIPSState {
 #define CP0C5_NFExists   0
     int32_t CP0_Config6;
     int32_t CP0_Config7;
+#define CP0C7_WII        31

Same as above, Config6 and Config7 are implementation dependent.

Quoted 32 lines

target-mips/cpu.h +0 -0

     /* XXX: Maybe make LLAddr per-TC? */
     uint64_t lladdr;
     target_ulong llval;

target-mips/translate_init.c +21 -0

index ddfaff8..430a547 100644
@@ -232,6 +232,52 @@ static const mips_def_t mips_defs[] =
         .mmu_type = MMU_TYPE_FMT,
     },
     {
+        /* Configuration for Microchip PIC32MX microcontroller. */
+        .name = "M4K",
+        .CP0_PRid = 0x00018765,
+        .CP0_Config0 = MIPS_CONFIG0 | (2 << CP0C0_K23) | (2 << CP0C0_KU) |
+                       (1 << CP0C0_SB) | (1 << CP0C0_BM) |
+                       (1 << CP0C0_AR) | (MMU_TYPE_FMT << CP0C0_MT),
+        .CP0_Config1 = (1U << CP0C1_M) | (1 << CP0C1_CA) | (1 << CP0C1_EP),
+        .CP0_Config2 = MIPS_CONFIG2,
+        .CP0_Config3 = (1 << CP0C3_VEIC) | (1 << CP0C3_VInt),
+        .CP0_LLAddr_rw_bitmask = 0,
+        .CP0_LLAddr_shift = 4,
+        .SYNCI_Step = 32,
+        .CCRes = 2,
+        .CP0_Status_rw_bitmask = 0x1258FF17,
+        .SEGBITS = 32,
+        .PABITS = 32,
+        .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
+        .mmu_type = MMU_TYPE_FMT,
+    },
+    {
+        /* Configuration for Microchip PIC32MZ microcontroller. */

target-mips/translate_init.c static const mips_def_t mips_defs[] = · line 265

Quoted 10 lines

target-mips/translate_init.c +10 -0

+        .name = "microAptivP",
+        .CP0_PRid = 0x00019e28,
+        .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
+                    (MMU_TYPE_R4000 << CP0C0_MT),
+        .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | (1 << CP0C1_PC),
+        .CP0_Config2 = MIPS_CONFIG2,
+        .CP0_Config3 = (1 << CP0C3_M) | (1 << CP0C3_IPLW) | (1 << CP0C3_MCU) |
+                    (2 << CP0C3_ISA) | (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) |
+                    (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) | (1 << CP0C3_VEIC) |
+                    (1 << CP0C3_VInt),

DSP and DSPr2 are enabled here...

target-mips/translate_init.c static const mips_def_t mips_defs[] = · line 277

Quoted 12 lines

target-mips/translate_init.c +12 -0

+        .CP0_Config4 = (1 << CP0C4_M),
+        .CP0_Config5 = (1 << CP0C5_NFExists),
+        .CP0_Config6 = 0,
+        .CP0_Config7 = (1 << CP0C7_WII),
+        .CP0_LLAddr_rw_bitmask = 0,
+        .CP0_LLAddr_shift = 4,
+        .SYNCI_Step = 32,
+        .CCRes = 2,
+        .CP0_Status_rw_bitmask = 0x1278FF17,
+        .SEGBITS = 32,
+        .PABITS = 32,
+        .insn_flags = CPU_MIPS32R2,

so I guess you want to enable ASE_DSP and ASE_DSPR2 here.

target-mips/translate_init.c static const mips_def_t mips_defs[] = · line 283

Quoted 6 lines

target-mips/translate_init.c +3 -0

+        .mmu_type = MMU_TYPE_R4000,
+    },
+    {
         .name = "24Kc",
         .CP0_PRid = 0x00019300,
         .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |

Otherwise it looks ok, though I haven't look at the PIC32 manual to check the values.

--
Aurelien Jarno GPG: 4096R/1DDD8C9B
[email protected] http://www.aurel32.net

Quoted 7 lines · Aurelien Jarno

Quoted 6 lines · Serge Vakulenko

Signed-off-by Serge Vakulenko <[email protected]>

---
 target-mips/cpu.h            |  2 ++
 target-mips/translate_init.c | 46 ++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 48 insertions(+)

Quoted 13 lines

target-mips/cpu.h struct CPUMIPSState { · line 397

Quoted 9 lines

target-mips/cpu.h +1 -0

index ab830ee..9f5890c 100644
@@ -394,6 +394,7 @@ struct CPUMIPSState {
 #define CP0C0_M    31
 #define CP0C0_K23  28
 #define CP0C0_KU   25
+#define CP0C0_SB   21

Bits in the range 16:24 are implementation specific, so I do wonder if we want to have this bit there. At least we should mark it as implementation specific.

I tried to make the configuration as close as possible to a real PIC32 microcontroller - that's why I added Config0.SB and Config7.WII bits. These bits are described in appropriate Microchip docs. As they are not relevant for the simulation purposes, I'll better remove them for simplicity.

Signed-off-by Serge Vakulenko <[email protected]>

---
 hw/mips/Makefile.objs       |    3 +
 hw/mips/mips_pic32mx7.c     | 1652 +++++++++++++++++++++++++
 hw/mips/mips_pic32mz.c      | 2840 +++++++++++++++++++++++++++++++++++++++++++
 hw/mips/pic32_ethernet.c    |  557 +++++++++
 hw/mips/pic32_gpio.c        |   39 +
 hw/mips/pic32_load_hex.c    |  238 ++++
 hw/mips/pic32_peripherals.h |  210 ++++
 hw/mips/pic32_sdcard.c      |  428 +++++++
 hw/mips/pic32_spi.c         |  121 ++
 hw/mips/pic32_uart.c        |  228 ++++
 hw/mips/pic32mx.h           | 1290 ++++++++++++++++++++
 hw/mips/pic32mz.h           | 2093 +++++++++++++++++++++++++++++++
 12 files changed, 9699 insertions(+)
 create mode 100644 hw/mips/mips_pic32mx7.c
 create mode 100644 hw/mips/mips_pic32mz.c
 create mode 100644 hw/mips/pic32_ethernet.c

 create mode 100644 hw/mips/pic32_gpio.c
 create mode 100644 hw/mips/pic32_load_hex.c
 create mode 100644 hw/mips/pic32_peripherals.h
 create mode 100644 hw/mips/pic32_sdcard.c
 create mode 100644 hw/mips/pic32_spi.c
 create mode 100644 hw/mips/pic32_uart.c
 create mode 100644 hw/mips/pic32mx.h
 create mode 100644 hw/mips/pic32mz.h

Quoted 18 lines · Serge Vakulenko

Signed-off-by Serge Vakulenko <[email protected]>

---
 hw/mips/Makefile.objs       |    3 +
 hw/mips/mips_pic32mx7.c     | 1652 +++++++++++++++++++++++++
 hw/mips/mips_pic32mz.c      | 2840 +++++++++++++++++++++++++++++++++++++++++++
 hw/mips/pic32_ethernet.c    |  557 +++++++++
 hw/mips/pic32_gpio.c        |   39 +
 hw/mips/pic32_load_hex.c    |  238 ++++
 hw/mips/pic32_peripherals.h |  210 ++++
 hw/mips/pic32_sdcard.c      |  428 +++++++
 hw/mips/pic32_spi.c         |  121 ++
 hw/mips/pic32_uart.c        |  228 ++++
 hw/mips/pic32mx.h           | 1290 ++++++++++++++++++++
 hw/mips/pic32mz.h           | 2093 +++++++++++++++++++++++++++++++
 12 files changed, 9699 insertions(+)
 create mode 100644 hw/mips/mips_pic32mx7.c
 create mode 100644 hw/mips/mips_pic32mz.c
 create mode 100644 hw/mips/pic32_ethernet.c

Quoted 8 lines

 create mode 100644 hw/mips/pic32_gpio.c
 create mode 100644 hw/mips/pic32_load_hex.c
 create mode 100644 hw/mips/pic32_peripherals.h
 create mode 100644 hw/mips/pic32_sdcard.c
 create mode 100644 hw/mips/pic32_spi.c
 create mode 100644 hw/mips/pic32_uart.c
 create mode 100644 hw/mips/pic32mx.h
 create mode 100644 hw/mips/pic32mz.h

This patch is huge, and needs to be splitted to ease the review.

--
Aurelien Jarno GPG: 4096R/1DDD8C9B
[email protected] http://www.aurel32.net

Quoted 28 lines · Aurelien Jarno

Quoted 26 lines · Serge Vakulenko

Signed-off-by Serge Vakulenko <[email protected]>

---
 hw/mips/Makefile.objs       |    3 +
 hw/mips/mips_pic32mx7.c     | 1652 +++++++++++++++++++++++++
 hw/mips/mips_pic32mz.c      | 2840 +++++++++++++++++++++++++++++++++++++++++++
 hw/mips/pic32_ethernet.c    |  557 +++++++++
 hw/mips/pic32_gpio.c        |   39 +
 hw/mips/pic32_load_hex.c    |  238 ++++
 hw/mips/pic32_peripherals.h |  210 ++++
 hw/mips/pic32_sdcard.c      |  428 +++++++
 hw/mips/pic32_spi.c         |  121 ++
 hw/mips/pic32_uart.c        |  228 ++++
 hw/mips/pic32mx.h           | 1290 ++++++++++++++++++++
 hw/mips/pic32mz.h           | 2093 +++++++++++++++++++++++++++++++
 12 files changed, 9699 insertions(+)
 create mode 100644 hw/mips/mips_pic32mx7.c
 create mode 100644 hw/mips/mips_pic32mz.c
 create mode 100644 hw/mips/pic32_ethernet.c
 create mode 100644 hw/mips/pic32_gpio.c
 create mode 100644 hw/mips/pic32_load_hex.c
 create mode 100644 hw/mips/pic32_peripherals.h
 create mode 100644 hw/mips/pic32_sdcard.c
 create mode 100644 hw/mips/pic32_spi.c
 create mode 100644 hw/mips/pic32_uart.c
 create mode 100644 hw/mips/pic32mx.h
 create mode 100644 hw/mips/pic32mz.h

Quoted 1 line

This patch is huge, and needs to be splitted to ease the review.

I'll prepare a new patch set, with every new file put into a separate message. Other issues fixed as well.

Quoted 29 lines · On Sun, 5 Jul 2015 21:18:11 -0700 Serge Vakulenko <[email protected]>…

Quoted 28 lines · Aurelien Jarno

Quoted 26 lines · Serge Vakulenko

Signed-off-by Serge Vakulenko <[email protected]>

---
 hw/mips/Makefile.objs       |    3 +
 hw/mips/mips_pic32mx7.c     | 1652 +++++++++++++++++++++++++
 hw/mips/mips_pic32mz.c      | 2840 +++++++++++++++++++++++++++++++++++++++++++
 hw/mips/pic32_ethernet.c    |  557 +++++++++
 hw/mips/pic32_gpio.c        |   39 +
 hw/mips/pic32_load_hex.c    |  238 ++++
 hw/mips/pic32_peripherals.h |  210 ++++
 hw/mips/pic32_sdcard.c      |  428 +++++++
 hw/mips/pic32_spi.c         |  121 ++
 hw/mips/pic32_uart.c        |  228 ++++
 hw/mips/pic32mx.h           | 1290 ++++++++++++++++++++
 hw/mips/pic32mz.h           | 2093 +++++++++++++++++++++++++++++++
 12 files changed, 9699 insertions(+)
 create mode 100644 hw/mips/mips_pic32mx7.c
 create mode 100644 hw/mips/mips_pic32mz.c
 create mode 100644 hw/mips/pic32_ethernet.c
 create mode 100644 hw/mips/pic32_gpio.c
 create mode 100644 hw/mips/pic32_load_hex.c
 create mode 100644 hw/mips/pic32_peripherals.h
 create mode 100644 hw/mips/pic32_sdcard.c
 create mode 100644 hw/mips/pic32_spi.c
 create mode 100644 hw/mips/pic32_uart.c
 create mode 100644 hw/mips/pic32mx.h
 create mode 100644 hw/mips/pic32mz.h

Quoted 4 lines

Quoted 1 line

This patch is huge, and needs to be splitted to ease the review.

I'll prepare a new patch set, with every new file put into a separate message. Other issues fixed as well.

Putting every new file into a separate message is a nonsense. Please separate __logical changes__ into a single patch.

--
Best regards,
Antony Pavlov

Quoted 34 lines · Antony Pavlov

Quoted 31 lines · On Sun, 5 Jul 2015 21:18:11 -0700 Serge Vakulenko <[email protected]>…

Quoted 29 lines · Aurelien Jarno

Quoted 18 lines · Serge Vakulenko

Signed-off-by Serge Vakulenko <[email protected]>

---
 hw/mips/Makefile.objs       |    3 +
 hw/mips/mips_pic32mx7.c     | 1652 +++++++++++++++++++++++++
 hw/mips/mips_pic32mz.c      | 2840 +++++++++++++++++++++++++++++++++++++++++++
 hw/mips/pic32_ethernet.c    |  557 +++++++++
 hw/mips/pic32_gpio.c        |   39 +
 hw/mips/pic32_load_hex.c    |  238 ++++
 hw/mips/pic32_peripherals.h |  210 ++++
 hw/mips/pic32_sdcard.c      |  428 +++++++
 hw/mips/pic32_spi.c         |  121 ++
 hw/mips/pic32_uart.c        |  228 ++++
 hw/mips/pic32mx.h           | 1290 ++++++++++++++++++++
 hw/mips/pic32mz.h           | 2093 +++++++++++++++++++++++++++++++
 12 files changed, 9699 insertions(+)
 create mode 100644 hw/mips/mips_pic32mx7.c
 create mode 100644 hw/mips/mips_pic32mz.c
 create mode 100644 hw/mips/pic32_ethernet.c

Quoted 8 lines

 create mode 100644 hw/mips/pic32_gpio.c
 create mode 100644 hw/mips/pic32_load_hex.c
 create mode 100644 hw/mips/pic32_peripherals.h
 create mode 100644 hw/mips/pic32_sdcard.c
 create mode 100644 hw/mips/pic32_spi.c
 create mode 100644 hw/mips/pic32_uart.c
 create mode 100644 hw/mips/pic32mx.h
 create mode 100644 hw/mips/pic32mz.h

This patch is huge, and needs to be splitted to ease the review.

Quoted 5 lines

Quoted 2 lines

I'll prepare a new patch set, with every new file put into a separate message. Other issues fixed as well.

Putting every new file into a separate message is a nonsense. Please separate __logical changes__ into a single patch.

Aurelien Jarno asked to split this patch to ease the review.

Quoted 3 lines

--
Best regards,
Antony Pavlov

Quoted 34 lines · Antony Pavlov

Quoted 31 lines · On Sun, 5 Jul 2015 21:18:11 -0700 Serge Vakulenko <[email protected]>…

Quoted 29 lines · Aurelien Jarno

Quoted 18 lines · Serge Vakulenko

Signed-off-by Serge Vakulenko <[email protected]>

---
 hw/mips/Makefile.objs       |    3 +
 hw/mips/mips_pic32mx7.c     | 1652 +++++++++++++++++++++++++
 hw/mips/mips_pic32mz.c      | 2840 +++++++++++++++++++++++++++++++++++++++++++
 hw/mips/pic32_ethernet.c    |  557 +++++++++
 hw/mips/pic32_gpio.c        |   39 +
 hw/mips/pic32_load_hex.c    |  238 ++++
 hw/mips/pic32_peripherals.h |  210 ++++
 hw/mips/pic32_sdcard.c      |  428 +++++++
 hw/mips/pic32_spi.c         |  121 ++
 hw/mips/pic32_uart.c        |  228 ++++
 hw/mips/pic32mx.h           | 1290 ++++++++++++++++++++
 hw/mips/pic32mz.h           | 2093 +++++++++++++++++++++++++++++++
 12 files changed, 9699 insertions(+)
 create mode 100644 hw/mips/mips_pic32mx7.c
 create mode 100644 hw/mips/mips_pic32mz.c
 create mode 100644 hw/mips/pic32_ethernet.c

Quoted 8 lines

 create mode 100644 hw/mips/pic32_gpio.c
 create mode 100644 hw/mips/pic32_load_hex.c
 create mode 100644 hw/mips/pic32_peripherals.h
 create mode 100644 hw/mips/pic32_sdcard.c
 create mode 100644 hw/mips/pic32_spi.c
 create mode 100644 hw/mips/pic32_uart.c
 create mode 100644 hw/mips/pic32mx.h
 create mode 100644 hw/mips/pic32mz.h

This patch is huge, and needs to be splitted to ease the review.

Quoted 5 lines

Quoted 2 lines

I'll prepare a new patch set, with every new file put into a separate message. Other issues fixed as well.

Putting every new file into a separate message is a nonsense. Please separate __logical changes__ into a single patch.

Aurelien Jarno asked to split this patch to ease the review.

Quoted 38 lines · On Mon, 6 Jul 2015 11:58:54 -0700 Serge Vakulenko <[email protected]>…

Quoted 37 lines · Antony Pavlov

Quoted 33 lines · On Sun, 5 Jul 2015 21:18:11 -0700 Serge Vakulenko <[email protected]>…

Quoted 28 lines · Aurelien Jarno

Quoted 18 lines · Serge Vakulenko

Signed-off-by Serge Vakulenko <[email protected]>

---
 hw/mips/Makefile.objs       |    3 +
 hw/mips/mips_pic32mx7.c     | 1652 +++++++++++++++++++++++++
 hw/mips/mips_pic32mz.c      | 2840 +++++++++++++++++++++++++++++++++++++++++++
 hw/mips/pic32_ethernet.c    |  557 +++++++++
 hw/mips/pic32_gpio.c        |   39 +
 hw/mips/pic32_load_hex.c    |  238 ++++
 hw/mips/pic32_peripherals.h |  210 ++++
 hw/mips/pic32_sdcard.c      |  428 +++++++
 hw/mips/pic32_spi.c         |  121 ++
 hw/mips/pic32_uart.c        |  228 ++++
 hw/mips/pic32mx.h           | 1290 ++++++++++++++++++++
 hw/mips/pic32mz.h           | 2093 +++++++++++++++++++++++++++++++
 12 files changed, 9699 insertions(+)
 create mode 100644 hw/mips/mips_pic32mx7.c
 create mode 100644 hw/mips/mips_pic32mz.c
 create mode 100644 hw/mips/pic32_ethernet.c

Quoted 8 lines

 create mode 100644 hw/mips/pic32_gpio.c
 create mode 100644 hw/mips/pic32_load_hex.c
 create mode 100644 hw/mips/pic32_peripherals.h
 create mode 100644 hw/mips/pic32_sdcard.c
 create mode 100644 hw/mips/pic32_spi.c
 create mode 100644 hw/mips/pic32_uart.c
 create mode 100644 hw/mips/pic32mx.h
 create mode 100644 hw/mips/pic32mz.h

Quoted 1 line

This patch is huge, and needs to be splitted to ease the review.

I'll prepare a new patch set, with every new file put into a separate message. Other issues fixed as well.

Quoted 4 lines

Quoted 2 lines

Putting every new file into a separate message is a nonsense. Please separate __logical changes__ into a single patch.

Aurelien Jarno asked to split this patch to ease the review.

IMHO he meant something very different.

Please reread the qemu submitting patch manual carefully (see http://wiki.qemu.org/Contribute/SubmitAPatch).

Here is a quote:

Split up longer patches into a patch series of logical code changes. Each change should compile and execute successfully. For instance, don't add a file to the makefile in patch one and then add the file itself in patch two. (This rule is here so that people can later use tools like git bisect without hitting points in the commit history where QEMU doesn't work for reasons unrelated to the bug they're chasing.)

Also please reread this Peter's comment very very carefully:

   http://lists.nongnu.org/archive/html/qemu-devel/2015-07/msg01430.html

Peter asks you to rework your device support code: every device should be self-contained. E.g. for UART support code this means that:

0. Object model is used. Your UART code implements operation of one UART instance. private structure is used for storing UART instance's current state. The SoC code (or even board code) creates as many UART instances as it needs.

Also please see this Aurilien's comment: http://lists.nongnu.org/archive/html/qemu-devel/2015-07/msg01242.html

1. UART C code go to qemu.git/hw/char/;

2. externally visible UART stuff (header file) go to qemu.git/include/hw/char/;

Pay attention that there is no need to put all UART related macro into header file. If nobody outside your UART C code use these macros then you can keep their definition in the C code.

3. UART C code compilation has to be enabled only for mips-softmmu target. So make your UART C code compilation dependendent on a Makefile option, enable this option only in qemu.git/default-configs/mips-softmmu.mak.

4. UART support have to be added in a separate patch. So this patch have to contain changes in these files:

default-configs/mips-softmmu.mak
hw/char/Makefile.objs
hw/char/pic32_uart.c
include/hw/char/pic32_uart.h

This UART support patch has to be submitted __before__ a patch with SoC/board code that use UART.

As Peter suggests please use 'Netduino 2 Machine Model' patchseries as a model,
see http://lists.gnu.org/archive/html/qemu-devel/2015-02/msg03398.html

Signed-off-by Serge Vakulenko <[email protected]>

---
 hw/mips/Makefile.objs       |    3 +
 hw/mips/mips_pic32mx7.c     | 1652 +++++++++++++++++++++++++
 hw/mips/mips_pic32mz.c      | 2840 +++++++++++++++++++++++++++++++++++++++++++
 hw/mips/pic32_ethernet.c    |  557 +++++++++
 hw/mips/pic32_gpio.c        |   39 +
 hw/mips/pic32_load_hex.c    |  238 ++++
 hw/mips/pic32_peripherals.h |  210 ++++
 hw/mips/pic32_sdcard.c      |  428 +++++++
 hw/mips/pic32_spi.c         |  121 ++
 hw/mips/pic32_uart.c        |  228 ++++
 hw/mips/pic32mx.h           | 1290 ++++++++++++++++++++
 hw/mips/pic32mz.h           | 2093 +++++++++++++++++++++++++++++++
 12 files changed, 9699 insertions(+)
 create mode 100644 hw/mips/mips_pic32mx7.c
 create mode 100644 hw/mips/mips_pic32mz.c
 create mode 100644 hw/mips/pic32_ethernet.c
 create mode 100644 hw/mips/pic32_gpio.c
 create mode 100644 hw/mips/pic32_load_hex.c
 create mode 100644 hw/mips/pic32_peripherals.h
 create mode 100644 hw/mips/pic32_sdcard.c
 create mode 100644 hw/mips/pic32_spi.c
 create mode 100644 hw/mips/pic32_uart.c
 create mode 100644 hw/mips/pic32mx.h
 create mode 100644 hw/mips/pic32mz.h

hw/mips/Makefile.objs +0 -0

index 9633f3a..dcbaec9 100644

hw/mips/mips_pic32mx7.c new file +17 -0

new file mode 100644
index 0000000..1d8ffb5
@@ -0,0 +1,1652 @@
+/*
+ * QEMU support for Microchip PIC32MX7 microcontroller.
+ *
+ * Copyright (c) 2015 Serge Vakulenko
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

Quoted 27 lines · On Tue, 30 Jun 2015 21:12:34 -0700 Serge Vakulenko <[email protected]>…

Signed-off-by Serge Vakulenko <[email protected]>

---
 hw/mips/Makefile.objs       |    3 +
 hw/mips/mips_pic32mx7.c     | 1652 +++++++++++++++++++++++++
 hw/mips/mips_pic32mz.c      | 2840 +++++++++++++++++++++++++++++++++++++++++++
 hw/mips/pic32_ethernet.c    |  557 +++++++++
 hw/mips/pic32_gpio.c        |   39 +
 hw/mips/pic32_load_hex.c    |  238 ++++
 hw/mips/pic32_peripherals.h |  210 ++++
 hw/mips/pic32_sdcard.c      |  428 +++++++
 hw/mips/pic32_spi.c         |  121 ++
 hw/mips/pic32_uart.c        |  228 ++++
 hw/mips/pic32mx.h           | 1290 ++++++++++++++++++++
 hw/mips/pic32mz.h           | 2093 +++++++++++++++++++++++++++++++
 12 files changed, 9699 insertions(+)
 create mode 100644 hw/mips/mips_pic32mx7.c
 create mode 100644 hw/mips/mips_pic32mz.c
 create mode 100644 hw/mips/pic32_ethernet.c
 create mode 100644 hw/mips/pic32_gpio.c
 create mode 100644 hw/mips/pic32_load_hex.c
 create mode 100644 hw/mips/pic32_peripherals.h
 create mode 100644 hw/mips/pic32_sdcard.c
 create mode 100644 hw/mips/pic32_spi.c
 create mode 100644 hw/mips/pic32_uart.c
 create mode 100644 hw/mips/pic32mx.h
 create mode 100644 hw/mips/pic32mz.h

hw/mips/Makefile.objs obj-y += addr.o cputimer.o mips_int.o · line 8

Quoted 11 lines

hw/mips/Makefile.objs +3 -0

index 9633f3a..dcbaec9 100644
@@ -3,3 +3,6 @@ obj-y += addr.o cputimer.o mips_int.o
 obj-$(CONFIG_JAZZ) += mips_jazz.o
 obj-$(CONFIG_FULONG) += mips_fulong2e.o
 obj-y += gt64xxx_pci.o
+obj-y += mips_pic32mz.o mips_pic32mx7.o
+obj-y += pic32_load_hex.o pic32_sdcard.o pic32_spi.o pic32_uart.o pic32_gpio.o
+obj-y += pic32_ethernet.o

Can we move mips-unrelated stuff to the appropriate dirs? E.g. pic32_gpio.c can to go to hw/gpio.

Also please use separate patch for every peripheral controller (see Aurelien's comment).

Quoted 28 lines

hw/mips/mips_pic32mx7.c new file +22 -0

new file mode 100644
index 0000000..1d8ffb5
@@ -0,0 +1,1652 @@
+/*
+ * QEMU support for Microchip PIC32MX7 microcontroller.
+ *
+ * Copyright (c) 2015 Serge Vakulenko
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.

hw/mips/mips_pic32mx7.c line 27

Quoted 5 lines

hw/mips/mips_pic32mx7.c new file +5 -0

+ */
+
+/* Only 32-bit little endian mode supported. */
+#include "config.h"
+#if !defined TARGET_MIPS64 && !defined TARGET_WORDS_BIGENDIAN

Please don't use C preprocessor directive for conditional compilation of the whole file. Use Makefile instead. See CONFIG_FULONG for example (fulong2e is mips64le-only).

--
Best regards,
Antony Pavlov

Quoted 30 lines · Antony Pavlov

Quoted 27 lines · On Tue, 30 Jun 2015 21:12:34 -0700 Serge Vakulenko <[email protected]>…

Signed-off-by Serge Vakulenko <[email protected]>

---
 hw/mips/Makefile.objs       |    3 +
 hw/mips/mips_pic32mx7.c     | 1652 +++++++++++++++++++++++++
 hw/mips/mips_pic32mz.c      | 2840 +++++++++++++++++++++++++++++++++++++++++++
 hw/mips/pic32_ethernet.c    |  557 +++++++++
 hw/mips/pic32_gpio.c        |   39 +
 hw/mips/pic32_load_hex.c    |  238 ++++
 hw/mips/pic32_peripherals.h |  210 ++++
 hw/mips/pic32_sdcard.c      |  428 +++++++
 hw/mips/pic32_spi.c         |  121 ++
 hw/mips/pic32_uart.c        |  228 ++++
 hw/mips/pic32mx.h           | 1290 ++++++++++++++++++++
 hw/mips/pic32mz.h           | 2093 +++++++++++++++++++++++++++++++
 12 files changed, 9699 insertions(+)
 create mode 100644 hw/mips/mips_pic32mx7.c
 create mode 100644 hw/mips/mips_pic32mz.c
 create mode 100644 hw/mips/pic32_ethernet.c
 create mode 100644 hw/mips/pic32_gpio.c
 create mode 100644 hw/mips/pic32_load_hex.c
 create mode 100644 hw/mips/pic32_peripherals.h
 create mode 100644 hw/mips/pic32_sdcard.c
 create mode 100644 hw/mips/pic32_spi.c
 create mode 100644 hw/mips/pic32_uart.c
 create mode 100644 hw/mips/pic32mx.h
 create mode 100644 hw/mips/pic32mz.h

Quoted 14 lines

hw/mips/Makefile.objs obj-y += addr.o cputimer.o mips_int.o · line 8

Quoted 11 lines

hw/mips/Makefile.objs +3 -0

index 9633f3a..dcbaec9 100644
@@ -3,3 +3,6 @@ obj-y += addr.o cputimer.o mips_int.o
 obj-$(CONFIG_JAZZ) += mips_jazz.o
 obj-$(CONFIG_FULONG) += mips_fulong2e.o
 obj-y += gt64xxx_pci.o
+obj-y += mips_pic32mz.o mips_pic32mx7.o
+obj-y += pic32_load_hex.o pic32_sdcard.o pic32_spi.o pic32_uart.o pic32_gpio.o
+obj-y += pic32_ethernet.o

Can we move mips-unrelated stuff to the appropriate dirs? E.g. pic32_gpio.c can to go to hw/gpio.

All these files are pic32-related. They depend on pic32_t data structure declared in pic32_peripherals.h and register definitions in pic32mx.h and pic32mz.h. I see no point to move them around.

Quoted 1 line

Also please use separate patch for every peripheral controller (see Aurelien's comment).

Agreed.

Quoted 28 lines

Quoted 28 lines

hw/mips/mips_pic32mx7.c new file +22 -0

new file mode 100644
index 0000000..1d8ffb5
@@ -0,0 +1,1652 @@
+/*
+ * QEMU support for Microchip PIC32MX7 microcontroller.
+ *
+ * Copyright (c) 2015 Serge Vakulenko
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.

Quoted 8 lines

hw/mips/mips_pic32mx7.c line 27

Quoted 5 lines

hw/mips/mips_pic32mx7.c new file +5 -0

+ */
+
+/* Only 32-bit little endian mode supported. */
+#include "config.h"
+#if !defined TARGET_MIPS64 && !defined TARGET_WORDS_BIGENDIAN

Please don't use C preprocessor directive for conditional compilation of the whole file. Use Makefile instead. See CONFIG_FULONG for example (fulong2e is mips64le-only).

Makes sense.

Thanks,
--Serge

Quoted 3 lines

--
Best regards,
Antony Pavlov

Please find below a set of patches, which allow to simulate Microchip PIC32 microcontrollers on QEMU. For examples of real PIC32 applications running on QEMU, see page: https://github.com/sergev/qemu/wiki

(1) Make the CPU clock frequency configurable per platform. Currently the clock rate for all MIPS platforms is fixed at 100MHz. Need to make it 40MHz for pic32mx7.

(2) For TLBWR instruction, the generated random index value has been not quite random and did not take into account the Wired register value. Fixed.

(3) Added support for external interrupt controller mode (EIC). Required for pic32.

(4) Added two processor variants: M4K and microAptivUP. Needed for pic32mx and pic32mz simulation.

(5) Added two machine platforms: Microchip pic32mx7 and pic32mz microcontrollers. Several board types supported for each platform:

pic32mx7-explorer16 PIC32MX7 microcontroller on Microchip Explorer-16 board
pic32mx7-max32 PIC32MX7 microcontroller on chipKIT Max32 board
pic32mx7-maximite PIC32MX7 microcontroller on Geoff's Maximite computer
pic32mz-explorer16 PIC32MZ microcontroller on Microchip Explorer-16 board
pic32mz-meb2 PIC32MZ microcontroller on Microchip MEB-II board
pic32mz-wifire PIC32MZ microcontroller on chipKIT WiFire board

Serge Vakulenko (5):
Speed of MIPS CPU timer made configurable per platform. Fixed random index generation for TLBWR instruction. It was not quite
random and did not skip Wired entries.
Added support for external interrupt controller (EIC) mode. Two new processor variants: M4K and microAptivP.
Two new machine platforms: pic32mz7 and pic32mz.

Quoted 28 lines · On Tue, 30 Jun 2015 21:12:29 -0700 Serge Vakulenko <[email protected]>…

Please find below a set of patches, which allow to simulate Microchip PIC32 microcontrollers on QEMU. For examples of real PIC32 applications running on QEMU, see page: https://github.com/sergev/qemu/wiki

(1) Make the CPU clock frequency configurable per platform. Currently the clock rate for all MIPS platforms is fixed at 100MHz. Need to make it 40MHz for pic32mx7.

(2) For TLBWR instruction, the generated random index value has been not quite random and did not take into account the Wired register value. Fixed.

(3) Added support for external interrupt controller mode (EIC). Required for pic32.

(4) Added two processor variants: M4K and microAptivUP. Needed for pic32mx and pic32mz simulation.

(5) Added two machine platforms: Microchip pic32mx7 and pic32mz microcontrollers. Several board types supported for each platform:

pic32mx7-explorer16 PIC32MX7 microcontroller on Microchip Explorer-16 board
pic32mx7-max32 PIC32MX7 microcontroller on chipKIT Max32 board
pic32mx7-maximite PIC32MX7 microcontroller on Geoff's Maximite computer
pic32mz-explorer16 PIC32MZ microcontroller on Microchip Explorer-16 board
pic32mz-meb2 PIC32MZ microcontroller on Microchip MEB-II board
pic32mz-wifire PIC32MZ microcontroller on chipKIT WiFire board

Quoted 7 lines

Serge Vakulenko (5):
Speed of MIPS CPU timer made configurable per platform. Fixed random index generation for TLBWR instruction. It was not quite
random and did not skip Wired entries.
Added support for external interrupt controller (EIC) mode. Two new processor variants: M4K and microAptivP.
Two new machine platforms: pic32mz7 and pic32mz.

Please fix your subject lines according to "Write a good commit message" section of http://wiki.qemu.org/Contribute/SubmitAPatch.

Also please use the imperative mood in the subject line.

--
Best regards,
Antony Pavlov