Fix exceptions handling for MIPS, PowerPC, and i386
v5 cover Fix exceptions handling for MIPS, PowerPC, and i386
QEMU targets ISAs contain instruction that can break the execution flow with exceptions. When exception breaks the execution of the translation block it may corrupt PC and icount values.
This set of patches fixes exception handling for MIPS, PowerPC, and i386 targets.
Incorrect execution for i386 is causes by exceptions raised by MMU functions. MMU helper functions are called from generated code and other helper functions. In both cases they try to get function's return address for restoring virtual CPU state.
When MMU helper is called from some other helper function (like helper_maskmov_xmm) through cpu_st* function, the return address will point to that helper. That is why CPU state cannot be restored in the case of MMU fault.
This bug can occur when maskmov instruction is located in the middle of the translation block.
Execution sequence for this example:
TB start:
PC1: instr1
instr2
PC2: maskmov <page fault>
<page fault processing>
PC1: instr1
instr2
maskmov
At the start of TB execution guest PC points to instr1. When page fault occurs QEMU tries to restore guest PC (which should be equal to PC2). It reads host PC from the call stack and checks whether it points to TB or not. Bug in ldst helpers implementation provides incorrect host PC, which is not located within the TB. That's why QEMU cannot recover guest PC and it remains the same (PC1). After page fault processing QEMU restarts TB and executes instr1 and instr2 for the second time, because guest PC was not recovered.
Bugs in helper functions for other targets do not break the execution in regular TCG mode, because PC value is updated before calling the functions that can raise an exception. But icount value cannot be updated this way. Therefore exceptions make execution in icount mode non-determinisic. In icount mode every translation block looks as follows:
if icount < n then exit
icount -= n
instr1
instr2
...
instrn
exit
When one of these instructions initiates an exception, icount should be restored and adjusted number of instructions should be subtracted from icount instead of initial n.
tlb_fill function passes retaddr to raise_exception, which allows restoring current instructions in TB and correct icount calculation.
When exception triggered with other function (e.g. by embedding call to exception raising helper into TB), then PC is not passed as retaddr and correct icount is not recovered. In such cases icount will be decreased by the value equal to the size of TB.
This behavior leads to incorrect values of virtual clock and non-deterministic execution of the code.
These patches passes pointer to the translation block code to the exception handler. It allows correct restoring of PC and icount values.
v5 changes:
* Added helper functions for usermode ldst (as suggested by Aurelien Jarno)
* Fixed memory helpers for MIPS (as suggested by Aurelien Jarno)
* Added _ra version of raise_exception functions (as suggested by Richard Henderson)
* Split i386 patch into several parts (as suggested by Richard Henderson)
v4 changes:
* Fixed exceptions handling for PowerPC
* Fixed passing of mmu_idx into helpers (as suggested by Aurelien Jarno)
* Added cpu_loop_exit_restore function (as suggested by Aurelien Jarno)
* Fixed exceptions handling in compare helper functions for MIPS (as suggested by Aurelien Jarno)
* Removed several CPU state saving calls for MIPS (as suggested by Aurelien Jarno)
v3 changes:
* Modified exception handling for syscall (as suggested by Aurelien Jarno)
* Removed redundant calls to save_cpu_state (as suggested by Aurelien Jarno)
* Removed helper_call* functions from softmmu (as suggested by Paolo Bonzini)
v2 changes:
* Added softmmu functions to pass TB return value into memory operations handlers
* Fixed memory operations handling for MIPS
* Disabled updates of the PC that are overridden with cpu_restore_state
* Fixed memory operations and exceptions invoked by i386 helpers
---
Pavel Dovgalyuk (11):
softmmu: add helper function to pass through retaddr
cpu-exec: introduce loop exit with restore function
target-mips: improve exceptions handling
target-i386: introduce new raise_exception functions
target-i386: exception handling for FPU instructions
target-i386: exception handling for div instructions
target-i386: exception handling for memory helpers
target-i386: exception handling for seg_helper functions
target-i386: exception handling for other helper functions
target-i386: remove useless PC updates
target-ppc: exceptions handling in icount mode
cpu-exec.c | 9 include/exec/cpu_ldst_template.h | 59 ++- include/exec/cpu_ldst_useronly_template.h | 25 + include/exec/exec-all.h | 1 softmmu_template.h | 6 target-i386/cc_helper.c | 2 target-i386/cpu.h | 4 target-i386/excp_helper.c | 26 + target-i386/fpu_helper.c | 146 ++++--- target-i386/int_helper.c | 32 + target-i386/mem_helper.c | 39 +- target-i386/misc_helper.c | 10 target-i386/ops_sse.h | 2 target-i386/seg_helper.c | 646 +++++++++++++++-------------- target-i386/svm_helper.c | 4 target-i386/translate.c | 25 - target-mips/cpu.h | 23 + target-mips/helper.h | 1 target-mips/msa_helper.c | 158 ++++--- target-mips/op_helper.c | 169 +++----- target-mips/translate.c | 363 ++++++++-------- target-ppc/cpu.h | 3 target-ppc/excp_helper.c | 38 +- target-ppc/fpu_helper.c | 191 ++++----- target-ppc/helper.h | 1 target-ppc/mem_helper.c | 6 target-ppc/misc_helper.c | 8 target-ppc/mmu-hash64.c | 12 - target-ppc/mmu_helper.c | 18 - target-ppc/timebase_helper.c | 20 - target-ppc/translate.c | 84 ---- tcg/tcg.h | 23 + 32 files changed, 1111 insertions(+), 1043 deletions(-)
Signature · 1 line
Pavel Dovgalyuk
PATCH v5 1/11 softmmu: add helper function to pass through retaddr
This patch introduces several helpers to pass return address which points to the TB. Correct return address allows correct restoring of the guest PC and icount. These functions should be used when helpers embedded into TB invoke memory operations.
Reviewed-by Richard Henderson <[email protected]>
Signed-off-by Pavel Dovgalyuk <[email protected]>
--- include/exec/cpu_ldst_template.h | 59 +++++++++++++++++++++++++---- include/exec/cpu_ldst_useronly_template.h | 25 ++++++++++++ softmmu_template.h | 6 --- tcg/tcg.h | 23 +++++++++++ 4 files changed, 99 insertions(+), 14 deletions(-)
include/exec/cpu_ldst_template.h +51 -8
@@ -27,20 +27,24 @@#define SUFFIX q#define USUFFIX q#define DATA_TYPE uint64_t +#define SHIFT 3#elif DATA_SIZE ==4 #define SUFFIX l#define USUFFIX l#define DATA_TYPE uint32_t +#define SHIFT 2#elif DATA_SIZE ==2 #define SUFFIX w#define USUFFIX uw#define DATA_TYPE uint16_t#define DATA_STYPE int16_t +#define SHIFT 1#elif DATA_SIZE ==1 #define SUFFIX b#define USUFFIX ub#define DATA_TYPE uint8_t#define DATA_STYPE int8_t +#define SHIFT 0#else #error unsupported data size#endif
@@ -54,27 +58,36 @@#ifdef SOFTMMU_CODE_ACCESS #define ADDR_READ addr_code#define MMUSUFFIX _cmmu +#define URETSUFFIX SUFFIX +#define SRETSUFFIX SUFFIX#else #define ADDR_READ addr_read#define MMUSUFFIX _mmu +#define URETSUFFIX USUFFIX +#define SRETSUFFIX glue(s, SUFFIX)#endif /* generic load/store macros */ static inline RES_TYPE -glue (glue (cpu_ld ,USUFFIX ),MEMSUFFIX )(CPUArchState *env,target_ulong ptr) +glue (glue (glue (cpu_ld ,USUFFIX ),MEMSUFFIX ),_ra )(CPUArchState *env, +target_ulong ptr, +uintptr_t retaddr) {int page_index;RES_TYPE res;target_ulong addr;int mmu_idx; +TCGMemOpIdx oi; addr = ptr; page_index = (addr >>TARGET_PAGE_BITS ) & (CPU_TLB_SIZE -1 ); mmu_idx =CPU_MMU_INDEX ;if (unlikely (env->tlb_table[mmu_idx][page_index].ADDR_READ != (addr & (TARGET_PAGE_MASK | (DATA_SIZE -1 ))))) { - res =glue (glue (helper_ld,SUFFIX ),MMUSUFFIX )(env, addr, mmu_idx); + oi =make_memop_idx (SHIFT , mmu_idx); + res =glue (glue (helper_ret_ld,URETSUFFIX ),MMUSUFFIX )(env, addr, + oi, retaddr); }else {uintptr_t hostaddr = addr + env->tlb_table[mmu_idx][page_index].addend; res =glue (glue (ld,USUFFIX ), _p)((uint8_t *)hostaddr);
@@ -82,27 +95,43 @@ glue(glue(cpu_ld, USUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr)return res; } +static inline RES_TYPE +glue (glue (cpu_ld ,USUFFIX ),MEMSUFFIX )(CPUArchState *env,target_ulong ptr) +{ +return glue (glue (glue (cpu_ld,USUFFIX ),MEMSUFFIX ), _ra)(env, ptr,0 ); +} +#if DATA_SIZE <=2 static inline int -glue (glue (cpu_lds ,SUFFIX ),MEMSUFFIX )(CPUArchState *env,target_ulong ptr) +glue (glue (glue (cpu_lds ,SUFFIX ),MEMSUFFIX ),_ra )(CPUArchState *env, +target_ulong ptr, +uintptr_t retaddr) {int res, page_index;target_ulong addr;int mmu_idx; +TCGMemOpIdx oi; addr = ptr; page_index = (addr >>TARGET_PAGE_BITS ) & (CPU_TLB_SIZE -1 ); mmu_idx =CPU_MMU_INDEX ;if (unlikely (env->tlb_table[mmu_idx][page_index].ADDR_READ != (addr & (TARGET_PAGE_MASK | (DATA_SIZE -1 ))))) { - res = (DATA_STYPE )glue (glue (helper_ld,SUFFIX ), -MMUSUFFIX )(env, addr, mmu_idx); + oi =make_memop_idx (SHIFT , mmu_idx); + res = (DATA_STYPE )glue (glue (helper_ret_ld,SRETSUFFIX ), +MMUSUFFIX )(env, addr, oi, retaddr); }else {uintptr_t hostaddr = addr + env->tlb_table[mmu_idx][page_index].addend; res =glue (glue (lds,SUFFIX ), _p)((uint8_t *)hostaddr); }return res; } + +static inline int +glue (glue (cpu_lds ,SUFFIX ),MEMSUFFIX )(CPUArchState *env,target_ulong ptr) +{ +return glue (glue (glue (cpu_lds,SUFFIX ),MEMSUFFIX ), _ra)(env, ptr,0 ); +}#endif #ifndef SOFTMMU_CODE_ACCESS
@@ -110,25 +139,36 @@ glue(glue(cpu_lds, SUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr)/* generic store macro */ static inline void -glue (glue (cpu_st ,SUFFIX ),MEMSUFFIX )(CPUArchState *env,target_ulong ptr, -RES_TYPE v) +glue (glue (glue (cpu_st ,SUFFIX ),MEMSUFFIX ),_ra )(CPUArchState *env, +target_ulong ptr, +RES_TYPE v,uintptr_t retaddr) {int page_index;target_ulong addr;int mmu_idx; +TCGMemOpIdx oi; addr = ptr; page_index = (addr >>TARGET_PAGE_BITS ) & (CPU_TLB_SIZE -1 ); mmu_idx =CPU_MMU_INDEX ;if (unlikely (env->tlb_table[mmu_idx][page_index].addr_write != (addr & (TARGET_PAGE_MASK | (DATA_SIZE -1 ))))) { -glue (glue (helper_st,SUFFIX ),MMUSUFFIX )(env, addr, v, mmu_idx); + oi =make_memop_idx (SHIFT , mmu_idx); +glue (glue (helper_ret_st,SUFFIX ),MMUSUFFIX )(env, addr, v, oi, + retaddr); }else {uintptr_t hostaddr = addr + env->tlb_table[mmu_idx][page_index].addend;glue (glue (st,SUFFIX ), _p)((uint8_t *)hostaddr, v); } } +static inline void +glue (glue (cpu_st ,SUFFIX ),MEMSUFFIX )(CPUArchState *env,target_ulong ptr, +RES_TYPE v) +{ +glue (glue (glue (cpu_st,SUFFIX ),MEMSUFFIX ), _ra)(env, ptr, v,0 ); +} +#endif /* !SOFTMMU_CODE_ACCESS */ #undef RES_TYPE
@@ -139,3 +179,6 @@ glue(glue(cpu_st, SUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr,#undef DATA_SIZE#undef MMUSUFFIX#undef ADDR_READ +#undef URETSUFFIX +#undef SRETSUFFIX +#undef SHIFT
include/exec/cpu_ldst_useronly_template.h +25 -0
@@ -56,12 +56,28 @@ glue(glue(cpu_ld, USUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr)return glue (glue (ld,USUFFIX ), _p)(g2h (ptr)); } +static inline RES_TYPE +glue (glue (glue (cpu_ld ,USUFFIX ),MEMSUFFIX ),_ra )(CPUArchState *env, +target_ulong ptr, +uintptr_t retaddr) +{ +return glue (glue (cpu_ld,USUFFIX ),MEMSUFFIX )(env, ptr); +} +#if DATA_SIZE <=2 static inline int glue (glue (cpu_lds ,SUFFIX ),MEMSUFFIX )(CPUArchState *env,target_ulong ptr) {return glue (glue (lds,SUFFIX ), _p)(g2h (ptr)); } + +static inline int +glue (glue (glue (cpu_lds ,SUFFIX ),MEMSUFFIX ),_ra )(CPUArchState *env, +target_ulong ptr, +uintptr_t retaddr) +{ +return glue (glue (cpu_lds,SUFFIX ),MEMSUFFIX )(env, ptr); +}#endif #ifndef CODE_ACCESS
@@ -71,6 +87,15 @@ glue(glue(cpu_st, SUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr, {glue (glue (st,SUFFIX ), _p)(g2h (ptr), v); } + +static inline void +glue (glue (glue (cpu_st ,SUFFIX ),MEMSUFFIX ),_ra )(CPUArchState *env, +target_ulong ptr, +RES_TYPE v, +uintptr_t retaddr) +{ +glue (glue (cpu_st,SUFFIX ),MEMSUFFIX )(env, ptr, v); +}#endif #undef RES_TYPE
softmmu_template.h +0 -6
@@ -165,9 +165,6 @@ static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env, }#endif -#ifdef SOFTMMU_CODE_ACCESS -static __attribute__((unused)) -#endifWORD_TYPE helper_le_ld_name (CPUArchState *env,target_ulong addr,TCGMemOpIdx oi,uintptr_t retaddr) {
@@ -252,9 +249,6 @@ WORD_TYPE helper_le_ld_name(CPUArchState *env, target_ulong addr, }#if DATA_SIZE >1 -#ifdef SOFTMMU_CODE_ACCESS -static __attribute__((unused)) -#endifWORD_TYPE helper_be_ld_name (CPUArchState *env,target_ulong addr,TCGMemOpIdx oi,uintptr_t retaddr) {
tcg/tcg.h +23 -0
@@ -983,25 +983,48 @@ void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,void helper_be_stq_mmu (CPUArchState *env,target_ulong addr,uint64_t val,TCGMemOpIdx oi,uintptr_t retaddr); +uint8_t helper_ret_ldb_cmmu (CPUArchState *env,target_ulong addr, +TCGMemOpIdx oi,uintptr_t retaddr); +uint16_t helper_le_ldw_cmmu (CPUArchState *env,target_ulong addr, +TCGMemOpIdx oi,uintptr_t retaddr); +uint32_t helper_le_ldl_cmmu (CPUArchState *env,target_ulong addr, +TCGMemOpIdx oi,uintptr_t retaddr); +uint64_t helper_le_ldq_cmmu (CPUArchState *env,target_ulong addr, +TCGMemOpIdx oi,uintptr_t retaddr); +uint16_t helper_be_ldw_cmmu (CPUArchState *env,target_ulong addr, +TCGMemOpIdx oi,uintptr_t retaddr); +uint32_t helper_be_ldl_cmmu (CPUArchState *env,target_ulong addr, +TCGMemOpIdx oi,uintptr_t retaddr); +uint64_t helper_be_ldq_cmmu (CPUArchState *env,target_ulong addr, +TCGMemOpIdx oi,uintptr_t retaddr); +/* Temporary aliases until backends are converted. */ #ifdef TARGET_WORDS_BIGENDIAN # define helper_ret_ldsw_mmu helper_be_ldsw_mmu# define helper_ret_lduw_mmu helper_be_lduw_mmu# define helper_ret_ldsl_mmu helper_be_ldsl_mmu# define helper_ret_ldul_mmu helper_be_ldul_mmu +# define helper_ret_ldl_mmu helper_be_ldul_mmu# define helper_ret_ldq_mmu helper_be_ldq_mmu# define helper_ret_stw_mmu helper_be_stw_mmu# define helper_ret_stl_mmu helper_be_stl_mmu# define helper_ret_stq_mmu helper_be_stq_mmu +# define helper_ret_ldw_cmmu helper_be_ldw_cmmu +# define helper_ret_ldl_cmmu helper_be_ldl_cmmu +# define helper_ret_ldq_cmmu helper_be_ldq_cmmu#else # define helper_ret_ldsw_mmu helper_le_ldsw_mmu# define helper_ret_lduw_mmu helper_le_lduw_mmu# define helper_ret_ldsl_mmu helper_le_ldsl_mmu# define helper_ret_ldul_mmu helper_le_ldul_mmu +# define helper_ret_ldl_mmu helper_le_ldul_mmu# define helper_ret_ldq_mmu helper_le_ldq_mmu# define helper_ret_stw_mmu helper_le_stw_mmu# define helper_ret_stl_mmu helper_le_stl_mmu# define helper_ret_stq_mmu helper_le_stq_mmu +# define helper_ret_ldw_cmmu helper_le_ldw_cmmu +# define helper_ret_ldl_cmmu helper_le_ldl_cmmu +# define helper_ret_ldq_cmmu helper_le_ldq_cmmu#endif #endif /* CONFIG_SOFTMMU */
Re: [Qemu-devel] [PATCH v5 01/11] softmmu: add helper function to pass through retaddr
Quoted 6 lines · Pavel Dovgalyuk
This patch introduces several helpers to pass return address which points to the TB. Correct return address allows correct restoring of the guest PC and icount. These functions should be used when helpers embedded into TB invoke memory operations.
Reviewed-by Richard Henderson <[email protected]>
Given that you have changed the patch, the reviewed-by should have been removed.
Quoted 8 lines
Signed-off-by Pavel Dovgalyuk <[email protected]>--- include/exec/cpu_ldst_template.h | 59 +++++++++++++++++++++++++---- include/exec/cpu_ldst_useronly_template.h | 25 ++++++++++++ softmmu_template.h | 6 --- tcg/tcg.h | 23 +++++++++++ 4 files changed, 99 insertions(+), 14 deletions(-)
That said it looks fine to me, so you can add mine:
Reviewed-by Aurelien Jarno <[email protected]>
Signature · 2 lines
Aurelien Jarno GPG: 4096R/1DDD8C9B [email protected] http://www.aurel32.net
PATCH v5 2/11 cpu-exec: introduce loop exit with restore function
In reply to Pavel DovgalyukThis patch introduces loop exit function, which also restores guest CPU state according to the value of host program counter.
Reviewed-by Richard Henderson <[email protected]>
Reviewed-by Aurelien Jarno <[email protected]>
Signed-off-by Pavel Dovgalyuk <[email protected]>
--- cpu-exec.c | 9 +++++++++ include/exec/exec-all.h | 1 + 2 files changed, 10 insertions(+), 0 deletions(-)
cpu-exec.c +9 -0
@@ -134,6 +134,15 @@ void cpu_loop_exit(CPUState *cpu)siglongjmp (cpu->jmp_env,1 ); } +void cpu_loop_exit_restore (CPUState *cpu,uintptr_t pc) +{ +if (pc) { +cpu_restore_state (cpu, pc); + } + cpu->current_tb =NULL ; +siglongjmp (cpu->jmp_env,1 ); +} +/* exit the current TB from a signal handler. The host registers are restored in a state compatible with the CPU emulator */
include/exec/exec-all.h +1 -0
@@ -90,6 +90,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, int cflags);void cpu_exec_init (CPUArchState *env); void QEMU_NORETURN cpu_loop_exit(CPUState *cpu); +void QEMU_NORETURN cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc);#if !defined(CONFIG_USER_ONLY )//bool qemu_in_vcpu_thread(void);
Re: [Qemu-devel] [PATCH v5 02/11] cpu-exec: introduce loop exit with restore function
Quoted 38 lines · Pavel Dovgalyuk
This patch introduces loop exit function, which also restores guest CPU state according to the value of host program counter.
Reviewed-by Richard Henderson <[email protected]>Reviewed-by Aurelien Jarno <[email protected]>Signed-off-by Pavel Dovgalyuk <[email protected]>--- cpu-exec.c | 9 +++++++++ include/exec/exec-all.h | 1 + 2 files changed, 10 insertions(+), 0 deletions(-)cpu-exec.c +9
-0@@ -134,6 +134,15 @@ void cpu_loop_exit(CPUState *cpu)siglongjmp (cpu->jmp_env,1 ); } +void cpu_loop_exit_restore (CPUState *cpu,uintptr_t pc) +{ +if (pc) { +cpu_restore_state (cpu, pc); + } + cpu->current_tb =NULL ; +siglongjmp (cpu->jmp_env,1 ); +} +/* exit the current TB from a signal handler. The host registers are restored in a state compatible with the CPU emulator */ include/exec/exec-all.h +0
-0
include/exec/exec-all.h TranslationBlock *tb_gen_code(CPUState *cpu, · line 96
Quoted 7 lines
include/exec/exec-all.h +1
-0@@ -90,6 +90,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, int cflags);void cpu_exec_init (CPUArchState *env); void QEMU_NORETURN cpu_loop_exit(CPUState *cpu); +void QEMU_NORETURN cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc);#if !defined(CONFIG_USER_ONLY )//bool qemu_in_vcpu_thread(void);
Note that this line is not commented in QEMU master, so your patch doesn't apply cleanly.
Signature · 2 lines
Aurelien Jarno GPG: 4096R/1DDD8C9B [email protected] http://www.aurel32.net
PATCH v5 3/11 target-mips: improve exceptions handling
In reply to Pavel DovgalyukThis patch improves exception handling in MIPS.
Instructions generate several types of exceptions.
When exception is generated, it breaks the execution of the current translation block. Implementation of the exceptions handling does not correctly restore icount for the instruction which caused the exception. In most cases icount will be decreased by the value equal to the size of TB. This patch passes pointer to the translation block internals to the exception handler. It allows correct restoring of the icount value.
v3 changes:
This patch stops translation when instruction which always generates exception is translated. This improves the performance of the patched version compared to original one.
Signed-off-by Pavel Dovgalyuk <[email protected]>
--- target-mips/cpu.h | 23 +++ target-mips/helper.h | 1 target-mips/msa_helper.c | 158 +++++++++++--------- target-mips/op_helper.c | 169 ++++++++++----------- target-mips/translate.c | 363 ++++++++++++++++++++++------------------------ 5 files changed, 359 insertions(+), 355 deletions(-)
target-mips/cpu.h +23 -0
@@ -1049,4 +1049,27 @@ static inline void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val) }#endif +static inline void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, +uint32_t exception, +int error_code, +uintptr_t pc) +{ +CPUState *cs =CPU (mips_env_get_cpu (env)); + +if (exception <EXCP_SC ) { +qemu_log ("%s: %d %d\n" , __func__, exception, error_code); + } + cs->exception_index = exception; + env->error_code = error_code; + +cpu_loop_exit_restore (cs, pc); +} + +static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env, +uint32_t exception, +uintptr_t pc) +{ +do_raise_exception_err (env, exception,0 , pc); +} +#endif /* !defined (__MIPS_CPU_H__) */
target-mips/helper.h +1 -0
@@ -1,5 +1,6 @@ DEF_HELPER_3(raise_exception_err, noreturn, env, i32, int) DEF_HELPER_2(raise_exception, noreturn, env, i32) +DEF_HELPER_1(raise_exception_debug, noreturn, env)DEF_HELPER_1 (do_semihosting, void, env)
target-mips/msa_helper.c +85 -73
586 lines not on this page · raw message
target-mips/op_helper.c +77 -92
419 lines not on this page · raw message
target-mips/translate.c +173 -190
1,414 lines not on this page · raw message
Re: [Qemu-devel] [PATCH v5 03/11] target-mips: improve exceptions handling
Quoted 14 lines · Pavel Dovgalyuk
This patch improves exception handling in MIPS.
Instructions generate several types of exceptions.
When exception is generated, it breaks the execution of the current translation block. Implementation of the exceptions handling does not correctly restore icount for the instruction which caused the exception. In most cases icount will be decreased by the value equal to the size of TB. This patch passes pointer to the translation block internals to the exception handler. It allows correct restoring of the icount value.v3 changes:
This patch stops translation when instruction which always generates exception is translated. This improves the performance of the patched version compared to original one.
Quoted 8 lines
Signed-off-by Pavel Dovgalyuk <[email protected]>--- target-mips/cpu.h | 23 +++ target-mips/helper.h | 1 target-mips/msa_helper.c | 158 +++++++++++--------- target-mips/op_helper.c | 169 ++++++++++----------- target-mips/translate.c | 363 ++++++++++++++++++++++------------------------ 5 files changed, 359 insertions(+), 355 deletions(-)
Reviewed-by Aurelien Jarno <[email protected]>
Signature · 2 lines
Aurelien Jarno GPG: 4096R/1DDD8C9B [email protected] http://www.aurel32.net
PATCH v5 4/11 target-i386: introduce new raise_exception functions
In reply to Pavel DovgalyukThis patch introduces new versions of raise_exception functions that receive TB return address as an argument.
Signed-off-by Pavel Dovgalyuk <[email protected]>
--- target-i386/cpu.h | 4 ++++ target-i386/excp_helper.c | 26 +++++++++++++++++++------- 2 files changed, 23 insertions(+), 7 deletions(-)
target-i386/cpu.h +4 -0
@@ -1263,8 +1263,12 @@ void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank,/* excp_helper.c */ void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index); +void QEMU_NORETURN raise_exception_ra(CPUX86State *env, int exception_index, +uintptr_t retaddr); void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_index,int error_code); +void QEMU_NORETURN raise_exception_err_ra(CPUX86State *env, int exception_index, +int error_code,uintptr_t retaddr); void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_int,int error_code,int next_eip_addend);
target-i386/excp_helper.c +19 -7
@@ -23,10 +23,10 @@#include "exec/helper-proto.h" #if 0 -#define raise_exception_err (env, a, b) \ +#define raise_exception_err (env, a, b, c) \ do { \ qemu_log("raise_exception line=%d\n", __LINE__); \ - (raise_exception_err)(env, a, b); \ + (raise_exception_err)(env, a, b, c); \ } while (0)#endif
@@ -92,7 +92,8 @@ static int check_exception(CPUX86State *env, int intno, int *error_code)*/ static void QEMU_NORETURN raise_interrupt2(CPUX86State *env, int intno,int is_int,int error_code, -int next_eip_addend) +int next_eip_addend, +uintptr_t retaddr) {CPUState *cs =CPU (x86_env_get_cpu (env));
@@ -108,7 +109,7 @@ static void QEMU_NORETURN raise_interrupt2(CPUX86State *env, int intno, env->error_code = error_code; env->exception_is_int = is_int; env->exception_next_eip = env->eip + next_eip_addend; -cpu_loop_exit (cs); +cpu_loop_exit_restore (cs, retaddr); }/* shortcuts to generate exceptions */
@@ -116,16 +117,27 @@ static void QEMU_NORETURN raise_interrupt2(CPUX86State *env, int intno, void QEMU_NORETURN raise_interrupt(CPUX86State *env, int intno, int is_int,int error_code,int next_eip_addend) { -raise_interrupt2 (env, intno, is_int, error_code, next_eip_addend); +raise_interrupt2 (env, intno, is_int, error_code, next_eip_addend,0 ); }void raise_exception_err (CPUX86State *env,int exception_index,int error_code) { -raise_interrupt2 (env, exception_index,0 , error_code,0 ); +raise_interrupt2 (env, exception_index,0 , error_code,0 ,0 ); +} + +void raise_exception_err_ra (CPUX86State *env,int exception_index, +int error_code,uintptr_t retaddr) +{ +raise_interrupt2 (env, exception_index,0 , error_code,0 , retaddr); }void raise_exception (CPUX86State *env,int exception_index) { -raise_interrupt2 (env, exception_index,0 ,0 ,0 ); +raise_interrupt2 (env, exception_index,0 ,0 ,0 ,0 ); +} + +void raise_exception_ra (CPUX86State *env,int exception_index,uintptr_t retaddr) +{ +raise_interrupt2 (env, exception_index,0 ,0 ,0 , retaddr); }
Re: [Qemu-devel] [PATCH v5 04/11] target-i386: introduce new raise_exception functions
target-i386/excp_helper.c line 31
Quoted 10 lines · Pavel Dovgalyuk
#if 0target-i386/excp_helper.c +2
-2-#define raise_exception_err (env, a, b) \ +#define raise_exception_err (env, a, b, c) \ do { \ qemu_log("raise_exception line=%d\n", __LINE__); \ - (raise_exception_err)(env, a, b); \ + (raise_exception_err)(env, a, b, c); \ } while (0)#endif
This change wouldn't compile. That said, I'm ok simply deleting the whole if 0 block. I think keeping it around is silly.
r~
Re: [Qemu-devel] [PATCH v5 04/11] target-i386: introduce new raise_exception functions
In reply to Pavel DovgalyukQuoted 9 lines · Pavel Dovgalyuk
This patch introduces new versions of
raise_exceptionfunctions that receive TB return address as an argument.Signed-off-by Pavel Dovgalyuk <[email protected]>--- target-i386/cpu.h | 4 ++++ target-i386/excp_helper.c | 26 +++++++++++++++++++------- 2 files changed, 23 insertions(+), 7 deletions(-)
Besides the comment from Richard:
Reviewed-by Aurelien Jarno <[email protected]>
Signature · 2 lines
Aurelien Jarno GPG: 4096R/1DDD8C9B [email protected] http://www.aurel32.net
PATCH v5 5/11 target-i386: exception handling for FPU instructions
In reply to Pavel DovgalyukThis patch fixes exception handling for FPU instructions.
Signed-off-by Pavel Dovgalyuk <[email protected]>
--- target-i386/fpu_helper.c | 146 +++++++++++++++++++++++++--------------------- 1 files changed, 80 insertions(+), 66 deletions(-)
target-i386/fpu_helper.c +80 -66
@@ -68,22 +68,24 @@ static inline void fpop(CPUX86State *env) env->fpstt = (env->fpstt +1 ) &7 ; } -static inline floatx80 helper_fldt (CPUX86State *env,target_ulong ptr) +static inline floatx80 helper_fldt (CPUX86State *env,target_ulong ptr, +uintptr_t retaddr) {CPU_LDoubleU temp; - temp.l.lower =cpu_ldq_data (env, ptr); - temp.l.upper =cpu_lduw_data (env, ptr +8 ); + temp.l.lower =cpu_ldq_data_ra (env, ptr, retaddr); + temp.l.upper =cpu_lduw_data_ra (env, ptr +8 , retaddr);return temp.d; } -static inline void helper_fstt (CPUX86State *env,floatx80 f,target_ulong ptr) +static inline void helper_fstt (CPUX86State *env,floatx80 f,target_ulong ptr, +uintptr_t retaddr) {CPU_LDoubleU temp; temp.d = f; -cpu_stq_data (env, ptr, temp.l.lower); -cpu_stw_data (env, ptr +8 , temp.l.upper); +cpu_stq_data_ra (env, ptr, temp.l.lower, retaddr); +cpu_stw_data_ra (env, ptr +8 , temp.l.upper, retaddr); }/* x87 FPU helpers */
@@ -126,10 +128,10 @@ static inline floatx80 helper_fdiv(CPUX86State *env, floatx80 a, floatx80 b)return floatx80_div (a, b, &env->fp_status); } -static void fpu_raise_exception (CPUX86State *env) +static void fpu_raise_exception (CPUX86State *env,uintptr_t retaddr) {if (env->cr[0 ] &CR0_NE_MASK ) { -raise_exception (env,EXCP10_COPR ); +raise_exception_ra (env,EXCP10_COPR , retaddr); }#if !defined(CONFIG_USER_ONLY ) else {
@@ -314,14 +316,14 @@ void helper_fldt_ST0(CPUX86State *env, target_ulong ptr)int new_fpstt; new_fpstt = (env->fpstt -1 ) &7 ; - env->fpregs[new_fpstt].d =helper_fldt (env, ptr); + env->fpregs[new_fpstt].d =helper_fldt (env, ptr,GETPC ()); env->fpstt = new_fpstt; env->fptags[new_fpstt] =0 ;/* validate stack entry */ }void helper_fstt_ST0 (CPUX86State *env,target_ulong ptr) { -helper_fstt (env,ST0 , ptr); +helper_fstt (env,ST0 , ptr,GETPC ()); }void helper_fpush (CPUX86State *env)
@@ -604,7 +606,7 @@ void helper_fclex(CPUX86State *env)void helper_fwait (CPUX86State *env) {if (env->fpus &FPUS_SE ) { -fpu_raise_exception (env); +fpu_raise_exception (env,GETPC ()); } }
@@ -634,11 +636,11 @@ void helper_fbld_ST0(CPUX86State *env, target_ulong ptr) val =0 ;for (i =8 ; i >=0 ; i--) { - v =cpu_ldub_data (env, ptr + i); + v =cpu_ldub_data_ra (env, ptr + i,GETPC ()); val = (val *100 ) + ((v >>4 ) *10 ) + (v &0xf ); } tmp =int64_to_floatx80 (val, &env->fp_status); -if (cpu_ldub_data (env, ptr +9 ) &0x80 ) { +if (cpu_ldub_data_ra (env, ptr +9 ,GETPC ()) &0x80 ) { tmp =floatx80_chs (tmp); }fpush (env);
@@ -655,10 +657,10 @@ void helper_fbst_ST0(CPUX86State *env, target_ulong ptr) mem_ref = ptr; mem_end = mem_ref +9 ;if (val <0 ) { -cpu_stb_data (env, mem_end,0x80 ); +cpu_stb_data_ra (env, mem_end,0x80 ,GETPC ()); val = -val; }else { -cpu_stb_data (env, mem_end,0x00 ); +cpu_stb_data_ra (env, mem_end,0x00 ,GETPC ()); }while (mem_ref < mem_end) {if (val ==0 ) {
@@ -667,10 +669,10 @@ void helper_fbst_ST0(CPUX86State *env, target_ulong ptr) v = val %100 ; val = val /100 ; v = ((v /10 ) <<4 ) | (v %10 ); -cpu_stb_data (env, mem_ref++, v); +cpu_stb_data_ra (env, mem_ref++, v,GETPC ()); }while (mem_ref < mem_end) { -cpu_stb_data (env, mem_ref++,0 ); +cpu_stb_data_ra (env, mem_ref++,0 ,GETPC ()); } }
@@ -978,7 +980,8 @@ void helper_fxam_ST0(CPUX86State *env) } } -void helper_fstenv (CPUX86State *env,target_ulong ptr,int data32) +static void do_fstenv (CPUX86State *env,target_ulong ptr,int data32, +uintptr_t retaddr) {int fpus, fptag, exp, i;uint64_t mant;
@@ -1006,37 +1009,43 @@ void helper_fstenv(CPUX86State *env, target_ulong ptr, int data32) }if (data32) {/* 32 bit */ -cpu_stl_data (env, ptr, env->fpuc); -cpu_stl_data (env, ptr +4 , fpus); -cpu_stl_data (env, ptr +8 , fptag); -cpu_stl_data (env, ptr +12 ,0 );/* fpip */ -cpu_stl_data (env, ptr +16 ,0 );/* fpcs */ -cpu_stl_data (env, ptr +20 ,0 );/* fpoo */ -cpu_stl_data (env, ptr +24 ,0 );/* fpos */ +cpu_stl_data_ra (env, ptr, env->fpuc, retaddr); +cpu_stl_data_ra (env, ptr +4 , fpus, retaddr); +cpu_stl_data_ra (env, ptr +8 , fptag, retaddr); +cpu_stl_data_ra (env, ptr +12 ,0 , retaddr);/* fpip */ +cpu_stl_data_ra (env, ptr +16 ,0 , retaddr);/* fpcs */ +cpu_stl_data_ra (env, ptr +20 ,0 , retaddr);/* fpoo */ +cpu_stl_data_ra (env, ptr +24 ,0 , retaddr);/* fpos */ }else {/* 16 bit */ -cpu_stw_data (env, ptr, env->fpuc); -cpu_stw_data (env, ptr +2 , fpus); -cpu_stw_data (env, ptr +4 , fptag); -cpu_stw_data (env, ptr +6 ,0 ); -cpu_stw_data (env, ptr +8 ,0 ); -cpu_stw_data (env, ptr +10 ,0 ); -cpu_stw_data (env, ptr +12 ,0 ); +cpu_stw_data_ra (env, ptr, env->fpuc, retaddr); +cpu_stw_data_ra (env, ptr +2 , fpus, retaddr); +cpu_stw_data_ra (env, ptr +4 , fptag, retaddr); +cpu_stw_data_ra (env, ptr +6 ,0 , retaddr); +cpu_stw_data_ra (env, ptr +8 ,0 , retaddr); +cpu_stw_data_ra (env, ptr +10 ,0 , retaddr); +cpu_stw_data_ra (env, ptr +12 ,0 , retaddr); } } -void helper_fldenv (CPUX86State *env,target_ulong ptr,int data32) +void helper_fstenv (CPUX86State *env,target_ulong ptr,int data32) +{ +do_fstenv (env, ptr, data32,GETPC ()); +} + +static void do_fldenv (CPUX86State *env,target_ulong ptr,int data32, +uintptr_t retaddr) {int i, fpus, fptag;if (data32) { -cpu_set_fpuc (env,cpu_lduw_data (env, ptr)); - fpus =cpu_lduw_data (env, ptr +4 ); - fptag =cpu_lduw_data (env, ptr +8 ); +cpu_set_fpuc (env,cpu_lduw_data_ra (env, ptr, retaddr)); + fpus =cpu_lduw_data_ra (env, ptr +4 , retaddr); + fptag =cpu_lduw_data_ra (env, ptr +8 , retaddr); }else { -cpu_set_fpuc (env,cpu_lduw_data (env, ptr)); - fpus =cpu_lduw_data (env, ptr +2 ); - fptag =cpu_lduw_data (env, ptr +4 ); +cpu_set_fpuc (env,cpu_lduw_data_ra (env, ptr, retaddr)); + fpus =cpu_lduw_data_ra (env, ptr +2 , retaddr); + fptag =cpu_lduw_data_ra (env, ptr +4 , retaddr); } env->fpstt = (fpus >>11 ) &7 ; env->fpus = fpus & ~0x3800 ;
@@ -1046,17 +1055,22 @@ void helper_fldenv(CPUX86State *env, target_ulong ptr, int data32) } } +void helper_fldenv (CPUX86State *env,target_ulong ptr,int data32) +{ +do_fldenv (env, ptr, data32,GETPC ()); +} +void helper_fsave (CPUX86State *env,target_ulong ptr,int data32) {floatx80 tmp;int i; -helper_fstenv (env, ptr, data32); +do_fstenv (env, ptr, data32,GETPC ()); ptr += (14 << data32);for (i =0 ; i <8 ; i++) { tmp =ST (i); -helper_fstt (env, tmp, ptr); +helper_fstt (env, tmp, ptr,GETPC ()); ptr +=10 ; }
@@ -1079,11 +1093,11 @@ void helper_frstor(CPUX86State *env, target_ulong ptr, int data32)floatx80 tmp;int i; -helper_fldenv (env, ptr, data32); +do_fldenv (env, ptr, data32,GETPC ()); ptr += (14 << data32);for (i =0 ; i <8 ; i++) { - tmp =helper_fldt (env, ptr); + tmp =helper_fldt (env, ptr,GETPC ());ST (i) = tmp; ptr +=10 ; }
@@ -1109,7 +1123,7 @@ void helper_fxsave(CPUX86State *env, target_ulong ptr, int data64)/* The operand must be 16 byte aligned */ if (ptr &0xf ) { -raise_exception (env,EXCP0D_GPF ); +raise_exception_ra (env,EXCP0D_GPF ,GETPC ()); } fpus = (env->fpus & ~0x3800 ) | (env->fpstt &0x7 ) <<11 ;
@@ -1117,33 +1131,33 @@ void helper_fxsave(CPUX86State *env, target_ulong ptr, int data64)for (i =0 ; i <8 ; i++) { fptag |= (env->fptags[i] << i); } -cpu_stw_data (env, ptr, env->fpuc); -cpu_stw_data (env, ptr +2 , fpus); -cpu_stw_data (env, ptr +4 , fptag ^0xff ); +cpu_stw_data_ra (env, ptr, env->fpuc,GETPC ()); +cpu_stw_data_ra (env, ptr +2 , fpus,GETPC ()); +cpu_stw_data_ra (env, ptr +4 , fptag ^0xff ,GETPC ());#ifdef TARGET_X86_64 if (data64) { -cpu_stq_data (env, ptr +0x08 ,0 );/* rip */ -cpu_stq_data (env, ptr +0x10 ,0 );/* rdp */ +cpu_stq_data_ra (env, ptr +0x08 ,0 ,GETPC ());/* rip */ +cpu_stq_data_ra (env, ptr +0x10 ,0 ,GETPC ());/* rdp */ } else#endif { -cpu_stl_data (env, ptr +0x08 ,0 );/* eip */ -cpu_stl_data (env, ptr +0x0c ,0 );/* sel */ -cpu_stl_data (env, ptr +0x10 ,0 );/* dp */ -cpu_stl_data (env, ptr +0x14 ,0 );/* sel */ +cpu_stl_data_ra (env, ptr +0x08 ,0 ,GETPC ());/* eip */ +cpu_stl_data_ra (env, ptr +0x0c ,0 ,GETPC ());/* sel */ +cpu_stl_data_ra (env, ptr +0x10 ,0 ,GETPC ());/* dp */ +cpu_stl_data_ra (env, ptr +0x14 ,0 ,GETPC ());/* sel */ } addr = ptr +0x20 ;for (i =0 ; i <8 ; i++) { tmp =ST (i); -helper_fstt (env, tmp, addr); +helper_fstt (env, tmp, addr,GETPC ()); addr +=16 ; }if (env->cr[4 ] &CR4_OSFXSR_MASK ) {/* XXX: finish it */ -cpu_stl_data (env, ptr +0x18 , env->mxcsr);/* mxcsr */ -cpu_stl_data (env, ptr +0x1c ,0x0000ffff );/* mxcsr_mask */ +cpu_stl_data_ra (env, ptr +0x18 , env->mxcsr,GETPC ());/* mxcsr */ +cpu_stl_data_ra (env, ptr +0x1c ,0x0000ffff ,GETPC ());/* mxcsr_mask */ if (env->hflags &HF_CS64_MASK ) { nb_xmm_regs =16 ; }else {
@@ -1155,8 +1169,8 @@ void helper_fxsave(CPUX86State *env, target_ulong ptr, int data64) || (env->hflags & HF_CPL_MASK) || !(env->hflags & HF_LMA_MASK)) {for (i =0 ; i < nb_xmm_regs; i++) { -cpu_stq_data (env, addr, env->xmm_regs[i].XMM_Q (0 )); -cpu_stq_data (env, addr +8 , env->xmm_regs[i].XMM_Q (1 )); +cpu_stq_data_ra (env, addr, env->xmm_regs[i].XMM_Q (0 ),GETPC ()); +cpu_stq_data_ra (env, addr +8 , env->xmm_regs[i].XMM_Q (1 ),GETPC ()); addr +=16 ; } }
@@ -1171,12 +1185,12 @@ void helper_fxrstor(CPUX86State *env, target_ulong ptr, int data64)/* The operand must be 16 byte aligned */ if (ptr &0xf ) { -raise_exception (env,EXCP0D_GPF ); +raise_exception_ra (env,EXCP0D_GPF ,GETPC ()); } -cpu_set_fpuc (env,cpu_lduw_data (env, ptr)); - fpus =cpu_lduw_data (env, ptr +2 ); - fptag =cpu_lduw_data (env, ptr +4 ); +cpu_set_fpuc (env,cpu_lduw_data_ra (env, ptr,GETPC ())); + fpus =cpu_lduw_data_ra (env, ptr +2 ,GETPC ()); + fptag =cpu_lduw_data_ra (env, ptr +4 ,GETPC ()); env->fpstt = (fpus >>11 ) &7 ; env->fpus = fpus & ~0x3800 ; fptag ^=0xff ;
@@ -1186,14 +1200,14 @@ void helper_fxrstor(CPUX86State *env, target_ulong ptr, int data64) addr = ptr +0x20 ;for (i =0 ; i <8 ; i++) { - tmp =helper_fldt (env, addr); + tmp =helper_fldt (env, addr,GETPC ());ST (i) = tmp; addr +=16 ; }if (env->cr[4 ] &CR4_OSFXSR_MASK ) {/* XXX: finish it */ -cpu_set_mxcsr (env,cpu_ldl_data (env, ptr +0x18 )); +cpu_set_mxcsr (env,cpu_ldl_data_ra (env, ptr +0x18 ,GETPC ()));/* cpu_ldl_data(env, ptr + 0x1c); */ if (env->hflags &HF_CS64_MASK ) { nb_xmm_regs =16 ;
@@ -1206,8 +1220,8 @@ void helper_fxrstor(CPUX86State *env, target_ulong ptr, int data64) || (env->hflags & HF_CPL_MASK) || !(env->hflags & HF_LMA_MASK)) {for (i =0 ; i < nb_xmm_regs; i++) { - env->xmm_regs[i].XMM_Q (0 ) =cpu_ldq_data (env, addr); - env->xmm_regs[i].XMM_Q (1 ) =cpu_ldq_data (env, addr +8 ); + env->xmm_regs[i].XMM_Q (0 ) =cpu_ldq_data_ra (env, addr,GETPC ()); + env->xmm_regs[i].XMM_Q (1 ) =cpu_ldq_data_ra (env, addr +8 ,GETPC ()); addr +=16 ; } }
Re: [Qemu-devel] [PATCH v5 05/11] target-i386: exception handling for FPU instructions
target-i386/fpu_helper.c void helper_fxsave(CPUX86State *env, target_ulong ptr, int data64) · line 1136
Quoted 10 lines · Pavel Dovgalyuk
target-i386/fpu_helper.c +3
-3@@ -1117,33 +1131,33 @@ void helper_fxsave(CPUX86State *env, target_ulong ptr, int data64)for (i =0 ; i <8 ; i++) { fptag |= (env->fptags[i] << i); } -cpu_stw_data (env, ptr, env->fpuc); -cpu_stw_data (env, ptr +2 , fpus); -cpu_stw_data (env, ptr +4 , fptag ^0xff ); +cpu_stw_data_ra (env, ptr, env->fpuc,GETPC ()); +cpu_stw_data_ra (env, ptr +2 , fpus,GETPC ()); +cpu_stw_data_ra (env, ptr +4 , fptag ^0xff ,GETPC ());
helper_fxsave and helper_fxrstor ought to have do_* versions just like you did for fstenv/fldenv. (I'm working on a patch set that adds xsave/xrstor support and I'll need to re-use these functions.)
r~
Re: [Qemu-devel] [PATCH v5 05/11] target-i386: exception handling for FPU instructions
Quoted 16 lines
From: Richard Henderson [mailto:[email protected]] On Behalf Of Richard Henderson
target-i386/fpu_helper.c void helper_fxsave(CPUX86State *env, target_ulong ptr, int data64) · line 1136
Quoted 10 lines · Pavel Dovgalyuk
target-i386/fpu_helper.c +3
-3@@ -1117,33 +1131,33 @@ void helper_fxsave(CPUX86State *env, target_ulong ptr, int data64)for (i =0 ; i <8 ; i++) { fptag |= (env->fptags[i] << i); } -cpu_stw_data (env, ptr, env->fpuc); -cpu_stw_data (env, ptr +2 , fpus); -cpu_stw_data (env, ptr +4 , fptag ^0xff ); +cpu_stw_data_ra (env, ptr, env->fpuc,GETPC ()); +cpu_stw_data_ra (env, ptr +2 , fpus,GETPC ()); +cpu_stw_data_ra (env, ptr +4 , fptag ^0xff ,GETPC ());
helper_fxsaveandhelper_fxrstorought to have do_* versions just like you did for fstenv/fldenv. (I'm working on a patch set that adds xsave/xrstor support and I'll need to re-use these functions.)
Why do_* functions should be in this series?
These changes will look orphaned.
Pavel Dovgalyuk
A message that is not in the archive (sent off-list or not yet received): 559a77d3.4e58980a.7a073.ffff997eSMTPIN_ADDED_BROKEN@mx.google.com
Re: [Qemu-devel] [PATCH v5 05/11] target-i386: exception handling for FPU instructions
Quoted 17 lines · Pavel Dovgaluk
Quoted 16 lines
From: Richard Henderson [mailto:[email protected]] On Behalf Of Richard Henderson
target-i386/fpu_helper.c void helper_fxsave(CPUX86State *env, target_ulong ptr, int data64) · line 1136
Quoted 10 lines · Pavel Dovgalyuk
target-i386/fpu_helper.c +3
-3@@ -1117,33 +1131,33 @@ void helper_fxsave(CPUX86State *env, target_ulong ptr, int data64)for (i =0 ; i <8 ; i++) { fptag |= (env->fptags[i] << i); } -cpu_stw_data (env, ptr, env->fpuc); -cpu_stw_data (env, ptr +2 , fpus); -cpu_stw_data (env, ptr +4 , fptag ^0xff ); +cpu_stw_data_ra (env, ptr, env->fpuc,GETPC ()); +cpu_stw_data_ra (env, ptr +2 , fpus,GETPC ()); +cpu_stw_data_ra (env, ptr +4 , fptag ^0xff ,GETPC ());
helper_fxsaveandhelper_fxrstorought to have do_* versions just like you did for fstenv/fldenv. (I'm working on a patch set that adds xsave/xrstor support and I'll need to re-use these functions.)
Quoted 2 lines
Why do_* functions should be in this series?
These changes will look orphaned.
No they won't. They'll be called by helper_fxsave.
r~
Re: [Qemu-devel] [PATCH v5 05/11] target-i386: exception handling for FPU instructions
In reply to Pavel DovgalyukQuoted 323 lines · Pavel Dovgalyuk
This patch fixes exception handling for FPU instructions.
Signed-off-by Pavel Dovgalyuk <[email protected]>--- target-i386/fpu_helper.c | 146 +++++++++++++++++++++++++--------------------- 1 files changed, 80 insertions(+), 66 deletions(-)target-i386/fpu_helper.c +76
-63@@ -68,22 +68,24 @@ static inline void fpop(CPUX86State *env) env->fpstt = (env->fpstt +1 ) &7 ; } -static inline floatx80 helper_fldt (CPUX86State *env,target_ulong ptr) +static inline floatx80 helper_fldt (CPUX86State *env,target_ulong ptr, +uintptr_t retaddr) {CPU_LDoubleU temp; - temp.l.lower =cpu_ldq_data (env, ptr); - temp.l.upper =cpu_lduw_data (env, ptr +8 ); + temp.l.lower =cpu_ldq_data_ra (env, ptr, retaddr); + temp.l.upper =cpu_lduw_data_ra (env, ptr +8 , retaddr);return temp.d; } -static inline void helper_fstt (CPUX86State *env,floatx80 f,target_ulong ptr) +static inline void helper_fstt (CPUX86State *env,floatx80 f,target_ulong ptr, +uintptr_t retaddr)Status {CPU_LDoubleU temp; temp.d = f; -cpu_stq_data (env, ptr, temp.l.lower); -cpu_stw_data (env, ptr +8 , temp.l.upper); +cpu_stq_data_ra (env, ptr, temp.l.lower, retaddr); +cpu_stw_data_ra (env, ptr +8 , temp.l.upper, retaddr); }/* x87 FPU helpers */ @@ -126,10 +128,10 @@ static inline floatx80 helper_fdiv(CPUX86State *env, floatx80 a, floatx80 b)return floatx80_div (a, b, &env->fp_status); } -static void fpu_raise_exception (CPUX86State *env) +static void fpu_raise_exception (CPUX86State *env,uintptr_t retaddr) {if (env->cr[0 ] &CR0_NE_MASK ) { -raise_exception (env,EXCP10_COPR ); +raise_exception_ra (env,EXCP10_COPR , retaddr); }#if !defined(CONFIG_USER_ONLY ) else {@@ -314,14 +316,14 @@ void helper_fldt_ST0(CPUX86State *env, target_ulong ptr)int new_fpstt; new_fpstt = (env->fpstt -1 ) &7 ; - env->fpregs[new_fpstt].d =helper_fldt (env, ptr); + env->fpregs[new_fpstt].d =helper_fldt (env, ptr,GETPC ()); env->fpstt = new_fpstt; env->fptags[new_fpstt] =0 ;/* validate stack entry */ }void helper_fstt_ST0 (CPUX86State *env,target_ulong ptr) { -helper_fstt (env,ST0 , ptr); +helper_fstt (env,ST0 , ptr,GETPC ()); }void helper_fpush (CPUX86State *env)@@ -604,7 +606,7 @@ void helper_fclex(CPUX86State *env)void helper_fwait (CPUX86State *env) {if (env->fpus &FPUS_SE ) { -fpu_raise_exception (env); +fpu_raise_exception (env,GETPC ()); } }@@ -634,11 +636,11 @@ void helper_fbld_ST0(CPUX86State *env, target_ulong ptr) val =0 ;for (i =8 ; i >=0 ; i--) { - v =cpu_ldub_data (env, ptr + i); + v =cpu_ldub_data_ra (env, ptr + i,GETPC ()); val = (val *100 ) + ((v >>4 ) *10 ) + (v &0xf ); } tmp =int64_to_floatx80 (val, &env->fp_status); -if (cpu_ldub_data (env, ptr +9 ) &0x80 ) { +if (cpu_ldub_data_ra (env, ptr +9 ,GETPC ()) &0x80 ) { tmp =floatx80_chs (tmp); }fpush (env);@@ -655,10 +657,10 @@ void helper_fbst_ST0(CPUX86State *env, target_ulong ptr) mem_ref = ptr; mem_end = mem_ref +9 ;if (val <0 ) { -cpu_stb_data (env, mem_end,0x80 ); +cpu_stb_data_ra (env, mem_end,0x80 ,GETPC ()); val = -val; }else { -cpu_stb_data (env, mem_end,0x00 ); +cpu_stb_data_ra (env, mem_end,0x00 ,GETPC ()); }while (mem_ref < mem_end) {if (val ==0 ) {@@ -667,10 +669,10 @@ void helper_fbst_ST0(CPUX86State *env, target_ulong ptr) v = val %100 ; val = val /100 ; v = ((v /10 ) <<4 ) | (v %10 ); -cpu_stb_data (env, mem_ref++, v); +cpu_stb_data_ra (env, mem_ref++, v,GETPC ()); }while (mem_ref < mem_end) { -cpu_stb_data (env, mem_ref++,0 ); +cpu_stb_data_ra (env, mem_ref++,0 ,GETPC ()); } }@@ -978,7 +980,8 @@ void helper_fxam_ST0(CPUX86State *env) } } -void helper_fstenv (CPUX86State *env,target_ulong ptr,int data32) +static void do_fstenv (CPUX86State *env,target_ulong ptr,int data32, +uintptr_t retaddr) {int fpus, fptag, exp, i;uint64_t mant;@@ -1006,37 +1009,43 @@ void helper_fstenv(CPUX86State *env, target_ulong ptr, int data32) }if (data32) {/* 32 bit */ -cpu_stl_data (env, ptr, env->fpuc); -cpu_stl_data (env, ptr +4 , fpus); -cpu_stl_data (env, ptr +8 , fptag); -cpu_stl_data (env, ptr +12 ,0 );/* fpip */ -cpu_stl_data (env, ptr +16 ,0 );/* fpcs */ -cpu_stl_data (env, ptr +20 ,0 );/* fpoo */ -cpu_stl_data (env, ptr +24 ,0 );/* fpos */ +cpu_stl_data_ra (env, ptr, env->fpuc, retaddr); +cpu_stl_data_ra (env, ptr +4 , fpus, retaddr); +cpu_stl_data_ra (env, ptr +8 , fptag, retaddr); +cpu_stl_data_ra (env, ptr +12 ,0 , retaddr);/* fpip */ +cpu_stl_data_ra (env, ptr +16 ,0 , retaddr);/* fpcs */ +cpu_stl_data_ra (env, ptr +20 ,0 , retaddr);/* fpoo */ +cpu_stl_data_ra (env, ptr +24 ,0 , retaddr);/* fpos */ }else {/* 16 bit */ -cpu_stw_data (env, ptr, env->fpuc); -cpu_stw_data (env, ptr +2 , fpus); -cpu_stw_data (env, ptr +4 , fptag); -cpu_stw_data (env, ptr +6 ,0 ); -cpu_stw_data (env, ptr +8 ,0 ); -cpu_stw_data (env, ptr +10 ,0 ); -cpu_stw_data (env, ptr +12 ,0 ); +cpu_stw_data_ra (env, ptr, env->fpuc, retaddr); +cpu_stw_data_ra (env, ptr +2 , fpus, retaddr); +cpu_stw_data_ra (env, ptr +4 , fptag, retaddr); +cpu_stw_data_ra (env, ptr +6 ,0 , retaddr); +cpu_stw_data_ra (env, ptr +8 ,0 , retaddr); +cpu_stw_data_ra (env, ptr +10 ,0 , retaddr); +cpu_stw_data_ra (env, ptr +12 ,0 , retaddr); } } -void helper_fldenv (CPUX86State *env,target_ulong ptr,int data32) +void helper_fstenv (CPUX86State *env,target_ulong ptr,int data32) +{ +do_fstenv (env, ptr, data32,GETPC ()); +} + +static void do_fldenv (CPUX86State *env,target_ulong ptr,int data32, +uintptr_t retaddr) {int i, fpus, fptag;if (data32) { -cpu_set_fpuc (env,cpu_lduw_data (env, ptr)); - fpus =cpu_lduw_data (env, ptr +4 ); - fptag =cpu_lduw_data (env, ptr +8 ); +cpu_set_fpuc (env,cpu_lduw_data_ra (env, ptr, retaddr)); + fpus =cpu_lduw_data_ra (env, ptr +4 , retaddr); + fptag =cpu_lduw_data_ra (env, ptr +8 , retaddr); }else { -cpu_set_fpuc (env,cpu_lduw_data (env, ptr)); - fpus =cpu_lduw_data (env, ptr +2 ); - fptag =cpu_lduw_data (env, ptr +4 ); +cpu_set_fpuc (env,cpu_lduw_data_ra (env, ptr, retaddr)); + fpus =cpu_lduw_data_ra (env, ptr +2 , retaddr); + fptag =cpu_lduw_data_ra (env, ptr +4 , retaddr); } env->fpstt = (fpus >>11 ) &7 ; env->fpus = fpus & ~0x3800 ;@@ -1046,17 +1055,22 @@ void helper_fldenv(CPUX86State *env, target_ulong ptr, int data32) } } +void helper_fldenv (CPUX86State *env,target_ulong ptr,int data32) +{ +do_fldenv (env, ptr, data32,GETPC ()); +} +void helper_fsave (CPUX86State *env,target_ulong ptr,int data32) {floatx80 tmp;int i; -helper_fstenv (env, ptr, data32); +do_fstenv (env, ptr, data32,GETPC ()); ptr += (14 << data32);for (i =0 ; i <8 ; i++) { tmp =ST (i); -helper_fstt (env, tmp, ptr); +helper_fstt (env, tmp, ptr,GETPC ()); ptr +=10 ; }@@ -1079,11 +1093,11 @@ void helper_frstor(CPUX86State *env, target_ulong ptr, int data32)floatx80 tmp;int i; -helper_fldenv (env, ptr, data32); +do_fldenv (env, ptr, data32,GETPC ()); ptr += (14 << data32);for (i =0 ; i <8 ; i++) { - tmp =helper_fldt (env, ptr); + tmp =helper_fldt (env, ptr,GETPC ());ST (i) = tmp; ptr +=10 ; }@@ -1109,7 +1123,7 @@ void helper_fxsave(CPUX86State *env, target_ulong ptr, int data64)/* The operand must be 16 byte aligned */ if (ptr &0xf ) { -raise_exception (env,EXCP0D_GPF ); +raise_exception_ra (env,EXCP0D_GPF ,GETPC ()); } fpus = (env->fpus & ~0x3800 ) | (env->fpstt &0x7 ) <<11 ;@@ -1117,33 +1131,33 @@ void helper_fxsave(CPUX86State *env, target_ulong ptr, int data64)for (i =0 ; i <8 ; i++) { fptag |= (env->fptags[i] << i); } -cpu_stw_data (env, ptr, env->fpuc); -cpu_stw_data (env, ptr +2 , fpus); -cpu_stw_data (env, ptr +4 , fptag ^0xff ); +cpu_stw_data_ra (env, ptr, env->fpuc,GETPC ()); +cpu_stw_data_ra (env, ptr +2 , fpus,GETPC ()); +cpu_stw_data_ra (env, ptr +4 , fptag ^0xff ,GETPC ());#ifdef TARGET_X86_64 if (data64) { -cpu_stq_data (env, ptr +0x08 ,0 );/* rip */ -cpu_stq_data (env, ptr +0x10 ,0 );/* rdp */ +cpu_stq_data_ra (env, ptr +0x08 ,0 ,GETPC ());/* rip */ +cpu_stq_data_ra (env, ptr +0x10 ,0 ,GETPC ());/* rdp */ } else#endif { -cpu_stl_data (env, ptr +0x08 ,0 );/* eip */ -cpu_stl_data (env, ptr +0x0c ,0 );/* sel */ -cpu_stl_data (env, ptr +0x10 ,0 );/* dp */ -cpu_stl_data (env, ptr +0x14 ,0 );/* sel */ +cpu_stl_data_ra (env, ptr +0x08 ,0 ,GETPC ());/* eip */ +cpu_stl_data_ra (env, ptr +0x0c ,0 ,GETPC ());/* sel */ +cpu_stl_data_ra (env, ptr +0x10 ,0 ,GETPC ());/* dp */ +cpu_stl_data_ra (env, ptr +0x14 ,0 ,GETPC ());/* sel */ } addr = ptr +0x20 ;for (i =0 ; i <8 ; i++) { tmp =ST (i); -helper_fstt (env, tmp, addr); +helper_fstt (env, tmp, addr,GETPC ()); addr +=16 ; }if (env->cr[4 ] &CR4_OSFXSR_MASK ) {/* XXX: finish it */ -cpu_stl_data (env, ptr +0x18 , env->mxcsr);/* mxcsr */ -cpu_stl_data (env, ptr +0x1c ,0x0000ffff );/* mxcsr_mask */ +cpu_stl_data_ra (env, ptr +0x18 , env->mxcsr,GETPC ());/* mxcsr */ +cpu_stl_data_ra (env, ptr +0x1c ,0x0000ffff ,GETPC ());/* mxcsr_mask */ if (env->hflags &HF_CS64_MASK ) { nb_xmm_regs =16 ; }else {@@ -1155,8 +1169,8 @@ void helper_fxsave(CPUX86State *env, target_ulong ptr, int data64) || (env->hflags & HF_CPL_MASK) || !(env->hflags & HF_LMA_MASK)) {for (i =0 ; i < nb_xmm_regs; i++) { -cpu_stq_data (env, addr, env->xmm_regs[i].XMM_Q (0 )); -cpu_stq_data (env, addr +8 , env->xmm_regs[i].XMM_Q (1 )); +cpu_stq_data_ra (env, addr, env->xmm_regs[i].XMM_Q (0 ),GETPC ()); +cpu_stq_data_ra (env, addr +8 , env->xmm_regs[i].XMM_Q (1 ),GETPC ()); addr +=16 ; } }@@ -1171,12 +1185,12 @@ void helper_fxrstor(CPUX86State *env, target_ulong ptr, int data64)/* The operand must be 16 byte aligned */ if (ptr &0xf ) { -raise_exception (env,EXCP0D_GPF ); +raise_exception_ra (env,EXCP0D_GPF ,GETPC ()); } -cpu_set_fpuc (env,cpu_lduw_data (env, ptr)); - fpus =cpu_lduw_data (env, ptr +2 ); - fptag =cpu_lduw_data (env, ptr +4 ); +cpu_set_fpuc (env,cpu_lduw_data_ra (env, ptr,GETPC ())); + fpus =cpu_lduw_data_ra (env, ptr +2 ,GETPC ()); + fptag =cpu_lduw_data_ra (env, ptr +4 ,GETPC ()); env->fpstt = (fpus >>11 ) &7 ; env->fpus = fpus & ~0x3800 ; fptag ^=0xff ;@@ -1186,14 +1200,14 @@ void helper_fxrstor(CPUX86State *env, target_ulong ptr, int data64) addr = ptr +0x20 ;for (i =0 ; i <8 ; i++) { - tmp =helper_fldt (env, addr);
target-i386/fpu_helper.c void helper_fxrstor(CPUX86State *env, target_ulong ptr, int data64) · line 1211
Quoted 10 lines
target-i386/fpu_helper.c +2
-1+ tmp =helper_fldt (env, addr,GETPC ());ST (i) = tmp; addr +=16 ; }if (env->cr[4 ] &CR4_OSFXSR_MASK ) {/* XXX: finish it */ -cpu_set_mxcsr (env,cpu_ldl_data (env, ptr +0x18 )); +cpu_set_mxcsr (env,cpu_ldl_data_ra (env, ptr +0x18 ,GETPC ()));/* cpu_ldl_data(env, ptr + 0x1c); */
Please also convert this one, even if commented out. That said:
Reviewed-by Aurelien Jarno <[email protected]>
Aurelien
Signature · 2 lines
Aurelien Jarno GPG: 4096R/1DDD8C9B [email protected] http://www.aurel32.net
PATCH v5 6/11 target-i386: exception handling for div instructions
In reply to Pavel DovgalyukThis patch fixes exception handling for div instructions.
Signed-off-by Pavel Dovgalyuk <[email protected]>
--- target-i386/int_helper.c | 32 ++++++++++++++++---------------- 1 files changed, 16 insertions(+), 16 deletions(-)
target-i386/int_helper.c +16 -16
@@ -48,11 +48,11 @@ void helper_divb_AL(CPUX86State *env, target_ulong t0) num = (env->regs[R_EAX ] &0xffff ); den = (t0 &0xff );if (den ==0 ) { -raise_exception (env,EXCP00_DIVZ ); +raise_exception_ra (env,EXCP00_DIVZ ,GETPC ()); } q = (num / den);if (q >0xff ) { -raise_exception (env,EXCP00_DIVZ ); +raise_exception_ra (env,EXCP00_DIVZ ,GETPC ()); } q &=0xff ; r = (num % den) &0xff ;
@@ -66,11 +66,11 @@ void helper_idivb_AL(CPUX86State *env, target_ulong t0) num = (int16_t )env->regs[R_EAX ]; den = (int8_t )t0;if (den ==0 ) { -raise_exception (env,EXCP00_DIVZ ); +raise_exception_ra (env,EXCP00_DIVZ ,GETPC ()); } q = (num / den);if (q != (int8_t )q) { -raise_exception (env,EXCP00_DIVZ ); +raise_exception_ra (env,EXCP00_DIVZ ,GETPC ()); } q &=0xff ; r = (num % den) &0xff ;
@@ -84,11 +84,11 @@ void helper_divw_AX(CPUX86State *env, target_ulong t0) num = (env->regs[R_EAX ] &0xffff ) | ((env->regs[R_EDX ] &0xffff ) <<16 ); den = (t0 &0xffff );if (den ==0 ) { -raise_exception (env,EXCP00_DIVZ ); +raise_exception_ra (env,EXCP00_DIVZ ,GETPC ()); } q = (num / den);if (q >0xffff ) { -raise_exception (env,EXCP00_DIVZ ); +raise_exception_ra (env,EXCP00_DIVZ ,GETPC ()); } q &=0xffff ; r = (num % den) &0xffff ;
@@ -103,11 +103,11 @@ void helper_idivw_AX(CPUX86State *env, target_ulong t0) num = (env->regs[R_EAX ] &0xffff ) | ((env->regs[R_EDX ] &0xffff ) <<16 ); den = (int16_t )t0;if (den ==0 ) { -raise_exception (env,EXCP00_DIVZ ); +raise_exception_ra (env,EXCP00_DIVZ ,GETPC ()); } q = (num / den);if (q != (int16_t )q) { -raise_exception (env,EXCP00_DIVZ ); +raise_exception_ra (env,EXCP00_DIVZ ,GETPC ()); } q &=0xffff ; r = (num % den) &0xffff ;
@@ -123,12 +123,12 @@ void helper_divl_EAX(CPUX86State *env, target_ulong t0) num = ((uint32_t )env->regs[R_EAX ]) | ((uint64_t )((uint32_t )env->regs[R_EDX ]) <<32 ); den = t0;if (den ==0 ) { -raise_exception (env,EXCP00_DIVZ ); +raise_exception_ra (env,EXCP00_DIVZ ,GETPC ()); } q = (num / den); r = (num % den);if (q >0xffffffff ) { -raise_exception (env,EXCP00_DIVZ ); +raise_exception_ra (env,EXCP00_DIVZ ,GETPC ()); } env->regs[R_EAX ] = (uint32_t )q; env->regs[R_EDX ] = (uint32_t )r;
@@ -142,12 +142,12 @@ void helper_idivl_EAX(CPUX86State *env, target_ulong t0) num = ((uint32_t )env->regs[R_EAX ]) | ((uint64_t )((uint32_t )env->regs[R_EDX ]) <<32 ); den = t0;if (den ==0 ) { -raise_exception (env,EXCP00_DIVZ ); +raise_exception_ra (env,EXCP00_DIVZ ,GETPC ()); } q = (num / den); r = (num % den);if (q != (int32_t )q) { -raise_exception (env,EXCP00_DIVZ ); +raise_exception_ra (env,EXCP00_DIVZ ,GETPC ()); } env->regs[R_EAX ] = (uint32_t )q; env->regs[R_EDX ] = (uint32_t )r;
@@ -379,12 +379,12 @@ void helper_divq_EAX(CPUX86State *env, target_ulong t0)uint64_t r0, r1;if (t0 ==0 ) { -raise_exception (env,EXCP00_DIVZ ); +raise_exception_ra (env,EXCP00_DIVZ ,GETPC ()); } r0 = env->regs[R_EAX ]; r1 = env->regs[R_EDX ];if (div64 (&r0, &r1, t0)) { -raise_exception (env,EXCP00_DIVZ ); +raise_exception_ra (env,EXCP00_DIVZ ,GETPC ()); } env->regs[R_EAX ] = r0; env->regs[R_EDX ] = r1;
@@ -395,12 +395,12 @@ void helper_idivq_EAX(CPUX86State *env, target_ulong t0)uint64_t r0, r1;if (t0 ==0 ) { -raise_exception (env,EXCP00_DIVZ ); +raise_exception_ra (env,EXCP00_DIVZ ,GETPC ()); } r0 = env->regs[R_EAX ]; r1 = env->regs[R_EDX ];if (idiv64 (&r0, &r1, t0)) { -raise_exception (env,EXCP00_DIVZ ); +raise_exception_ra (env,EXCP00_DIVZ ,GETPC ()); } env->regs[R_EAX ] = r0; env->regs[R_EDX ] = r1;
Re: [Qemu-devel] [PATCH v5 06/11] target-i386: exception handling for div instructions
Quoted 6 lines · Pavel Dovgalyuk
This patch fixes exception handling for div instructions.
Signed-off-by Pavel Dovgalyuk<[email protected]>--- target-i386/int_helper.c | 32 ++++++++++++++++---------------- 1 files changed, 16 insertions(+), 16 deletions(-)
Reviewed-by Richard Henderson <[email protected]>
r~
Re: [Qemu-devel] [PATCH v5 06/11] target-i386: exception handling for div instructions
In reply to Pavel DovgalyukQuoted 7 lines · Pavel Dovgalyuk
This patch fixes exception handling for div instructions.
Signed-off-by Pavel Dovgalyuk <[email protected]>--- target-i386/int_helper.c | 32 ++++++++++++++++---------------- 1 files changed, 16 insertions(+), 16 deletions(-)
Reviewed-by Aurelien Jarno <[email protected]>
Signature · 2 lines
Aurelien Jarno GPG: 4096R/1DDD8C9B [email protected] http://www.aurel32.net
PATCH v5 7/11 target-i386: exception handling for memory helpers
In reply to Pavel DovgalyukThis patch fixes exception handling for memory helpers.
Signed-off-by Pavel Dovgalyuk <[email protected]>
--- target-i386/mem_helper.c | 39 ++++++++++++++++++--------------------- 1 files changed, 18 insertions(+), 21 deletions(-)
target-i386/mem_helper.c +18 -21
@@ -41,13 +41,14 @@ void helper_cmpxchg8b(CPUX86State *env, target_ulong a0)int eflags; eflags =cpu_cc_compute_all (env,CC_OP ); - d =cpu_ldq_data (env, a0); + d =cpu_ldq_data_ra (env, a0,GETPC ());if (d == (((uint64_t )env->regs[R_EDX ] <<32 ) | (uint32_t )env->regs[R_EAX ])) { -cpu_stq_data (env, a0, ((uint64_t )env->regs[R_ECX ] <<32 ) | (uint32_t )env->regs[R_EBX ]); +cpu_stq_data_ra (env, a0, ((uint64_t )env->regs[R_ECX ] <<32 ) + | (uint32_t )env->regs[R_EBX ],GETPC ()); eflags |=CC_Z ; }else {/* always do the store */ -cpu_stq_data (env, a0, d); +cpu_stq_data_ra (env, a0, d,GETPC ()); env->regs[R_EDX ] = (uint32_t )(d >>32 ); env->regs[R_EAX ] = (uint32_t )d; eflags &= ~CC_Z ;
@@ -62,19 +63,19 @@ void helper_cmpxchg16b(CPUX86State *env, target_ulong a0)int eflags;if ((a0 &0xf ) !=0 ) { -raise_exception (env,EXCP0D_GPF ); +raise_exception_ra (env,EXCP0D_GPF ,GETPC ()); } eflags =cpu_cc_compute_all (env,CC_OP ); - d0 =cpu_ldq_data (env, a0); - d1 =cpu_ldq_data (env, a0 +8 ); + d0 =cpu_ldq_data_ra (env, a0,GETPC ()); + d1 =cpu_ldq_data_ra (env, a0 +8 ,GETPC ());if (d0 == env->regs[R_EAX ] && d1 == env->regs[R_EDX ]) { -cpu_stq_data (env, a0, env->regs[R_EBX ]); -cpu_stq_data (env, a0 +8 , env->regs[R_ECX ]); +cpu_stq_data_ra (env, a0, env->regs[R_EBX ],GETPC ()); +cpu_stq_data_ra (env, a0 +8 , env->regs[R_ECX ],GETPC ()); eflags |=CC_Z ; }else {/* always do the store */ -cpu_stq_data (env, a0, d0); -cpu_stq_data (env, a0 +8 , d1); +cpu_stq_data_ra (env, a0, d0,GETPC ()); +cpu_stq_data_ra (env, a0 +8 , d1,GETPC ()); env->regs[R_EDX ] = d1; env->regs[R_EAX ] = d0; eflags &= ~CC_Z ;
@@ -87,11 +88,11 @@ void helper_boundw(CPUX86State *env, target_ulong a0, int v) {int low, high; - low =cpu_ldsw_data (env, a0); - high =cpu_ldsw_data (env, a0 +2 ); + low =cpu_ldsw_data_ra (env, a0,GETPC ()); + high =cpu_ldsw_data_ra (env, a0 +2 ,GETPC ()); v = (int16_t )v;if (v < low || v > high) { -raise_exception (env,EXCP05_BOUND ); +raise_exception_ra (env,EXCP05_BOUND ,GETPC ()); } }
@@ -99,10 +100,10 @@ void helper_boundl(CPUX86State *env, target_ulong a0, int v) {int low, high; - low =cpu_ldl_data (env, a0); - high =cpu_ldl_data (env, a0 +4 ); + low =cpu_ldl_data_ra (env, a0,GETPC ()); + high =cpu_ldl_data_ra (env, a0 +4 ,GETPC ());if (v < low || v > high) { -raise_exception (env,EXCP05_BOUND ); +raise_exception_ra (env,EXCP05_BOUND ,GETPC ()); } }
@@ -122,11 +123,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,X86CPU *cpu =X86_CPU (cs);CPUX86State *env = &cpu->env; -if (retaddr) { -/* now we have a real cpu fault */ -cpu_restore_state (cs, retaddr); - } - raise_exception_err(env, cs->exception_index, env->error_code); + raise_exception_err_ra(env, cs->exception_index, env->error_code, retaddr); } }#endif
Re: [Qemu-devel] [PATCH v5 07/11] target-i386: exception handling for memory helpers
Quoted 6 lines · Pavel Dovgalyuk
This patch fixes exception handling for memory helpers.
Signed-off-by Pavel Dovgalyuk<[email protected]>--- target-i386/mem_helper.c | 39 ++++++++++++++++++--------------------- 1 files changed, 18 insertions(+), 21 deletions(-)
Reviewed-by Richard Henderson <[email protected]>
r~
Re: [Qemu-devel] [PATCH v5 07/11] target-i386: exception handling for memory helpers
In reply to Pavel DovgalyukQuoted 6 lines · Pavel Dovgalyuk
This patch fixes exception handling for memory helpers.
Signed-off-by Pavel Dovgalyuk <[email protected]>--- target-i386/mem_helper.c | 39 ++++++++++++++++++--------------------- 1 files changed, 18 insertions(+), 21 deletions(-)
Reviewed-by Aurelien Jarno <[email protected]>
Signature · 2 lines
Aurelien Jarno GPG: 4096R/1DDD8C9B [email protected] http://www.aurel32.net
PATCH v5 8/11 target-i386: exception handling for seg_helper functions
In reply to Pavel DovgalyukThis patch fixes exception handling for seg_helper functions.
Signed-off-by Pavel Dovgalyuk <[email protected]>
--- target-i386/seg_helper.c | 646 +++++++++++++++++++++++----------------------- 1 files changed, 330 insertions(+), 316 deletions(-)
target-i386/seg_helper.c +330 -316
@@ -68,7 +68,8 @@/* return non zero if error */ static inline int load_segment (CPUX86State *env,uint32_t *e1_ptr, -uint32_t *e2_ptr,int selector) +uint32_t *e2_ptr,int selector, +uintptr_t retaddr) {SegmentCache *dt;int index;
@@ -84,8 +85,8 @@ static inline int load_segment(CPUX86State *env, uint32_t *e1_ptr,return -1 ; } ptr = dt->base + index; - *e1_ptr =cpu_ldl_kernel (env, ptr); - *e2_ptr =cpu_ldl_kernel (env, ptr +4 ); + *e1_ptr =cpu_ldl_kernel_ra (env, ptr, retaddr); + *e2_ptr =cpu_ldl_kernel_ra (env, ptr +4 , retaddr);return 0 ; }
@@ -124,7 +125,8 @@ static inline void load_seg_vm(CPUX86State *env, int seg, int selector) }static inline void get_ss_esp_from_tss (CPUX86State *env,uint32_t *ss_ptr, -uint32_t *esp_ptr,int dpl) +uint32_t *esp_ptr,int dpl, +uintptr_t retaddr) {X86CPU *cpu =x86_env_get_cpu (env);int type, index, shift;
@@ -153,60 +155,61 @@ static inline void get_ss_esp_from_tss(CPUX86State *env, uint32_t *ss_ptr, shift = type >>3 ; index = (dpl *4 +2 ) << shift;if (index + (4 << shift) -1 > env->tr.limit) { -raise_exception_err (env,EXCP0A_TSS , env->tr.selector &0xfffc ); +raise_exception_err_ra (env,EXCP0A_TSS , env->tr.selector &0xfffc , retaddr); }if (shift ==0 ) { - *esp_ptr =cpu_lduw_kernel (env, env->tr.base + index); - *ss_ptr =cpu_lduw_kernel (env, env->tr.base + index +2 ); + *esp_ptr =cpu_lduw_kernel_ra (env, env->tr.base + index, retaddr); + *ss_ptr =cpu_lduw_kernel_ra (env, env->tr.base + index +2 , retaddr); }else { - *esp_ptr =cpu_ldl_kernel (env, env->tr.base + index); - *ss_ptr =cpu_lduw_kernel (env, env->tr.base + index +4 ); + *esp_ptr =cpu_ldl_kernel_ra (env, env->tr.base + index, retaddr); + *ss_ptr =cpu_lduw_kernel_ra (env, env->tr.base + index +4 , retaddr); } } -static void tss_load_seg (CPUX86State *env,int seg_reg,int selector,int cpl) +static void tss_load_seg (CPUX86State *env,int seg_reg,int selector,int cpl, +uintptr_t retaddr) {uint32_t e1, e2;int rpl, dpl;if ((selector &0xfffc ) !=0 ) { -if (load_segment (env, &e1, &e2, selector) !=0 ) { -raise_exception_err (env,EXCP0A_TSS , selector &0xfffc ); +if (load_segment (env, &e1, &e2, selector, retaddr) !=0 ) { +raise_exception_err_ra (env,EXCP0A_TSS , selector &0xfffc , retaddr); }if (!(e2 &DESC_S_MASK )) { -raise_exception_err (env,EXCP0A_TSS , selector &0xfffc ); +raise_exception_err_ra (env,EXCP0A_TSS , selector &0xfffc , retaddr); } rpl = selector &3 ; dpl = (e2 >>DESC_DPL_SHIFT ) &3 ;if (seg_reg ==R_CS ) {if (!(e2 &DESC_CS_MASK )) { -raise_exception_err (env,EXCP0A_TSS , selector &0xfffc ); +raise_exception_err_ra (env,EXCP0A_TSS , selector &0xfffc , retaddr); }if (dpl != rpl) { -raise_exception_err (env,EXCP0A_TSS , selector &0xfffc ); +raise_exception_err_ra (env,EXCP0A_TSS , selector &0xfffc , retaddr); } }else if (seg_reg ==R_SS ) {/* SS must be writable data */ if ((e2 &DESC_CS_MASK ) || !(e2 &DESC_W_MASK )) { -raise_exception_err (env,EXCP0A_TSS , selector &0xfffc ); +raise_exception_err_ra (env,EXCP0A_TSS , selector &0xfffc , retaddr); }if (dpl != cpl || dpl != rpl) { -raise_exception_err (env,EXCP0A_TSS , selector &0xfffc ); +raise_exception_err_ra (env,EXCP0A_TSS , selector &0xfffc , retaddr); } }else {/* not readable code */ if ((e2 &DESC_CS_MASK ) && !(e2 &DESC_R_MASK )) { -raise_exception_err (env,EXCP0A_TSS , selector &0xfffc ); +raise_exception_err_ra (env,EXCP0A_TSS , selector &0xfffc , retaddr); }/* if data or non conforming code, checks the rights */ if (((e2 >>DESC_TYPE_SHIFT ) &0xf ) <12 ) {if (dpl < cpl || dpl < rpl) { -raise_exception_err (env,EXCP0A_TSS , selector &0xfffc ); +raise_exception_err_ra (env,EXCP0A_TSS , selector &0xfffc , retaddr); } } }if (!(e2 &DESC_P_MASK )) { -raise_exception_err (env,EXCP0B_NOSEG , selector &0xfffc ); +raise_exception_err_ra (env,EXCP0B_NOSEG , selector &0xfffc , retaddr); } cpu_x86_load_seg_cache(env, seg_reg, selector, get_seg_base(e1, e2),
@@ -214,7 +217,7 @@ static void tss_load_seg(CPUX86State *env, int seg_reg, int selector, int cpl) e2); }else {if (seg_reg ==R_SS || seg_reg ==R_CS ) { -raise_exception_err (env,EXCP0A_TSS , selector &0xfffc ); +raise_exception_err_ra (env,EXCP0A_TSS , selector &0xfffc , retaddr); } } }
@@ -226,7 +229,7 @@ static void tss_load_seg(CPUX86State *env, int seg_reg, int selector, int cpl)/* XXX: restore CPU state in registers (PowerPC case) */ static void switch_tss (CPUX86State *env,int tss_selector,uint32_t e1,uint32_t e2,int source, -uint32_t next_eip) +uint32_t next_eip,uintptr_t retaddr) {int tss_limit, tss_limit_max, type, old_tss_limit_max, old_type, v1, v2, i;target_ulong tss_base;
@@ -244,26 +247,26 @@ static void switch_tss(CPUX86State *env, int tss_selector,/* if task gate, we read the TSS segment and we load it */ if (type ==5 ) {if (!(e2 &DESC_P_MASK )) { -raise_exception_err (env,EXCP0B_NOSEG , tss_selector &0xfffc ); +raise_exception_err_ra (env,EXCP0B_NOSEG , tss_selector &0xfffc , retaddr); } tss_selector = e1 >>16 ;if (tss_selector &4 ) { -raise_exception_err (env,EXCP0A_TSS , tss_selector &0xfffc ); +raise_exception_err_ra (env,EXCP0A_TSS , tss_selector &0xfffc , retaddr); } -if (load_segment (env, &e1, &e2, tss_selector) !=0 ) { -raise_exception_err (env,EXCP0D_GPF , tss_selector &0xfffc ); +if (load_segment (env, &e1, &e2, tss_selector, retaddr) !=0 ) { +raise_exception_err_ra (env,EXCP0D_GPF , tss_selector &0xfffc , retaddr); }if (e2 &DESC_S_MASK ) { -raise_exception_err (env,EXCP0D_GPF , tss_selector &0xfffc ); +raise_exception_err_ra (env,EXCP0D_GPF , tss_selector &0xfffc , retaddr); } type = (e2 >>DESC_TYPE_SHIFT ) &0xf ;if ((type &7 ) !=1 ) { -raise_exception_err (env,EXCP0D_GPF , tss_selector &0xfffc ); +raise_exception_err_ra (env,EXCP0D_GPF , tss_selector &0xfffc , retaddr); } }if (!(e2 &DESC_P_MASK )) { -raise_exception_err (env,EXCP0B_NOSEG , tss_selector &0xfffc ); +raise_exception_err_ra (env,EXCP0B_NOSEG , tss_selector &0xfffc , retaddr); }if (type &8 ) {
@@ -275,7 +278,7 @@ static void switch_tss(CPUX86State *env, int tss_selector, tss_base =get_seg_base (e1, e2);if ((tss_selector &4 ) !=0 || tss_limit < tss_limit_max) { -raise_exception_err (env,EXCP0A_TSS , tss_selector &0xfffc ); +raise_exception_err_ra (env,EXCP0A_TSS , tss_selector &0xfffc , retaddr); } old_type = (env->tr.flags >>DESC_TYPE_SHIFT ) &0xf ;if (old_type &8 ) {
@@ -287,30 +290,33 @@ static void switch_tss(CPUX86State *env, int tss_selector,/* read all the registers from the new TSS */ if (type &8 ) {/* 32 bit */ - new_cr3 =cpu_ldl_kernel (env, tss_base +0x1c ); - new_eip =cpu_ldl_kernel (env, tss_base +0x20 ); - new_eflags =cpu_ldl_kernel (env, tss_base +0x24 ); + new_cr3 =cpu_ldl_kernel_ra (env, tss_base +0x1c , retaddr); + new_eip =cpu_ldl_kernel_ra (env, tss_base +0x20 , retaddr); + new_eflags =cpu_ldl_kernel_ra (env, tss_base +0x24 , retaddr);for (i =0 ; i <8 ; i++) { - new_regs[i] =cpu_ldl_kernel (env, tss_base + (0x28 + i *4 )); + new_regs[i] =cpu_ldl_kernel_ra (env, tss_base + (0x28 + i *4 ), + retaddr); }for (i =0 ; i <6 ; i++) { - new_segs[i] =cpu_lduw_kernel (env, tss_base + (0x48 + i *4 )); + new_segs[i] =cpu_lduw_kernel_ra (env, tss_base + (0x48 + i *4 ), + retaddr); } - new_ldt =cpu_lduw_kernel (env, tss_base +0x60 ); - new_trap =cpu_ldl_kernel (env, tss_base +0x64 ); + new_ldt =cpu_lduw_kernel_ra (env, tss_base +0x60 , retaddr); + new_trap =cpu_ldl_kernel_ra (env, tss_base +0x64 , retaddr); }else {/* 16 bit */ new_cr3 =0 ; - new_eip =cpu_lduw_kernel (env, tss_base +0x0e ); - new_eflags =cpu_lduw_kernel (env, tss_base +0x10 ); + new_eip =cpu_lduw_kernel_ra (env, tss_base +0x0e , retaddr); + new_eflags =cpu_lduw_kernel_ra (env, tss_base +0x10 , retaddr);for (i =0 ; i <8 ; i++) { - new_regs[i] =cpu_lduw_kernel (env, tss_base + (0x12 + i *2 )) | -0xffff0000 ; + new_regs[i] =cpu_lduw_kernel_ra (env, tss_base + (0x12 + i *2 ), + retaddr) |0xffff0000 ; }for (i =0 ; i <4 ; i++) { - new_segs[i] =cpu_lduw_kernel (env, tss_base + (0x22 + i *4 )); + new_segs[i] =cpu_lduw_kernel_ra (env, tss_base + (0x22 + i *4 ), + retaddr); } - new_ldt =cpu_lduw_kernel (env, tss_base +0x2a ); + new_ldt =cpu_lduw_kernel_ra (env, tss_base +0x2a , retaddr); new_segs[R_FS ] =0 ; new_segs[R_GS ] =0 ; new_trap =0 ;
@@ -325,10 +331,10 @@ static void switch_tss(CPUX86State *env, int tss_selector,/* XXX: it can still fail in some cases, so a bigger hack is necessary to valid the TLB after having done the accesses */ - v1 =cpu_ldub_kernel (env, env->tr.base); - v2 =cpu_ldub_kernel (env, env->tr.base + old_tss_limit_max); -cpu_stb_kernel (env, env->tr.base, v1); -cpu_stb_kernel (env, env->tr.base + old_tss_limit_max, v2); + v1 =cpu_ldub_kernel_ra (env, env->tr.base, retaddr); + v2 =cpu_ldub_kernel_ra (env, env->tr.base + old_tss_limit_max, retaddr); +cpu_stb_kernel_ra (env, env->tr.base, v1, retaddr); +cpu_stb_kernel_ra (env, env->tr.base + old_tss_limit_max, v2, retaddr);/* clear busy bit (it is restartable) */ if (source ==SWITCH_TSS_JMP || source ==SWITCH_TSS_IRET ) {
@@ -336,9 +342,9 @@ static void switch_tss(CPUX86State *env, int tss_selector,uint32_t e2; ptr = env->gdt.base + (env->tr.selector & ~7 ); - e2 =cpu_ldl_kernel (env, ptr +4 ); + e2 =cpu_ldl_kernel_ra (env, ptr +4 , retaddr); e2 &= ~DESC_TSS_BUSY_MASK ; -cpu_stl_kernel (env, ptr +4 , e2); +cpu_stl_kernel_ra (env, ptr +4 , e2, retaddr); } old_eflags =cpu_compute_eflags (env);if (source ==SWITCH_TSS_IRET ) {
@@ -348,35 +354,35 @@ static void switch_tss(CPUX86State *env, int tss_selector,/* save the current state in the old TSS */ if (type &8 ) {/* 32 bit */ -cpu_stl_kernel (env, env->tr.base +0x20 , next_eip); -cpu_stl_kernel (env, env->tr.base +0x24 , old_eflags); -cpu_stl_kernel (env, env->tr.base + (0x28 +0 *4 ), env->regs[R_EAX ]); -cpu_stl_kernel (env, env->tr.base + (0x28 +1 *4 ), env->regs[R_ECX ]); -cpu_stl_kernel (env, env->tr.base + (0x28 +2 *4 ), env->regs[R_EDX ]); -cpu_stl_kernel (env, env->tr.base + (0x28 +3 *4 ), env->regs[R_EBX ]); -cpu_stl_kernel (env, env->tr.base + (0x28 +4 *4 ), env->regs[R_ESP ]); -cpu_stl_kernel (env, env->tr.base + (0x28 +5 *4 ), env->regs[R_EBP ]); -cpu_stl_kernel (env, env->tr.base + (0x28 +6 *4 ), env->regs[R_ESI ]); -cpu_stl_kernel (env, env->tr.base + (0x28 +7 *4 ), env->regs[R_EDI ]); +cpu_stl_kernel_ra (env, env->tr.base +0x20 , next_eip, retaddr); +cpu_stl_kernel_ra (env, env->tr.base +0x24 , old_eflags, retaddr); +cpu_stl_kernel_ra (env, env->tr.base + (0x28 +0 *4 ), env->regs[R_EAX ], retaddr); +cpu_stl_kernel_ra (env, env->tr.base + (0x28 +1 *4 ), env->regs[R_ECX ], retaddr); +cpu_stl_kernel_ra (env, env->tr.base + (0x28 +2 *4 ), env->regs[R_EDX ], retaddr); +cpu_stl_kernel_ra (env, env->tr.base + (0x28 +3 *4 ), env->regs[R_EBX ], retaddr); +cpu_stl_kernel_ra (env, env->tr.base + (0x28 +4 *4 ), env->regs[R_ESP ], retaddr); +cpu_stl_kernel_ra (env, env->tr.base + (0x28 +5 *4 ), env->regs[R_EBP ], retaddr); +cpu_stl_kernel_ra (env, env->tr.base + (0x28 +6 *4 ), env->regs[R_ESI ], retaddr); +cpu_stl_kernel_ra (env, env->tr.base + (0x28 +7 *4 ), env->regs[R_EDI ], retaddr);for (i =0 ; i <6 ; i++) { -cpu_stw_kernel (env, env->tr.base + (0x48 + i *4 ), - env->segs[i].selector); +cpu_stw_kernel_ra (env, env->tr.base + (0x48 + i *4 ), + env->segs[i].selector, retaddr); } }else {/* 16 bit */ -cpu_stw_kernel (env, env->tr.base +0x0e , next_eip); -cpu_stw_kernel (env, env->tr.base +0x10 , old_eflags); -cpu_stw_kernel (env, env->tr.base + (0x12 +0 *2 ), env->regs[R_EAX ]); -cpu_stw_kernel (env, env->tr.base + (0x12 +1 *2 ), env->regs[R_ECX ]); -cpu_stw_kernel (env, env->tr.base + (0x12 +2 *2 ), env->regs[R_EDX ]); -cpu_stw_kernel (env, env->tr.base + (0x12 +3 *2 ), env->regs[R_EBX ]); -cpu_stw_kernel (env, env->tr.base + (0x12 +4 *2 ), env->regs[R_ESP ]); -cpu_stw_kernel (env, env->tr.base + (0x12 +5 *2 ), env->regs[R_EBP ]); -cpu_stw_kernel (env, env->tr.base + (0x12 +6 *2 ), env->regs[R_ESI ]); -cpu_stw_kernel (env, env->tr.base + (0x12 +7 *2 ), env->regs[R_EDI ]); +cpu_stw_kernel_ra (env, env->tr.base +0x0e , next_eip, retaddr); +cpu_stw_kernel_ra (env, env->tr.base +0x10 , old_eflags, retaddr); +cpu_stw_kernel_ra (env, env->tr.base + (0x12 +0 *2 ), env->regs[R_EAX ], retaddr); +cpu_stw_kernel_ra (env, env->tr.base + (0x12 +1 *2 ), env->regs[R_ECX ], retaddr); +cpu_stw_kernel_ra (env, env->tr.base + (0x12 +2 *2 ), env->regs[R_EDX ], retaddr); +cpu_stw_kernel_ra (env, env->tr.base + (0x12 +3 *2 ), env->regs[R_EBX ], retaddr); +cpu_stw_kernel_ra (env, env->tr.base + (0x12 +4 *2 ), env->regs[R_ESP ], retaddr); +cpu_stw_kernel_ra (env, env->tr.base + (0x12 +5 *2 ), env->regs[R_EBP ], retaddr); +cpu_stw_kernel_ra (env, env->tr.base + (0x12 +6 *2 ), env->regs[R_ESI ], retaddr); +cpu_stw_kernel_ra (env, env->tr.base + (0x12 +7 *2 ), env->regs[R_EDI ], retaddr);for (i =0 ; i <4 ; i++) { -cpu_stw_kernel (env, env->tr.base + (0x22 + i *4 ), - env->segs[i].selector); +cpu_stw_kernel_ra (env, env->tr.base + (0x22 + i *4 ), + env->segs[i].selector, retaddr); } }
@@ -384,7 +390,7 @@ static void switch_tss(CPUX86State *env, int tss_selector,context */ if (source ==SWITCH_TSS_CALL ) { -cpu_stw_kernel (env, tss_base, env->tr.selector); +cpu_stw_kernel_ra (env, tss_base, env->tr.selector, retaddr); new_eflags |=NT_MASK ; }
@@ -394,9 +400,9 @@ static void switch_tss(CPUX86State *env, int tss_selector,uint32_t e2; ptr = env->gdt.base + (tss_selector & ~7 ); - e2 =cpu_ldl_kernel (env, ptr +4 ); + e2 =cpu_ldl_kernel_ra (env, ptr +4 , retaddr); e2 |=DESC_TSS_BUSY_MASK ; -cpu_stl_kernel (env, ptr +4 , e2); +cpu_stl_kernel_ra (env, ptr +4 , e2, retaddr); }/* set the new CPU state */
@@ -448,23 +454,23 @@ static void switch_tss(CPUX86State *env, int tss_selector,/* load the LDT */ if (new_ldt &4 ) { -raise_exception_err (env,EXCP0A_TSS , new_ldt &0xfffc ); +raise_exception_err_ra (env,EXCP0A_TSS , new_ldt &0xfffc , retaddr); }if ((new_ldt &0xfffc ) !=0 ) { dt = &env->gdt; index = new_ldt & ~7 ;if ((index +7 ) > dt->limit) { -raise_exception_err (env,EXCP0A_TSS , new_ldt &0xfffc ); +raise_exception_err_ra (env,EXCP0A_TSS , new_ldt &0xfffc , retaddr); } ptr = dt->base + index; - e1 =cpu_ldl_kernel (env, ptr); - e2 =cpu_ldl_kernel (env, ptr +4 ); + e1 =cpu_ldl_kernel_ra (env, ptr, retaddr); + e2 =cpu_ldl_kernel_ra (env, ptr +4 , retaddr);if ((e2 &DESC_S_MASK ) || ((e2 >>DESC_TYPE_SHIFT ) &0xf ) !=2 ) { -raise_exception_err (env,EXCP0A_TSS , new_ldt &0xfffc ); +raise_exception_err_ra (env,EXCP0A_TSS , new_ldt &0xfffc , retaddr); }if (!(e2 &DESC_P_MASK )) { -raise_exception_err (env,EXCP0A_TSS , new_ldt &0xfffc ); +raise_exception_err_ra (env,EXCP0A_TSS , new_ldt &0xfffc , retaddr); }load_seg_cache_raw_dt (&env->ldt, e1, e2); }
@@ -472,18 +478,18 @@ static void switch_tss(CPUX86State *env, int tss_selector,/* load the segments */ if (!(new_eflags &VM_MASK )) {int cpl = new_segs[R_CS ] &3 ; -tss_load_seg (env,R_CS , new_segs[R_CS ], cpl); -tss_load_seg (env,R_SS , new_segs[R_SS ], cpl); -tss_load_seg (env,R_ES , new_segs[R_ES ], cpl); -tss_load_seg (env,R_DS , new_segs[R_DS ], cpl); -tss_load_seg (env,R_FS , new_segs[R_FS ], cpl); -tss_load_seg (env,R_GS , new_segs[R_GS ], cpl); +tss_load_seg (env,R_CS , new_segs[R_CS ], cpl, retaddr); +tss_load_seg (env,R_SS , new_segs[R_SS ], cpl, retaddr); +tss_load_seg (env,R_ES , new_segs[R_ES ], cpl, retaddr); +tss_load_seg (env,R_DS , new_segs[R_DS ], cpl, retaddr); +tss_load_seg (env,R_FS , new_segs[R_FS ], cpl, retaddr); +tss_load_seg (env,R_GS , new_segs[R_GS ], cpl, retaddr); }/* check that env->eip is in the CS segment limits */ if (new_eip > env->segs[R_CS ].limit) {/* XXX: different exception if CALL? */ -raise_exception_err (env,EXCP0D_GPF ,0 ); +raise_exception_err_ra (env,EXCP0D_GPF ,0 , retaddr); }#ifndef CONFIG_USER_ONLY
@@ -549,27 +555,27 @@ static int exception_has_error_code(int intno)#define SEG_ADDL (ssp, sp, sp_mask) ((uint32_t)((ssp) + (sp & (sp_mask))))/* XXX: add a is_user flag to have proper security support */ -#define PUSHW (ssp, sp, sp_mask, val) \ +#define PUSHW (ssp, sp, sp_mask, val, ra) \ { \ sp -= 2; \ - cpu_stw_kernel(env, (ssp) + (sp & (sp_mask)), (val)); \ + cpu_stw_kernel_ra(env, (ssp) + (sp & (sp_mask)), (val), ra); \ } -#define PUSHL (ssp, sp, sp_mask, val) \ +#define PUSHL (ssp, sp, sp_mask, val, ra) \ { \ sp -= 4; \ - cpu_stl_kernel(env, SEG_ADDL(ssp, sp, sp_mask), (uint32_t)(val)); \ + cpu_stl_kernel_ra(env, SEG_ADDL(ssp, sp, sp_mask), (uint32_t)(val), ra); \ } -#define POPW (ssp, sp, sp_mask, val) \ +#define POPW (ssp, sp, sp_mask, val, ra) \ { \ - val = cpu_lduw_kernel(env, (ssp) + (sp & (sp_mask))); \ + val = cpu_lduw_kernel_ra(env, (ssp) + (sp & (sp_mask)), ra); \ sp += 2; \ } -#define POPL (ssp, sp, sp_mask, val) \ +#define POPL (ssp, sp, sp_mask, val, ra) \ { \ - val = (uint32_t)cpu_ldl_kernel(env, SEG_ADDL(ssp, sp, sp_mask)); \ + val = (uint32_t)cpu_ldl_kernel_ra(env, SEG_ADDL(ssp, sp, sp_mask), ra); \ sp += 4; \ }
@@ -611,7 +617,7 @@ static void do_interrupt_protected(CPUX86State *env, int intno, int is_int,if (!(e2 &DESC_P_MASK )) {raise_exception_err (env,EXCP0B_NOSEG , intno *8 +2 ); } -switch_tss (env, intno *8 , e1, e2,SWITCH_TSS_CALL , old_eip); +switch_tss (env, intno *8 , e1, e2,SWITCH_TSS_CALL , old_eip,0 );if (has_error_code) {int type;uint32_t mask;
@@ -658,7 +664,7 @@ static void do_interrupt_protected(CPUX86State *env, int intno, int is_int,if ((selector &0xfffc ) ==0 ) {raise_exception_err (env,EXCP0D_GPF ,0 ); } -if (load_segment (env, &e1, &e2, selector) !=0 ) { +if (load_segment (env, &e1, &e2, selector,0 ) !=0 ) {raise_exception_err (env,EXCP0D_GPF , selector &0xfffc ); }if (!(e2 &DESC_S_MASK ) || !(e2 & (DESC_CS_MASK ))) {
@@ -673,14 +679,14 @@ static void do_interrupt_protected(CPUX86State *env, int intno, int is_int, }if (!(e2 &DESC_C_MASK ) && dpl < cpl) {/* to inner privilege */ -get_ss_esp_from_tss (env, &ss, &esp, dpl); +get_ss_esp_from_tss (env, &ss, &esp, dpl,0 );if ((ss &0xfffc ) ==0 ) {raise_exception_err (env,EXCP0A_TSS , ss &0xfffc ); }if ((ss &3 ) != dpl) {raise_exception_err (env,EXCP0A_TSS , ss &0xfffc ); } -if (load_segment (env, &ss_e1, &ss_e2, ss) !=0 ) { +if (load_segment (env, &ss_e1, &ss_e2, ss,0 ) !=0 ) {raise_exception_err (env,EXCP0A_TSS , ss &0xfffc ); } ss_dpl = (ss_e2 >>DESC_DPL_SHIFT ) &3 ;
@@ -729,36 +735,36 @@ static void do_interrupt_protected(CPUX86State *env, int intno, int is_int,if (shift ==1 ) {if (new_stack) {if (vm86) { -PUSHL (ssp, esp, sp_mask, env->segs[R_GS ].selector); -PUSHL (ssp, esp, sp_mask, env->segs[R_FS ].selector); -PUSHL (ssp, esp, sp_mask, env->segs[R_DS ].selector); -PUSHL (ssp, esp, sp_mask, env->segs[R_ES ].selector); +PUSHL (ssp, esp, sp_mask, env->segs[R_GS ].selector,0 ); +PUSHL (ssp, esp, sp_mask, env->segs[R_FS ].selector,0 ); +PUSHL (ssp, esp, sp_mask, env->segs[R_DS ].selector,0 ); +PUSHL (ssp, esp, sp_mask, env->segs[R_ES ].selector,0 ); } -PUSHL (ssp, esp, sp_mask, env->segs[R_SS ].selector); -PUSHL (ssp, esp, sp_mask, env->regs[R_ESP ]); +PUSHL (ssp, esp, sp_mask, env->segs[R_SS ].selector,0 ); +PUSHL (ssp, esp, sp_mask, env->regs[R_ESP ],0 ); } -PUSHL (ssp, esp, sp_mask,cpu_compute_eflags (env)); -PUSHL (ssp, esp, sp_mask, env->segs[R_CS ].selector); -PUSHL (ssp, esp, sp_mask, old_eip); +PUSHL (ssp, esp, sp_mask,cpu_compute_eflags (env),0 ); +PUSHL (ssp, esp, sp_mask, env->segs[R_CS ].selector,0 ); +PUSHL (ssp, esp, sp_mask, old_eip,0 );if (has_error_code) { -PUSHL (ssp, esp, sp_mask, error_code); +PUSHL (ssp, esp, sp_mask, error_code,0 ); } }else {if (new_stack) {if (vm86) { -PUSHW (ssp, esp, sp_mask, env->segs[R_GS ].selector); -PUSHW (ssp, esp, sp_mask, env->segs[R_FS ].selector); -PUSHW (ssp, esp, sp_mask, env->segs[R_DS ].selector); -PUSHW (ssp, esp, sp_mask, env->segs[R_ES ].selector); +PUSHW (ssp, esp, sp_mask, env->segs[R_GS ].selector,0 ); +PUSHW (ssp, esp, sp_mask, env->segs[R_FS ].selector,0 ); +PUSHW (ssp, esp, sp_mask, env->segs[R_DS ].selector,0 ); +PUSHW (ssp, esp, sp_mask, env->segs[R_ES ].selector,0 ); } -PUSHW (ssp, esp, sp_mask, env->segs[R_SS ].selector); -PUSHW (ssp, esp, sp_mask, env->regs[R_ESP ]); +PUSHW (ssp, esp, sp_mask, env->segs[R_SS ].selector,0 ); +PUSHW (ssp, esp, sp_mask, env->regs[R_ESP ],0 ); } -PUSHW (ssp, esp, sp_mask,cpu_compute_eflags (env)); -PUSHW (ssp, esp, sp_mask, env->segs[R_CS ].selector); -PUSHW (ssp, esp, sp_mask, old_eip); +PUSHW (ssp, esp, sp_mask,cpu_compute_eflags (env),0 ); +PUSHW (ssp, esp, sp_mask, env->segs[R_CS ].selector,0 ); +PUSHW (ssp, esp, sp_mask, old_eip,0 );if (has_error_code) { -PUSHW (ssp, esp, sp_mask, error_code); +PUSHW (ssp, esp, sp_mask, error_code,0 ); } }
@@ -791,15 +797,15 @@ static void do_interrupt_protected(CPUX86State *env, int intno, int is_int,#ifdef TARGET_X86_64 -#define PUSHQ (sp, val) \ +#define PUSHQ (sp, val, ra) \ { \ sp -= 8; \ - cpu_stq_kernel(env, sp, (val)); \ + cpu_stq_kernel_ra(env, sp, (val), ra); \ } -#define POPQ (sp, val) \ +#define POPQ (sp, val, ra) \ { \ - val = cpu_ldq_kernel(env, sp); \ + val = cpu_ldq_kernel_ra(env, sp, ra); \ sp += 8; \ }
@@ -879,7 +885,7 @@ static void do_interrupt64(CPUX86State *env, int intno, int is_int,raise_exception_err (env,EXCP0D_GPF ,0 ); } -if (load_segment (env, &e1, &e2, selector) !=0 ) { +if (load_segment (env, &e1, &e2, selector,0 ) !=0 ) {raise_exception_err (env,EXCP0D_GPF , selector &0xfffc ); }if (!(e2 &DESC_S_MASK ) || !(e2 & (DESC_CS_MASK ))) {
@@ -915,13 +921,13 @@ static void do_interrupt64(CPUX86State *env, int intno, int is_int, } esp &= ~0xfLL ;/* align stack */ -PUSHQ (esp, env->segs[R_SS ].selector); -PUSHQ (esp, env->regs[R_ESP ]); -PUSHQ (esp,cpu_compute_eflags (env)); -PUSHQ (esp, env->segs[R_CS ].selector); -PUSHQ (esp, old_eip); +PUSHQ (esp, env->segs[R_SS ].selector,0 ); +PUSHQ (esp, env->regs[R_ESP ],0 ); +PUSHQ (esp,cpu_compute_eflags (env),0 ); +PUSHQ (esp, env->segs[R_CS ].selector,0 ); +PUSHQ (esp, old_eip,0 );if (has_error_code) { -PUSHQ (esp, error_code); +PUSHQ (esp, error_code,0 ); }/* interrupt gate clear IF mask */
@@ -961,7 +967,7 @@ void helper_syscall(CPUX86State *env, int next_eip_addend)int selector;if (!(env->efer &MSR_EFER_SCE )) { -raise_exception_err (env,EXCP06_ILLOP ,0 ); +raise_exception_err_ra (env,EXCP06_ILLOP ,0 ,GETPC ()); } selector = (env->star >>32 ) &0xffff ;if (env->hflags &HF_LMA_MASK ) {
@@ -1016,11 +1022,11 @@ void helper_sysret(CPUX86State *env, int dflag)int cpl, selector;if (!(env->efer &MSR_EFER_SCE )) { -raise_exception_err (env,EXCP06_ILLOP ,0 ); +raise_exception_err_ra (env,EXCP06_ILLOP ,0 ,GETPC ()); } cpl = env->hflags &HF_CPL_MASK ;if (!(env->cr[0 ] &CR0_PE_MASK ) || cpl !=0 ) { -raise_exception_err (env,EXCP0D_GPF ,0 ); +raise_exception_err_ra (env,EXCP0D_GPF ,0 ,GETPC ()); } selector = (env->star >>48 ) &0xffff ;if (env->hflags &HF_LMA_MASK ) {
@@ -1092,9 +1098,9 @@ static void do_interrupt_real(CPUX86State *env, int intno, int is_int, } old_cs = env->segs[R_CS ].selector;/* XXX: use SS segment size? */ -PUSHW (ssp, esp,0xffff ,cpu_compute_eflags (env)); -PUSHW (ssp, esp,0xffff , old_cs); -PUSHW (ssp, esp,0xffff , old_eip); +PUSHW (ssp, esp,0xffff ,cpu_compute_eflags (env),0 ); +PUSHW (ssp, esp,0xffff , old_cs,0 ); +PUSHW (ssp, esp,0xffff , old_eip,0 );/* update processor state */ env->regs[R_ESP ] = (env->regs[R_ESP ] & ~0xffff ) | (esp &0xffff );
@@ -1372,22 +1378,26 @@ void helper_enter_level(CPUX86State *env, int level, int data32,while (--level) { esp -=4 ; ebp -=4 ; -cpu_stl_data (env, ssp + (esp & esp_mask), -cpu_ldl_data (env, ssp + (ebp & esp_mask))); +cpu_stl_data_ra (env, ssp + (esp & esp_mask), +cpu_ldl_data_ra (env, ssp + (ebp & esp_mask), +GETPC ()), +GETPC ()); } esp -=4 ; -cpu_stl_data (env, ssp + (esp & esp_mask), t1); +cpu_stl_data_ra (env, ssp + (esp & esp_mask), t1,GETPC ()); }else {/* 16 bit */ esp -=2 ;while (--level) { esp -=2 ; ebp -=2 ; -cpu_stw_data (env, ssp + (esp & esp_mask), -cpu_lduw_data (env, ssp + (ebp & esp_mask))); +cpu_stw_data_ra (env, ssp + (esp & esp_mask), +cpu_lduw_data_ra (env, ssp + (ebp & esp_mask), +GETPC ()), +GETPC ()); } esp -=2 ; -cpu_stw_data (env, ssp + (esp & esp_mask), t1); +cpu_stw_data_ra (env, ssp + (esp & esp_mask), t1,GETPC ()); } }
@@ -1406,20 +1416,22 @@ void helper_enter64_level(CPUX86State *env, int level, int data64,while (--level) { esp -=8 ; ebp -=8 ; -cpu_stq_data (env, esp,cpu_ldq_data (env, ebp)); +cpu_stq_data_ra (env, esp,cpu_ldq_data_ra (env, ebp,GETPC ()), +GETPC ()); } esp -=8 ; - cpu_stq_data(env, esp, t1); + cpu_stq_data_ra(env, esp, t1, GETPC()); }else {/* 16 bit */ esp -=2 ;while (--level) { esp -=2 ; ebp -=2 ; -cpu_stw_data (env, esp,cpu_lduw_data (env, ebp)); +cpu_stw_data_ra (env, esp,cpu_lduw_data_ra (env, ebp,GETPC ()), +GETPC ()); } esp -=2 ; -cpu_stw_data (env, esp, t1); +cpu_stw_data_ra (env, esp, t1,GETPC ()); } }#endif
@@ -1438,7 +1450,7 @@ void helper_lldt(CPUX86State *env, int selector) env->ldt.limit =0 ; }else {if (selector &0x4 ) { -raise_exception_err (env,EXCP0D_GPF , selector &0xfffc ); +raise_exception_err_ra (env,EXCP0D_GPF , selector &0xfffc ,GETPC ()); } dt = &env->gdt; index = selector & ~7 ;
@@ -1451,22 +1463,22 @@ void helper_lldt(CPUX86State *env, int selector) entry_limit =7 ; }if ((index + entry_limit) > dt->limit) { -raise_exception_err (env,EXCP0D_GPF , selector &0xfffc ); +raise_exception_err_ra (env,EXCP0D_GPF , selector &0xfffc ,GETPC ()); } ptr = dt->base + index; - e1 =cpu_ldl_kernel (env, ptr); - e2 =cpu_ldl_kernel (env, ptr +4 ); + e1 =cpu_ldl_kernel_ra (env, ptr,GETPC ()); + e2 =cpu_ldl_kernel_ra (env, ptr +4 ,GETPC ());if ((e2 &DESC_S_MASK ) || ((e2 >>DESC_TYPE_SHIFT ) &0xf ) !=2 ) { -raise_exception_err (env,EXCP0D_GPF , selector &0xfffc ); +raise_exception_err_ra (env,EXCP0D_GPF , selector &0xfffc ,GETPC ()); }if (!(e2 &DESC_P_MASK )) { -raise_exception_err (env,EXCP0B_NOSEG , selector &0xfffc ); +raise_exception_err_ra (env,EXCP0B_NOSEG , selector &0xfffc ,GETPC ()); }#ifdef TARGET_X86_64 if (env->hflags &HF_LMA_MASK ) {uint32_t e3; - e3 =cpu_ldl_kernel (env, ptr +8 ); + e3 =cpu_ldl_kernel_ra (env, ptr +8 ,GETPC ());load_seg_cache_raw_dt (&env->ldt, e1, e2); env->ldt.base |= (target_ulong )e3 <<32 ; }else
@@ -1493,7 +1505,7 @@ void helper_ltr(CPUX86State *env, int selector) env->tr.flags =0 ; }else {if (selector &0x4 ) { -raise_exception_err (env,EXCP0D_GPF , selector &0xfffc ); +raise_exception_err_ra (env,EXCP0D_GPF , selector &0xfffc ,GETPC ()); } dt = &env->gdt; index = selector & ~7 ;
@@ -1506,27 +1518,27 @@ void helper_ltr(CPUX86State *env, int selector) entry_limit =7 ; }if ((index + entry_limit) > dt->limit) { -raise_exception_err (env,EXCP0D_GPF , selector &0xfffc ); +raise_exception_err_ra (env,EXCP0D_GPF , selector &0xfffc ,GETPC ()); } ptr = dt->base + index; - e1 =cpu_ldl_kernel (env, ptr); - e2 =cpu_ldl_kernel (env, ptr +4 ); + e1 =cpu_ldl_kernel_ra (env, ptr,GETPC ()); + e2 =cpu_ldl_kernel_ra (env, ptr +4 ,GETPC ()); type = (e2 >>DESC_TYPE_SHIFT ) &0xf ;if ((e2 &DESC_S_MASK ) || (type !=1 && type !=9 )) { -raise_exception_err (env,EXCP0D_GPF , selector &0xfffc ); +raise_exception_err_ra (env,EXCP0D_GPF , selector &0xfffc ,GETPC ()); }if (!(e2 &DESC_P_MASK )) { -raise_exception_err (env,EXCP0B_NOSEG , selector &0xfffc ); +raise_exception_err_ra (env,EXCP0B_NOSEG , selector &0xfffc ,GETPC ()); }#ifdef TARGET_X86_64 if (env->hflags &HF_LMA_MASK ) {uint32_t e3, e4; - e3 =cpu_ldl_kernel (env, ptr +8 ); - e4 =cpu_ldl_kernel (env, ptr +12 ); + e3 =cpu_ldl_kernel_ra (env, ptr +8 ,GETPC ()); + e4 =cpu_ldl_kernel_ra (env, ptr +12 ,GETPC ());if ((e4 >>DESC_TYPE_SHIFT ) &0xf ) { -raise_exception_err (env,EXCP0D_GPF , selector &0xfffc ); +raise_exception_err_ra (env,EXCP0D_GPF , selector &0xfffc ,GETPC ()); }load_seg_cache_raw_dt (&env->tr, e1, e2); env->tr.base |= (target_ulong )e3 <<32 ;
@@ -1536,7 +1548,7 @@ void helper_ltr(CPUX86State *env, int selector)load_seg_cache_raw_dt (&env->tr, e1, e2); } e2 |=DESC_TSS_BUSY_MASK ; -cpu_stl_kernel (env, ptr +4 , e2); +cpu_stl_kernel_ra (env, ptr +4 , e2,GETPC ()); } env->tr.selector = selector; }
@@ -1559,7 +1571,7 @@ void helper_load_seg(CPUX86State *env, int seg_reg, int selector) && (!(env->hflags & HF_CS64_MASK) || cpl == 3) #endif ) { -raise_exception_err (env,EXCP0D_GPF ,0 ); +raise_exception_err_ra (env,EXCP0D_GPF ,0 ,GETPC ()); } cpu_x86_load_seg_cache(env, seg_reg, selector, 0, 0, 0); }else {
@@ -1571,51 +1583,51 @@ void helper_load_seg(CPUX86State *env, int seg_reg, int selector) } index = selector & ~7 ;if ((index +7 ) > dt->limit) { -raise_exception_err (env,EXCP0D_GPF , selector &0xfffc ); +raise_exception_err_ra (env,EXCP0D_GPF , selector &0xfffc ,GETPC ()); } ptr = dt->base + index; - e1 =cpu_ldl_kernel (env, ptr); - e2 =cpu_ldl_kernel (env, ptr +4 ); + e1 =cpu_ldl_kernel_ra (env, ptr,GETPC ()); + e2 =cpu_ldl_kernel_ra (env, ptr +4 ,GETPC ());if (!(e2 &DESC_S_MASK )) { -raise_exception_err (env,EXCP0D_GPF , selector &0xfffc ); +raise_exception_err_ra (env,EXCP0D_GPF , selector &0xfffc ,GETPC ()); } rpl = selector &3 ; dpl = (e2 >>DESC_DPL_SHIFT ) &3 ;if (seg_reg ==R_SS ) {/* must be writable segment */ if ((e2 &DESC_CS_MASK ) || !(e2 &DESC_W_MASK )) { -raise_exception_err (env,EXCP0D_GPF , selector &0xfffc ); +raise_exception_err_ra (env,EXCP0D_GPF , selector &0xfffc ,GETPC ()); }if (rpl != cpl || dpl != cpl) { -raise_exception_err (env,EXCP0D_GPF , selector &0xfffc ); +raise_exception_err_ra (env,EXCP0D_GPF , selector &0xfffc ,GETPC ()); } }else {/* must be readable segment */ if ((e2 & (DESC_CS_MASK |DESC_R_MASK )) ==DESC_CS_MASK ) { -raise_exception_err (env,EXCP0D_GPF , selector &0xfffc ); +raise_exception_err_ra (env,EXCP0D_GPF , selector &0xfffc ,GETPC ()); }if (!(e2 &DESC_CS_MASK ) || !(e2 &DESC_C_MASK )) {/* if not conforming code, test rights */ if (dpl < cpl || dpl < rpl) { -raise_exception_err (env,EXCP0D_GPF , selector &0xfffc ); +raise_exception_err_ra (env,EXCP0D_GPF , selector &0xfffc ,GETPC ()); } } }if (!(e2 &DESC_P_MASK )) {if (seg_reg ==R_SS ) { -raise_exception_err (env,EXCP0C_STACK , selector &0xfffc ); +raise_exception_err_ra (env,EXCP0C_STACK , selector &0xfffc ,GETPC ()); }else { -raise_exception_err (env,EXCP0B_NOSEG , selector &0xfffc ); +raise_exception_err_ra (env,EXCP0B_NOSEG , selector &0xfffc ,GETPC ()); } }/* set the access bit if not already set */ if (!(e2 &DESC_A_MASK )) { e2 |=DESC_A_MASK ; -cpu_stl_kernel (env, ptr +4 , e2); +cpu_stl_kernel_ra (env, ptr +4 , e2,GETPC ()); } cpu_x86_load_seg_cache(env, seg_reg, selector,
@@ -1638,39 +1650,39 @@ void helper_ljmp_protected(CPUX86State *env, int new_cs, target_ulong new_eip,target_ulong next_eip;if ((new_cs &0xfffc ) ==0 ) { -raise_exception_err (env,EXCP0D_GPF ,0 ); +raise_exception_err_ra (env,EXCP0D_GPF ,0 ,GETPC ()); } -if (load_segment (env, &e1, &e2, new_cs) !=0 ) { -raise_exception_err (env,EXCP0D_GPF , new_cs &0xfffc ); +if (load_segment (env, &e1, &e2, new_cs,GETPC ()) !=0 ) { +raise_exception_err_ra (env,EXCP0D_GPF , new_cs &0xfffc ,GETPC ()); } cpl = env->hflags &HF_CPL_MASK ;if (e2 &DESC_S_MASK ) {if (!(e2 &DESC_CS_MASK )) { -raise_exception_err (env,EXCP0D_GPF , new_cs &0xfffc ); +raise_exception_err_ra (env,EXCP0D_GPF , new_cs &0xfffc ,GETPC ()); } dpl = (e2 >>DESC_DPL_SHIFT ) &3 ;if (e2 &DESC_C_MASK ) {/* conforming code segment */ if (dpl > cpl) { -raise_exception_err (env,EXCP0D_GPF , new_cs &0xfffc ); +raise_exception_err_ra (env,EXCP0D_GPF , new_cs &0xfffc ,GETPC ()); } }else {/* non conforming code segment */ rpl = new_cs &3 ;if (rpl > cpl) { -raise_exception_err (env,EXCP0D_GPF , new_cs &0xfffc ); +raise_exception_err_ra (env,EXCP0D_GPF , new_cs &0xfffc ,GETPC ()); }if (dpl != cpl) { -raise_exception_err (env,EXCP0D_GPF , new_cs &0xfffc ); +raise_exception_err_ra (env,EXCP0D_GPF , new_cs &0xfffc ,GETPC ()); } }if (!(e2 &DESC_P_MASK )) { -raise_exception_err (env,EXCP0B_NOSEG , new_cs &0xfffc ); +raise_exception_err_ra (env,EXCP0B_NOSEG , new_cs &0xfffc ,GETPC ()); } limit =get_seg_limit (e1, e2);if (new_eip > limit && !(env->hflags &HF_LMA_MASK ) && !(e2 &DESC_L_MASK )) { -raise_exception_err (env,EXCP0D_GPF , new_cs &0xfffc ); +raise_exception_err_ra (env,EXCP0D_GPF , new_cs &0xfffc ,GETPC ()); }cpu_x86_load_seg_cache (env,R_CS , (new_cs &0xfffc ) | cpl,get_seg_base (e1, e2), limit, e2);
@@ -1686,50 +1698,50 @@ void helper_ljmp_protected(CPUX86State *env, int new_cs, target_ulong new_eip,case 9 :/* 386 TSS */ case 5 :/* task gate */ if (dpl < cpl || dpl < rpl) { -raise_exception_err (env,EXCP0D_GPF , new_cs &0xfffc ); +raise_exception_err_ra (env,EXCP0D_GPF , new_cs &0xfffc ,GETPC ()); } next_eip = env->eip + next_eip_addend; -switch_tss (env, new_cs, e1, e2,SWITCH_TSS_JMP , next_eip); +switch_tss (env, new_cs, e1, e2,SWITCH_TSS_JMP , next_eip,GETPC ());break ;case 4 :/* 286 call gate */ case 12 :/* 386 call gate */ if ((dpl < cpl) || (dpl < rpl)) { -raise_exception_err (env,EXCP0D_GPF , new_cs &0xfffc ); +raise_exception_err_ra (env,EXCP0D_GPF , new_cs &0xfffc ,GETPC ()); }if (!(e2 &DESC_P_MASK )) { -raise_exception_err (env,EXCP0B_NOSEG , new_cs &0xfffc ); +raise_exception_err_ra (env,EXCP0B_NOSEG , new_cs &0xfffc ,GETPC ()); } gate_cs = e1 >>16 ; new_eip = (e1 &0xffff );if (type ==12 ) { new_eip |= (e2 &0xffff0000 ); } -if (load_segment (env, &e1, &e2, gate_cs) !=0 ) { -raise_exception_err (env,EXCP0D_GPF , gate_cs &0xfffc ); +if (load_segment (env, &e1, &e2, gate_cs,GETPC ()) !=0 ) { +raise_exception_err_ra (env,EXCP0D_GPF , gate_cs &0xfffc ,GETPC ()); } dpl = (e2 >>DESC_DPL_SHIFT ) &3 ;/* must be code segment */ if (((e2 & (DESC_S_MASK |DESC_CS_MASK )) != (DESC_S_MASK |DESC_CS_MASK ))) { -raise_exception_err (env,EXCP0D_GPF , gate_cs &0xfffc ); +raise_exception_err_ra (env,EXCP0D_GPF , gate_cs &0xfffc ,GETPC ()); }if (((e2 &DESC_C_MASK ) && (dpl > cpl)) || (!(e2 &DESC_C_MASK ) && (dpl != cpl))) { -raise_exception_err (env,EXCP0D_GPF , gate_cs &0xfffc ); +raise_exception_err_ra (env,EXCP0D_GPF , gate_cs &0xfffc ,GETPC ()); }if (!(e2 &DESC_P_MASK )) { -raise_exception_err (env,EXCP0D_GPF , gate_cs &0xfffc ); +raise_exception_err_ra (env,EXCP0D_GPF , gate_cs &0xfffc ,GETPC ()); } limit =get_seg_limit (e1, e2);if (new_eip > limit) { -raise_exception_err (env,EXCP0D_GPF ,0 ); +raise_exception_err_ra (env,EXCP0D_GPF ,0 ,GETPC ()); }cpu_x86_load_seg_cache (env,R_CS , (gate_cs &0xfffc ) | cpl,get_seg_base (e1, e2), limit, e2); env->eip = new_eip;break ;default : -raise_exception_err (env,EXCP0D_GPF , new_cs &0xfffc ); +raise_exception_err_ra (env,EXCP0D_GPF , new_cs &0xfffc ,GETPC ());break ; } }
@@ -1748,11 +1760,11 @@ void helper_lcall_real(CPUX86State *env, int new_cs, target_ulong new_eip1, esp_mask =get_sp_mask (env->segs[R_SS ].flags); ssp = env->segs[R_SS ].base;if (shift) { -PUSHL (ssp, esp, esp_mask, env->segs[R_CS ].selector); -PUSHL (ssp, esp, esp_mask, next_eip); +PUSHL (ssp, esp, esp_mask, env->segs[R_CS ].selector,GETPC ()); +PUSHL (ssp, esp, esp_mask, next_eip,GETPC ()); }else { -PUSHW (ssp, esp, esp_mask, env->segs[R_CS ].selector); -PUSHW (ssp, esp, esp_mask, next_eip); +PUSHW (ssp, esp, esp_mask, env->segs[R_CS ].selector,GETPC ()); +PUSHW (ssp, esp, esp_mask, next_eip,GETPC ()); }SET_ESP (esp, esp_mask);
@@ -1775,35 +1787,35 @@ void helper_lcall_protected(CPUX86State *env, int new_cs, target_ulong new_eip,LOG_PCALL ("lcall %04x:%08x s=%d\n" , new_cs, (uint32_t )new_eip, shift);LOG_PCALL_STATE (CPU (x86_env_get_cpu (env)));if ((new_cs &0xfffc ) ==0 ) { -raise_exception_err (env,EXCP0D_GPF ,0 ); +raise_exception_err_ra (env,EXCP0D_GPF ,0 ,GETPC ()); } -if (load_segment (env, &e1, &e2, new_cs) !=0 ) { -raise_exception_err (env,EXCP0D_GPF , new_cs &0xfffc ); +if (load_segment (env, &e1, &e2, new_cs,GETPC ()) !=0 ) { +raise_exception_err_ra (env,EXCP0D_GPF , new_cs &0xfffc ,GETPC ()); } cpl = env->hflags &HF_CPL_MASK ;LOG_PCALL ("desc=%08x:%08x\n" , e1, e2);if (e2 &DESC_S_MASK ) {if (!(e2 &DESC_CS_MASK )) { -raise_exception_err (env,EXCP0D_GPF , new_cs &0xfffc ); +raise_exception_err_ra (env,EXCP0D_GPF , new_cs &0xfffc ,GETPC ()); } dpl = (e2 >>DESC_DPL_SHIFT ) &3 ;if (e2 &DESC_C_MASK ) {/* conforming code segment */ if (dpl > cpl) { -raise_exception_err (env,EXCP0D_GPF , new_cs &0xfffc ); +raise_exception_err_ra (env,EXCP0D_GPF , new_cs &0xfffc ,GETPC ()); } }else {/* non conforming code segment */ rpl = new_cs &3 ;if (rpl > cpl) { -raise_exception_err (env,EXCP0D_GPF , new_cs &0xfffc ); +raise_exception_err_ra (env,EXCP0D_GPF , new_cs &0xfffc ,GETPC ()); }if (dpl != cpl) { -raise_exception_err (env,EXCP0D_GPF , new_cs &0xfffc ); +raise_exception_err_ra (env,EXCP0D_GPF , new_cs &0xfffc ,GETPC ()); } }if (!(e2 &DESC_P_MASK )) { -raise_exception_err (env,EXCP0B_NOSEG , new_cs &0xfffc ); +raise_exception_err_ra (env,EXCP0B_NOSEG , new_cs &0xfffc ,GETPC ()); }#ifdef TARGET_X86_64
@@ -1813,8 +1825,8 @@ void helper_lcall_protected(CPUX86State *env, int new_cs, target_ulong new_eip,/* 64 bit case */ rsp = env->regs[R_ESP ]; -PUSHQ (rsp, env->segs[R_CS ].selector); -PUSHQ (rsp, next_eip); +PUSHQ (rsp, env->segs[R_CS ].selector,GETPC ()); +PUSHQ (rsp, next_eip,GETPC ());/* from this point, not restartable */ env->regs[R_ESP ] = rsp; cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
@@ -1828,16 +1840,16 @@ void helper_lcall_protected(CPUX86State *env, int new_cs, target_ulong new_eip, sp_mask =get_sp_mask (env->segs[R_SS ].flags); ssp = env->segs[R_SS ].base;if (shift) { -PUSHL (ssp, sp, sp_mask, env->segs[R_CS ].selector); -PUSHL (ssp, sp, sp_mask, next_eip); +PUSHL (ssp, sp, sp_mask, env->segs[R_CS ].selector,GETPC ()); +PUSHL (ssp, sp, sp_mask, next_eip,GETPC ()); }else { -PUSHW (ssp, sp, sp_mask, env->segs[R_CS ].selector); -PUSHW (ssp, sp, sp_mask, next_eip); +PUSHW (ssp, sp, sp_mask, env->segs[R_CS ].selector,GETPC ()); +PUSHW (ssp, sp, sp_mask, next_eip,GETPC ()); } limit =get_seg_limit (e1, e2);if (new_eip > limit) { -raise_exception_err (env,EXCP0D_GPF , new_cs &0xfffc ); +raise_exception_err_ra (env,EXCP0D_GPF , new_cs &0xfffc ,GETPC ()); }/* from this point, not restartable */ SET_ESP (sp, sp_mask);
@@ -1855,73 +1867,73 @@ void helper_lcall_protected(CPUX86State *env, int new_cs, target_ulong new_eip,case 9 :/* available 386 TSS */ case 5 :/* task gate */ if (dpl < cpl || dpl < rpl) { -raise_exception_err (env,EXCP0D_GPF , new_cs &0xfffc ); +raise_exception_err_ra (env,EXCP0D_GPF , new_cs &0xfffc ,GETPC ()); } -switch_tss (env, new_cs, e1, e2,SWITCH_TSS_CALL , next_eip); +switch_tss (env, new_cs, e1, e2,SWITCH_TSS_CALL , next_eip,GETPC ());return ;case 4 :/* 286 call gate */ case 12 :/* 386 call gate */ break ;default : -raise_exception_err (env,EXCP0D_GPF , new_cs &0xfffc ); +raise_exception_err_ra (env,EXCP0D_GPF , new_cs &0xfffc ,GETPC ());break ; } shift = type >>3 ;if (dpl < cpl || dpl < rpl) { -raise_exception_err (env,EXCP0D_GPF , new_cs &0xfffc ); +raise_exception_err_ra (env,EXCP0D_GPF , new_cs &0xfffc ,GETPC ()); }/* check valid bit */ if (!(e2 &DESC_P_MASK )) { -raise_exception_err (env,EXCP0B_NOSEG , new_cs &0xfffc ); +raise_exception_err_ra (env,EXCP0B_NOSEG , new_cs &0xfffc ,GETPC ()); } selector = e1 >>16 ; offset = (e2 &0xffff0000 ) | (e1 &0x0000ffff ); param_count = e2 &0x1f ;if ((selector &0xfffc ) ==0 ) { -raise_exception_err (env,EXCP0D_GPF ,0 ); +raise_exception_err_ra (env,EXCP0D_GPF ,0 ,GETPC ()); } -if (load_segment (env, &e1, &e2, selector) !=0 ) { -raise_exception_err (env,EXCP0D_GPF , selector &0xfffc ); +if (load_segment (env, &e1, &e2, selector,GETPC ()) !=0 ) { +raise_exception_err_ra (env,EXCP0D_GPF , selector &0xfffc ,GETPC ()); }if (!(e2 &DESC_S_MASK ) || !(e2 & (DESC_CS_MASK ))) { -raise_exception_err (env,EXCP0D_GPF , selector &0xfffc ); +raise_exception_err_ra (env,EXCP0D_GPF , selector &0xfffc ,GETPC ()); } dpl = (e2 >>DESC_DPL_SHIFT ) &3 ;if (dpl > cpl) { -raise_exception_err (env,EXCP0D_GPF , selector &0xfffc ); +raise_exception_err_ra (env,EXCP0D_GPF , selector &0xfffc ,GETPC ()); }if (!(e2 &DESC_P_MASK )) { -raise_exception_err (env,EXCP0B_NOSEG , selector &0xfffc ); +raise_exception_err_ra (env,EXCP0B_NOSEG , selector &0xfffc ,GETPC ()); }if (!(e2 &DESC_C_MASK ) && dpl < cpl) {/* to inner privilege */ -get_ss_esp_from_tss (env, &ss, &sp, dpl); +get_ss_esp_from_tss (env, &ss, &sp, dpl,GETPC ());LOG_PCALL ("new ss:esp=%04x:%08x param_count=%d env->regs[R_ESP]=" TARGET_FMT_lx"\n" , ss, sp, param_count, env->regs[R_ESP ]);if ((ss &0xfffc ) ==0 ) { -raise_exception_err (env,EXCP0A_TSS , ss &0xfffc ); +raise_exception_err_ra (env,EXCP0A_TSS , ss &0xfffc ,GETPC ()); }if ((ss &3 ) != dpl) { -raise_exception_err (env,EXCP0A_TSS , ss &0xfffc ); +raise_exception_err_ra (env,EXCP0A_TSS , ss &0xfffc ,GETPC ()); } -if (load_segment (env, &ss_e1, &ss_e2, ss) !=0 ) { -raise_exception_err (env,EXCP0A_TSS , ss &0xfffc ); +if (load_segment (env, &ss_e1, &ss_e2, ss,GETPC ()) !=0 ) { +raise_exception_err_ra (env,EXCP0A_TSS , ss &0xfffc ,GETPC ()); } ss_dpl = (ss_e2 >>DESC_DPL_SHIFT ) &3 ;if (ss_dpl != dpl) { -raise_exception_err (env,EXCP0A_TSS , ss &0xfffc ); +raise_exception_err_ra (env,EXCP0A_TSS , ss &0xfffc ,GETPC ()); }if (!(ss_e2 &DESC_S_MASK ) || (ss_e2 &DESC_CS_MASK ) || !(ss_e2 &DESC_W_MASK )) { -raise_exception_err (env,EXCP0A_TSS , ss &0xfffc ); +raise_exception_err_ra (env,EXCP0A_TSS , ss &0xfffc ,GETPC ()); }if (!(ss_e2 &DESC_P_MASK )) { -raise_exception_err (env,EXCP0A_TSS , ss &0xfffc ); +raise_exception_err_ra (env,EXCP0A_TSS , ss &0xfffc ,GETPC ()); }/* push_size = ((param_count * 2) + 8) << shift; */
@@ -1932,22 +1944,22 @@ void helper_lcall_protected(CPUX86State *env, int new_cs, target_ulong new_eip, sp_mask =get_sp_mask (ss_e2); ssp =get_seg_base (ss_e1, ss_e2);if (shift) { -PUSHL (ssp, sp, sp_mask, env->segs[R_SS ].selector); -PUSHL (ssp, sp, sp_mask, env->regs[R_ESP ]); +PUSHL (ssp, sp, sp_mask, env->segs[R_SS ].selector,GETPC ()); +PUSHL (ssp, sp, sp_mask, env->regs[R_ESP ],GETPC ());for (i = param_count -1 ; i >=0 ; i--) { - val =cpu_ldl_kernel (env, old_ssp + - ((env->regs[R_ESP ] + i *4 ) & - old_sp_mask)); -PUSHL (ssp, sp, sp_mask, val); + val =cpu_ldl_kernel_ra (env, old_ssp + + ((env->regs[R_ESP ] + i *4 ) & + old_sp_mask),GETPC ()); +PUSHL (ssp, sp, sp_mask, val,GETPC ()); } }else { -PUSHW (ssp, sp, sp_mask, env->segs[R_SS ].selector); -PUSHW (ssp, sp, sp_mask, env->regs[R_ESP ]); +PUSHW (ssp, sp, sp_mask, env->segs[R_SS ].selector,GETPC ()); +PUSHW (ssp, sp, sp_mask, env->regs[R_ESP ],GETPC ());for (i = param_count -1 ; i >=0 ; i--) { - val =cpu_lduw_kernel (env, old_ssp + - ((env->regs[R_ESP ] + i *2 ) & - old_sp_mask)); -PUSHW (ssp, sp, sp_mask, val); + val =cpu_lduw_kernel_ra (env, old_ssp + + ((env->regs[R_ESP ] + i *2 ) & + old_sp_mask),GETPC ()); +PUSHW (ssp, sp, sp_mask, val,GETPC ()); } } new_stack =1 ;
@@ -1961,11 +1973,11 @@ void helper_lcall_protected(CPUX86State *env, int new_cs, target_ulong new_eip, }if (shift) { -PUSHL (ssp, sp, sp_mask, env->segs[R_CS ].selector); -PUSHL (ssp, sp, sp_mask, next_eip); +PUSHL (ssp, sp, sp_mask, env->segs[R_CS ].selector,GETPC ()); +PUSHL (ssp, sp, sp_mask, next_eip,GETPC ()); }else { -PUSHW (ssp, sp, sp_mask, env->segs[R_CS ].selector); -PUSHW (ssp, sp, sp_mask, next_eip); +PUSHW (ssp, sp, sp_mask, env->segs[R_CS ].selector,GETPC ()); +PUSHW (ssp, sp, sp_mask, next_eip,GETPC ()); }/* from this point, not restartable */
@@ -2000,15 +2012,15 @@ void helper_iret_real(CPUX86State *env, int shift) ssp = env->segs[R_SS ].base;if (shift ==1 ) {/* 32 bits */ -POPL (ssp, sp, sp_mask, new_eip); -POPL (ssp, sp, sp_mask, new_cs); +POPL (ssp, sp, sp_mask, new_eip,GETPC ()); +POPL (ssp, sp, sp_mask, new_cs,GETPC ()); new_cs &=0xffff ; -POPL (ssp, sp, sp_mask, new_eflags); +POPL (ssp, sp, sp_mask, new_eflags,GETPC ()); }else {/* 16 bits */ -POPW (ssp, sp, sp_mask, new_eip); -POPW (ssp, sp, sp_mask, new_cs); -POPW (ssp, sp, sp_mask, new_eflags); +POPW (ssp, sp, sp_mask, new_eip,GETPC ()); +POPW (ssp, sp, sp_mask, new_cs,GETPC ()); +POPW (ssp, sp, sp_mask, new_eflags,GETPC ()); } env->regs[R_ESP ] = (env->regs[R_ESP ] & ~sp_mask) | (sp & sp_mask); env->segs[R_CS ].selector = new_cs;
@@ -2053,7 +2065,8 @@ static inline void validate_seg(CPUX86State *env, int seg_reg, int cpl)/* protected mode iret */ static inline void helper_ret_protected (CPUX86State *env,int shift, -int is_iret,int addend) +int is_iret,int addend, +uintptr_t retaddr) {uint32_t new_cs, new_eflags, new_ss;uint32_t new_es, new_ds, new_fs, new_gs;
@@ -2074,32 +2087,32 @@ static inline void helper_ret_protected(CPUX86State *env, int shift, new_eflags =0 ;/* avoid warning */ #ifdef TARGET_X86_64 if (shift ==2 ) { -POPQ (sp, new_eip); -POPQ (sp, new_cs); +POPQ (sp, new_eip, retaddr); +POPQ (sp, new_cs, retaddr); new_cs &=0xffff ;if (is_iret) { -POPQ (sp, new_eflags); +POPQ (sp, new_eflags, retaddr); } } else#endif {if (shift ==1 ) {/* 32 bits */ -POPL (ssp, sp, sp_mask, new_eip); -POPL (ssp, sp, sp_mask, new_cs); +POPL (ssp, sp, sp_mask, new_eip, retaddr); +POPL (ssp, sp, sp_mask, new_cs, retaddr); new_cs &=0xffff ;if (is_iret) { -POPL (ssp, sp, sp_mask, new_eflags); +POPL (ssp, sp, sp_mask, new_eflags, retaddr);if (new_eflags &VM_MASK ) { goto return_to_vm86; } } }else {/* 16 bits */ -POPW (ssp, sp, sp_mask, new_eip); -POPW (ssp, sp, sp_mask, new_cs); +POPW (ssp, sp, sp_mask, new_eip, retaddr); +POPW (ssp, sp, sp_mask, new_cs, retaddr);if (is_iret) { -POPW (ssp, sp, sp_mask, new_eflags); +POPW (ssp, sp, sp_mask, new_eflags, retaddr); } } }
@@ -2107,32 +2120,32 @@ static inline void helper_ret_protected(CPUX86State *env, int shift, new_cs, new_eip, shift, addend);LOG_PCALL_STATE (CPU (x86_env_get_cpu (env)));if ((new_cs &0xfffc ) ==0 ) { -raise_exception_err (env,EXCP0D_GPF , new_cs &0xfffc ); +raise_exception_err_ra (env,EXCP0D_GPF , new_cs &0xfffc , retaddr); } -if (load_segment (env, &e1, &e2, new_cs) !=0 ) { -raise_exception_err (env,EXCP0D_GPF , new_cs &0xfffc ); +if (load_segment (env, &e1, &e2, new_cs, retaddr) !=0 ) { +raise_exception_err_ra (env,EXCP0D_GPF , new_cs &0xfffc , retaddr); }if (!(e2 &DESC_S_MASK ) || !(e2 &DESC_CS_MASK )) { -raise_exception_err (env,EXCP0D_GPF , new_cs &0xfffc ); +raise_exception_err_ra (env,EXCP0D_GPF , new_cs &0xfffc , retaddr); } cpl = env->hflags &HF_CPL_MASK ; rpl = new_cs &3 ;if (rpl < cpl) { -raise_exception_err (env,EXCP0D_GPF , new_cs &0xfffc ); +raise_exception_err_ra (env,EXCP0D_GPF , new_cs &0xfffc , retaddr); } dpl = (e2 >>DESC_DPL_SHIFT ) &3 ;if (e2 &DESC_C_MASK ) {if (dpl > rpl) { -raise_exception_err (env,EXCP0D_GPF , new_cs &0xfffc ); +raise_exception_err_ra (env,EXCP0D_GPF , new_cs &0xfffc , retaddr); } }else {if (dpl != rpl) { -raise_exception_err (env,EXCP0D_GPF , new_cs &0xfffc ); +raise_exception_err_ra (env,EXCP0D_GPF , new_cs &0xfffc , retaddr); } }if (!(e2 &DESC_P_MASK )) { -raise_exception_err (env,EXCP0B_NOSEG , new_cs &0xfffc ); +raise_exception_err_ra (env,EXCP0B_NOSEG , new_cs &0xfffc , retaddr); } sp += addend;
@@ -2147,21 +2160,21 @@ static inline void helper_ret_protected(CPUX86State *env, int shift,/* return to different privilege level */ #ifdef TARGET_X86_64 if (shift ==2 ) { -POPQ (sp, new_esp); -POPQ (sp, new_ss); +POPQ (sp, new_esp, retaddr); +POPQ (sp, new_ss, retaddr); new_ss &=0xffff ; } else#endif {if (shift ==1 ) {/* 32 bits */ -POPL (ssp, sp, sp_mask, new_esp); -POPL (ssp, sp, sp_mask, new_ss); +POPL (ssp, sp, sp_mask, new_esp, retaddr); +POPL (ssp, sp, sp_mask, new_ss, retaddr); new_ss &=0xffff ; }else {/* 16 bits */ -POPW (ssp, sp, sp_mask, new_esp); -POPW (ssp, sp, sp_mask, new_ss); +POPW (ssp, sp, sp_mask, new_esp, retaddr); +POPW (ssp, sp, sp_mask, new_ss, retaddr); } } LOG_PCALL("new ss:esp=%04x:" TARGET_FMT_lx "\n",
@@ -2180,26 +2193,26 @@ static inline void helper_ret_protected(CPUX86State *env, int shift, } else#endif { -raise_exception_err (env,EXCP0D_GPF ,0 ); +raise_exception_err_ra (env,EXCP0D_GPF ,0 , retaddr); } }else {if ((new_ss &3 ) != rpl) { -raise_exception_err (env,EXCP0D_GPF , new_ss &0xfffc ); +raise_exception_err_ra (env,EXCP0D_GPF , new_ss &0xfffc , retaddr); } -if (load_segment (env, &ss_e1, &ss_e2, new_ss) !=0 ) { -raise_exception_err (env,EXCP0D_GPF , new_ss &0xfffc ); +if (load_segment (env, &ss_e1, &ss_e2, new_ss, retaddr) !=0 ) { +raise_exception_err_ra (env,EXCP0D_GPF , new_ss &0xfffc , retaddr); }if (!(ss_e2 &DESC_S_MASK ) || (ss_e2 &DESC_CS_MASK ) || !(ss_e2 &DESC_W_MASK )) { -raise_exception_err (env,EXCP0D_GPF , new_ss &0xfffc ); +raise_exception_err_ra (env,EXCP0D_GPF , new_ss &0xfffc , retaddr); } dpl = (ss_e2 >>DESC_DPL_SHIFT ) &3 ;if (dpl != rpl) { -raise_exception_err (env,EXCP0D_GPF , new_ss &0xfffc ); +raise_exception_err_ra (env,EXCP0D_GPF , new_ss &0xfffc , retaddr); }if (!(ss_e2 &DESC_P_MASK )) { -raise_exception_err (env,EXCP0B_NOSEG , new_ss &0xfffc ); +raise_exception_err_ra (env,EXCP0B_NOSEG , new_ss &0xfffc , retaddr); } cpu_x86_load_seg_cache(env, R_SS, new_ss, get_seg_base(ss_e1, ss_e2),
@@ -2249,12 +2262,12 @@ static inline void helper_ret_protected(CPUX86State *env, int shift,return ; return_to_vm86: -POPL (ssp, sp, sp_mask, new_esp); -POPL (ssp, sp, sp_mask, new_ss); -POPL (ssp, sp, sp_mask, new_es); -POPL (ssp, sp, sp_mask, new_ds); -POPL (ssp, sp, sp_mask, new_fs); -POPL (ssp, sp, sp_mask, new_gs); +POPL (ssp, sp, sp_mask, new_esp, retaddr); +POPL (ssp, sp, sp_mask, new_ss, retaddr); +POPL (ssp, sp, sp_mask, new_es, retaddr); +POPL (ssp, sp, sp_mask, new_ds, retaddr); +POPL (ssp, sp, sp_mask, new_fs, retaddr); +POPL (ssp, sp, sp_mask, new_gs, retaddr);/* modify processor state */ cpu_load_eflags(env, new_eflags, TF_MASK | AC_MASK | ID_MASK |
@@ -2280,37 +2293,37 @@ void helper_iret_protected(CPUX86State *env, int shift, int next_eip)if (env->eflags &NT_MASK ) {#ifdef TARGET_X86_64 if (env->hflags &HF_LMA_MASK ) { -raise_exception_err (env,EXCP0D_GPF ,0 ); +raise_exception_err_ra (env,EXCP0D_GPF ,0 ,GETPC ()); }#endif - tss_selector =cpu_lduw_kernel (env, env->tr.base +0 ); + tss_selector =cpu_lduw_kernel_ra (env, env->tr.base +0 ,GETPC ());if (tss_selector &4 ) { -raise_exception_err (env,EXCP0A_TSS , tss_selector &0xfffc ); +raise_exception_err_ra (env,EXCP0A_TSS , tss_selector &0xfffc ,GETPC ()); } -if (load_segment (env, &e1, &e2, tss_selector) !=0 ) { -raise_exception_err (env,EXCP0A_TSS , tss_selector &0xfffc ); +if (load_segment (env, &e1, &e2, tss_selector,GETPC ()) !=0 ) { +raise_exception_err_ra (env,EXCP0A_TSS , tss_selector &0xfffc ,GETPC ()); } type = (e2 >>DESC_TYPE_SHIFT ) &0x17 ;/* NOTE: we check both segment and busy TSS */ if (type !=3 ) { -raise_exception_err (env,EXCP0A_TSS , tss_selector &0xfffc ); +raise_exception_err_ra (env,EXCP0A_TSS , tss_selector &0xfffc ,GETPC ()); } -switch_tss (env, tss_selector, e1, e2,SWITCH_TSS_IRET , next_eip); +switch_tss (env, tss_selector, e1, e2,SWITCH_TSS_IRET , next_eip,GETPC ()); }else { -helper_ret_protected (env, shift,1 ,0 ); +helper_ret_protected (env, shift,1 ,0 ,GETPC ()); } env->hflags2 &= ~HF2_NMI_MASK ; }void helper_lret_protected (CPUX86State *env,int shift,int addend) { -helper_ret_protected (env, shift,0 , addend); +helper_ret_protected (env, shift,0 , addend,GETPC ()); }void helper_sysenter (CPUX86State *env) {if (env->sysenter_cs ==0 ) { -raise_exception_err (env,EXCP0D_GPF ,0 ); +raise_exception_err_ra (env,EXCP0D_GPF ,0 ,GETPC ()); } env->eflags &= ~(VM_MASK |IF_MASK |RF_MASK );
@@ -2346,7 +2359,7 @@ void helper_sysexit(CPUX86State *env, int dflag) cpl = env->hflags &HF_CPL_MASK ;if (env->sysenter_cs ==0 || cpl !=0 ) { -raise_exception_err (env,EXCP0D_GPF ,0 ); +raise_exception_err_ra (env,EXCP0D_GPF ,0 ,GETPC ()); }#ifdef TARGET_X86_64 if (dflag ==2 ) {
@@ -2390,7 +2403,7 @@ target_ulong helper_lsl(CPUX86State *env, target_ulong selector1)if ((selector &0xfffc ) ==0 ) { goto fail; } -if (load_segment (env, &e1, &e2, selector) !=0 ) { +if (load_segment (env, &e1, &e2, selector,GETPC ()) !=0 ) { goto fail; } rpl = selector &3 ;
@@ -2437,7 +2450,7 @@ target_ulong helper_lar(CPUX86State *env, target_ulong selector1)if ((selector &0xfffc ) ==0 ) { goto fail; } -if (load_segment (env, &e1, &e2, selector) !=0 ) { +if (load_segment (env, &e1, &e2, selector,GETPC ()) !=0 ) { goto fail; } rpl = selector &3 ;
@@ -2486,7 +2499,7 @@ void helper_verr(CPUX86State *env, target_ulong selector1)if ((selector &0xfffc ) ==0 ) { goto fail; } -if (load_segment (env, &e1, &e2, selector) !=0 ) { +if (load_segment (env, &e1, &e2, selector,GETPC ()) !=0 ) { goto fail; }if (!(e2 &DESC_S_MASK )) {
@@ -2524,7 +2537,7 @@ void helper_verw(CPUX86State *env, target_ulong selector1)if ((selector &0xfffc ) ==0 ) { goto fail; } -if (load_segment (env, &e1, &e2, selector) !=0 ) { +if (load_segment (env, &e1, &e2, selector,GETPC ()) !=0 ) { goto fail; }if (!(e2 &DESC_S_MASK )) {
@@ -2565,7 +2578,8 @@ void cpu_x86_load_seg(CPUX86State *env, int seg_reg, int selector)#endif /* check if Port I/O is allowed in TSS */ -static inline void check_io (CPUX86State *env,int addr,int size) +static inline void check_io (CPUX86State *env,int addr,int size, +uintptr_t retaddr) {int io_offset, val, mask;
@@ -2575,33 +2589,33 @@ static inline void check_io(CPUX86State *env, int addr, int size) env->tr.limit < 103) { goto fail; } - io_offset =cpu_lduw_kernel (env, env->tr.base +0x66 ); + io_offset =cpu_lduw_kernel_ra (env, env->tr.base +0x66 , retaddr); io_offset += (addr >>3 );/* Note: the check needs two bytes */ if ((io_offset +1 ) > env->tr.limit) { goto fail; } - val =cpu_lduw_kernel (env, env->tr.base + io_offset); + val =cpu_lduw_kernel_ra (env, env->tr.base + io_offset, retaddr); val >>= (addr &7 ); mask = (1 << size) -1 ;/* all bits must be zero to allow the I/O */ if ((val & mask) !=0 ) { fail: -raise_exception_err (env,EXCP0D_GPF ,0 ); +raise_exception_err_ra (env,EXCP0D_GPF ,0 , retaddr); } }void helper_check_iob (CPUX86State *env,uint32_t t0) { -check_io (env, t0,1 ); +check_io (env, t0,1 ,GETPC ()); }void helper_check_iow (CPUX86State *env,uint32_t t0) { -check_io (env, t0,2 ); +check_io (env, t0,2 ,GETPC ()); }void helper_check_iol (CPUX86State *env,uint32_t t0) { -check_io (env, t0,4 ); +check_io (env, t0,4 ,GETPC ()); }
Re: [Qemu-devel] [PATCH v5 08/11] target-i386: exception handling for seg_helper functions
Quoted 3 lines · Pavel Dovgalyuk
This patch fixes exception handling for
seg_helperfunctions.Signed-off-by Pavel Dovgalyuk <[email protected]>
No, you don't want to discriminately change every call. That was my original point about not needing to change seg_helper.c or smm_helper.c.
Further, any such changes would go along with the changes in translate.c to remove the state saving there.
I would only change those that are "normal" memory operations, like fp loads etc. The segmentation changes are rare. The task state helpers require state saving anyway, so requiring a TCG search is a pessimization.
r~
Re: [Qemu-devel] [PATCH v5 08/11] target-i386: exception handling for seg_helper functions
Quoted 10 lines
From: Richard Henderson [mailto:[email protected]] On Behalf Of Richard Henderson
Quoted 3 lines · Pavel Dovgalyuk
This patch fixes exception handling for
seg_helperfunctions.Signed-off-by Pavel Dovgalyuk <[email protected]>No, you don't want to discriminately change every call. That was my original point about not needing to change
seg_helper.corsmm_helper.c.
Quoted 6 lines
Further, any such changes would go along with the changes in
translate.cto remove the state saving there.I would only change those that are "normal" memory operations, like fp loads etc. The segmentation changes are rare. The task state helpers require state saving anyway, so requiring a TCG search is a pessimization.
Then we'll have to stop the translation after every instruction that uses these function. Is this a limited subset?
Pavel Dovgalyuk
Re: [Qemu-devel] [PATCH v5 08/11] target-i386: exception handling for seg_helper functions
In reply to Richard HendersonQuoted 10 lines
From: Richard Henderson [mailto:[email protected]] On Behalf Of Richard Henderson
Quoted 3 lines · Pavel Dovgalyuk
This patch fixes exception handling for
seg_helperfunctions.Signed-off-by Pavel Dovgalyuk <[email protected]>No, you don't want to discriminately change every call. That was my original point about not needing to change
seg_helper.corsmm_helper.c.
Quoted 6 lines
Further, any such changes would go along with the changes in
translate.cto remove the state saving there.I would only change those that are "normal" memory operations, like fp loads etc. The segmentation changes are rare. The task state helpers require state saving anyway, so requiring a TCG search is a pessimization.
I can refine the patch, but the most of the changes should remain. E.g., lcall helpers can cause an exception or not. TB ends in both cases. But icount and PC values in these two situations should be different. And lcall helpers use most of the seg functions I changed in the patch.
Pavel Dovgalyuk
PATCH v5 9/11 target-i386: exception handling for other helper functions
In reply to Pavel DovgalyukThis patch fixes exception handling for other helper functions.
Signed-off-by Pavel Dovgalyuk <[email protected]>
--- target-i386/cc_helper.c | 2 +- target-i386/misc_helper.c | 10 +++++----- target-i386/ops_sse.h | 2 +- target-i386/svm_helper.c | 4 ++-- 4 files changed, 9 insertions(+), 9 deletions(-)
target-i386/cc_helper.c +1 -1
@@ -378,7 +378,7 @@ void helper_sti_vm(CPUX86State *env) { env->eflags |=VIF_MASK ;if (env->eflags &VIP_MASK ) { -raise_exception (env,EXCP0D_GPF ); +raise_exception_ra (env,EXCP0D_GPF ,GETPC ()); } }#endif
target-i386/misc_helper.c +5 -5
@@ -220,7 +220,7 @@ void helper_rdtsc(CPUX86State *env)uint64_t val;if ((env->cr[4 ] &CR4_TSD_MASK ) && ((env->hflags &HF_CPL_MASK ) !=0 )) { -raise_exception (env,EXCP0D_GPF ); +raise_exception_ra (env,EXCP0D_GPF ,GETPC ()); }cpu_svm_check_intercept_param (env,SVM_EXIT_RDTSC ,0 );
@@ -238,13 +238,13 @@ void helper_rdtscp(CPUX86State *env)void helper_rdpmc (CPUX86State *env) {if ((env->cr[4 ] &CR4_PCE_MASK ) && ((env->hflags &HF_CPL_MASK ) !=0 )) { -raise_exception (env,EXCP0D_GPF ); +raise_exception_ra (env,EXCP0D_GPF ,GETPC ()); }cpu_svm_check_intercept_param (env,SVM_EXIT_RDPMC ,0 );/* currently unimplemented */ qemu_log_mask (LOG_UNIMP ,"x86: unimplemented rdpmc\n" ); -raise_exception_err (env,EXCP06_ILLOP ,0 ); +raise_exception_err_ra (env,EXCP06_ILLOP ,0 ,GETPC ()); }#if defined(CONFIG_USER_ONLY )
@@ -589,7 +589,7 @@ void helper_hlt(CPUX86State *env, int next_eip_addend)void helper_monitor (CPUX86State *env,target_ulong ptr) {if ((uint32_t )env->regs[R_ECX ] !=0 ) { -raise_exception (env,EXCP0D_GPF ); +raise_exception_ra (env,EXCP0D_GPF ,GETPC ()); }/* XXX: store address? */ cpu_svm_check_intercept_param (env,SVM_EXIT_MONITOR ,0 );
@@ -601,7 +601,7 @@ void helper_mwait(CPUX86State *env, int next_eip_addend)X86CPU *cpu;if ((uint32_t )env->regs[R_ECX ] !=0 ) { -raise_exception (env,EXCP0D_GPF ); +raise_exception_ra (env,EXCP0D_GPF ,GETPC ()); }cpu_svm_check_intercept_param (env,SVM_EXIT_MWAIT ,0 ); env->eip += next_eip_addend;
target-i386/ops_sse.h +1 -1
@@ -483,7 +483,7 @@ void glue(helper_maskmov, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,for (i =0 ; i < (8 <<SHIFT ); i++) {if (s->B (i) &0x80 ) { -cpu_stb_data (env, a0 + i, d->B (i)); +cpu_stb_data_ra (env, a0 + i, d->B (i),GETPC ()); } } }
target-i386/svm_helper.c +2 -2
@@ -354,7 +354,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)void helper_vmmcall (CPUX86State *env) {cpu_svm_check_intercept_param (env,SVM_EXIT_VMMCALL ,0 ); -raise_exception (env,EXCP06_ILLOP ); +raise_exception_ra (env,EXCP06_ILLOP ,GETPC ()); }void helper_vmload (CPUX86State *env,int aflag)
@@ -457,7 +457,7 @@ void helper_skinit(CPUX86State *env) {cpu_svm_check_intercept_param (env,SVM_EXIT_SKINIT ,0 );/* XXX: not implemented */ -raise_exception (env,EXCP06_ILLOP ); +raise_exception_ra (env,EXCP06_ILLOP ,GETPC ()); }void helper_invlpga (CPUX86State *env,int aflag)
PATCH v5 10/11 target-i386: remove useless PC updates
In reply to Pavel DovgalyukThis patch removes useless PC updates before executing instructions. PC can be recovered with correct exception handling by using TB return address.
Signed-off-by Pavel Dovgalyuk <[email protected]>
--- target-i386/translate.c | 25 ------------------------- 1 files changed, 0 insertions(+), 25 deletions(-)
target-i386/translate.c +0 -25
@@ -2303,7 +2303,6 @@ static void gen_movl_seg_T0(DisasContext *s, int seg_reg, target_ulong cur_eip)if (s->pe && !s->vm86) {/* XXX: optimize by finding processor state dynamically */ gen_update_cc_op (s); -gen_jmp_im (cur_eip);tcg_gen_trunc_tl_i32 (cpu_tmp2_i32, cpu_T[0 ]);gen_helper_load_seg (cpu_env,tcg_const_i32 (seg_reg), cpu_tmp2_i32);/* abort translation because the addseg value may change or
@@ -4842,21 +4841,17 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,case 6 :/* div */ switch (ot) {case MO_8 : -gen_jmp_im (pc_start - s->cs_base);gen_helper_divb_AL (cpu_env, cpu_T[0 ]);break ;case MO_16 : -gen_jmp_im (pc_start - s->cs_base);gen_helper_divw_AX (cpu_env, cpu_T[0 ]);break ;default :case MO_32 : -gen_jmp_im (pc_start - s->cs_base);gen_helper_divl_EAX (cpu_env, cpu_T[0 ]);break ;#ifdef TARGET_X86_64 case MO_64 : -gen_jmp_im (pc_start - s->cs_base);gen_helper_divq_EAX (cpu_env, cpu_T[0 ]);break ;#endif
@@ -4865,21 +4860,17 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,case 7 :/* idiv */ switch (ot) {case MO_8 : -gen_jmp_im (pc_start - s->cs_base);gen_helper_idivb_AL (cpu_env, cpu_T[0 ]);break ;case MO_16 : -gen_jmp_im (pc_start - s->cs_base);gen_helper_idivw_AX (cpu_env, cpu_T[0 ]);break ;default :case MO_32 : -gen_jmp_im (pc_start - s->cs_base);gen_helper_idivl_EAX (cpu_env, cpu_T[0 ]);break ;#ifdef TARGET_X86_64 case MO_64 : -gen_jmp_im (pc_start - s->cs_base);gen_helper_idivq_EAX (cpu_env, cpu_T[0 ]);break ;#endif
@@ -5212,7 +5203,6 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,if (dflag ==MO_64 ) {if (!(s->cpuid_ext_features &CPUID_EXT_CX16 )) goto illegal_op; -gen_jmp_im (pc_start - s->cs_base);gen_update_cc_op (s);gen_lea_modrm (env, s, modrm);gen_helper_cmpxchg16b (cpu_env, cpu_A0);
@@ -5221,7 +5211,6 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, {if (!(s->cpuid_features &CPUID_CX8 )) goto illegal_op; -gen_jmp_im (pc_start - s->cs_base);gen_update_cc_op (s);gen_lea_modrm (env, s, modrm);gen_helper_cmpxchg8b (cpu_env, cpu_A0);
@@ -5838,7 +5827,6 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,break ;case 0x0c :/* fldenv mem */ gen_update_cc_op (s); -gen_jmp_im (pc_start - s->cs_base);gen_helper_fldenv (cpu_env, cpu_A0,tcg_const_i32 (dflag -1 ));break ;case 0x0d :/* fldcw mem */
@@ -5848,7 +5836,6 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,break ;case 0x0e :/* fnstenv mem */ gen_update_cc_op (s); -gen_jmp_im (pc_start - s->cs_base);gen_helper_fstenv (cpu_env, cpu_A0,tcg_const_i32 (dflag -1 ));break ;case 0x0f :/* fnstcw mem */
@@ -5858,23 +5845,19 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,break ;case 0x1d :/* fldt mem */ gen_update_cc_op (s); -gen_jmp_im (pc_start - s->cs_base);gen_helper_fldt_ST0 (cpu_env, cpu_A0);break ;case 0x1f :/* fstpt mem */ gen_update_cc_op (s); -gen_jmp_im (pc_start - s->cs_base);gen_helper_fstt_ST0 (cpu_env, cpu_A0);gen_helper_fpop (cpu_env);break ;case 0x2c :/* frstor mem */ gen_update_cc_op (s); -gen_jmp_im (pc_start - s->cs_base);gen_helper_frstor (cpu_env, cpu_A0,tcg_const_i32 (dflag -1 ));break ;case 0x2e :/* fnsave mem */ gen_update_cc_op (s); -gen_jmp_im (pc_start - s->cs_base);gen_helper_fsave (cpu_env, cpu_A0,tcg_const_i32 (dflag -1 ));break ;case 0x2f :/* fnstsw mem */
@@ -5889,7 +5872,6 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,break ;case 0x3e :/* fbstp */ gen_update_cc_op (s); -gen_jmp_im (pc_start - s->cs_base);gen_helper_fbst_ST0 (cpu_env, cpu_A0);gen_helper_fpop (cpu_env);break ;
@@ -5925,7 +5907,6 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,case 0 :/* fnop */ /* check exceptions (FreeBSD FPU probe) */ gen_update_cc_op (s); -gen_jmp_im (pc_start - s->cs_base);gen_helper_fwait (cpu_env);break ;default :
@@ -6896,7 +6877,6 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,gen_exception (s,EXCP07_PREX , pc_start - s->cs_base); }else {gen_update_cc_op (s); -gen_jmp_im (pc_start - s->cs_base);gen_helper_fwait (cpu_env); }break ;
@@ -6980,7 +6960,6 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, goto illegal_op;gen_op_mov_v_reg (ot, cpu_T[0 ], reg);gen_lea_modrm (env, s, modrm); -gen_jmp_im (pc_start - s->cs_base);tcg_gen_trunc_tl_i32 (cpu_tmp2_i32, cpu_T[0 ]);if (ot ==MO_16 ) {gen_helper_boundw (cpu_env, cpu_A0, cpu_tmp2_i32);
@@ -7172,7 +7151,6 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, }else {gen_svm_check_intercept (s, pc_start,SVM_EXIT_LDTR_WRITE );gen_ldst_modrm (env, s, modrm,MO_16 ,OR_TMP0 ,0 ); -gen_jmp_im (pc_start - s->cs_base);tcg_gen_trunc_tl_i32 (cpu_tmp2_i32, cpu_T[0 ]);gen_helper_lldt (cpu_env, cpu_tmp2_i32); }
@@ -7193,7 +7171,6 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, }else {gen_svm_check_intercept (s, pc_start,SVM_EXIT_TR_WRITE );gen_ldst_modrm (env, s, modrm,MO_16 ,OR_TMP0 ,0 ); -gen_jmp_im (pc_start - s->cs_base);tcg_gen_trunc_tl_i32 (cpu_tmp2_i32, cpu_T[0 ]);gen_helper_ltr (cpu_env, cpu_tmp2_i32); }
@@ -7727,7 +7704,6 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, }gen_lea_modrm (env, s, modrm);gen_update_cc_op (s); -gen_jmp_im (pc_start - s->cs_base);gen_helper_fxsave (cpu_env, cpu_A0,tcg_const_i32 (dflag ==MO_64 ));break ;case 1 :/* fxrstor */
@@ -7740,7 +7716,6 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, }gen_lea_modrm (env, s, modrm);gen_update_cc_op (s); -gen_jmp_im (pc_start - s->cs_base);gen_helper_fxrstor (cpu_env, cpu_A0,tcg_const_i32 (dflag ==MO_64 ));break ;case 2 :/* ldmxcsr */
Re: [Qemu-devel] [PATCH v5 10/11] target-i386: remove useless PC updates
Quoted 7 lines · Pavel Dovgalyuk
This patch removes useless PC updates before executing instructions. PC can be recovered with correct exception handling by using TB return address.
Signed-off-by Pavel Dovgalyuk <[email protected]>--- target-i386/translate.c | 25 ------------------------- 1 files changed, 0 insertions(+), 25 deletions(-)
This would be a lot easier to review, if each of this change is actually moved to the corresponding patch passing retaddr to the exception function. In addition to that you have left a few call to gen_update_cc_op(s). They are not needed if the helper doesn't read not write cc_op.
Finally, this patch misses at least helper_fbld_ST0.
Signature · 2 lines
Aurelien Jarno GPG: 4096R/1DDD8C9B [email protected] http://www.aurel32.net
PATCH v5 11/11 target-ppc: exceptions handling in icount mode
In reply to Pavel DovgalyukThis patch fixes exception handling in PowerPC.
Instructions generate several types of exceptions.
When exception is generated, it breaks the execution of the current translation block. Implementation of the exceptions handling does not correctly restore icount for the instruction which caused the exception. In most cases icount will be decreased by the value equal to the size of TB. This patch passes pointer to the translation block internals to the exception handler. It allows correct restoring of the icount value.
Signed-off-by Pavel Dovgalyuk <[email protected]>
--- target-ppc/cpu.h | 3 + target-ppc/excp_helper.c | 38 ++++++-- target-ppc/fpu_helper.c | 191 ++++++++++++++++++++++-------------------- target-ppc/helper.h | 1 target-ppc/mem_helper.c | 6 + target-ppc/misc_helper.c | 8 +- target-ppc/mmu-hash64.c | 12 +-- target-ppc/mmu_helper.c | 18 ++-- target-ppc/timebase_helper.c | 20 ++-- target-ppc/translate.c | 84 +----------------- 10 files changed, 167 insertions(+), 214 deletions(-)
target-ppc/cpu.h +3 -0
@@ -2328,4 +2328,7 @@ int ppc_get_vcpu_dt_id(PowerPCCPU *cpu);*/ PowerPCCPU *ppc_get_vcpu_by_dt_id (int cpu_dt_id); +void raise_exception_err (CPUPPCState *env,uint32_t exception, +uint32_t error_code,uintptr_t pc); +#endif /* !defined (__CPU_PPC_H__) */
target-ppc/excp_helper.c +29 -9
@@ -846,8 +846,8 @@ static void cpu_dump_rfi(target_ulong RA, target_ulong msr)/*****************************************************************************/ /* Exceptions processing helpers */ -void helper_raise_exception_err (CPUPPCState *env,uint32_t exception, -uint32_t error_code) +void raise_exception_err (CPUPPCState *env,uint32_t exception, +uint32_t error_code,uintptr_t pc) {CPUState *cs =CPU (ppc_env_get_cpu (env));
@@ -856,12 +856,29 @@ void helper_raise_exception_err(CPUPPCState *env, uint32_t exception,#endif cs->exception_index = exception; env->error_code = error_code; -cpu_loop_exit (cs); +cpu_loop_exit_restore (cs, pc); +} + +void helper_raise_exception_err (CPUPPCState *env,uint32_t exception, +uint32_t error_code) +{ +raise_exception_err (env, exception, error_code,GETPC ()); +} + +void helper_raise_exception_end (CPUPPCState *env,uint32_t exception, +uint32_t error_code) +{ +raise_exception_err (env, exception, error_code,0 ); }void helper_raise_exception (CPUPPCState *env,uint32_t exception) { -helper_raise_exception_err (env, exception,0 ); +raise_exception_err (env, exception,0 ,GETPC ()); +} + +static void raise_exception (CPUPPCState *env,uint32_t exception,uintptr_t pc) +{ +raise_exception_err (env, exception,0 , pc); }#if !defined(CONFIG_USER_ONLY )
@@ -873,7 +890,8 @@ void helper_store_msr(CPUPPCState *env, target_ulong val)if (val !=0 ) { cs =CPU (ppc_env_get_cpu (env)); cs->interrupt_request |=CPU_INTERRUPT_EXITTB ; -helper_raise_exception (env, val); +/* nip is updated by generated code */ +raise_exception (env, val,0 ); } }
@@ -971,8 +989,9 @@ void helper_tw(CPUPPCState *env, target_ulong arg1, target_ulong arg2, ((int32_t)arg1 == (int32_t)arg2 && (flags & 0x04)) || ((uint32_t)arg1 < (uint32_t)arg2 && (flags & 0x02)) || ((uint32_t)arg1 > (uint32_t)arg2 && (flags & 0x01))))) { -helper_raise_exception_err (env,POWERPC_EXCP_PROGRAM , -POWERPC_EXCP_TRAP ); +/* nip is updated in TB */ +raise_exception_err (env,POWERPC_EXCP_PROGRAM , +POWERPC_EXCP_TRAP ,0 ); } }
@@ -985,8 +1004,9 @@ void helper_td(CPUPPCState *env, target_ulong arg1, target_ulong arg2, ((int64_t)arg1 == (int64_t)arg2 && (flags & 0x04)) || ((uint64_t)arg1 < (uint64_t)arg2 && (flags & 0x02)) || ((uint64_t)arg1 > (uint64_t)arg2 && (flags & 0x01))))) { -helper_raise_exception_err (env,POWERPC_EXCP_PROGRAM , -POWERPC_EXCP_TRAP ); +/* nip is updated in TB */ +raise_exception_err (env,POWERPC_EXCP_PROGRAM , +POWERPC_EXCP_TRAP ,0 ); } }#endif
target-ppc/fpu_helper.c +98 -93
645 lines not on this page · raw message
target-ppc/helper.h +1 -0
@@ -1,4 +1,5 @@ DEF_HELPER_3(raise_exception_err, void, env, i32, i32) +DEF_HELPER_3(raise_exception_end, void, env, i32, i32) DEF_HELPER_2(raise_exception, void, env, i32) DEF_HELPER_4(tw, void, env, tl, tl, i32)#if defined(TARGET_PPC64 )
target-ppc/mem_helper.c +3 -3
@@ -102,9 +102,9 @@ void helper_lswx(CPUPPCState *env, target_ulong addr, uint32_t reg,if (likely (xer_bc !=0 )) {if (unlikely ((ra !=0 && reg < ra && (reg + xer_bc) > ra) || (reg < rb && (reg + xer_bc) > rb))) { -helper_raise_exception_err (env,POWERPC_EXCP_PROGRAM , -POWERPC_EXCP_INVAL | -POWERPC_EXCP_INVAL_LSWX ); +raise_exception_err (env,POWERPC_EXCP_PROGRAM , +POWERPC_EXCP_INVAL | +POWERPC_EXCP_INVAL_LSWX ,GETPC ()); }else {helper_lsw (env, addr, xer_bc, reg); }
target-ppc/misc_helper.c +4 -4
@@ -37,7 +37,7 @@ void helper_store_dump_spr(CPUPPCState *env, uint32_t sprn)#ifdef TARGET_PPC64 static void raise_fu_exception (CPUPPCState *env,uint32_t bit, -uint32_t sprn,uint32_t cause) +uint32_t sprn,uint32_t cause,uintptr_t retaddr) {qemu_log ("Facility SPR %d is unavailable (SPR FSCR:%d)\n" , sprn, bit);
@@ -45,7 +45,7 @@ static void raise_fu_exception(CPUPPCState *env, uint32_t bit, cause &=FSCR_IC_MASK ; env->spr[SPR_FSCR ] |= (target_ulong )cause <<FSCR_IC_POS ; - helper_raise_exception_err(env, POWERPC_EXCP_FU, 0); + raise_exception_err(env, POWERPC_EXCP_FU, 0, retaddr); }#endif
@@ -57,7 +57,7 @@ void helper_fscr_facility_check(CPUPPCState *env, uint32_t bit,/* Facility is enabled, continue */ return; } -raise_fu_exception (env, bit, sprn, cause); +raise_fu_exception (env, bit, sprn, cause,GETPC ());#endif }
@@ -69,7 +69,7 @@ void helper_msr_facility_check(CPUPPCState *env, uint32_t bit,/* Facility is enabled, continue */ return; } -raise_fu_exception (env, bit, sprn, cause); +raise_fu_exception (env, bit, sprn, cause,GETPC ());#endif }
target-ppc/mmu-hash64.c +6 -6
@@ -197,8 +197,8 @@ static int ppc_load_slb_vsid(CPUPPCState *env, target_ulong rb,void helper_store_slb (CPUPPCState *env,target_ulong rb,target_ulong rs) {if (ppc_store_slb (env, rb, rs) <0 ) { -helper_raise_exception_err (env,POWERPC_EXCP_PROGRAM , -POWERPC_EXCP_INVAL ); +raise_exception_err (env,POWERPC_EXCP_PROGRAM , +POWERPC_EXCP_INVAL ,GETPC ()); } }
@@ -207,8 +207,8 @@ target_ulong helper_load_slb_esid(CPUPPCState *env, target_ulong rb)target_ulong rt =0 ;if (ppc_load_slb_esid (env, rb, &rt) <0 ) { -helper_raise_exception_err (env,POWERPC_EXCP_PROGRAM , -POWERPC_EXCP_INVAL ); +raise_exception_err (env,POWERPC_EXCP_PROGRAM , +POWERPC_EXCP_INVAL ,GETPC ()); }return rt; }
@@ -218,8 +218,8 @@ target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb)target_ulong rt =0 ;if (ppc_load_slb_vsid (env, rb, &rt) <0 ) { -helper_raise_exception_err (env,POWERPC_EXCP_PROGRAM , -POWERPC_EXCP_INVAL ); +raise_exception_err (env,POWERPC_EXCP_PROGRAM , +POWERPC_EXCP_INVAL ,GETPC ()); }return rt; }
target-ppc/mmu_helper.c +7 -11
@@ -2635,9 +2635,9 @@ void helper_booke206_tlbwe(CPUPPCState *env) tlb =booke206_cur_tlb (env);if (!tlb) { -helper_raise_exception_err (env,POWERPC_EXCP_PROGRAM , -POWERPC_EXCP_INVAL | -POWERPC_EXCP_INVAL_INVAL ); +raise_exception_err (env,POWERPC_EXCP_PROGRAM , +POWERPC_EXCP_INVAL | +POWERPC_EXCP_INVAL_INVAL ,GETPC ()); }/* check that we support the targeted size */
@@ -2645,9 +2645,9 @@ void helper_booke206_tlbwe(CPUPPCState *env) size_ps =booke206_tlbnps (env, tlbn);if ((env->spr[SPR_BOOKE_MAS1 ] &MAS1_VALID ) && (tlbncfg & TLBnCFG_AVAIL) && !(size_ps & (1 << size_tlb))) { -helper_raise_exception_err (env,POWERPC_EXCP_PROGRAM , -POWERPC_EXCP_INVAL | -POWERPC_EXCP_INVAL_INVAL ); +raise_exception_err (env,POWERPC_EXCP_PROGRAM , +POWERPC_EXCP_INVAL | +POWERPC_EXCP_INVAL_INVAL ,GETPC ()); }if (msr_gs) {
@@ -2924,10 +2924,6 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, ret =cpu_ppc_handle_mmu_fault (env, addr, is_write, mmu_idx); }if (unlikely (ret !=0 )) { -if (likely (retaddr)) { -/* now we have a real cpu fault */ -cpu_restore_state (cs, retaddr); - } -helper_raise_exception_err (env, cs->exception_index, env->error_code); +raise_exception_err (env, cs->exception_index, env->error_code, retaddr); } }
target-ppc/timebase_helper.c +10 -10
@@ -131,14 +131,14 @@ target_ulong helper_load_dcr(CPUPPCState *env, target_ulong dcrn)if (unlikely (env->dcr_env ==NULL )) {qemu_log ("No DCR environment\n" ); -helper_raise_exception_err (env,POWERPC_EXCP_PROGRAM , -POWERPC_EXCP_INVAL | -POWERPC_EXCP_INVAL_INVAL ); +raise_exception_err (env,POWERPC_EXCP_PROGRAM , +POWERPC_EXCP_INVAL | +POWERPC_EXCP_INVAL_INVAL ,GETPC ()); }else if (unlikely (ppc_dcr_read (env->dcr_env, (uint32_t )dcrn, &val) !=0 )) {qemu_log ("DCR read error %d %03x\n" , (uint32_t )dcrn, (uint32_t )dcrn); -helper_raise_exception_err (env,POWERPC_EXCP_PROGRAM , -POWERPC_EXCP_INVAL |POWERPC_EXCP_PRIV_REG ); +raise_exception_err (env,POWERPC_EXCP_PROGRAM , +POWERPC_EXCP_INVAL |POWERPC_EXCP_PRIV_REG ,GETPC ()); }return val; }
@@ -147,13 +147,13 @@ void helper_store_dcr(CPUPPCState *env, target_ulong dcrn, target_ulong val) {if (unlikely (env->dcr_env ==NULL )) {qemu_log ("No DCR environment\n" ); -helper_raise_exception_err (env,POWERPC_EXCP_PROGRAM , -POWERPC_EXCP_INVAL | -POWERPC_EXCP_INVAL_INVAL ); +raise_exception_err (env,POWERPC_EXCP_PROGRAM , +POWERPC_EXCP_INVAL | +POWERPC_EXCP_INVAL_INVAL ,GETPC ()); }else if (unlikely (ppc_dcr_write (env->dcr_env, (uint32_t )dcrn, (uint32_t )val) !=0 )) {qemu_log ("DCR write error %d %03x\n" , (uint32_t )dcrn, (uint32_t )dcrn); -helper_raise_exception_err (env,POWERPC_EXCP_PROGRAM , -POWERPC_EXCP_INVAL |POWERPC_EXCP_PRIV_REG ); +raise_exception_err (env,POWERPC_EXCP_PROGRAM , +POWERPC_EXCP_INVAL |POWERPC_EXCP_PRIV_REG ,GETPC ()); } }
target-ppc/translate.c +6 -78
312 lines not on this page · raw message
Re: [Qemu-devel] [PATCH v5 11/11] target-ppc: exceptions handling in icount mode
Quoted 8 lines · Pavel Dovgalyuk
This patch fixes exception handling in PowerPC.
Instructions generate several types of exceptions.
When exception is generated, it breaks the execution of the current translation block. Implementation of the exceptions handling does not correctly restore icount for the instruction which caused the exception. In most cases icount will be decreased by the value equal to the size of TB. This patch passes pointer to the translation block internals to the exception handler. It allows correct restoring of the icount value.
With this patch, the ppc*-linux-user targets do not build:
| CC ppc-linux-user/target-ppc/excp_helper.o | /home/aurel32/git/qemu/target-ppc/excp_helper.c:879:13: error: ‘raise_exception’ defined but not used [-Werror=unused-function] | static void raise_exception(CPUPPCState *env, uint32_t exception, uintptr_t pc) | ^ | cc1: all warnings being treated as errors | /home/aurel32/git/qemu/rules.mak:57: recipe for target 'target-ppc/excp_helper.o' failed | make[1]: *** [target-ppc/excp_helper.o] Error 1 | Makefile:178: recipe for target 'subdir-ppc-linux-user' failed | make: *** [subdir-ppc-linux-user] Error 2
Quoted 1,356 lines
Signed-off-by Pavel Dovgalyuk <[email protected]>--- target-ppc/cpu.h | 3 + target-ppc/excp_helper.c | 38 ++++++-- target-ppc/fpu_helper.c | 191 ++++++++++++++++++++++-------------------- target-ppc/helper.h | 1 target-ppc/mem_helper.c | 6 + target-ppc/misc_helper.c | 8 +- target-ppc/mmu-hash64.c | 12 +-- target-ppc/mmu_helper.c | 18 ++-- target-ppc/timebase_helper.c | 20 ++-- target-ppc/translate.c | 84 +----------------- 10 files changed, 167 insertions(+), 214 deletions(-)target-ppc/cpu.h +3
-0@@ -2328,4 +2328,7 @@ int ppc_get_vcpu_dt_id(PowerPCCPU *cpu);*/ PowerPCCPU *ppc_get_vcpu_by_dt_id (int cpu_dt_id); +void raise_exception_err (CPUPPCState *env,uint32_t exception, +uint32_t error_code,uintptr_t pc); +#endif /* !defined (__CPU_PPC_H__) */ target-ppc/excp_helper.c +29
-9@@ -846,8 +846,8 @@ static void cpu_dump_rfi(target_ulong RA, target_ulong msr)/*****************************************************************************/ /* Exceptions processing helpers */ -void helper_raise_exception_err (CPUPPCState *env,uint32_t exception, -uint32_t error_code) +void raise_exception_err (CPUPPCState *env,uint32_t exception, +uint32_t error_code,uintptr_t pc) {CPUState *cs =CPU (ppc_env_get_cpu (env));@@ -856,12 +856,29 @@ void helper_raise_exception_err(CPUPPCState *env, uint32_t exception,#endif cs->exception_index = exception; env->error_code = error_code; -cpu_loop_exit (cs); +cpu_loop_exit_restore (cs, pc); +} + +void helper_raise_exception_err (CPUPPCState *env,uint32_t exception, +uint32_t error_code) +{ +raise_exception_err (env, exception, error_code,GETPC ()); +} + +void helper_raise_exception_end (CPUPPCState *env,uint32_t exception, +uint32_t error_code) +{ +raise_exception_err (env, exception, error_code,0 ); }void helper_raise_exception (CPUPPCState *env,uint32_t exception) { -helper_raise_exception_err (env, exception,0 ); +raise_exception_err (env, exception,0 ,GETPC ()); +} + +static void raise_exception (CPUPPCState *env,uint32_t exception,uintptr_t pc) +{ +raise_exception_err (env, exception,0 , pc); }#if !defined(CONFIG_USER_ONLY )@@ -873,7 +890,8 @@ void helper_store_msr(CPUPPCState *env, target_ulong val)if (val !=0 ) { cs =CPU (ppc_env_get_cpu (env)); cs->interrupt_request |=CPU_INTERRUPT_EXITTB ; -helper_raise_exception (env, val); +/* nip is updated by generated code */ +raise_exception (env, val,0 ); } }@@ -971,8 +989,9 @@ void helper_tw(CPUPPCState *env, target_ulong arg1, target_ulong arg2, ((int32_t)arg1 == (int32_t)arg2 && (flags & 0x04)) || ((uint32_t)arg1 < (uint32_t)arg2 && (flags & 0x02)) || ((uint32_t)arg1 > (uint32_t)arg2 && (flags & 0x01))))) { -helper_raise_exception_err (env,POWERPC_EXCP_PROGRAM , -POWERPC_EXCP_TRAP ); +/* nip is updated in TB */ +raise_exception_err (env,POWERPC_EXCP_PROGRAM , +POWERPC_EXCP_TRAP ,0 ); } }@@ -985,8 +1004,9 @@ void helper_td(CPUPPCState *env, target_ulong arg1, target_ulong arg2, ((int64_t)arg1 == (int64_t)arg2 && (flags & 0x04)) || ((uint64_t)arg1 < (uint64_t)arg2 && (flags & 0x02)) || ((uint64_t)arg1 > (uint64_t)arg2 && (flags & 0x01))))) { -helper_raise_exception_err (env,POWERPC_EXCP_PROGRAM , -POWERPC_EXCP_TRAP ); +/* nip is updated in TB */ +raise_exception_err (env,POWERPC_EXCP_PROGRAM , +POWERPC_EXCP_TRAP ,0 ); } }#endif target-ppc/fpu_helper.c +98
-93@@ -116,7 +116,7 @@ void helper_compute_fprf(CPUPPCState *env, uint64_t arg)/* Floating-point invalid operations exception */ static inline uint64_t fload_invalid_op_excp (CPUPPCState *env,int op, -int set_fpcc) +int set_fpcc,uintptr_t retaddr) {CPUState *cs =CPU (ppc_env_get_cpu (env));uint64_t ret =0 ;@@ -199,14 +199,14 @@ static inline uint64_t fload_invalid_op_excp(CPUPPCState *env, int op,/* Update the floating-point enabled exception summary */ env->fpscr |=1 <<FPSCR_FEX ;if (msr_fe0 !=0 || msr_fe1 !=0 ) { -helper_raise_exception_err (env,POWERPC_EXCP_PROGRAM , -POWERPC_EXCP_FP | op); +raise_exception_err (env,POWERPC_EXCP_PROGRAM , +POWERPC_EXCP_FP | op, retaddr); } }return ret; } -static inline void float_zero_divide_excp (CPUPPCState *env) +static inline void float_zero_divide_excp (CPUPPCState *env,uintptr_t retaddr) { env->fpscr |=1 <<FPSCR_ZX ; env->fpscr &= ~((1 <<FPSCR_FR ) | (1 <<FPSCR_FI ));@@ -216,8 +216,8 @@ static inline void float_zero_divide_excp(CPUPPCState *env)/* Update the floating-point enabled exception summary */ env->fpscr |=1 <<FPSCR_FEX ;if (msr_fe0 !=0 || msr_fe1 !=0 ) { -helper_raise_exception_err (env,POWERPC_EXCP_PROGRAM , -POWERPC_EXCP_FP |POWERPC_EXCP_FP_ZX ); +raise_exception_err (env,POWERPC_EXCP_PROGRAM , +POWERPC_EXCP_FP |POWERPC_EXCP_FP_ZX , retaddr); } } }@@ -490,13 +490,13 @@ void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask)helper_store_fpscr (env, arg, mask); } -void helper_float_check_status (CPUPPCState *env) +static void do_float_check_status (CPUPPCState *env,uintptr_t retaddr) {CPUState *cs =CPU (ppc_env_get_cpu (env));int status =get_float_exception_flags (&env->fp_status);if (status & float_flag_divbyzero) { -float_zero_divide_excp (env); +float_zero_divide_excp (env, retaddr); }else if (status & float_flag_overflow) {float_overflow_excp (env); }else if (status & float_flag_underflow) {@@ -509,12 +509,17 @@ void helper_float_check_status(CPUPPCState *env) (env->error_code & POWERPC_EXCP_FP)) {/* Differred floating-point exception after target FPR update */ if (msr_fe0 !=0 || msr_fe1 !=0 ) { -helper_raise_exception_err (env, cs->exception_index, - env->error_code); +raise_exception_err (env, cs->exception_index, + env->error_code, retaddr); } } } +void helper_float_check_status (CPUPPCState *env) +{ +do_float_check_status (env,GETPC ()); +} +void helper_reset_fpstatus (CPUPPCState *env) {set_float_exception_flags (0 , &env->fp_status);@@ -531,12 +536,12 @@ uint64_t helper_fadd(CPUPPCState *env, uint64_t arg1, uint64_t arg2)if (unlikely (float64_is_infinity (farg1.d) &&float64_is_infinity (farg2.d) &&float64_is_neg (farg1.d) !=float64_is_neg (farg2.d))) {/* Magnitude subtraction of infinities */ - farg1.ll =fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXISI ,1 ); + farg1.ll =fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXISI ,1 ,GETPC ()); }else {if (unlikely (float64_is_signaling_nan (farg1.d) ||float64_is_signaling_nan (farg2.d))) {/* sNaN addition */ -fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSNAN ,1 ); +fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSNAN ,1 ,GETPC ()); } farg1.d =float64_add (farg1.d, farg2.d, &env->fp_status); }@@ -555,12 +560,12 @@ uint64_t helper_fsub(CPUPPCState *env, uint64_t arg1, uint64_t arg2)if (unlikely (float64_is_infinity (farg1.d) &&float64_is_infinity (farg2.d) &&float64_is_neg (farg1.d) ==float64_is_neg (farg2.d))) {/* Magnitude subtraction of infinities */ - farg1.ll =fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXISI ,1 ); + farg1.ll =fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXISI ,1 ,GETPC ()); }else {if (unlikely (float64_is_signaling_nan (farg1.d) ||float64_is_signaling_nan (farg2.d))) {/* sNaN subtraction */ -fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSNAN ,1 ); +fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSNAN ,1 ,GETPC ()); } farg1.d =float64_sub (farg1.d, farg2.d, &env->fp_status); }@@ -579,12 +584,12 @@ uint64_t helper_fmul(CPUPPCState *env, uint64_t arg1, uint64_t arg2)if (unlikely ((float64_is_infinity (farg1.d) &&float64_is_zero (farg2.d)) || (float64_is_zero (farg1.d) &&float64_is_infinity (farg2.d)))) {/* Multiplication of zero by infinity */ - farg1.ll =fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXIMZ ,1 ); + farg1.ll =fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXIMZ ,1 ,GETPC ()); }else {if (unlikely (float64_is_signaling_nan (farg1.d) ||float64_is_signaling_nan (farg2.d))) {/* sNaN multiplication */ -fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSNAN ,1 ); +fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSNAN ,1 ,GETPC ()); } farg1.d =float64_mul (farg1.d, farg2.d, &env->fp_status); }@@ -603,15 +608,15 @@ uint64_t helper_fdiv(CPUPPCState *env, uint64_t arg1, uint64_t arg2)if (unlikely (float64_is_infinity (farg1.d) &&float64_is_infinity (farg2.d))) {/* Division of infinity by infinity */ - farg1.ll =fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXIDI ,1 ); + farg1.ll =fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXIDI ,1 ,GETPC ()); }else if (unlikely (float64_is_zero (farg1.d) &&float64_is_zero (farg2.d))) {/* Division of zero by zero */ - farg1.ll =fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXZDZ ,1 ); + farg1.ll =fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXZDZ ,1 ,GETPC ()); }else {if (unlikely (float64_is_signaling_nan (farg1.d) ||float64_is_signaling_nan (farg2.d))) {/* sNaN division */ -fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSNAN ,1 ); +fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSNAN ,1 ,GETPC ()); } farg1.d =float64_div (farg1.d, farg2.d, &env->fp_status); }@@ -630,16 +635,16 @@ uint64_t helper_##op(CPUPPCState *env, uint64_t arg) \ \if (unlikely (env->fp_status.float_exception_flags)) { \if (float64_is_any_nan (arg)) { \ -fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXCVI ,1 ); \ +fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXCVI ,1 ,GETPC ());\if (float64_is_signaling_nan (arg)) { \ -fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSNAN ,1 ); \ +fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSNAN ,1 ,GETPC ());\ } \ farg.ll = nanval; \ }else if (env->fp_status.float_exception_flags & \ float_flag_invalid) { \ -fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXCVI ,1 ); \ +fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXCVI ,1 ,GETPC ());\ } \ -helper_float_check_status (env); \ +do_float_check_status (env,GETPC ()); \ } \return farg.ll; \ }@@ -664,7 +669,7 @@ uint64_t helper_##op(CPUPPCState *env, uint64_t arg) \ }else { \ farg.d =cvtr (arg, &env->fp_status); \ } \ -helper_float_check_status (env); \ +do_float_check_status (env,GETPC ()); \return farg.ll; \ }@@ -674,7 +679,7 @@ FPU_FCFI(fcfidu, uint64_to_float64, 0) FPU_FCFI(fcfidus, uint64_to_float32, 1)static inline uint64_t do_fri (CPUPPCState *env,uint64_t arg, -int rounding_mode) +int rounding_mode,uint64_t retaddr) {CPU_DoubleU farg;@@ -682,7 +687,7 @@ static inline uint64_t do_fri(CPUPPCState *env, uint64_t arg,if (unlikely (float64_is_signaling_nan (farg.d))) {/* sNaN round */ -fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSNAN ,1 ); +fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSNAN ,1 , retaddr); farg.ll = arg |0x0008000000000000ULL ; }else { int inexact = get_float_exception_flags(&env->fp_status) &@@ -697,28 +702,28 @@ static inline uint64_t do_fri(CPUPPCState *env, uint64_t arg, env->fp_status.float_exception_flags &= ~float_flag_inexact; } } -helper_float_check_status (env); +do_float_check_status (env,GETPC ());return farg.ll; }uint64_t helper_frin (CPUPPCState *env,uint64_t arg) { -return do_fri (env, arg, float_round_ties_away); +return do_fri (env, arg, float_round_ties_away,GETPC ()); }uint64_t helper_friz (CPUPPCState *env,uint64_t arg) { -return do_fri (env, arg, float_round_to_zero); +return do_fri (env, arg, float_round_to_zero,GETPC ()); }uint64_t helper_frip (CPUPPCState *env,uint64_t arg) { -return do_fri (env, arg, float_round_up); +return do_fri (env, arg, float_round_up,GETPC ()); }uint64_t helper_frim (CPUPPCState *env,uint64_t arg) { -return do_fri (env, arg, float_round_down); +return do_fri (env, arg, float_round_down,GETPC ()); }/* fmadd - fmadd. */ @@ -734,13 +739,13 @@ uint64_t helper_fmadd(CPUPPCState *env, uint64_t arg1, uint64_t arg2,if (unlikely ((float64_is_infinity (farg1.d) &&float64_is_zero (farg2.d)) || (float64_is_zero (farg1.d) &&float64_is_infinity (farg2.d)))) {/* Multiplication of zero by infinity */ - farg1.ll =fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXIMZ ,1 ); + farg1.ll =fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXIMZ ,1 ,GETPC ()); }else {if (unlikely (float64_is_signaling_nan (farg1.d) ||float64_is_signaling_nan (farg2.d) ||float64_is_signaling_nan (farg3.d))) {/* sNaN operation */ -fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSNAN ,1 ); +fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSNAN ,1 ,GETPC ()); }/* This is the way the PowerPC specification defines it */ float128 ft0_128, ft1_128;@@ -752,7 +757,7 @@ uint64_t helper_fmadd(CPUPPCState *env, uint64_t arg1, uint64_t arg2, float64_is_infinity(farg3.d) && float128_is_neg(ft0_128) != float64_is_neg(farg3.d))) { /* Magnitude subtraction of infinities */ - farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1); + farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1, GETPC()); } else { ft1_128 =float64_to_float128 (farg3.d, &env->fp_status); ft0_128 =float128_add (ft0_128, ft1_128, &env->fp_status);@@ -777,13 +782,13 @@ uint64_t helper_fmsub(CPUPPCState *env, uint64_t arg1, uint64_t arg2, (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) { /* Multiplication of zero by infinity */ - farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1); + farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1, GETPC()); } else {if (unlikely (float64_is_signaling_nan (farg1.d) ||float64_is_signaling_nan (farg2.d) ||float64_is_signaling_nan (farg3.d))) {/* sNaN operation */ -fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSNAN ,1 ); +fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSNAN ,1 ,GETPC ()); }/* This is the way the PowerPC specification defines it */ float128 ft0_128, ft1_128;@@ -795,7 +800,7 @@ uint64_t helper_fmsub(CPUPPCState *env, uint64_t arg1, uint64_t arg2, float64_is_infinity(farg3.d) && float128_is_neg(ft0_128) == float64_is_neg(farg3.d))) { /* Magnitude subtraction of infinities */ - farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1); + farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1, GETPC()); } else { ft1_128 =float64_to_float128 (farg3.d, &env->fp_status); ft0_128 =float128_sub (ft0_128, ft1_128, &env->fp_status);@@ -818,13 +823,13 @@ uint64_t helper_fnmadd(CPUPPCState *env, uint64_t arg1, uint64_t arg2,if (unlikely ((float64_is_infinity (farg1.d) &&float64_is_zero (farg2.d)) || (float64_is_zero (farg1.d) &&float64_is_infinity (farg2.d)))) {/* Multiplication of zero by infinity */ - farg1.ll =fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXIMZ ,1 ); + farg1.ll =fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXIMZ ,1 ,GETPC ()); }else {if (unlikely (float64_is_signaling_nan (farg1.d) ||float64_is_signaling_nan (farg2.d) ||float64_is_signaling_nan (farg3.d))) {/* sNaN operation */ -fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSNAN ,1 ); +fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSNAN ,1 ,GETPC ()); }/* This is the way the PowerPC specification defines it */ float128 ft0_128, ft1_128;@@ -836,7 +841,7 @@ uint64_t helper_fnmadd(CPUPPCState *env, uint64_t arg1, uint64_t arg2, float64_is_infinity(farg3.d) && float128_is_neg(ft0_128) != float64_is_neg(farg3.d))) { /* Magnitude subtraction of infinities */ - farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1); + farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1, GETPC()); } else { ft1_128 =float64_to_float128 (farg3.d, &env->fp_status); ft0_128 =float128_add (ft0_128, ft1_128, &env->fp_status);@@ -863,13 +868,13 @@ uint64_t helper_fnmsub(CPUPPCState *env, uint64_t arg1, uint64_t arg2, (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) { /* Multiplication of zero by infinity */ - farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1); + farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1, GETPC()); } else {if (unlikely (float64_is_signaling_nan (farg1.d) ||float64_is_signaling_nan (farg2.d) ||float64_is_signaling_nan (farg3.d))) {/* sNaN operation */ -fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSNAN ,1 ); +fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSNAN ,1 ,GETPC ()); }/* This is the way the PowerPC specification defines it */ float128 ft0_128, ft1_128;@@ -881,7 +886,7 @@ uint64_t helper_fnmsub(CPUPPCState *env, uint64_t arg1, uint64_t arg2, float64_is_infinity(farg3.d) && float128_is_neg(ft0_128) == float64_is_neg(farg3.d))) { /* Magnitude subtraction of infinities */ - farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1); + farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1, GETPC()); } else { ft1_128 =float64_to_float128 (farg3.d, &env->fp_status); ft0_128 =float128_sub (ft0_128, ft1_128, &env->fp_status);@@ -904,7 +909,7 @@ uint64_t helper_frsp(CPUPPCState *env, uint64_t arg)if (unlikely (float64_is_signaling_nan (farg.d))) {/* sNaN square root */ -fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSNAN ,1 ); +fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSNAN ,1 ,GETPC ()); } f32 =float64_to_float32 (farg.d, &env->fp_status); farg.d =float32_to_float64 (f32, &env->fp_status);@@ -922,12 +927,12 @@ uint64_t helper_fsqrt(CPUPPCState *env, uint64_t arg)if (unlikely (float64_is_any_nan (farg.d))) {if (unlikely (float64_is_signaling_nan (farg.d))) {/* sNaN reciprocal square root */ -fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSNAN ,1 ); +fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSNAN ,1 ,GETPC ()); farg.ll =float64_snan_to_qnan (farg.ll); } }else if (unlikely (float64_is_neg (farg.d) && !float64_is_zero (farg.d))) {/* Square root of a negative nonzero number */ - farg.ll =fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSQRT ,1 ); + farg.ll =fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSQRT ,1 ,GETPC ()); }else { farg.d =float64_sqrt (farg.d, &env->fp_status); }@@ -943,7 +948,7 @@ uint64_t helper_fre(CPUPPCState *env, uint64_t arg)if (unlikely (float64_is_signaling_nan (farg.d))) {/* sNaN reciprocal */ -fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSNAN ,1 ); +fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSNAN ,1 ,GETPC ()); } farg.d =float64_div (float64_one, farg.d, &env->fp_status);return farg.d;@@ -959,7 +964,7 @@ uint64_t helper_fres(CPUPPCState *env, uint64_t arg)if (unlikely (float64_is_signaling_nan (farg.d))) {/* sNaN reciprocal */ -fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSNAN ,1 ); +fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSNAN ,1 ,GETPC ()); } farg.d =float64_div (float64_one, farg.d, &env->fp_status); f32 =float64_to_float32 (farg.d, &env->fp_status);@@ -978,12 +983,12 @@ uint64_t helper_frsqrte(CPUPPCState *env, uint64_t arg)if (unlikely (float64_is_any_nan (farg.d))) {if (unlikely (float64_is_signaling_nan (farg.d))) {/* sNaN reciprocal square root */ -fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSNAN ,1 ); +fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSNAN ,1 ,GETPC ()); farg.ll =float64_snan_to_qnan (farg.ll); } }else if (unlikely (float64_is_neg (farg.d) && !float64_is_zero (farg.d))) {/* Reciprocal square root of a negative nonzero number */ - farg.ll =fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSQRT ,1 ); + farg.ll =fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSQRT ,1 ,GETPC ()); }else { farg.d =float64_sqrt (farg.d, &env->fp_status); farg.d =float64_div (float64_one, farg.d, &env->fp_status);@@ -1102,7 +1107,7 @@ void helper_fcmpu(CPUPPCState *env, uint64_t arg1, uint64_t arg2, && (float64_is_signaling_nan(farg1.d) || float64_is_signaling_nan(farg2.d)))) {/* sNaN comparison */ -fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSNAN ,1 ); +fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSNAN ,1 ,GETPC ()); } }@@ -1134,10 +1139,10 @@ void helper_fcmpo(CPUPPCState *env, uint64_t arg1, uint64_t arg2, float64_is_signaling_nan(farg2.d)) { /* sNaN comparison */ fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN | - POWERPC_EXCP_FP_VXVC, 1); + POWERPC_EXCP_FP_VXVC, 1, GETPC()); } else {/* qNaN comparison */ -fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXVC ,1 ); +fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXVC ,1 ,GETPC ()); } } }@@ -1837,10 +1842,10 @@ void helper_##name(CPUPPCState *env, uint32_t opcode) \ \if (unlikely (tstat.float_exception_flags & float_flag_invalid)) { \ if (tp##_is_infinity(xa.fld) && tp##_is_infinity(xb.fld)) { \ -fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXISI , sfprf); \ +fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXISI , sfprf,GETPC ());\ } else if (tp##_is_signaling_nan(xa.fld) || \ tp##_is_signaling_nan(xb.fld)) { \ -fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSNAN , sfprf); \ +fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSNAN , sfprf,GETPC ());\ } \ } \ \@@ -1853,7 +1858,7 @@ void helper_##name(CPUPPCState *env, uint32_t opcode) \ } \ } \putVSR (xT (opcode), &xt, env); \ -helper_float_check_status (env); \ +do_float_check_status (env,GETPC ()); \ }VSX_ADD_SUB (xsadddp, add,1 , float64,VsrD (0 ),1 ,0 )@@ -1892,10 +1897,10 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \if (unlikely (tstat.float_exception_flags & float_flag_invalid)) { \ if ((tp##_is_infinity(xa.fld) && tp##_is_zero(xb.fld)) || \ (tp##_is_infinity(xb.fld) && tp##_is_zero(xa.fld))) { \ -fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXIMZ , sfprf); \ +fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXIMZ , sfprf,GETPC ());\ } else if (tp##_is_signaling_nan(xa.fld) || \ tp##_is_signaling_nan(xb.fld)) { \ -fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSNAN , sfprf); \ +fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSNAN , sfprf,GETPC ());\ } \ } \ \@@ -1909,7 +1914,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ } \ \putVSR (xT (opcode), &xt, env); \ -helper_float_check_status (env); \ +do_float_check_status (env,GETPC ()); \ }VSX_MUL (xsmuldp,1 , float64,VsrD (0 ),1 ,0 )@@ -1943,13 +1948,13 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ \if (unlikely (tstat.float_exception_flags & float_flag_invalid)) { \ if (tp##_is_infinity(xa.fld) && tp##_is_infinity(xb.fld)) { \ -fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXIDI , sfprf); \ +fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXIDI , sfprf,GETPC ());\ } else if (tp##_is_zero(xa.fld) && \ tp##_is_zero(xb.fld)) { \ -fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXZDZ , sfprf); \ +fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXZDZ , sfprf,GETPC ());\ } else if (tp##_is_signaling_nan(xa.fld) || \ tp##_is_signaling_nan(xb.fld)) { \ -fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSNAN , sfprf); \ +fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSNAN , sfprf,GETPC ());\ } \ } \ \@@ -1963,7 +1968,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ } \ \putVSR (xT (opcode), &xt, env); \ -helper_float_check_status (env); \ +do_float_check_status (env,GETPC ()); \ }VSX_DIV (xsdivdp,1 , float64,VsrD (0 ),1 ,0 )@@ -1990,7 +1995,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ \for (i =0 ; i < nels; i++) { \ if (unlikely(tp##_is_signaling_nan(xb.fld))) { \ -fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSNAN , sfprf); \ +fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSNAN , sfprf,GETPC ());\ } \ xt.fld = tp##_div(tp##_one, xb.fld, &env->fp_status); \ \@@ -2004,7 +2009,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ } \ \putVSR (xT (opcode), &xt, env); \ -helper_float_check_status (env); \ +do_float_check_status (env,GETPC ()); \ }VSX_RE (xsredp,1 , float64,VsrD (0 ),1 ,0 )@@ -2037,9 +2042,9 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ \if (unlikely (tstat.float_exception_flags & float_flag_invalid)) { \ if (tp##_is_neg(xb.fld) && !tp##_is_zero(xb.fld)) { \ -fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSQRT , sfprf); \ +fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSQRT , sfprf,GETPC ());\ } else if (tp##_is_signaling_nan(xb.fld)) { \ -fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSNAN , sfprf); \ +fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSNAN , sfprf,GETPC ());\ } \ } \ \@@ -2053,7 +2058,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ } \ \putVSR (xT (opcode), &xt, env); \ -helper_float_check_status (env); \ +do_float_check_status (env,GETPC ()); \ }VSX_SQRT (xssqrtdp,1 , float64,VsrD (0 ),1 ,0 )@@ -2087,9 +2092,9 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ \if (unlikely (tstat.float_exception_flags & float_flag_invalid)) { \ if (tp##_is_neg(xb.fld) && !tp##_is_zero(xb.fld)) { \ -fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSQRT , sfprf); \ +fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSQRT , sfprf,GETPC ());\ } else if (tp##_is_signaling_nan(xb.fld)) { \ -fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSNAN , sfprf); \ +fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSNAN , sfprf,GETPC ());\ } \ } \ \@@ -2103,7 +2108,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ } \ \putVSR (xT (opcode), &xt, env); \ -helper_float_check_status (env); \ +do_float_check_status (env,GETPC ()); \ }VSX_RSQRTE (xsrsqrtedp,1 , float64,VsrD (0 ),1 ,0 )@@ -2276,20 +2281,20 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ if (tp##_is_signaling_nan(xa.fld) || \ tp##_is_signaling_nan(b->fld) || \ tp##_is_signaling_nan(c->fld)) { \ -fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSNAN , sfprf); \ +fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSNAN , sfprf,GETPC ());\ tstat.float_exception_flags &= ~float_flag_invalid; \ } \ if ((tp##_is_infinity(xa.fld) && tp##_is_zero(b->fld)) || \ (tp##_is_zero(xa.fld) && tp##_is_infinity(b->fld))) { \ xt_out.fld = float64_to_##tp(fload_invalid_op_excp(env, \ - POWERPC_EXCP_FP_VXIMZ, sfprf), &env->fp_status); \ + POWERPC_EXCP_FP_VXIMZ, sfprf, GETPC()), &env->fp_status); \ tstat.float_exception_flags &= ~float_flag_invalid; \ } \ if ((tstat.float_exception_flags & float_flag_invalid) && \ ((tp##_is_infinity(xa.fld) || \ tp##_is_infinity(b->fld)) && \ tp##_is_infinity(c->fld))) { \ - fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, sfprf); \ + fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, sfprf, GETPC());\ } \ } \ \@@ -2302,7 +2307,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ } \ } \putVSR (xT (opcode), &xt_out, env); \ -helper_float_check_status (env); \ +do_float_check_status (env,GETPC ()); \ }#define MADD_FLGS 0@@ -2359,10 +2364,10 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ float64_is_any_nan(xb.VsrD(0)))) { \if (float64_is_signaling_nan (xa.VsrD (0 )) || \float64_is_signaling_nan (xb.VsrD (0 ))) { \ -fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSNAN ,0 ); \ +fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSNAN ,0 ,GETPC ());\ } \if (ordered) { \ -fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXVC ,0 ); \ +fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXVC ,0 ,GETPC ());\ } \ cc =1 ; \ } else { \@@ -2380,7 +2385,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ env->fpscr |= cc <<FPSCR_FPRF ; \ env->crf[BF (opcode)] = cc; \ \ -helper_float_check_status (env); \ +do_float_check_status (env,GETPC ()); \ }VSX_SCALAR_CMP (xscmpodp,1 )@@ -2407,12 +2412,12 @@ void helper_##name(CPUPPCState *env, uint32_t opcode) \ xt.fld = tp##_##op(xa.fld, xb.fld, &env->fp_status); \ if (unlikely(tp##_is_signaling_nan(xa.fld) || \ tp##_is_signaling_nan(xb.fld))) { \ - fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \ + fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0, GETPC()); \ } \ } \ \ putVSR(xT(opcode), &xt, env); \ - helper_float_check_status(env); \ + do_float_check_status(env, GETPC()); \ }VSX_MAX_MIN (xsmaxdp, maxnum,1 , float64,VsrD (0 ))@@ -2447,10 +2452,10 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ tp##_is_any_nan(xb.fld))) { \ if (tp##_is_signaling_nan(xa.fld) || \ tp##_is_signaling_nan(xb.fld)) { \ -fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSNAN ,0 ); \ +fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSNAN ,0 ,GETPC ());\ } \if (svxvc) { \ -fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXVC ,0 ); \ +fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXVC ,0 ,GETPC ());\ } \ xt.fld =0 ; \ all_true =0 ; \@@ -2469,7 +2474,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \if ((opcode >> (31 -21 )) &1 ) { \ env->crf[6 ] = (all_true ?0x8 :0 ) | (all_false ?0x2 :0 ); \ } \ -helper_float_check_status (env); \ +do_float_check_status (env,GETPC ()); \ }VSX_CMP (xvcmpeqdp,2 , float64,VsrD (i), eq,0 )@@ -2500,7 +2505,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \for (i =0 ; i < nels; i++) { \ xt.tfld = stp##_to_##ttp(xb.sfld, &env->fp_status); \ if (unlikely(stp##_is_signaling_nan(xb.sfld))) { \ - fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \ + fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0, GETPC()); \ xt.tfld = ttp##_snan_to_qnan(xt.tfld); \ } \ if (sfprf) { \@@ -2510,7 +2515,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ } \ \putVSR (xT (opcode), &xt, env); \ -helper_float_check_status (env); \ +do_float_check_status (env,GETPC ()); \ }VSX_CVT_FP_TO_FP (xscvdpsp,1 , float64, float32,VsrD (0 ),VsrW (0 ),1 )@@ -2555,21 +2560,21 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \for (i =0 ; i < nels; i++) { \ if (unlikely(stp##_is_any_nan(xb.sfld))) { \ if (stp##_is_signaling_nan(xb.sfld)) { \ -fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSNAN ,0 ); \ +fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSNAN ,0 ,GETPC ());\ } \ -fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXCVI ,0 ); \ +fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXCVI ,0 ,GETPC ()); \ xt.tfld = rnan; \ }else { \ xt.tfld = stp##_to_##ttp##_round_to_zero(xb.sfld, \ &env->fp_status); \if (env->fp_status.float_exception_flags & float_flag_invalid) { \ -fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXCVI ,0 ); \ +fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXCVI ,0 ,GETPC ());\ } \ } \ } \ \putVSR (xT (opcode), &xt, env); \ -helper_float_check_status (env); \ +do_float_check_status (env,GETPC ()); \ } VSX_CVT_FP_TO_INT(xscvdpsxds, 1, float64, int64, VsrD(0), VsrD(0), \@@ -2620,7 +2625,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ } \ \putVSR (xT (opcode), &xt, env); \ -helper_float_check_status (env); \ +do_float_check_status (env,GETPC ()); \ }VSX_CVT_INT_TO_FP (xscvsxddp,1 , int64, float64,VsrD (0 ),VsrD (0 ),1 ,0 )@@ -2664,7 +2669,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ \for (i =0 ; i < nels; i++) { \ if (unlikely(tp##_is_signaling_nan(xb.fld))) { \ -fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSNAN ,0 ); \ +fload_invalid_op_excp (env,POWERPC_EXCP_FP_VXSNAN ,0 ,GETPC ());\ xt.fld = tp##_snan_to_qnan(xb.fld); \ }else { \ xt.fld = tp##_round_to_int(xb.fld, &env->fp_status); \@@ -2683,7 +2688,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ } \ \putVSR (xT (opcode), &xt, env); \ -helper_float_check_status (env); \ +do_float_check_status (env,GETPC ()); \ }VSX_ROUND (xsrdpi,1 , float64,VsrD (0 ), float_round_nearest_even,1 )@@ -2711,6 +2716,6 @@ uint64_t helper_xsrsp(CPUPPCState *env, uint64_t xb)uint64_t xt =helper_frsp (env, xb);helper_compute_fprf (env, xt); -helper_float_check_status (env); +do_float_check_status (env,GETPC ());return xt; }target-ppc/helper.h +1
-0@@ -1,4 +1,5 @@ DEF_HELPER_3(raise_exception_err, void, env, i32, i32) +DEF_HELPER_3(raise_exception_end, void, env, i32, i32) DEF_HELPER_2(raise_exception, void, env, i32) DEF_HELPER_4(tw, void, env, tl, tl, i32)#if defined(TARGET_PPC64 )target-ppc/mem_helper.c +3
-3@@ -102,9 +102,9 @@ void helper_lswx(CPUPPCState *env, target_ulong addr, uint32_t reg,if (likely (xer_bc !=0 )) {if (unlikely ((ra !=0 && reg < ra && (reg + xer_bc) > ra) || (reg < rb && (reg + xer_bc) > rb))) { -helper_raise_exception_err (env,POWERPC_EXCP_PROGRAM , -POWERPC_EXCP_INVAL | -POWERPC_EXCP_INVAL_LSWX ); +raise_exception_err (env,POWERPC_EXCP_PROGRAM , +POWERPC_EXCP_INVAL | +POWERPC_EXCP_INVAL_LSWX ,GETPC ()); }else {helper_lsw (env, addr, xer_bc, reg); }target-ppc/misc_helper.c +4
-4@@ -37,7 +37,7 @@ void helper_store_dump_spr(CPUPPCState *env, uint32_t sprn)#ifdef TARGET_PPC64 static void raise_fu_exception (CPUPPCState *env,uint32_t bit, -uint32_t sprn,uint32_t cause) +uint32_t sprn,uint32_t cause,uintptr_t retaddr) {qemu_log ("Facility SPR %d is unavailable (SPR FSCR:%d)\n" , sprn, bit);@@ -45,7 +45,7 @@ static void raise_fu_exception(CPUPPCState *env, uint32_t bit, cause &=FSCR_IC_MASK ; env->spr[SPR_FSCR ] |= (target_ulong )cause <<FSCR_IC_POS ; - helper_raise_exception_err(env, POWERPC_EXCP_FU, 0); + raise_exception_err(env, POWERPC_EXCP_FU, 0, retaddr); }#endif @@ -57,7 +57,7 @@ void helper_fscr_facility_check(CPUPPCState *env, uint32_t bit,/* Facility is enabled, continue */ return; } -raise_fu_exception (env, bit, sprn, cause); +raise_fu_exception (env, bit, sprn, cause,GETPC ());#endif }@@ -69,7 +69,7 @@ void helper_msr_facility_check(CPUPPCState *env, uint32_t bit,/* Facility is enabled, continue */ return; } -raise_fu_exception (env, bit, sprn, cause); +raise_fu_exception (env, bit, sprn, cause,GETPC ());#endif }target-ppc/mmu-hash64.c +6
-6@@ -197,8 +197,8 @@ static int ppc_load_slb_vsid(CPUPPCState *env, target_ulong rb,void helper_store_slb (CPUPPCState *env,target_ulong rb,target_ulong rs) {if (ppc_store_slb (env, rb, rs) <0 ) { -helper_raise_exception_err (env,POWERPC_EXCP_PROGRAM , -POWERPC_EXCP_INVAL ); +raise_exception_err (env,POWERPC_EXCP_PROGRAM , +POWERPC_EXCP_INVAL ,GETPC ()); } }@@ -207,8 +207,8 @@ target_ulong helper_load_slb_esid(CPUPPCState *env, target_ulong rb)target_ulong rt =0 ;if (ppc_load_slb_esid (env, rb, &rt) <0 ) { -helper_raise_exception_err (env,POWERPC_EXCP_PROGRAM , -POWERPC_EXCP_INVAL ); +raise_exception_err (env,POWERPC_EXCP_PROGRAM , +POWERPC_EXCP_INVAL ,GETPC ()); }return rt; }@@ -218,8 +218,8 @@ target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb)target_ulong rt =0 ;if (ppc_load_slb_vsid (env, rb, &rt) <0 ) { -helper_raise_exception_err (env,POWERPC_EXCP_PROGRAM , -POWERPC_EXCP_INVAL ); +raise_exception_err (env,POWERPC_EXCP_PROGRAM , +POWERPC_EXCP_INVAL ,GETPC ()); }return rt; }target-ppc/mmu_helper.c +7
-11@@ -2635,9 +2635,9 @@ void helper_booke206_tlbwe(CPUPPCState *env) tlb =booke206_cur_tlb (env);if (!tlb) { -helper_raise_exception_err (env,POWERPC_EXCP_PROGRAM , -POWERPC_EXCP_INVAL | -POWERPC_EXCP_INVAL_INVAL ); +raise_exception_err (env,POWERPC_EXCP_PROGRAM , +POWERPC_EXCP_INVAL | +POWERPC_EXCP_INVAL_INVAL ,GETPC ()); }/* check that we support the targeted size */ @@ -2645,9 +2645,9 @@ void helper_booke206_tlbwe(CPUPPCState *env) size_ps =booke206_tlbnps (env, tlbn);if ((env->spr[SPR_BOOKE_MAS1 ] &MAS1_VALID ) && (tlbncfg & TLBnCFG_AVAIL) && !(size_ps & (1 << size_tlb))) { -helper_raise_exception_err (env,POWERPC_EXCP_PROGRAM , -POWERPC_EXCP_INVAL | -POWERPC_EXCP_INVAL_INVAL ); +raise_exception_err (env,POWERPC_EXCP_PROGRAM , +POWERPC_EXCP_INVAL | +POWERPC_EXCP_INVAL_INVAL ,GETPC ()); }if (msr_gs) {@@ -2924,10 +2924,6 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, ret =cpu_ppc_handle_mmu_fault (env, addr, is_write, mmu_idx); }if (unlikely (ret !=0 )) { -if (likely (retaddr)) { -/* now we have a real cpu fault */ -cpu_restore_state (cs, retaddr); - } -helper_raise_exception_err (env, cs->exception_index, env->error_code); +raise_exception_err (env, cs->exception_index, env->error_code, retaddr); } }target-ppc/timebase_helper.c +10
-10@@ -131,14 +131,14 @@ target_ulong helper_load_dcr(CPUPPCState *env, target_ulong dcrn)if (unlikely (env->dcr_env ==NULL )) {qemu_log ("No DCR environment\n" ); -helper_raise_exception_err (env,POWERPC_EXCP_PROGRAM , -POWERPC_EXCP_INVAL | -POWERPC_EXCP_INVAL_INVAL ); +raise_exception_err (env,POWERPC_EXCP_PROGRAM , +POWERPC_EXCP_INVAL | +POWERPC_EXCP_INVAL_INVAL ,GETPC ()); }else if (unlikely (ppc_dcr_read (env->dcr_env, (uint32_t )dcrn, &val) !=0 )) {qemu_log ("DCR read error %d %03x\n" , (uint32_t )dcrn, (uint32_t )dcrn); -helper_raise_exception_err (env,POWERPC_EXCP_PROGRAM , -POWERPC_EXCP_INVAL |POWERPC_EXCP_PRIV_REG ); +raise_exception_err (env,POWERPC_EXCP_PROGRAM , +POWERPC_EXCP_INVAL |POWERPC_EXCP_PRIV_REG ,GETPC ()); }return val; }@@ -147,13 +147,13 @@ void helper_store_dcr(CPUPPCState *env, target_ulong dcrn, target_ulong val) {if (unlikely (env->dcr_env ==NULL )) {qemu_log ("No DCR environment\n" ); -helper_raise_exception_err (env,POWERPC_EXCP_PROGRAM , -POWERPC_EXCP_INVAL | -POWERPC_EXCP_INVAL_INVAL ); +raise_exception_err (env,POWERPC_EXCP_PROGRAM , +POWERPC_EXCP_INVAL | +POWERPC_EXCP_INVAL_INVAL ,GETPC ()); }else if (unlikely (ppc_dcr_write (env->dcr_env, (uint32_t )dcrn, (uint32_t )val) !=0 )) {qemu_log ("DCR write error %d %03x\n" , (uint32_t )dcrn, (uint32_t )dcrn); -helper_raise_exception_err (env,POWERPC_EXCP_PROGRAM , -POWERPC_EXCP_INVAL |POWERPC_EXCP_PRIV_REG ); +raise_exception_err (env,POWERPC_EXCP_PROGRAM , +POWERPC_EXCP_INVAL |POWERPC_EXCP_PRIV_REG ,GETPC ()); } }target-ppc/translate.c +6
-78@@ -288,7 +288,7 @@ static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t } t0 =tcg_const_i32 (excp); t1 =tcg_const_i32 (error); -gen_helper_raise_exception_err (cpu_env, t0, t1); +gen_helper_raise_exception_end (cpu_env, t0, t1);tcg_temp_free_i32 (t0);tcg_temp_free_i32 (t1); ctx->exception = (excp);@@ -296,14 +296,7 @@ static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_tstatic inline void gen_exception (DisasContext *ctx,uint32_t excp) { -TCGv_i32 t0; -if (ctx->exception ==POWERPC_EXCP_NONE ) { -gen_update_nip (ctx, ctx->nip); - } - t0 =tcg_const_i32 (excp); -gen_helper_raise_exception (cpu_env, t0); -tcg_temp_free_i32 (t0); - ctx->exception = (excp); +gen_exception_err (ctx, excp,0 ); }static inline void gen_debug_exception (DisasContext *ctx)@@ -2090,8 +2083,6 @@ static void gen_f##name(DisasContext *ctx) \gen_exception (ctx,POWERPC_EXCP_FPU ); \return ; \ } \ -/* NIP cannot be restored if the memory exception comes from an helper */ \ -gen_update_nip (ctx, ctx->nip -4 ); \gen_reset_fpstatus (); \ gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \ cpu_fpr[rA(ctx->opcode)], \@@ -2119,8 +2110,6 @@ static void gen_f##name(DisasContext *ctx) \gen_exception (ctx,POWERPC_EXCP_FPU ); \return ; \ } \ -/* NIP cannot be restored if the memory exception comes from an helper */ \ -gen_update_nip (ctx, ctx->nip -4 ); \gen_reset_fpstatus (); \ gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \ cpu_fpr[rA(ctx->opcode)], \@@ -2147,8 +2136,6 @@ static void gen_f##name(DisasContext *ctx) \gen_exception (ctx,POWERPC_EXCP_FPU ); \return ; \ } \ -/* NIP cannot be restored if the memory exception comes from an helper */ \ -gen_update_nip (ctx, ctx->nip -4 ); \gen_reset_fpstatus (); \ gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \ cpu_fpr[rA(ctx->opcode)], \@@ -2175,8 +2162,6 @@ static void gen_f##name(DisasContext *ctx) \gen_exception (ctx,POWERPC_EXCP_FPU ); \return ; \ } \ -/* NIP cannot be restored if the memory exception comes from an helper */ \ -gen_update_nip (ctx, ctx->nip -4 ); \gen_reset_fpstatus (); \ gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \ cpu_fpr[rB(ctx->opcode)]); \@@ -2195,8 +2180,6 @@ static void gen_f##name(DisasContext *ctx) \gen_exception (ctx,POWERPC_EXCP_FPU ); \return ; \ } \ -/* NIP cannot be restored if the memory exception comes from an helper */ \ -gen_update_nip (ctx, ctx->nip -4 ); \gen_reset_fpstatus (); \ gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \ cpu_fpr[rB(ctx->opcode)]); \@@ -2231,8 +2214,6 @@ static void gen_frsqrtes(DisasContext *ctx)gen_exception (ctx,POWERPC_EXCP_FPU );return ; } -/* NIP cannot be restored if the memory exception comes from an helper */ -gen_update_nip (ctx, ctx->nip -4 );gen_reset_fpstatus ();gen_helper_frsqrte (cpu_fpr[rD (ctx->opcode)], cpu_env, cpu_fpr[rB (ctx->opcode)]);@@ -2257,8 +2238,6 @@ static void gen_fsqrt(DisasContext *ctx)gen_exception (ctx,POWERPC_EXCP_FPU );return ; } -/* NIP cannot be restored if the memory exception comes from an helper */ -gen_update_nip (ctx, ctx->nip -4 );gen_reset_fpstatus ();gen_helper_fsqrt (cpu_fpr[rD (ctx->opcode)], cpu_env, cpu_fpr[rB (ctx->opcode)]);@@ -2274,8 +2253,6 @@ static void gen_fsqrts(DisasContext *ctx)gen_exception (ctx,POWERPC_EXCP_FPU );return ; } -/* NIP cannot be restored if the memory exception comes from an helper */ -gen_update_nip (ctx, ctx->nip -4 );gen_reset_fpstatus ();gen_helper_fsqrt (cpu_fpr[rD (ctx->opcode)], cpu_env, cpu_fpr[rB (ctx->opcode)]);@@ -2365,8 +2342,6 @@ static void gen_fcmpo(DisasContext *ctx)gen_exception (ctx,POWERPC_EXCP_FPU );return ; } -/* NIP cannot be restored if the memory exception comes from an helper */ -gen_update_nip (ctx, ctx->nip -4 );gen_reset_fpstatus (); crf =tcg_const_i32 (crfD (ctx->opcode)); gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],@@ -2383,8 +2358,6 @@ static void gen_fcmpu(DisasContext *ctx)gen_exception (ctx,POWERPC_EXCP_FPU );return ; } -/* NIP cannot be restored if the memory exception comes from an helper */ -gen_update_nip (ctx, ctx->nip -4 );gen_reset_fpstatus (); crf =tcg_const_i32 (crfD (ctx->opcode)); gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],@@ -2541,8 +2514,6 @@ static void gen_mtfsb0(DisasContext *ctx)gen_reset_fpstatus ();if (likely (crb !=FPSCR_FEX && crb !=FPSCR_VX )) {TCGv_i32 t0; -/* NIP cannot be restored if the memory exception comes from an helper */ -gen_update_nip (ctx, ctx->nip -4 ); t0 =tcg_const_i32 (crb);gen_helper_fpscr_clrbit (cpu_env, t0);tcg_temp_free_i32 (t0);@@ -2567,8 +2538,6 @@ static void gen_mtfsb1(DisasContext *ctx)/* XXX: we pretend we can only do IEEE floating-point computations */ if (likely (crb !=FPSCR_FEX && crb !=FPSCR_VX && crb !=FPSCR_NI )) {TCGv_i32 t0; -/* NIP cannot be restored if the memory exception comes from an helper */ -gen_update_nip (ctx, ctx->nip -4 ); t0 =tcg_const_i32 (crb);gen_helper_fpscr_setbit (cpu_env, t0);tcg_temp_free_i32 (t0);@@ -2598,8 +2567,6 @@ static void gen_mtfsf(DisasContext *ctx)gen_inval_exception (ctx,POWERPC_EXCP_INVAL_INVAL );return ; } -/* NIP cannot be restored if the memory exception comes from an helper */ -gen_update_nip (ctx, ctx->nip -4 );gen_reset_fpstatus ();if (l) { t0 =tcg_const_i32 ((ctx->insns_flags2 &PPC2_ISA205 ) ?0xffff :0xff );@@ -2634,8 +2601,6 @@ static void gen_mtfsfi(DisasContext *ctx)return ; } sh = (8 * w) +7 - bf; -/* NIP cannot be restored if the memory exception comes from an helper */ -gen_update_nip (ctx, ctx->nip -4 );gen_reset_fpstatus (); t0 =tcg_const_i64 (((uint64_t )FPIMM (ctx->opcode)) << (4 * sh)); t1 =tcg_const_i32 (1 << sh);@@ -2718,8 +2683,6 @@ static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)TCGLabel *l1 =gen_new_label ();TCGv t0 =tcg_temp_new ();TCGv_i32 t1, t2; -/* NIP cannot be restored if the memory exception comes from an helper */ -gen_update_nip (ctx, ctx->nip -4 );tcg_gen_andi_tl (t0,EA , mask);tcg_gen_brcondi_tl (TCG_COND_EQ , t0,0 , l1); t1 =tcg_const_i32 (POWERPC_EXCP_ALIGN );@@ -3167,8 +3130,6 @@ static void gen_lmw(DisasContext *ctx)TCGv t0;TCGv_i32 t1;gen_set_access_type (ctx,ACCESS_INT ); -/* NIP cannot be restored if the memory exception comes from an helper */ -gen_update_nip (ctx, ctx->nip -4 ); t0 =tcg_temp_new (); t1 =tcg_const_i32 (rD (ctx->opcode));gen_addr_imm_index (ctx, t0,0 );@@ -3183,8 +3144,6 @@ static void gen_stmw(DisasContext *ctx)TCGv t0;TCGv_i32 t1;gen_set_access_type (ctx,ACCESS_INT ); -/* NIP cannot be restored if the memory exception comes from an helper */ -gen_update_nip (ctx, ctx->nip -4 ); t0 =tcg_temp_new (); t1 =tcg_const_i32 (rS (ctx->opcode));gen_addr_imm_index (ctx, t0,0 );@@ -3220,8 +3179,6 @@ static void gen_lswi(DisasContext *ctx)return ; }gen_set_access_type (ctx,ACCESS_INT ); -/* NIP cannot be restored if the memory exception comes from an helper */ -gen_update_nip (ctx, ctx->nip -4 ); t0 =tcg_temp_new ();gen_addr_register (ctx, t0); t1 =tcg_const_i32 (nb);@@ -3238,8 +3195,6 @@ static void gen_lswx(DisasContext *ctx)TCGv t0;TCGv_i32 t1, t2, t3;gen_set_access_type (ctx,ACCESS_INT ); -/* NIP cannot be restored if the memory exception comes from an helper */ -gen_update_nip (ctx, ctx->nip -4 ); t0 =tcg_temp_new ();gen_addr_reg_index (ctx, t0); t1 =tcg_const_i32 (rD (ctx->opcode));@@ -3259,8 +3214,6 @@ static void gen_stswi(DisasContext *ctx)TCGv_i32 t1, t2;int nb =NB (ctx->opcode);gen_set_access_type (ctx,ACCESS_INT ); -/* NIP cannot be restored if the memory exception comes from an helper */ -gen_update_nip (ctx, ctx->nip -4 ); t0 =tcg_temp_new ();gen_addr_register (ctx, t0);if (nb ==0 )@@ -3279,8 +3232,6 @@ static void gen_stswx(DisasContext *ctx)TCGv t0;TCGv_i32 t1, t2;gen_set_access_type (ctx,ACCESS_INT ); -/* NIP cannot be restored if the memory exception comes from an helper */ -gen_update_nip (ctx, ctx->nip -4 ); t0 =tcg_temp_new ();gen_addr_reg_index (ctx, t0); t1 =tcg_temp_new_i32 ();@@ -4106,7 +4057,7 @@ static void gen_tw(DisasContext *ctx) {TCGv_i32 t0 =tcg_const_i32 (TO (ctx->opcode));/* Update the nip since this might generate a trap exception */ -gen_update_nip (ctx, ctx->nip); +gen_stop_exception (ctx);gen_helper_tw (cpu_env, cpu_gpr[rA (ctx->opcode)], cpu_gpr[rB (ctx->opcode)], t0);tcg_temp_free_i32 (t0);@@ -4118,7 +4069,7 @@ static void gen_twi(DisasContext *ctx)TCGv t0 =tcg_const_tl (SIMM (ctx->opcode));TCGv_i32 t1 =tcg_const_i32 (TO (ctx->opcode));/* Update the nip since this might generate a trap exception */ -gen_update_nip (ctx, ctx->nip); +gen_stop_exception (ctx);gen_helper_tw (cpu_env, cpu_gpr[rA (ctx->opcode)], t0, t1);tcg_temp_free (t0);tcg_temp_free_i32 (t1);@@ -4130,7 +4081,7 @@ static void gen_td(DisasContext *ctx) {TCGv_i32 t0 =tcg_const_i32 (TO (ctx->opcode));/* Update the nip since this might generate a trap exception */ -gen_update_nip (ctx, ctx->nip); +gen_stop_exception (ctx);gen_helper_td (cpu_env, cpu_gpr[rA (ctx->opcode)], cpu_gpr[rB (ctx->opcode)], t0);tcg_temp_free_i32 (t0);@@ -4142,7 +4093,7 @@ static void gen_tdi(DisasContext *ctx)TCGv t0 =tcg_const_tl (SIMM (ctx->opcode));TCGv_i32 t1 =tcg_const_i32 (TO (ctx->opcode));/* Update the nip since this might generate a trap exception */ -gen_update_nip (ctx, ctx->nip); +gen_stop_exception (ctx);gen_helper_td (cpu_env, cpu_gpr[rA (ctx->opcode)], t0, t1);tcg_temp_free (t0);tcg_temp_free_i32 (t1);@@ -4533,8 +4484,6 @@ static void gen_dcbz(DisasContext *ctx)int is_dcbzl = ctx->opcode &0x00200000 ?1 :0 ;gen_set_access_type (ctx,ACCESS_CACHE ); -/* NIP cannot be restored if the memory exception comes from an helper */ -gen_update_nip (ctx, ctx->nip -4 ); tcgv_addr =tcg_temp_new (); tcgv_is_dcbzl =tcg_const_i32 (is_dcbzl);@@ -4577,8 +4526,6 @@ static void gen_icbi(DisasContext *ctx) {TCGv t0;gen_set_access_type (ctx,ACCESS_CACHE ); -/* NIP cannot be restored if the memory exception comes from an helper */ -gen_update_nip (ctx, ctx->nip -4 ); t0 =tcg_temp_new ();gen_addr_reg_index (ctx, t0);gen_helper_icbi (cpu_env, t0);@@ -5072,8 +5019,6 @@ static void gen_lscbx(DisasContext *ctx)TCGv_i32 t3 =tcg_const_i32 (rB (ctx->opcode));gen_addr_reg_index (ctx, t0); -/* NIP cannot be restored if the memory exception comes from an helper */ -gen_update_nip (ctx, ctx->nip -4 );gen_helper_lscbx (t0, cpu_env, t0, t1, t2, t3);tcg_temp_free_i32 (t1);tcg_temp_free_i32 (t2);@@ -6127,8 +6072,6 @@ static void gen_mfdcr(DisasContext *ctx)gen_inval_exception (ctx,POWERPC_EXCP_PRIV_REG );return ; } -/* NIP cannot be restored if the memory exception comes from an helper */ -gen_update_nip (ctx, ctx->nip -4 ); dcrn =tcg_const_tl (SPR (ctx->opcode));gen_helper_load_dcr (cpu_gpr[rD (ctx->opcode)], cpu_env, dcrn);tcg_temp_free (dcrn);@@ -6146,8 +6089,6 @@ static void gen_mtdcr(DisasContext *ctx)gen_inval_exception (ctx,POWERPC_EXCP_PRIV_REG );return ; } -/* NIP cannot be restored if the memory exception comes from an helper */ -gen_update_nip (ctx, ctx->nip -4 ); dcrn =tcg_const_tl (SPR (ctx->opcode));gen_helper_store_dcr (cpu_env, dcrn, cpu_gpr[rS (ctx->opcode)]);tcg_temp_free (dcrn);@@ -6165,8 +6106,6 @@ static void gen_mfdcrx(DisasContext *ctx)gen_inval_exception (ctx,POWERPC_EXCP_PRIV_REG );return ; } -/* NIP cannot be restored if the memory exception comes from an helper */ -gen_update_nip (ctx, ctx->nip -4 );gen_helper_load_dcr (cpu_gpr[rD (ctx->opcode)], cpu_env, cpu_gpr[rA (ctx->opcode)]);/* Note: Rc update flag set leads to undefined state of Rc0 */ @@ -6184,8 +6123,6 @@ static void gen_mtdcrx(DisasContext *ctx)gen_inval_exception (ctx,POWERPC_EXCP_PRIV_REG );return ; } -/* NIP cannot be restored if the memory exception comes from an helper */ -gen_update_nip (ctx, ctx->nip -4 );gen_helper_store_dcr (cpu_env, cpu_gpr[rA (ctx->opcode)], cpu_gpr[rS (ctx->opcode)]);/* Note: Rc update flag set leads to undefined state of Rc0 */ @@ -6195,8 +6132,6 @@ static void gen_mtdcrx(DisasContext *ctx)/* mfdcrux (PPC 460) : user-mode access to DCR */ static void gen_mfdcrux (DisasContext *ctx) { -/* NIP cannot be restored if the memory exception comes from an helper */ -gen_update_nip (ctx, ctx->nip -4 );gen_helper_load_dcr (cpu_gpr[rD (ctx->opcode)], cpu_env, cpu_gpr[rA (ctx->opcode)]);/* Note: Rc update flag set leads to undefined state of Rc0 */ @@ -6205,8 +6140,6 @@ static void gen_mfdcrux(DisasContext *ctx)/* mtdcrux (PPC 460) : user-mode access to DCR */ static void gen_mtdcrux (DisasContext *ctx) { -/* NIP cannot be restored if the memory exception comes from an helper */ -gen_update_nip (ctx, ctx->nip -4 );gen_helper_store_dcr (cpu_env, cpu_gpr[rA (ctx->opcode)], cpu_gpr[rS (ctx->opcode)]);/* Note: Rc update flag set leads to undefined state of Rc0 */ @@ -7915,8 +7848,6 @@ static void gen_##name(DisasContext * ctx) \gen_exception (ctx,POWERPC_EXCP_VSXU ); \return ; \ } \ -/* NIP cannot be restored if the memory exception comes from an helper */ \ -gen_update_nip (ctx, ctx->nip -4 ); \ opc =tcg_const_i32 (ctx->opcode); \ gen_helper_##name(cpu_env, opc); \ tcg_temp_free_i32(opc); \@@ -7929,9 +7860,6 @@ static void gen_##name(DisasContext * ctx) \gen_exception (ctx,POWERPC_EXCP_VSXU ); \return ; \ } \ -/* NIP cannot be restored if the exception comes */ \ -/* from a helper. */ \ -gen_update_nip (ctx, ctx->nip -4 ); \ \ gen_helper_##name(cpu_vsrh(xT(ctx->opcode)), cpu_env, \ cpu_vsrh(xB(ctx->opcode))); \
Signature · 2 lines
Aurelien Jarno GPG: 4096R/1DDD8C9B [email protected] http://www.aurel32.net