mmc:fsl_esdhc invalidate dcache before read

PATCH New Peng Fan 4 participants 8 messages Jun 25, 2015 – Jul 27, 2015 MMC, SD and SDIO

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Peng Fan

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2015-06-25 02:32 UTC #0 lore raw

PATCH 1/1 mmc:fsl_esdhc invalidate dcache before read

DCIMVAC is upgraded to DCCIMVAC for the individual processor (Cortex-A7) that the DCIMVAC is executed on.

We should follow the linux dma follow. Before DMA read, first invalidate dcache then after DMA read, invalidate dcache again.

With the DMA direction DMA_FROM_DEVICE, the dcache need be invalidated again after the DMA completion. The reason is
that we need explicity make sure the dcache been invalidated thus to get the DMA'ed memory correctly from the physical memory. Any cache-line fill during the DMA operations such as the pre-fetching can cause the DMA coherency issue, thus CPU get the stale data.

Signed-off-by Peng Fan <[email protected]>

Signed-off-by Ye.Li <[email protected]>

Signed-off-by Nitin Garg <[email protected]>

Signed-off-by Jason Liu <[email protected]>

---
 drivers/mmc/fsl_esdhc.c | 8 ++++++++
 1 file changed, 8 insertions(+)

drivers/mmc/fsl_esdhc.c +8 -0

index c4719e6..0510bf0 100644
@@ -341,6 +341,9 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 		err = esdhc_setup_data(mmc, data);
 		if(err)
 			return err;
+
+		if (data->flags & MMC_DATA_READ)
+			check_and_invalidate_dcache_range(cmd, data);
 	}
 
 	/* Figure out the transfer arguments */

@@ -437,6 +440,11 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 			}
 		} while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
 
+		/*
+		 * Need invalidate the dcache here again to avoid any
+		 * cache-fill during the DMA operations such as the
+		 * speculative pre-fetching etc.
+		 */
 		if (data->flags & MMC_DATA_READ)
 			check_and_invalidate_dcache_range(cmd, data);
 #endif

Signature · 1 line

1.8.4

Peng Fan

2015-07-10 00:21 UTC #1 lore raw

PATCH 1/1 mmc:fsl_esdhc invalidate dcache before read

Ping. Anyone review/apply this patch?

Quoted 55 lines · Peng Fan

DCIMVAC is upgraded to DCCIMVAC for the individual processor (Cortex-A7) that the DCIMVAC is executed on.
We should follow the linux dma follow. Before DMA read, first invalidate dcache then after DMA read, invalidate dcache again.
With the DMA direction DMA_FROM_DEVICE, the dcache need be invalidated again after the DMA completion. The reason is
that we need explicity make sure the dcache been invalidated thus to get the DMA'ed memory correctly from the physical memory. Any cache-line fill during the DMA operations such as the pre-fetching can cause the DMA coherency issue, thus CPU get the stale data.
Signed-off-by Peng Fan <[email protected]>
Signed-off-by Ye.Li <[email protected]>
Signed-off-by Nitin Garg <[email protected]>
Signed-off-by Jason Liu <[email protected]>
---
drivers/mmc/fsl_esdhc.c | 8 ++++++++
1 file changed, 8 insertions(+)
drivers/mmc/fsl_esdhc.c +8 -0
index c4719e6..0510bf0 100644
@@ -341,6 +341,9 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 		err = esdhc_setup_data(mmc, data);
 		if(err)
 			return err;
+
+		if (data->flags & MMC_DATA_READ)
+			check_and_invalidate_dcache_range(cmd, data);
 	}
 
 	/* Figure out the transfer arguments */
@@ -437,6 +440,11 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 			}
 		} while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
 
+		/*
+		 * Need invalidate the dcache here again to avoid any
+		 * cache-fill during the DMA operations such as the
+		 * speculative pre-fetching etc.
+		 */
 		if (data->flags & MMC_DATA_READ)
 			check_and_invalidate_dcache_range(cmd, data);
 #endif
Signature · 7 lines
1.8.4


_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Regards,
Peng.

Stefano Babic

2015-07-10 07:56 UTC #2 lore raw

PATCH 1/1 mmc:fsl_esdhc invalidate dcache before read

In reply to Peng Fan

Hi Peng,

I see this patch is now delegated to me. Then, I have no objections to merge it into u-boot-imx if Pantelis agree.

Quoted 3 lines · Peng Fan

DCIMVAC is upgraded to DCCIMVAC for the individual processor (Cortex-A7) that the DCIMVAC is executed on.

Can you better explain it ? What are the consequences of using DCCIMVAC into this driver ?

This driver is not only for i.MX. It runs on PowerPc, too. Do you tested this patch on PowerPC architecture, too ? Maybe someone else can do it ?

Quoted 35 lines

We should follow the linux dma follow. Before DMA read, first invalidate dcache then after DMA read, invalidate dcache again.
With the DMA direction DMA_FROM_DEVICE, the dcache need be invalidated again after the DMA completion. The reason is
that we need explicity make sure the dcache been invalidated thus to get the DMA'ed memory correctly from the physical memory. Any cache-line fill during the DMA operations such as the pre-fetching can cause the DMA coherency issue, thus CPU get the stale data.
Signed-off-by Peng Fan <[email protected]>
Signed-off-by Ye.Li <[email protected]>
Signed-off-by Nitin Garg <[email protected]>
Signed-off-by Jason Liu <[email protected]>
---
 drivers/mmc/fsl_esdhc.c | 8 ++++++++
 1 file changed, 8 insertions(+)
drivers/mmc/fsl_esdhc.c +3 -0
index c4719e6..0510bf0 100644
@@ -341,6 +341,9 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 		err = esdhc_setup_data(mmc, data);
 		if(err)
 			return err;
+
+		if (data->flags & MMC_DATA_READ)
+			check_and_invalidate_dcache_range(cmd, data);
 	}
 
 	/* Figure out the transfer arguments */
@@ -437,6 +440,11 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 			}

drivers/mmc/fsl_esdhc.c esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) · line 450

Quoted 10 lines

drivers/mmc/fsl_esdhc.c +5 -0

 		} while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
 
+		/*
+		 * Need invalidate the dcache here again to avoid any
+		 * cache-fill during the DMA operations such as the
+		 * speculative pre-fetching etc.
+		 */
 		if (data->flags & MMC_DATA_READ)
 			check_and_invalidate_dcache_range(cmd, data);
 #endif

From my side it is ok.

Reviewed-by Stefano Babic <[email protected]>

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Peng Fan

2015-07-11 02:43 UTC #3 lore raw

PATCH 1/1 mmc:fsl_esdhc invalidate dcache before read

Hi Stefano,

Quoted 7 lines · Stefano Babic

Hi Peng,
I see this patch is now delegated to me. Then, I have no objections to merge it into u-boot-imx if Pantelis agree.

Quoted 6 lines

Quoted 3 lines · Peng Fan
DCIMVAC is upgraded to DCCIMVAC for the individual processor (Cortex-A7) that the DCIMVAC is executed on.
Can you better explain it ? What are the consequences of using DCCIMVAC into this driver ?

This is from http://infocenter.arm.com/help/topic/com.arm.doc.ddi0464f/DDI0464F_cortex_a7_mpcore_r0p5_trm.pdf

"
DCIMVAC means Data cache invalidate by MVA to PoC DCCIMVAC means Data cache clean and invalidate line by MVA to PoC

DCIMVAC is upgraded to DCCIMVAC for the individual processor that the DCIMVAC is executed on. Additionally, if the DCIMVAC is executed from a Non-secure state other than Hyp mode without second state write permissions then the DCIMVAC is upgraded to DCCIMVAC when broadcast to other processors or broadcast on the ACE interface.
"
See page 4-9, Table 4-8 c7 register summary (continued).

Quoted 3 lines

This driver is not only for i.MX. It runs on PowerPc, too. Do you tested this patch on PowerPC architecture, too ? Maybe someone else can do it ?

I do not have Powerpc board to test this patch.

York, do you have such a board or is this patch is ok for powerpc?

Quoted 37 lines

Quoted 37 lines
We should follow the linux dma follow. Before DMA read, first invalidate dcache then after DMA read, invalidate dcache again.
With the DMA direction DMA_FROM_DEVICE, the dcache need be invalidated again after the DMA completion. The reason is
that we need explicity make sure the dcache been invalidated thus to get the DMA'ed memory correctly from the physical memory. Any cache-line fill during the DMA operations such as the pre-fetching can cause the DMA coherency issue, thus CPU get the stale data.
Signed-off-by Peng Fan <[email protected]>
Signed-off-by Ye.Li <[email protected]>
Signed-off-by Nitin Garg <[email protected]>
Signed-off-by Jason Liu <[email protected]>
---
 drivers/mmc/fsl_esdhc.c | 8 ++++++++
 1 file changed, 8 insertions(+)
drivers/mmc/fsl_esdhc.c +3 -0
index c4719e6..0510bf0 100644
@@ -341,6 +341,9 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 		err = esdhc_setup_data(mmc, data);
 		if(err)
 			return err;
+
+		if (data->flags & MMC_DATA_READ)
+			check_and_invalidate_dcache_range(cmd, data);
 	}
 
 	/* Figure out the transfer arguments */
@@ -437,6 +440,11 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 			}
 		} while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
 

Quoted 10 lines

drivers/mmc/fsl_esdhc.c esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) · line 450
Quoted 9 lines
drivers/mmc/fsl_esdhc.c +5 -0
+		/*
+		 * Need invalidate the dcache here again to avoid any
+		 * cache-fill during the DMA operations such as the
+		 * speculative pre-fetching etc.
+		 */
 		if (data->flags & MMC_DATA_READ)
 			check_and_invalidate_dcache_range(cmd, data);
 #endif

From my side it is ok.

Quoted 14 lines

Reviewed-by Stefano Babic <[email protected]>

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Regards,
Peng

Stefano Babic

2015-07-26 10:20 UTC #4 lore raw

PATCH 1/1 mmc:fsl_esdhc invalidate dcache before read

Hi Peng,

Quoted 32 lines · Peng Fan

Hi Stefano,
Quoted 7 lines · Stefano Babic
Hi Peng,
I see this patch is now delegated to me. Then, I have no objections to merge it into u-boot-imx if Pantelis agree.
Quoted 6 lines
Quoted 3 lines · Peng Fan
DCIMVAC is upgraded to DCCIMVAC for the individual processor (Cortex-A7) that the DCIMVAC is executed on.
Can you better explain it ? What are the consequences of using DCCIMVAC into this driver ?
This is from http://infocenter.arm.com/help/topic/com.arm.doc.ddi0464f/DDI0464F_cortex_a7_mpcore_r0p5_trm.pdf
"
DCIMVAC means Data cache invalidate by MVA to PoC DCCIMVAC means Data cache clean and invalidate line by MVA to PoC
DCIMVAC is upgraded to DCCIMVAC for the individual processor that the DCIMVAC is executed on. Additionally, if the DCIMVAC is executed from a Non-secure state other than Hyp mode without second state write permissions then the DCIMVAC is upgraded to DCCIMVAC when broadcast to other processors or broadcast on the ACE interface.
"
See page 4-9, Table 4-8 c7 register summary (continued).
Quoted 1 line

Quoted 58 lines

Quoted 2 lines
This driver is not only for i.MX. It runs on PowerPc, too. Do you tested this patch on PowerPC architecture, too ? Maybe someone else can do it ?
I do not have Powerpc board to test this patch.
York, do you have such a board or is this patch is ok for powerpc?
Quoted 51 lines
Quoted 36 lines
We should follow the linux dma follow. Before DMA read, first invalidate dcache then after DMA read, invalidate dcache again.
With the DMA direction DMA_FROM_DEVICE, the dcache need be invalidated again after the DMA completion. The reason is
that we need explicity make sure the dcache been invalidated thus to get the DMA'ed memory correctly from the physical memory. Any cache-line fill during the DMA operations such as the pre-fetching can cause the DMA coherency issue, thus CPU get the stale data.
Signed-off-by Peng Fan <[email protected]>
Signed-off-by Ye.Li <[email protected]>
Signed-off-by Nitin Garg <[email protected]>
Signed-off-by Jason Liu <[email protected]>
---
 drivers/mmc/fsl_esdhc.c | 8 ++++++++
 1 file changed, 8 insertions(+)
drivers/mmc/fsl_esdhc.c +3 -0
index c4719e6..0510bf0 100644
@@ -341,6 +341,9 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 		err = esdhc_setup_data(mmc, data);
 		if(err)
 			return err;
+
+		if (data->flags & MMC_DATA_READ)
+			check_and_invalidate_dcache_range(cmd, data);
 	}
 
 	/* Figure out the transfer arguments */
@@ -437,6 +440,11 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 			}
drivers/mmc/fsl_esdhc.c esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) · line 450
Quoted 10 lines
drivers/mmc/fsl_esdhc.c +5 -0
 		} while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
 
+		/*
+		 * Need invalidate the dcache here again to avoid any
+		 * cache-fill during the DMA operations such as the
+		 * speculative pre-fetching etc.
+		 */
 		if (data->flags & MMC_DATA_READ)
 			check_and_invalidate_dcache_range(cmd, data);
 #endif
From my side it is ok.
Reviewed-by Stefano Babic <[email protected]>

I apply it to u-boot-imx - merging into mainline, we will have more chances to get it tested on PowerPc.

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

York Sun

2015-07-27 16:36 UTC #5 lore raw

PATCH 1/1 mmc:fsl_esdhc invalidate dcache before read

Quoted 5 lines · Stefano Babic

I apply it to u-boot-imx - merging into mainline, we will have more chances to get it tested on PowerPc.
Applied to u-boot-imx, thanks !

Sorry I didn't see this thread until Stefano CC'ed me. I will see if I can test it on powerpc boards.

York

York Sun

2015-07-27 18:15 UTC #6 lore raw

PATCH 1/1 mmc:fsl_esdhc invalidate dcache before read

Quoted 12 lines · York Sun

Quoted 5 lines · Stefano Babic
I apply it to u-boot-imx - merging into mainline, we will have more chances to get it tested on PowerPc.
Applied to u-boot-imx, thanks !
Sorry I didn't see this thread until Stefano CC'ed me. I will see if I can test it on powerpc boards.

The change is safe for powerpc. Verified on T4240RDB with SD read/write.

York

Stefano Babic

2015-07-27 18:55 UTC #7 lore raw

PATCH 1/1 mmc:fsl_esdhc invalidate dcache before read

Quoted 9 lines · York Sun

Quoted 6 lines · York Sun
Quoted 3 lines · Stefano Babic
I apply it to u-boot-imx - merging into mainline, we will have more chances to get it tested on PowerPc.

Quoted 9 lines

Quoted 6 lines
Quoted 2 lines
Applied to u-boot-imx, thanks !
Sorry I didn't see this thread until Stefano CC'ed me. I will see if I can test it on powerpc boards.
The change is safe for powerpc. Verified on T4240RDB with SD read/write.

Thanks !

Regards,
Stefano

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================