drivers/ddr/altera: Add the DDR controller driver for SoCFPGA
Subsystems (2)
v4 cover drivers/ddr/altera: Add the DDR controller driver for SoCFPGA
From: Dinh Nguyen <[email protected]>
Hi,
This is v4 of the patch series that adds the DDR controller driver for Altera's SoCFPGA platform.
v4:
- Further cleanup by removing comments that do not apply for Cyclone5.
- Removed more unused functions
Thanks,
Dinh Nguyen (3):
driver/ddr/altera: Add DDR driver for Altera's SDRAM controller driver/ddr/altera: Add the sdram calibration portion
arm: socfpga: enable the Altera SDRAM controller driver
Makefile | 1 + arch/arm/include/asm/arch-socfpga/sdram.h | 306 ++ arch/arm/include/asm/arch-socfpga/sdram_config.h | 100 + drivers/ddr/altera/Makefile | 11 + drivers/ddr/altera/sdram.c | 799 +++++ drivers/ddr/altera/sequencer.c | 4051 ++++++++++++++++++++++ drivers/ddr/altera/sequencer.h | 322 ++ drivers/ddr/altera/sequencer_auto.h | 128 + drivers/ddr/altera/sequencer_auto_ac_init.h | 84 + drivers/ddr/altera/sequencer_auto_inst_init.h | 268 ++ drivers/ddr/altera/sequencer_defines.h | 121 + include/configs/socfpga_common.h | 5 + scripts/Makefile.spl | 1 + 13 files changed, 6197 insertions(+) create mode 100644 arch/arm/include/asm/arch-socfpga/sdram.h create mode 100644 arch/arm/include/asm/arch-socfpga/sdram_config.h create mode 100644 drivers/ddr/altera/Makefile create mode 100644 drivers/ddr/altera/sdram.c create mode 100644 drivers/ddr/altera/sequencer.c create mode 100644 drivers/ddr/altera/sequencer.h create mode 100644 drivers/ddr/altera/sequencer_auto.h create mode 100644 drivers/ddr/altera/sequencer_auto_ac_init.h create mode 100644 drivers/ddr/altera/sequencer_auto_inst_init.h create mode 100644 drivers/ddr/altera/sequencer_defines.h
Signature · 1 line
2.2.1
PATCH v4 1/3 driver/ddr/altera: Add DDR driver for Altera's SDRAM controller
From: Dinh Nguyen <[email protected]>
This patch enables the SDRAM controller that is used on Altera's SoCFPGA family. This patch configures the SDRAM controller based on a configuration file that is generated from the Quartus tool, sdram_config.h.
---
v4: none
v3: none
v2: clean up from comments from Pavel
--- Makefile | 1 + arch/arm/include/asm/arch-socfpga/sdram.h | 306 +++++++++ arch/arm/include/asm/arch-socfpga/sdram_config.h | 100 +++ drivers/ddr/altera/sdram.c | 799 +++++++++++++++++++++++ scripts/Makefile.spl | 1 + 5 files changed, 1207 insertions(+) create mode 100644 arch/arm/include/asm/arch-socfpga/sdram.h create mode 100644 arch/arm/include/asm/arch-socfpga/sdram_config.h create mode 100644 drivers/ddr/altera/sdram.c
Makefile +1 -0
@@ -649,6 +649,7 @@ libs-y += drivers/power/ \ libs-y += drivers/spi/ libs-$(CONFIG_FMAN_ENET) += drivers/net/fm/ libs-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/ +libs-$(CONFIG_ALTERA_SDRAM) += drivers/ddr/altera/ libs-y += drivers/serial/ libs-y += drivers/usb/dwc3/ libs-y += drivers/usb/eth/
arch/arm/include/asm/arch-socfpga/sdram.h new file +306 -0
306 lines not on this page · raw message
arch/arm/include/asm/arch-socfpga/sdram_config.h new file +100 -0
100 lines not on this page · raw message
drivers/ddr/altera/sdram.c new file +799 -0
799 lines not on this page · raw message
scripts/Makefile.spl +1 -0
@@ -60,6 +60,7 @@ libs-$(CONFIG_SPL_GPIO_SUPPORT) += drivers/gpio/ libs-$(CONFIG_SPL_MMC_SUPPORT) += drivers/mmc/ libs-$(CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT) += drivers/ddr/fsl/ libs-$(CONFIG_SYS_MVEBU_DDR) += drivers/ddr/mvebu/ +libs-$(CONFIG_ALTERA_SDRAM) += drivers/ddr/altera/ libs-$(CONFIG_SPL_SERIAL_SUPPORT) += drivers/serial/ libs-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += drivers/mtd/spi/ libs-$(CONFIG_SPL_SPI_SUPPORT) += drivers/spi/
Signature · 1 line
2.2.1
PATCH v4 1/3 driver/ddr/altera: Add DDR driver for Altera's SDRAM controller
Hi!
arch/arm/include/asm/arch-socfpga/sdram.h line 80
Quoted 5 lines
arch/arm/include/asm/arch-socfpga/sdram.h new file +5
-0+struct sdram_prot_rule { +uint64_t sdram_start;/* SDRAM start address */ +uint64_t sdram_end;/* SDRAM end address */ +uint32_t rule;/* SDRAM protection rule number: 0-19 */ +int valid;/* Rule valid or not? 1 - valid, 0 not*/
There should be space before "*/".
arch/arm/include/asm/arch-socfpga/sdram_config.h line 7
Quoted 13 lines
arch/arm/include/asm/arch-socfpga/sdram_config.h new file +7
-0@@ -0,0 +1,100 @@ +/* +* Copyright Altera Corporation (C) 2012-2015 +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/* This file is autogenerated from tools provided by Altera.*/
Here too.
arch/arm/include/asm/arch-socfpga/sdram_config.h line 100
Quoted 1 line
arch/arm/include/asm/arch-socfpga/sdram_config.h new file +1
-0+#endif /*#ifndef__SDRAM_CONFIG_H*/
You should not need to comment for include guards... (and comment style).
arch/arm/include/asm/arch-socfpga/sdram_config.h line 11
Quoted 3 lines
arch/arm/include/asm/arch-socfpga/sdram_config.h new file +3
-0+static int compute_errata_rows (unsigned long long memsize,int cs,int width, +int rows,int banks,int cols) +{
Comment what kind of errata this is working around?
arch/arm/include/asm/arch-socfpga/sdram_config.h line 17
Quoted 6 lines
arch/arm/include/asm/arch-socfpga/sdram_config.h new file +6
-0+#if defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS ) && \ +defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS ) && \ +defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS ) && \ +defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS ) && \ +defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS ) +
Hmm? Is this really neccessary? Is it valid to provide configuration w/o those defines?
arch/arm/include/asm/arch-socfpga/sdram_config.h
Quoted 10 lines
arch/arm/include/asm/arch-socfpga/sdram_config.h new file +9
-0+writel (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS , + &sysmgr_regs->iswgrp_handoff[4 ]); +#endif + +/* Restore the SDR PHY Register if valid */ +if (sdr_phy_reg !=0xffffffff ) +writel (sdr_phy_reg, &sdr_ctrl->phy_ctrl0); + +/***** Final step - apply configuration changes *****/
Comment style...
Quoted 21 lines
arch/arm/include/asm/arch-socfpga/sdram_config.h new file +21
-0+/* +* To calculate SDRAM device size based on SDRAM controller parameters. +* Size is specified in bytes. +* +* NOTE: +* This function is compiled and linked into the preloader and +* Uboot (there may be others). So if this function changes, the Preloader +* and UBoot must be updated simultaneously. +*/ +unsigned long sdram_calculate_size (void ) +{ +unsigned long temp; +unsigned long row, bank, col, cs, width; + + temp =readl (&sdr_ctrl->dram_addrw); + col = (temp &SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK ) >> +SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB ; + +/* SDRAM Failure When Accessing Non-Existent Memory +* Use ROWBITS from Quartus/QSys to calculate SDRAM size +* since the FB specifies we modify ROWBITs to work around SDRAM
arch/arm/include/asm/arch-socfpga/sdram_config.h
Quoted 10 lines
arch/arm/include/asm/arch-socfpga/sdram_config.h new file +10
-0+* controller issue. +* +* If the stored handoff value for rows is 0, it probably means +* the preloader is older than UBoot. Use the +* #define from the SOCEDS Tools per Crucible review +* uboot-socfpga-204. Note that this is not a supported +* configuration and is not tested. The customer +* should be using preloader and uboot built from the +* same tag. +*/
U-Boot is normally spelled "U-Boot". You have two different variants in comments here.
Second part of the comment is probably not relevant any more....?
Pavel
Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
PATCH v4 1/3 driver/ddr/altera: Add DDR driver for Altera's SDRAM controller
Dear Pavel,
Quoted 3 lines · In message <20150609115532.GA29408@amd> you wrote:
U-Boot is normally spelled "U-Boot". You have two different variants in comments here.
Thanks for pointing out. This is actually quite important as "U-Boot" is _not_ a copyrighted name, while some other spellings are (search for text "u-boot" at [1]).
For example, "uboot" is a registered trade mark of the "uboot.com mobile internet services gmbh" in Vienna (who actively pursuit violations).
[1] http://www.wipo.int/branddb/en/
Best regards,
Wolfgang Denk
Signature · 4 lines
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de Given a choice between two theories, take the one which is funnier.
PATCH v4 1/3 driver/ddr/altera: Add DDR driver for Altera's SDRAM controller
In reply to Pavel MachekQuoted 10 lines · Pavel Machek
Hi!
arch/arm/include/asm/arch-socfpga/sdram.h line 80
Quoted 5 lines
arch/arm/include/asm/arch-socfpga/sdram.h new file +5
-0+struct sdram_prot_rule { +uint64_t sdram_start;/* SDRAM start address */ +uint64_t sdram_end;/* SDRAM end address */ +uint32_t rule;/* SDRAM protection rule number: 0-19 */ +int valid;/* Rule valid or not? 1 - valid, 0 not*/ There should be space before "*/".
Ok...
Quoted 7 lines
Quoted 7 lines
arch/arm/include/asm/arch-socfpga/sdram_config.h new file +1
-0@@ -0,0 +1,100 @@ +/*
Quoted 9 lines
arch/arm/include/asm/arch-socfpga/sdram_config.h line 7
Quoted 6 lines
arch/arm/include/asm/arch-socfpga/sdram_config.h new file +6
-0+* Copyright Altera Corporation (C) 2012-2015 +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/* This file is autogenerated from tools provided by Altera.*/ Here too.
Ok...
Quoted 11 lines
arch/arm/include/asm/arch-socfpga/sdram_config.h line 100
Quoted 1 line
arch/arm/include/asm/arch-socfpga/sdram_config.h new file +1
-0+#endif /*#ifndef__SDRAM_CONFIG_H*/ You should not need to comment for include guards... (and comment style).
arch/arm/include/asm/arch-socfpga/sdram_config.h line 11
Quoted 3 lines
arch/arm/include/asm/arch-socfpga/sdram_config.h new file +3
-0+static int compute_errata_rows (unsigned long long memsize,int cs,int width, +int rows,int banks,int cols) +{Comment what kind of errata this is working around?
I'll have to ask around.
Quoted 11 lines
arch/arm/include/asm/arch-socfpga/sdram_config.h line 17
Quoted 7 lines
arch/arm/include/asm/arch-socfpga/sdram_config.h new file +6
-0+#if defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS ) && \ +defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS ) && \ +defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS ) && \ +defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS ) && \ +defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS ) +Hmm? Is this really neccessary? Is it valid to provide configuration w/o those defines?
These defines are necessary as I want to keep some level of continuity with the Altera tools that generates these config files to this.
Quoted 4 lines
Quoted 3 lines
arch/arm/include/asm/arch-socfpga/sdram_config.h new file +3
-0+writel (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS , + &sysmgr_regs->iswgrp_handoff[4 ]); +#endif
Quoted 9 lines
arch/arm/include/asm/arch-socfpga/sdram_config.h line 26
Quoted 6 lines
arch/arm/include/asm/arch-socfpga/sdram_config.h new file +6
-0+ +/* Restore the SDR PHY Register if valid */ +if (sdr_phy_reg !=0xffffffff ) +writel (sdr_phy_reg, &sdr_ctrl->phy_ctrl0); + +/***** Final step - apply configuration changes *****/ Comment style...
Ok..
Quoted 26 lines
Quoted 26 lines
arch/arm/include/asm/arch-socfpga/sdram_config.h new file +26
-0+/* +* To calculate SDRAM device size based on SDRAM controller parameters. +* Size is specified in bytes. +* +* NOTE: +* This function is compiled and linked into the preloader and +* Uboot (there may be others). So if this function changes, the Preloader +* and UBoot must be updated simultaneously. +*/ +unsigned long sdram_calculate_size (void ) +{ +unsigned long temp; +unsigned long row, bank, col, cs, width; + + temp =readl (&sdr_ctrl->dram_addrw); + col = (temp &SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK ) >> +SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB ; + +/* SDRAM Failure When Accessing Non-Existent Memory +* Use ROWBITS from Quartus/QSys to calculate SDRAM size +* since the FB specifies we modify ROWBITs to work around SDRAM +* controller issue. +* +* If the stored handoff value for rows is 0, it probably means +* the preloader is older than UBoot. Use the +* #define from the SOCEDS Tools per Crucible review
Quoted 8 lines
arch/arm/include/asm/arch-socfpga/sdram_config.h line 57
Quoted 5 lines
arch/arm/include/asm/arch-socfpga/sdram_config.h new file +5
-0+* uboot-socfpga-204. Note that this is not a supported +* configuration and is not tested. The customer +* should be using preloader and uboot built from the +* same tag. +*/ U-Boot is normally spelled "U-Boot". You have two different variants in comments here.
Thanks for the comment here, and will be more cognizant in the future on this fact.
Quoted 3 lines
Second part of the comment is probably not relevant any more....?
removed...
Quoted 2 lines
Acked-by Pavel Machek <[email protected]>Pavel
Thanks,
Dinh
PATCH v4 1/3 driver/ddr/altera: Add DDR driver for Altera's SDRAM controller
Hi,
Quoted 39 lines · Dinh Nguyen
Quoted 10 lines · Pavel Machek
Hi!
arch/arm/include/asm/arch-socfpga/sdram.h line 80
Quoted 5 lines
arch/arm/include/asm/arch-socfpga/sdram.h new file +5
-0+struct sdram_prot_rule { +uint64_t sdram_start;/* SDRAM start address */ +uint64_t sdram_end;/* SDRAM end address */ +uint32_t rule;/* SDRAM protection rule number: 0-19 */ +int valid;/* Rule valid or not? 1 - valid, 0 not*/ There should be space before "*/".
Ok...
Quoted 7 lines
Quoted 7 lines
arch/arm/include/asm/arch-socfpga/sdram_config.h new file +1
-0@@ -0,0 +1,100 @@ +/* Quoted 9 lines
arch/arm/include/asm/arch-socfpga/sdram_config.h line 7
Quoted 6 lines
arch/arm/include/asm/arch-socfpga/sdram_config.h new file +6
-0+* Copyright Altera Corporation (C) 2012-2015 +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/* This file is autogenerated from tools provided by Altera.*/ Here too.
Ok...
Quoted 5 lines
arch/arm/include/asm/arch-socfpga/sdram_config.h line 100
Quoted 1 line
arch/arm/include/asm/arch-socfpga/sdram_config.h new file +1
-0+#endif /*#ifndef__SDRAM_CONFIG_H*/ You should not need to comment for include guards... (and comment style).
Quoted 8 lines
Quoted 6 lines
arch/arm/include/asm/arch-socfpga/sdram_config.h line 11
Quoted 3 lines
arch/arm/include/asm/arch-socfpga/sdram_config.h new file +3
-0+static int compute_errata_rows (unsigned long long memsize,int cs,int width, +int rows,int banks,int cols) +{Comment what kind of errata this is working around?
I'll have to ask around.
It is to workaround the computational of SDRAM rows. The info is then
used to calculate the SDRAM size. By doing this, we can remove from
hardcoding the SDRAM size into the code. More info at
https://github.com/altera-opensource/u-boot-socfpga/commit/93815696dce132ff8abc4ab2f4c195339ff821a0. Hope this explains.
Quoted 83 lines
Quoted 12 lines
arch/arm/include/asm/arch-socfpga/sdram_config.h line 17
Quoted 8 lines
arch/arm/include/asm/arch-socfpga/sdram_config.h new file +6
-0+#if defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS ) && \ +defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS ) && \ +defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS ) && \ +defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS ) && \ +defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS ) +Hmm? Is this really neccessary? Is it valid to provide configuration w/o those defines?
These defines are necessary as I want to keep some level of continuity with the Altera tools that generates these config files to this.
Quoted 4 lines
Quoted 3 lines
arch/arm/include/asm/arch-socfpga/sdram_config.h new file +3
-0+writel (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS , + &sysmgr_regs->iswgrp_handoff[4 ]); +#endif Quoted 9 lines
arch/arm/include/asm/arch-socfpga/sdram_config.h line 26
Quoted 6 lines
arch/arm/include/asm/arch-socfpga/sdram_config.h new file +6
-0+ +/* Restore the SDR PHY Register if valid */ +if (sdr_phy_reg !=0xffffffff ) +writel (sdr_phy_reg, &sdr_ctrl->phy_ctrl0); + +/***** Final step - apply configuration changes *****/ Comment style...
Ok..
Quoted 26 lines
Quoted 26 lines
arch/arm/include/asm/arch-socfpga/sdram_config.h new file +26
-0+/* +* To calculate SDRAM device size based on SDRAM controller parameters. +* Size is specified in bytes. +* +* NOTE: +* This function is compiled and linked into the preloader and +* Uboot (there may be others). So if this function changes, the Preloader +* and UBoot must be updated simultaneously. +*/ +unsigned long sdram_calculate_size (void ) +{ +unsigned long temp; +unsigned long row, bank, col, cs, width; + + temp =readl (&sdr_ctrl->dram_addrw); + col = (temp &SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK ) >> +SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB ; + +/* SDRAM Failure When Accessing Non-Existent Memory +* Use ROWBITS from Quartus/QSys to calculate SDRAM size +* since the FB specifies we modify ROWBITs to work around SDRAM +* controller issue. +* +* If the stored handoff value for rows is 0, it probably means +* the preloader is older than UBoot. Use the +* #define from the SOCEDS Tools per Crucible review Quoted 8 lines
arch/arm/include/asm/arch-socfpga/sdram_config.h line 57
Quoted 5 lines
arch/arm/include/asm/arch-socfpga/sdram_config.h new file +5
-0+* uboot-socfpga-204. Note that this is not a supported +* configuration and is not tested. The customer +* should be using preloader and uboot built from the +* same tag. +*/ U-Boot is normally spelled "U-Boot". You have two different variants in comments here.
Thanks for the comment here, and will be more cognizant in the future on this fact.
Quoted 3 lines
Second part of the comment is probably not relevant any more....?
removed...
Quoted 2 lines
Acked-by Pavel Machek <[email protected]>Pavel
Thanks,
Dinh
PATCH v4 1/3 driver/ddr/altera: Add DDR driver for Altera's SDRAM controller
Hi!
Quoted 11 lines
Quoted 4 lines
Quoted 2 lines
Comment what kind of errata this is working around?
I'll have to ask around.
It is to workaround the computational of SDRAM rows. The info is then
used to calculate the SDRAM size. By doing this, we can remove from
hardcoding the SDRAM size into the code. More info at
https://github.com/altera-opensource/u-boot-socfpga/commit/93815696dce132ff8abc4ab2f4c195339ff821a0. Hope this explains.
Ok, can you add a comment into the sources explaining what is going on?
Normally, chip errata are documented somewhere and have numbers, that would be best thing to link there. (But the github link is also better than nothing...)
Pavel
Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
PATCH v4 2/3 driver/ddr/altera: Add the sdram calibration portion
In reply to dinguyen at opensource.altera.comFrom: Dinh Nguyen <[email protected]>
This patch adds the DDR calibration portion of the Altera SDRAM driver.
---
v4:
- further cleanup by removing all of the inlined functions, which then resulted in removing a few unused functions.
- Removed comment that is only applicable for DDR configuration that is done by NIOS2
v3: more clean up
v2: more clean from Marek's comments
--- drivers/ddr/altera/Makefile | 11 + drivers/ddr/altera/sequencer.c | 4051 +++++++++++++++++++++++++ drivers/ddr/altera/sequencer.h | 322 ++ drivers/ddr/altera/sequencer_auto.h | 128 + drivers/ddr/altera/sequencer_auto_ac_init.h | 84 + drivers/ddr/altera/sequencer_auto_inst_init.h | 268 ++ drivers/ddr/altera/sequencer_defines.h | 121 + 7 files changed, 4985 insertions(+) create mode 100644 drivers/ddr/altera/Makefile create mode 100644 drivers/ddr/altera/sequencer.c create mode 100644 drivers/ddr/altera/sequencer.h create mode 100644 drivers/ddr/altera/sequencer_auto.h create mode 100644 drivers/ddr/altera/sequencer_auto_ac_init.h create mode 100644 drivers/ddr/altera/sequencer_auto_inst_init.h create mode 100644 drivers/ddr/altera/sequencer_defines.h
drivers/ddr/altera/Makefile new file +11 -0
@@ -0,0 +1,11 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd at denx.de. +# +# (C) Copyright 2010, Thomas Chou <[email protected]> +# Copyright (C) 2014 Altera Corporation <www.altera.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_ALTERA_SDRAM) += sdram.o sequencer.o
drivers/ddr/altera/sequencer.c new file +4051 -0
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drivers/ddr/altera/sequencer.h new file +322 -0
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drivers/ddr/altera/sequencer_auto.h new file +128 -0
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drivers/ddr/altera/sequencer_auto_ac_init.h new file +84 -0
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drivers/ddr/altera/sequencer_auto_inst_init.h new file +268 -0
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drivers/ddr/altera/sequencer_defines.h new file +121 -0
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The rest of this diff is not shown. View the raw message.
Signature · 1 line
2.2.1
Part of the diff is not shown here. View the raw message.
PATCH v4 2/3 driver/ddr/altera: Add the sdram calibration portion
In title, you can convert sdram->SDRAM
Quoted 6 lines · dinguyen at opensource.altera.com
From: Dinh Nguyen <[email protected]>
This patch adds the DDR calibration portion of the Altera SDRAM driver.
Signed-off-by Dinh Nguyen <[email protected]>
Quoted 10 lines
+/*
+ * In order to reduce ROM size, most of the selectable calibration steps are
+ * decided at compile time based on the user's calibration mode selection,
+ * as captured by theSTATIC_CALIB_STEPSselection below.
+ *
+ * However, to support simulation-time selection of fast simulation mode, where
+ * we skip everything except the bare minimum, we need a few of the steps to
+ * be dynamic. In those cases, we either use theDYNAMIC_CALIB_STEPSfor the
+ * check, which is based on the rtl-supplied value, or we dynamically compute
+ * the value to use based on the dynamically-chosen calibration mode
"." at the end of sentence.
drivers/ddr/altera/sequencer.c line 59
Quoted 7 lines
drivers/ddr/altera/sequencer.c new file +7
-0+ +#define DLEVEL 0 +#define STATIC_IN_RTL_SIM 0 +#define STATIC_SKIP_DELAY_LOOPS 0 + +#define STATIC_CALIB_STEPS (STATIC_IN_RTL_SIM | CALIB_SKIP_FULL_TEST | \ + STATIC_SKIP_DELAY_LOOPS)
Would it make sense to drop simulation-time support for initial merge?
drivers/ddr/altera/sequencer.c line 62
Quoted 2 lines
drivers/ddr/altera/sequencer.c new file +2
-0+/* calibration steps requested by the rtl */ +uint16_t dyn_calib_steps;
rtl?
Quoted 8 lines
+/*
+ * To makeCALIB_SKIP_DELAY_LOOPSa dynamic conditional option
+ * instead of static, we use boolean logic to select between
+ * non-skip and skip values
+ *
+ * The mask is set to include all bits when not-skipping, but is
+ * zero when skipping
+ */
"." at the end of sentence. Twice here :-).
Quoted 7 lines
drivers/ddr/altera/sequencer.c new file +7
-0+ +uint16_t skip_delay_mask;/* mask off bits when skipping/not-skipping */ + +#define SKIP_DELAY_LOOP_VALUE_OR_ZERO (non_skip_value) \ + ((non_skip_value) & skip_delay_mask) + +struct gbl_type *gbl;
drivers/ddr/altera/sequencer.c line 88
Quoted 10 lines
drivers/ddr/altera/sequencer.c new file +10
-0+struct param_type *param; +uint32_t curr_shadow_reg; + +static uint32_t rw_mgr_mem_calibrate_write_test (uint32_t rank_bgn, +uint32_t write_group,uint32_t use_dm, +uint32_t all_correct,uint32_t *bit_chk,uint32_t all_ranks); + +static u32 sdr_get_addr (u32 *base) +{ +u32 addr = (u32 )base &MGR_SELECT_MASK ;
You sometimes use uint32_t, and sometimes u32, as seen here. Would it be more readable to just use u32 everywhere?
And this function would be really helped by taking "u32 base", not "u32 *", as youd reduce number of typecasts below...
Quoted 10 lines
drivers/ddr/altera/sequencer.c new file +10
-0+switch (addr) { +case BASE_PHY_MGR : + addr = (((u32 )base >>8 ) & (1 <<6 )) | ((u32 )base &0x3f ) | +SDR_PHYGRP_PHYMGRGRP_ADDRESS ; +break ; +case BASE_RW_MGR : + addr = ((u32 )base &0x1fff ) |SDR_PHYGRP_RWMGRGRP_ADDRESS ; +break ; +case BASE_DATA_MGR : + addr = ((u32 )base &0x7ff ) |SDR_PHYGRP_DATAMGRGRP_ADDRESS ;
drivers/ddr/altera/sequencer.c line 109
Quoted 10 lines
drivers/ddr/altera/sequencer.c new file +10
-0+break ; +case BASE_SCC_MGR : + addr = ((u32 )base &0xfff ) |SDR_PHYGRP_SCCGRP_ADDRESS ; +break ; +case BASE_REG_FILE : + addr = ((u32 )base &0x7ff ) |SDR_PHYGRP_REGFILEGRP_ADDRESS ; +break ; +case BASE_MMR : + addr = ((u32 )base &0xfff ) |SDR_CTRLGRP_ADDRESS ; +break ;
Or at least introduce temporary variable...
drivers/ddr/altera/sequencer.c line 184
Quoted 5 lines
drivers/ddr/altera/sequencer.c new file +5
-0+static void initialize (void ) +{ +u32 addr =sdr_get_addr (&phy_mgr_cfg->mux_sel); + +debug ("%s:%d\n" , __func__, __LINE__);
Is this debugging neccessary? It will change when you for example change comment in here...
drivers/ddr/altera/sequencer.c line 193
Quoted 9 lines
drivers/ddr/altera/sequencer.c new file +9
-0+/* USER calibration has control over path to memory */ +/* +* In Hard PHY this is a 2-bit control: +* 0: AFI Mux Select +* 1: DDIO Mux Select +*/ +writel (0x3 ,SOCFPGA_SDR_ADDRESS + addr); + +/* USER memory clock is not stable we begin initialization */
" */" -> " */"
drivers/ddr/altera/sequencer.c line 336
Quoted 3 lines
drivers/ddr/altera/sequencer.c new file +3
-0+for (i =0 ; i <16 ; i++) { +debug_cond (DLEVEL ==1 ,"%s:%d: Clearing SCC RFILE index %u" , + __func__, __LINE__, i);
Ok, custom debugging system. Neccessary?
drivers/ddr/altera/sequencer.c line 439
Quoted 3 lines
drivers/ddr/altera/sequencer.c new file +3
-0+static void scc_mgr_set_dqs_en_delay (uint32_t read_group,uint32_t delay) +{ +uint32_t addr =sdr_get_addr ((u32 *)SCC_MGR_DQS_EN_DELAY );
Now uint32_t vs. u32 on single line...
Quoted 17 lines
drivers/ddr/altera/sequencer.c new file +17
-0+for (r =0 ; r <RW_MGR_MEM_NUMBER_OF_RANKS ; + r +=NUM_RANKS_PER_SHADOW_REG ) { +scc_mgr_set_dqs_en_delay (read_group, delay); + + addr =sdr_get_addr (&sdr_scc_mgr->dqs_ena); +writel (read_group,SOCFPGA_SDR_ADDRESS + addr); +/* +* In shadow register mode, the T11 settings are stored in +* registers in the core, which are updated by the DQS_ENA +* signals. Not issuing the SCC_MGR_UPD command allows us to +* save lots of rank switching overhead, by calling +* select_shadow_regs_for_update with update_scan_chains +* set to 0. +*/ + addr =sdr_get_addr (&sdr_scc_mgr->update); +writel (0 ,SOCFPGA_SDR_ADDRESS + addr); + }
drivers/ddr/altera/sequencer.c line 478
Quoted 10 lines
drivers/ddr/altera/sequencer.c new file +10
-0+/* +* In shadow register mode, the T11 settings are stored in +* registers in the core, which are updated by the DQS_ENA +* signals. Not issuing the SCC_MGR_UPD command allows us to +* save lots of rank switching overhead, by calling +* select_shadow_regs_for_update with update_scan_chains +* set to 0. +*/ + addr =sdr_get_addr (&sdr_scc_mgr->update); +writel (0 ,SOCFPGA_SDR_ADDRESS + addr);
Umm. Two completely same comments, two same pieces of code. Make it function?
Does it make sense to run this twice in fact?
drivers/ddr/altera/sequencer.c line 599
Quoted 5 lines
drivers/ddr/altera/sequencer.c new file +5
-0+static void scc_set_bypass_mode (uint32_t write_group,uint32_t mode) +{ +uint32_t addr; +/* mode = 0 : Do NOT bypass - Half Rate Mode */ +/* mode = 1 : Bypass - Full Rate Mode */
Then perhaps the parameter should be named "do_bypass" or "full_rate"?
drivers/ddr/altera/sequencer.c line 1107
Quoted 8 lines
drivers/ddr/altera/sequencer.c new file +8
-0+if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) &0x1 ) { +set_jump_as_return (); + addr =sdr_get_addr ((u32 *)RW_MGR_RUN_SINGLE_GROUP ); +writel (RW_MGR_MRS2_MIRR ,SOCFPGA_SDR_ADDRESS + addr); +delay_for_n_mem_clocks (4 ); +set_jump_as_return (); +writel (RW_MGR_MRS3_MIRR ,SOCFPGA_SDR_ADDRESS + addr); +delay_for_n_mem_clocks (4 );
What is this, some kind of bytecode interpretter? Or does it create a bytecode for someone?
drivers/ddr/altera/sequencer.c line 1500
Quoted 5 lines
drivers/ddr/altera/sequencer.c new file +5
-0+static int find_working_phase (uint32_t *grp,uint32_t *bit_chk, +uint32_t dtaps_per_ptap,uint32_t *work_bgn, +uint32_t *v,uint32_t *d,uint32_t *p, +uint32_t *i,uint32_t *max_working_cnt) +{
Undocumented, single-letter parameters do not really make reading the code easy...
Should we have structure for work_bgn, v, d, p, i ... instead of separate parameters?
drivers/ddr/altera/sequencer.c line 1512
Quoted 12 lines
drivers/ddr/altera/sequencer.c new file +12
-0+uint32_t found_begin =0 ; +uint32_t tmp_delay =0 ; +uint32_t test_status; + +for (*d =0 ; *d <= dtaps_per_ptap; (*d)++, tmp_delay += +IO_DELAY_PER_DQS_EN_DCHAIN_TAP ) { + *work_bgn = tmp_delay; +scc_mgr_set_dqs_en_delay_all_ranks (*grp, *d); + +for (*i =0 ; *i <VFIFO_SIZE ; (*i)++) { +for (*p =0 ; *p <=IO_DQS_EN_PHASE_MAX ; (*p)++, *work_bgn += +IO_DELAY_PER_OPA_TAP ) {
Does this look like c-code to you?
Quoted 6 lines
drivers/ddr/altera/sequencer.c new file +6
-0+ }else { +/* ******************************************************* */ +/* * step 3-5b: Find the right edge of the window using +delay taps * */ + debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase:vfifo=%u \ + ptap=%u dtap=%u bgn=%u\n", __func__, __LINE__,
drivers/ddr/altera/sequencer.c line 1798
Quoted 10 lines
drivers/ddr/altera/sequencer.c new file +10
-0+ v, p, d, work_bgn); + + work_end = work_bgn; + +/* * The actual increment of dtaps is done outside of the +if/else loop to share code */ + +/* Only here to counterbalance a subtract later on which is +not needed if this branch of the algorithm is taken */ + max_working_cnt++;
Comment style in this block is even stranger than in other pieces of this patch.
Quoted 18 lines
drivers/ddr/altera/sequencer.c new file +18
-0+ }else { +for (i =0 ; i <RW_MGR_MEM_DQ_PER_READ_DQS ; i++) { +if (bit_chk &1 ) { +/* Remember a passing test as +the right_edge */ + right_edge[i] = d; + }else { +if (d !=0 ) { +/* If a right edge has not been +seen yet, then a future passing +test will mark this edge as the +left edge */ +if (right_edge[i] == +IO_IO_IN_DELAY_MAX +1 ) { + left_edge[i] = -(d +1 ); + } + }else { +/* d = 0 failed, but it passed
drivers/ddr/altera/sequencer.c line 2190
Quoted 10 lines
drivers/ddr/altera/sequencer.c new file +10
-0+when testing the left edge, +so it must be marginal, +set it to -1 */ +if (right_edge[i] == +IO_IO_IN_DELAY_MAX +1 && + left_edge[i] != +IO_IO_IN_DELAY_MAX + +1 ) { + right_edge[i] =-1 ; + }
When this happens to your code, you know it is time to split your function into sub-functions.
Quoted 18 lines
drivers/ddr/altera/sequencer.c new file +18
-0+if (rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay + (write_group, read_group, test_bgn)) { +/* +* USER Read per-bit deskew can be done on a +* per shadow register basis. +*/ +for (rank_bgn =0 , sr =0 ; + rank_bgn <RW_MGR_MEM_NUMBER_OF_RANKS ; + rank_bgn +=NUM_RANKS_PER_SHADOW_REG , + ++sr) { +/* +* Determine if this set of ranks +* should be skipped entirely. +*/ +if (!param->skip_shadow_regs[sr]) { +/* +* If doing read after write +* calibration, do not update
drivers/ddr/altera/sequencer.c line 2482
Quoted 10 lines
drivers/ddr/altera/sequencer.c new file +10
-0+* FOM, now - do it then. +*/ +if (!rw_mgr_mem_calibrate_vfifo_center + (rank_bgn, write_group, + read_group, test_bgn,1 ,0 )) { + grp_calibrated =0 ; + failed_substage = +CAL_SUBSTAGE_VFIFO_CENTER ; + } + }
Here too. Notice that indentation is actually wrong/confusing here, the ifs are nested.
Quoted 16 lines
drivers/ddr/altera/sequencer.c new file +16
-0+/* VFIFO Calibration -- Read Deskew Calibration after write deskew */ +static uint32_t rw_mgr_mem_calibrate_vfifo_end (uint32_t read_group, +uint32_t test_bgn) +{ +uint32_t rank_bgn, sr; +uint32_t grp_calibrated; +uint32_t write_group; + +debug ("%s:%d %u %u" , __func__, __LINE__, read_group, test_bgn); + +/* update info for sims */ + +reg_file_set_stage (CAL_STAGE_VFIFO_AFTER_WRITES ); +reg_file_set_sub_stage (CAL_SUBSTAGE_VFIFO_CENTER ); + + write_group = read_group;
drivers/ddr/altera/sequencer.c line 2533
Quoted 10 lines
drivers/ddr/altera/sequencer.c new file +10
-0+ +/* update info for sims */ +reg_file_set_group (read_group); + + grp_calibrated =1 ; +/* Read per-bit deskew can be done on a per shadow register basis */ +for (rank_bgn =0 , sr =0 ; rank_bgn <RW_MGR_MEM_NUMBER_OF_RANKS ; + rank_bgn +=NUM_RANKS_PER_SHADOW_REG , ++sr) { +/* Determine if this set of ranks should be skipped entirely */ +if (!param->skip_shadow_regs[sr]) {
if (param...)
continue;
Then you get one less level of identation.
drivers/ddr/altera/sequencer.c line 2541
Quoted 8 lines
drivers/ddr/altera/sequencer.c new file +8
-0+/* This is the last calibration round, update FOM here */ +if (!rw_mgr_mem_calibrate_vfifo_center (rank_bgn, + write_group, + read_group, + test_bgn,0 , +1 )) { + grp_calibrated =0 ; + }
..and you'll be able to do something with this.
drivers/ddr/altera/sequencer.c line 2584
Quoted 10 lines
drivers/ddr/altera/sequencer.c new file +10
-0+writel (gbl->curr_read_lat,SOCFPGA_SDR_ADDRESS + addr); +debug_cond (DLEVEL ==2 ,"%s:%d lfifo: read_lat=%u" , + __func__, __LINE__, gbl->curr_read_lat); + +if (!rw_mgr_mem_calibrate_read_test_all_ranks (0 , +NUM_READ_TESTS , +PASS_ALL_BITS , + &bit_chk,1 )) { +break ; + }
If you can't fix it any other way,
if (!rw_mgr_mem_calibrate_read_test_all_ranks(0,
NUM_READ_TESTS, PASS_ALL_BITS, &bit_chk, 1)) {is preferable. And you don't need {}'s around break;
Quoted 49 lines
drivers/ddr/altera/sequencer.c new file +49
-0+if (stop ==1 ) { +if (d ==0 ) { +for (i =0 ; i <RW_MGR_MEM_DQ_PER_WRITE_DQS ; + i++) { +/* d = 0 failed, but it passed when +testing the left edge, so it must be +marginal, set it to -1 */ +if (right_edge[i] == +IO_IO_OUT1_DELAY_MAX +1 && + left_edge[i] != +IO_IO_OUT1_DELAY_MAX +1 ) { + right_edge[i] =-1 ; + } + } + } +break ; + }else { +for (i =0 ; i <RW_MGR_MEM_DQ_PER_WRITE_DQS ; i++) { +if (bit_chk &1 ) { +/* +* Remember a passing test as +* the right_edge. +*/ + right_edge[i] = d; + }else { +if (d !=0 ) { +/* +* If a right edge has not +* been seen yet, then a future +* passing test will mark this +* edge as the left edge. +*/ +if (right_edge[i] == +IO_IO_OUT1_DELAY_MAX +1 ) + left_edge[i] = -(d +1 ); + }else { +/* +* d = 0 failed, but it passed +* when testing the left edge, +* so it must be marginal, set +* it to -1. +*/ +if (right_edge[i] == +IO_IO_OUT1_DELAY_MAX +1 && + left_edge[i] != +IO_IO_OUT1_DELAY_MAX +1 ) + right_edge[i] =-1 ; +/* +* If a right edge has not been
drivers/ddr/altera/sequencer.c line 3039
Quoted 10 lines
drivers/ddr/altera/sequencer.c new file +10
-0+* seen yet, then a future +* passing test will mark this +* edge as the left edge. +*/ + else if (right_edge[i] == + IO_IO_OUT1_DELAY_MAX + + 1) + left_edge[i] = -(d +1 ); + } + }
Something needs to be done here, too...
Quoted 80 lines
drivers/ddr/altera/sequencer.c new file +80
-0+for (read_group = write_group * +RW_MGR_MEM_IF_READ_DQS_WIDTH / +RW_MGR_MEM_IF_WRITE_DQS_WIDTH , + read_test_bgn =0 ; + read_group < (write_group +1 ) * +RW_MGR_MEM_IF_READ_DQS_WIDTH / +RW_MGR_MEM_IF_WRITE_DQS_WIDTH && + group_failed ==0 ; + read_group++, read_test_bgn += +RW_MGR_MEM_DQ_PER_READ_DQS ) { +/* Calibrate the VFIFO */ +if (!((STATIC_CALIB_STEPS ) & +CALIB_SKIP_VFIFO )) { +if (!rw_mgr_mem_calibrate_vfifo + (read_group, + read_test_bgn)) { + group_failed =1 ; + +if (!(gbl-> + phy_debug_mode_flags & +PHY_DEBUG_SWEEP_ALL_GROUPS )) { +return 0 ; + } + } + } + } + +/* Calibrate the output side */ +if (group_failed ==0 ) { +for (rank_bgn =0 , sr =0 ; rank_bgn + <RW_MGR_MEM_NUMBER_OF_RANKS ; + rank_bgn += +NUM_RANKS_PER_SHADOW_REG , + ++sr) { + sr_failed =0 ; +if (!((STATIC_CALIB_STEPS ) & +CALIB_SKIP_WRITES )) { +if ((STATIC_CALIB_STEPS ) + &CALIB_SKIP_DELAY_SWEEPS ) { +/* not needed in quick mode! */ + }else { +/* +* Determine if this set of +* ranks should be skipped +* entirely. +*/ +if (!param->skip_shadow_regs[sr]) { +if (!rw_mgr_mem_calibrate_writes + (rank_bgn, write_group, + write_test_bgn)) { + sr_failed =1 ; +if (!(gbl-> + phy_debug_mode_flags & +PHY_DEBUG_SWEEP_ALL_GROUPS )) { +return 0 ; + } + } + } + } + } +if (sr_failed !=0 ) + group_failed =1 ; + } + } + +if (group_failed ==0 ) { +for (read_group = write_group * +RW_MGR_MEM_IF_READ_DQS_WIDTH / +RW_MGR_MEM_IF_WRITE_DQS_WIDTH , + read_test_bgn =0 ; + read_group < (write_group +1 ) + *RW_MGR_MEM_IF_READ_DQS_WIDTH + /RW_MGR_MEM_IF_WRITE_DQS_WIDTH && + group_failed ==0 ; + read_group++, read_test_bgn += +RW_MGR_MEM_DQ_PER_READ_DQS ) { +if (!((STATIC_CALIB_STEPS ) & +CALIB_SKIP_WRITES )) { +if (!rw_mgr_mem_calibrate_vfifo_end + (read_group, read_test_bgn)) {
drivers/ddr/altera/sequencer.c line 3660
Quoted 10 lines
drivers/ddr/altera/sequencer.c new file +10
-0+ group_failed =1 ; + +if (!(gbl->phy_debug_mode_flags + &PHY_DEBUG_SWEEP_ALL_GROUPS )) { +return 0 ; + } + } + } + } + }
And here. Note how indentation is so deep ifs are actually indented the other way around here.
I guess it would be better to ignore 80-columns rule than _this_. But splitting it into smaller functions is of course preffered.
Thanks,
Pavel
Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
PATCH v4 3/3 arm: socfpga: enable the Altera SDRAM controller driver
In reply to dinguyen at opensource.altera.comFrom: Dinh Nguyen <[email protected]>
Enable the Altera SDRAM driver for the SoCFPGA platform.
--- include/configs/socfpga_common.h | 5 +++++ 1 file changed, 5 insertions(+)
include/configs/socfpga_common.h +5 -0
@@ -77,6 +77,11 @@#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS/* +* SDRAM controller +*/ +#define CONFIG_ALTERA_SDRAM + +/* * EPCS/EPCQx1 Serial Flash Controller */ #ifdef CONFIG_ALTERA_SPI
Signature · 1 line
2.2.1
PATCH v4 3/3 arm: socfpga: enable the Altera SDRAM controller driver
Quoted 6 lines · dinguyen at opensource.altera.com
From: Dinh Nguyen <[email protected]>
Enable the Altera SDRAM driver for the SoCFPGA platform.
Signed-off-by Dinh Nguyen <[email protected]>Acked-by Marek Vasut <[email protected]>
Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
v4 cover drivers/ddr/altera: Add the DDR controller driver for SoCFPGA
In reply to dinguyen at opensource.altera.comQuoted 4 lines · dinguyen at opensource.altera.com
From: Dinh Nguyen <[email protected]>
Hi,
Quoted 8 lines
This is v4 of the patch series that adds the DDR controller driver for Altera's SoCFPGA platform.
v4:
- Further cleanup by removing comments that do not apply for Cyclone5.
- Removed more unused functionsThanks,
I applied this to u-boot/master and tried building for socfpga_cyclone5, this is what I'm getting after I fixed these patches to actually apply to u-boot/master (there was a minor conflict in Makefile):
drivers/ddr/altera/sdram.c:11:35: fatal error: asm/arch/sdram_config.h: No such file or directory
#include <asm/arch/sdram_config.h>
^compilation terminated.
make[1]: *** [drivers/ddr/altera/sdram.o] Error 1
make[1]: *** Waiting for unfinished jobs.... drivers/ddr/altera/sequencer.c: In function 'sdr_get_addr':drivers/ddr/altera/sequencer.c:108:32: error: 'SDR_CTRLGRP_ADDRESS' undeclared (first use in this function)
addr = ((u32)base & 0xfff) | SDR_CTRLGRP_ADDRESS;
^drivers/ddr/altera/sequencer.c:108:32: note: each undeclared identifier is reported only once for each function it appears in drivers/ddr/altera/sequencer.c: In function 'initialize_hps_phy':drivers/ddr/altera/sequencer.c:3850:2: warning: implicit declaration of function 'SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET' [-Wimplicit-function-declaration]
reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(2);
Am I missing something ?
Best regards,
Marek Vasut
v4 cover drivers/ddr/altera: Add the DDR controller driver for SoCFPGA
Quoted 16 lines · Marek Vasut
On Wednesday, June 03, 2015 at 05:52:47 AM, dinguyen at opensource.altera.com
Quoted 4 lines · wrote:
From: Dinh Nguyen <[email protected]>
Hi,
Quoted 8 lines
This is v4 of the patch series that adds the DDR controller driver for Altera's SoCFPGA platform.
v4:
- Further cleanup by removing comments that do not apply for Cyclone5.
- Removed more unused functionsThanks,
Quoted 7 lines
I applied this to u-boot/master and tried building for
socfpga_cyclone5, this is what I'm getting after I fixed these patches to actually apply to u-boot/master (there was a minor conflict inMakefile):
drivers/ddr/altera/sdram.c:11:35: fatal error:asm/arch/sdram_config.h: No such file or directory
#include <asm/arch/sdram_config.h>
OK, these files were misplaced by the patch. Now I got it to compile, only to see that when I try to init DRAM on sockit using those, PHY calibration fails (run_mem_calibrate() returns 1).
btw. I also think sdram_config.h should go into board/altera/ instead .
Best regards,
Marek Vasut
v4 cover drivers/ddr/altera: Add the DDR controller driver for SoCFPGA
Quoted 25 lines · Marek Vasut
Quoted 24 lines · Marek Vasut
On Wednesday, June 03, 2015 at 05:52:47 AM,
dinguyen at opensource.altera.comQuoted 4 lines · wrote:
From: Dinh Nguyen <[email protected]>
Hi,
Quoted 8 lines
This is v4 of the patch series that adds the DDR controller driver for Altera's SoCFPGA platform.
v4:
- Further cleanup by removing comments that do not apply for Cyclone5.
- Removed more unused functionsThanks,
I applied this to u-boot/master and tried building for
socfpga_cyclone5, this is what I'm getting after I fixed these patches to actually apply to u-boot/master (there was a minor conflict inMakefile):
drivers/ddr/altera/sdram.c:11:35: fatal error:asm/arch/sdram_config.h:
No such file or directory
Quoted 7 lines
Quoted 1 line
#include <
asm/arch/sdram_config.h>OK, these files were misplaced by the patch. Now I got it to compile, only to see that when I try to init DRAM on sockit using those, PHY calibration fails (
run_mem_calibrate()returns 1).btw. I also think
sdram_config.hshould go into board/altera/ instead .
Just a quick heads-up, I'm cleaning this and the SPL up. I got SoCkit booting from SD/MMC and I'm over 50 patches now. I'll submit them when I'm done with this. I'd like to avoid merge conflicts now, so please wait for my submission if possible.
Best regards,
Marek Vasut
v4 cover drivers/ddr/altera: Add the DDR controller driver for SoCFPGA
Quoted 32 lines · Marek Vasut
Quoted 31 lines · Marek Vasut
Quoted 17 lines · Marek Vasut
On Wednesday, June 03, 2015 at 05:52:47 AM,
dinguyen at opensource.altera.comQuoted 4 lines · wrote:
From: Dinh Nguyen <[email protected]>
Hi,
Quoted 8 lines
This is v4 of the patch series that adds the DDR controller driver for Altera's SoCFPGA platform.
v4:
- Further cleanup by removing comments that do not apply for Cyclone5.
- Removed more unused functionsThanks,
Quoted 8 lines
I applied this to u-boot/master and tried building for
socfpga_cyclone5, this is what I'm getting after I fixed these patches to actually apply to u-boot/master (there was a minor conflict inMakefile):
drivers/ddr/altera/sdram.c:11:35: fatal error:asm/arch/sdram_config.h:
No such file or directory#include <
asm/arch/sdram_config.h>OK, these files were misplaced by the patch. Now I got it to compile, only to see that when I try to init DRAM on sockit using those, PHY calibration fails (
run_mem_calibrate()returns 1).
Quoted 7 lines
Quoted 1 line
btw. I also think
sdram_config.hshould go into board/altera/ instead .Just a quick heads-up, I'm cleaning this and the SPL up. I got SoCkit booting from SD/MMC and I'm over 50 patches now. I'll submit them when I'm done with this. I'd like to avoid merge conflicts now, so please wait for my submission if possible.
So you want me to wait regarding the SDRAM patches?
Dinh
v4 cover drivers/ddr/altera: Add the DDR controller driver for SoCFPGA
Quoted 34 lines · Dinh Nguyen
Quoted 33 lines · Marek Vasut
Quoted 32 lines · Marek Vasut
Quoted 22 lines · Marek Vasut
On Wednesday, June 03, 2015 at 05:52:47 AM,
dinguyen at opensource.altera.comQuoted 4 lines · wrote:
From: Dinh Nguyen <[email protected]>
Hi,
Quoted 8 lines
This is v4 of the patch series that adds the DDR controller driver for Altera's SoCFPGA platform.
v4:
- Further cleanup by removing comments that do not apply for Cyclone5.
- Removed more unused functionsThanks,
I applied this to u-boot/master and tried building for
socfpga_cyclone5, this is what I'm getting after I fixed these patches to actually apply to u-boot/master (there was a minor conflict inMakefile):Quoted 4 lines
drivers/ddr/altera/sdram.c:11:35: fatal error:asm/arch/sdram_config.h:
No such file or directory#include <
asm/arch/sdram_config.h>OK, these files were misplaced by the patch. Now I got it to compile, only to see that when I try to init DRAM on sockit using those, PHY calibration fails (
run_mem_calibrate()returns 1).
Quoted 8 lines
Quoted 6 lines
Quoted 1 line
btw. I also think
sdram_config.hshould go into board/altera/ instead .Just a quick heads-up, I'm cleaning this and the SPL up. I got SoCkit booting from SD/MMC and I'm over 50 patches now. I'll submit them when I'm done with this. I'd like to avoid merge conflicts now, so please wait for my submission if possible.
So you want me to wait regarding the SDRAM patches?
Hi,
yeah, I have some insane amount of cleanup patches and fixes already. I will post them once I'm done. What I am sorely missing is the UniPHY register interface documentation, it looks like that is not public, so I don't exactly know if what sequencer.c does is really correct. Sometimes I have serious doubts about that too . Can you give me the documentation please ?
Best regards,
Marek Vasut
v4 cover drivers/ddr/altera: Add the DDR controller driver for SoCFPGA
Quoted 45 lines · Marek Vasut
Quoted 37 lines · Dinh Nguyen
Quoted 36 lines · Marek Vasut
Quoted 34 lines · Marek Vasut
Quoted 22 lines · Marek Vasut
On Wednesday, June 03, 2015 at 05:52:47 AM,
dinguyen at opensource.altera.comQuoted 4 lines · wrote:
From: Dinh Nguyen <[email protected]>
Hi,
Quoted 8 lines
This is v4 of the patch series that adds the DDR controller driver for Altera's SoCFPGA platform.
v4:
- Further cleanup by removing comments that do not apply for Cyclone5. - Removed more unused functionsThanks,
I applied this to u-boot/master and tried building for
socfpga_cyclone5, this is what I'm getting after I fixed these patches to actually apply to u-boot/master (there was a minor conflict inMakefile):Quoted 4 lines
drivers/ddr/altera/sdram.c:11:35: fatal error:asm/arch/sdram_config.h: No such file or directory#include <
asm/arch/sdram_config.h>OK, these files were misplaced by the patch. Now I got it to compile, only to see that when I try to init DRAM on sockit using those, PHY calibration fails (
run_mem_calibrate()returns 1).btw. I also think
sdram_config.hshould go into board/altera/ instead .Quoted 6 lines
Quoted 4 lines
Just a quick heads-up, I'm cleaning this and the SPL up. I got SoCkit booting from SD/MMC and I'm over 50 patches now. I'll submit them when I'm done with this. I'd like to avoid merge conflicts now, so please wait for my submission if possible.
So you want me to wait regarding the SDRAM patches?
Quoted 8 lines
Hi,
yeah, I have some insane amount of cleanup patches and fixes already. I will post them once I'm done. What I am sorely missing is the UniPHY register interface documentation, it looks like that is not public, so I don't exactly know if what
sequencer.cdoes is really correct. Sometimes I have serious doubts about that too . Can you give me the documentation please ?
Small patchset is here :-) It's still work in progress, I'm still doing rebases and changes, but I wanted to share something at least ...
http://git.denx.de/?p=u-boot/u-boot-socfpga.git;a=shortlog;h=refs/heads/vip/spl
Best regards,
Marek Vasut
v4 cover drivers/ddr/altera: Add the DDR controller driver for SoCFPGA
In reply to Marek VasutQuoted 44 lines · Marek Vasut
Quoted 34 lines · Dinh Nguyen
Quoted 33 lines · Marek Vasut
Quoted 32 lines · Marek Vasut
Quoted 22 lines · Marek Vasut
On Wednesday, June 03, 2015 at 05:52:47 AM,
dinguyen at opensource.altera.comQuoted 4 lines · wrote:
From: Dinh Nguyen <[email protected]>
Hi,
Quoted 8 lines
This is v4 of the patch series that adds the DDR controller driver for Altera's SoCFPGA platform.
v4:
- Further cleanup by removing comments that do not apply for Cyclone5.
- Removed more unused functionsThanks,
I applied this to u-boot/master and tried building for
socfpga_cyclone5, this is what I'm getting after I fixed these patches to actually apply to u-boot/master (there was a minor conflict inMakefile):Quoted 4 lines
drivers/ddr/altera/sdram.c:11:35: fatal error:asm/arch/sdram_config.h:
No such file or directory#include <
asm/arch/sdram_config.h>OK, these files were misplaced by the patch. Now I got it to compile, only to see that when I try to init DRAM on sockit using those, PHY calibration fails (
run_mem_calibrate()returns 1).Quoted 8 lines
Quoted 6 lines
Quoted 1 line
btw. I also think
sdram_config.hshould go into board/altera/ instead .Just a quick heads-up, I'm cleaning this and the SPL up. I got SoCkit booting from SD/MMC and I'm over 50 patches now. I'll submit them when I'm done with this. I'd like to avoid merge conflicts now, so please wait for my submission if possible.
So you want me to wait regarding the SDRAM patches?
Quoted 9 lines
Hi,
yeah, I have some insane amount of cleanup patches and fixes already. I will post them once I'm done. What I am sorely missing is the UniPHY register interface documentation, it looks like that is not public, so I don't exactly know if what
sequencer.cdoes is really correct. Sometimes I have serious doubts about that too . Can you give me the documentation please ?
Have you seen this link[1]?
Dinh
[1] https://documentation.altera.com/#/00013681-AA$NT00067543
v4 cover drivers/ddr/altera: Add the DDR controller driver for SoCFPGA
Quoted 48 lines · Dinh Nguyen
Quoted 47 lines · Marek Vasut
Quoted 37 lines · Dinh Nguyen
Quoted 36 lines · Marek Vasut
Quoted 34 lines · Marek Vasut
Quoted 22 lines · Marek Vasut
On Wednesday, June 03, 2015 at 05:52:47 AM,
dinguyen at opensource.altera.comQuoted 4 lines · wrote:
From: Dinh Nguyen <[email protected]>
Hi,
Quoted 8 lines
This is v4 of the patch series that adds the DDR controller driver for Altera's SoCFPGA platform.
v4:
- Further cleanup by removing comments that do not apply for Cyclone5. - Removed more unused functionsThanks,
I applied this to u-boot/master and tried building for
socfpga_cyclone5, this is what I'm getting after I fixed these patches to actually apply to u-boot/master (there was a minor conflict inMakefile):Quoted 4 lines
drivers/ddr/altera/sdram.c:11:35: fatal error:asm/arch/sdram_config.h: No such file or directory#include <
asm/arch/sdram_config.h>OK, these files were misplaced by the patch. Now I got it to compile, only to see that when I try to init DRAM on sockit using those, PHY calibration fails (
run_mem_calibrate()returns 1).btw. I also think
sdram_config.hshould go into board/altera/ instead .Quoted 6 lines
Quoted 4 lines
Just a quick heads-up, I'm cleaning this and the SPL up. I got SoCkit booting from SD/MMC and I'm over 50 patches now. I'll submit them when I'm done with this. I'd like to avoid merge conflicts now, so please wait for my submission if possible.
So you want me to wait regarding the SDRAM patches?
Hi,
Quoted 8 lines
Quoted 6 lines
yeah, I have some insane amount of cleanup patches and fixes already. I will post them once I'm done. What I am sorely missing is the UniPHY register interface documentation, it looks like that is not public, so I don't exactly know if what
sequencer.cdoes is really correct. Sometimes I have serious doubts about that too . Can you give me the documentation please ?Have you seen this link[1]?
Yes, but that is by far not all of the registers used in the sequencer.c, is it ?
Quoted 2 lines
Dinh
[1] https://documentation.altera.com/#/00013681-AA$NT00067543
Best regards,
Marek Vasut
v4 cover drivers/ddr/altera: Add the DDR controller driver for SoCFPGA
Quoted 56 lines · Marek Vasut
Quoted 55 lines · Dinh Nguyen
Quoted 53 lines · Marek Vasut
Quoted 37 lines · Dinh Nguyen
Quoted 36 lines · Marek Vasut
Quoted 34 lines · Marek Vasut
Quoted 22 lines · Marek Vasut
On Wednesday, June 03, 2015 at 05:52:47 AM,
dinguyen at opensource.altera.comQuoted 4 lines · wrote:
From: Dinh Nguyen <[email protected]>
Hi,
Quoted 8 lines
This is v4 of the patch series that adds the DDR controller driver for Altera's SoCFPGA platform.
v4:
- Further cleanup by removing comments that do not apply for Cyclone5. - Removed more unused functionsThanks,
I applied this to u-boot/master and tried building for
socfpga_cyclone5, this is what I'm getting after I fixed these patches to actually apply to u-boot/master (there was a minor conflict inMakefile):Quoted 4 lines
drivers/ddr/altera/sdram.c:11:35: fatal error:asm/arch/sdram_config.h: No such file or directory#include <
asm/arch/sdram_config.h>OK, these files were misplaced by the patch. Now I got it to compile, only to see that when I try to init DRAM on sockit using those, PHY calibration fails (
run_mem_calibrate()returns 1).btw. I also think
sdram_config.hshould go into board/altera/ instead .Quoted 6 lines
Quoted 4 lines
Just a quick heads-up, I'm cleaning this and the SPL up. I got SoCkit booting from SD/MMC and I'm over 50 patches now. I'll submit them when I'm done with this. I'd like to avoid merge conflicts now, so please wait for my submission if possible.
So you want me to wait regarding the SDRAM patches?
Hi,
yeah, I have some insane amount of cleanup patches and fixes already. I will post them once I'm done. What I am sorely missing is the UniPHY register interface documentation, it looks like that is not public, so I don't exactly know if what
sequencer.cdoes is really correct. Sometimes I have serious doubts about that too . Can you give me the documentation please ?
Quoted 5 lines
Quoted 1 line
Have you seen this link[1]?
Yes, but that is by far not all of the registers used in the
sequencer.c, is it ?
Looks like it's in the entire emi.pdf file[1]. Please look at volume 3, or page 531 of 895. The section for the UniPHY.
v4 cover drivers/ddr/altera: Add the DDR controller driver for SoCFPGA
On Monday, July 20, 2015 at 09:31:39 PM, Dinh Nguyen wrote:
[...]
Quoted 9 lines
Quoted 9 lines
Quoted 9 lines
Quoted 8 lines
Hi,
yeah, I have some insane amount of cleanup patches and fixes already. I will post them once I'm done. What I am sorely missing is the UniPHY register interface documentation, it looks like that is not public, so I don't exactly know if what
sequencer.cdoes is really correct. Sometimes I have serious doubts about that too . Can you give me the documentation please ?
Quoted 7 lines
Quoted 4 lines
Quoted 1 line
Have you seen this link[1]?
Yes, but that is by far not all of the registers used in the
sequencer.c, is it ?Looks like it's in the entire emi.pdf file[1]. Please look at volume 3, or page 531 of 895. The section for the UniPHY.
I extracted all the possible addresses used in the sequencer while cleaning it up, they're below. I cannot find these in any documentation. I checked the EMI RM, sure, but there seems to be many more registers all around the place than what are described in the EMI RM. Any ideas please ? Maybe this is not even the UniPHY anymore ?
19 #define RW_MGR_RUN_SINGLE_GROUP_OFFSET 0x0 20 #define RW_MGR_RUN_ALL_GROUPS_OFFSET 0x0400 21 #define RW_MGR_RESET_READ_DATAPATH_OFFSET 0x1000 22 #define RW_MGR_SET_CS_AND_ODT_MASK_OFFSET 0x1400 23 #define RW_MGR_INST_ROM_WRITE_OFFSET 0x1800 24 #define RW_MGR_AC_ROM_WRITE_OFFSET 0x1C00 [...] 80 #define SCC_MGR_GROUP_COUNTER_OFFSET 0x0000 81 #define SCC_MGR_DQS_IN_DELAY_OFFSET 0x0100 82 #define SCC_MGR_DQS_EN_PHASE_OFFSET 0x0200 83 #define SCC_MGR_DQS_EN_DELAY_OFFSET 0x0300 84 #define SCC_MGR_DQDQS_OUT_PHASE_OFFSET 0x0400 85 #define SCC_MGR_OCT_OUT1_DELAY_OFFSET 0x0500 86 #define SCC_MGR_IO_OUT1_DELAY_OFFSET 0x0700 87 #define SCC_MGR_IO_IN_DELAY_OFFSET 0x0900 88 89 /* HHP-HPS-specific versions of some commands */ 90 #define SCC_MGR_DQS_EN_DELAY_GATE_OFFSET 0x0600 91 #define SCC_MGR_IO_OE_DELAY_OFFSET 0x0800 92 #define SCC_MGR_HHP_GLOBALS_OFFSET 0x0A00 93 #define SCC_MGR_HHP_RFILE_OFFSET 0x0B00 94 #define SCC_MGR_AFI_CAL_INIT_OFFSET 0x0D00 95 96 #define SDR_PHYGRP_SCCGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x0) 97 #define SDR_PHYGRP_PHYMGRGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x1000) 98 #define SDR_PHYGRP_RWMGRGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x2000) 99 #define SDR_PHYGRP_DATAMGRGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x4000) 100 #define SDR_PHYGRP_REGFILEGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x4800)
Then there's this in sequencer.c , again after cleanup:
17 static struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs =
18 (struct socfpga_sdr_rw_load_manager *)
(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800);
19
20 static struct socfpga_sdr_rw_load_jump_manager *sdr_rw_load_jump_mgr_regs =
21 (struct socfpga_sdr_rw_load_jump_manager *)
(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00);
22
23 static struct socfpga_sdr_reg_file *sdr_reg_file =
24 (struct socfpga_sdr_reg_file *)SDR_PHYGRP_REGFILEGRP_ADDRESS;
25
26 static struct socfpga_sdr_scc_mgr *sdr_scc_mgr =
27 (struct socfpga_sdr_scc_mgr *)(SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00);
28
29 static struct socfpga_phy_mgr_cmd *phy_mgr_cmd =
30 (struct socfpga_phy_mgr_cmd *)SDR_PHYGRP_PHYMGRGRP_ADDRESS;
31
32 static struct socfpga_phy_mgr_cfg *phy_mgr_cfg =
33 (struct socfpga_phy_mgr_cfg *)(SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40);
34
35 static struct socfpga_data_mgr *data_mgr =
36 (struct socfpga_data_mgr *)SDR_PHYGRP_DATAMGRGRP_ADDRESS;
37
38 static struct socfpga_sdr_ctrl *sdr_ctrl =
39 (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;Quoted 4 lines
Dinh
[1]
https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/
hb/external-memory/emi.pdf
Best regards,
Marek Vasut
v4 cover drivers/ddr/altera: Add the DDR controller driver for SoCFPGA
Quoted 16 lines · Marek Vasut
On Monday, July 20, 2015 at 09:31:39 PM, Dinh Nguyen wrote:
[...]Quoted 14 lines
Quoted 13 lines
Quoted 10 lines
Quoted 8 lines
Hi,
yeah, I have some insane amount of cleanup patches and fixes already. I will post them once I'm done. What I am sorely missing is the UniPHY register interface documentation, it looks like that is not public, so I don't exactly know if what
sequencer.cdoes is really correct. Sometimes I have serious doubts about that too . Can you give me the documentation please ?Have you seen this link[1]?
Yes, but that is by far not all of the registers used in the
sequencer.c, is it ?
Quoted 9 lines
Quoted 2 lines
Looks like it's in the entire emi.pdf file[1]. Please look at volume 3, or page 531 of 895. The section for the UniPHY.
I extracted all the possible addresses used in the sequencer while cleaning it up, they're below. I cannot find these in any documentation. I checked the EMI RM, sure, but there seems to be many more registers all around the place than what are described in the EMI RM. Any ideas please ? Maybe this is not even the UniPHY anymore ?
I'll try to get those questions answered for you shortly.
BTW, I tested out our your branch, but I think I'm missing a step as where to put the SPL DTB?
U-Boot SPL 2015.07-rc3-00100-ga2e2da6 (Jul 21 2015 - 17:15:54) drivers/ddr/altera/sequencer.c: Preparing to start memory calibration drivers/ddr/altera/sequencer.c: CALIBRATION PASSED drivers/ddr/altera/sequencer.c: Calibration complete Missing DTB
### ERROR ### Please RESET the board ###
Thanks,
Dinh
v4 cover drivers/ddr/altera: Add the DDR controller driver for SoCFPGA
Quoted 18 lines · Dinh Nguyen
Quoted 17 lines · Marek Vasut
On Monday, July 20, 2015 at 09:31:39 PM, Dinh Nguyen wrote:
[...]Quoted 14 lines
Quoted 13 lines
Quoted 10 lines
Quoted 8 lines
Hi,
yeah, I have some insane amount of cleanup patches and fixes already. I will post them once I'm done. What I am sorely missing is the UniPHY register interface documentation, it looks like that is not public, so I don't exactly know if what
sequencer.cdoes is really correct. Sometimes I have serious doubts about that too . Can you give me the documentation please ?Have you seen this link[1]?
Yes, but that is by far not all of the registers used in the
sequencer.c, is it ?
Quoted 8 lines
Quoted 8 lines
Quoted 2 lines
Looks like it's in the entire emi.pdf file[1]. Please look at volume 3, or page 531 of 895. The section for the UniPHY.
I extracted all the possible addresses used in the sequencer while cleaning it up, they're below. I cannot find these in any documentation. I checked the EMI RM, sure, but there seems to be many more registers all around the place than what are described in the EMI RM. Any ideas please ? Maybe this is not even the UniPHY anymore ?
Hi!
Quoted 1 line
I'll try to get those questions answered for you shortly.
Thanks!
Quoted 10 lines
BTW, I tested out our your branch, but I think I'm missing a step as where to put the SPL DTB?
U-Boot SPL 2015.07-rc3-00100-ga2e2da6 (Jul 21 2015 - 17:15:54)
drivers/ddr/altera/sequencer.c: Preparing to start memory calibrationdrivers/ddr/altera/sequencer.c: CALIBRATION PASSEDdrivers/ddr/altera/sequencer.c: Calibration complete Missing DTB
### ERROR ### Please RESET the board ###
Do:
make u-boot-with-spl-dtb.sfp
This will produce u-boot-with-spl-dtb.sfp, which you write directly to that 0xa2 socfpga boot partition. It includes U-Boot SPL, DTB and U-Boot. You will also need to define CONFIG_SPL_MMC_SUPPORT in include/configs/socfpga_common.h as I didn't solve how to configure this on per-board basis, do this before building the U-Boot of course.
Best regards,
Marek Vasut
v4 cover drivers/ddr/altera: Add the DDR controller driver for SoCFPGA
Quoted 45 lines · Marek Vasut
Quoted 18 lines · Dinh Nguyen
Quoted 17 lines · Marek Vasut
On Monday, July 20, 2015 at 09:31:39 PM, Dinh Nguyen wrote:
[...]Quoted 14 lines
Quoted 13 lines
Quoted 10 lines
Quoted 8 lines
Hi,
yeah, I have some insane amount of cleanup patches and fixes already. I will post them once I'm done. What I am sorely missing is the UniPHY register interface documentation, it looks like that is not public, so I don't exactly know if what
sequencer.cdoes is really correct. Sometimes I have serious doubts about that too . Can you give me the documentation please ?Have you seen this link[1]?
Yes, but that is by far not all of the registers used in the
sequencer.c, is it ?Quoted 8 lines
Quoted 8 lines
Quoted 2 lines
Looks like it's in the entire emi.pdf file[1]. Please look at volume 3, or page 531 of 895. The section for the UniPHY.
I extracted all the possible addresses used in the sequencer while cleaning it up, they're below. I cannot find these in any documentation. I checked the EMI RM, sure, but there seems to be many more registers all around the place than what are described in the EMI RM. Any ideas please ? Maybe this is not even the UniPHY anymore ?
Hi!
Quoted 1 line
I'll try to get those questions answered for you shortly.
Thanks!
Quoted 10 lines
BTW, I tested out our your branch, but I think I'm missing a step as where to put the SPL DTB?
U-Boot SPL 2015.07-rc3-00100-ga2e2da6 (Jul 21 2015 - 17:15:54)
drivers/ddr/altera/sequencer.c: Preparing to start memory calibrationdrivers/ddr/altera/sequencer.c: CALIBRATION PASSEDdrivers/ddr/altera/sequencer.c: Calibration complete Missing DTB
### ERROR ### Please RESET the board ###
Quoted 4 lines
Do:
make u-boot-with-spl-dtb.sfp
Does your updated branch still work for you on the SoCKit? I'm hitting the dreaded "CALIBRATION FAILED" on all my boards here, the devkit, SoCKit and the new Atlas SoCKit.
U-Boot SPL 2015.07-00293-ga6f4805 (Jul 23 2015 - 11:18:51) drivers/ddr/altera/sequencer.c: Preparing to start memory calibration drivers/ddr/altera/sequencer.c: CALIBRATION FAILED drivers/ddr/altera/sequencer.c: Calibration complete
SDRAM calibration failed.
### ERROR ### Please RESET the board ###
v4 cover drivers/ddr/altera: Add the DDR controller driver for SoCFPGA
On Thursday, July 23, 2015 at 08:29:42 PM, Dinh Nguyen wrote:
[...]
Quoted 19 lines
Quoted 11 lines
Quoted 10 lines
BTW, I tested out our your branch, but I think I'm missing a step as where to put the SPL DTB?
U-Boot SPL 2015.07-rc3-00100-ga2e2da6 (Jul 21 2015 - 17:15:54)
drivers/ddr/altera/sequencer.c: Preparing to start memory calibrationdrivers/ddr/altera/sequencer.c: CALIBRATION PASSEDdrivers/ddr/altera/sequencer.c: Calibration complete Missing DTB
### ERROR ### Please RESET the board ###Quoted 3 lines
Do:
make u-boot-with-spl-dtb.sfp
Does your updated branch still work for you on the SoCKit? I'm hitting the dreaded "CALIBRATION FAILED" on all my boards here, the devkit, SoCKit and the new Atlas SoCKit.
Quoted 6 lines
U-Boot SPL 2015.07-00293-ga6f4805 (Jul 23 2015 - 11:18:51)
drivers/ddr/altera/sequencer.c: Preparing to start memory calibrationdrivers/ddr/altera/sequencer.c: CALIBRATION FAILEDdrivers/ddr/altera/sequencer.c: Calibration complete
SDRAM calibration failed.
### ERROR ### Please RESET the board ###
Hi!
You probably need the use different DRAM config for the sockit (I do use different ones, generated from Quartus). I pushed my SoCkit hacks to [1] (u-boot-socfpga / vip/sockit). This is tested last time today, so it should work for you.
Also, notice the topmost patch [2]. You can ignore (and drop) the delay in spl.c , that's a hack I use to make it wait until my USB catches up after cold reset of the sockit. The change to timer.c is something that's baffling me -- without this change I also get calibration failure, but I didn't find out why yet.
To make it ever weirder, if I use gcc 5.0.x , I do NOT get the calibration failure even WITHOUT this patch ; if I use gcc 4.8.4 (ELDK 5.6.1rc), I do get calibration failure failure ; if I use gcc 4.7.x (ELDK 5.5.x) and the gcc from ELDK 5.4.x (I don't remember the version), I do get calibration failure failure. I am even starting to suspect compiler bugs here, but I don't want to draw hasty conclusions yet.
btw. where can I get the atlas kit ? it seems out of stock everywhere :(
[1] http://git.denx.de/?p=u-boot/u-boot-
socfpga.git;a=shortlog;h=refs/heads/vip/sockit
[2] http://git.denx.de/?p=u-boot/u-boot-
socfpga.git;a=commit;h=a8fd1c256c24eea79aad0079dbdf4db0593070e0
Best regards,
Marek Vasut
v4 cover drivers/ddr/altera: Add the DDR controller driver for SoCFPGA
In reply to Marek VasutQuoted 16 lines · Marek Vasut
On Monday, July 20, 2015 at 09:31:39 PM, Dinh Nguyen wrote:
[...]Quoted 14 lines
Quoted 13 lines
Quoted 10 lines
Quoted 8 lines
Hi,
yeah, I have some insane amount of cleanup patches and fixes already. I will post them once I'm done. What I am sorely missing is the UniPHY register interface documentation, it looks like that is not public, so I don't exactly know if what
sequencer.cdoes is really correct. Sometimes I have serious doubts about that too . Can you give me the documentation please ?Have you seen this link[1]?
Yes, but that is by far not all of the registers used in the
sequencer.c, is it ?
Quoted 8 lines
Quoted 2 lines
Looks like it's in the entire emi.pdf file[1]. Please look at volume 3, or page 531 of 895. The section for the UniPHY.
I extracted all the possible addresses used in the sequencer while cleaning it up, they're below. I cannot find these in any documentation. I checked the EMI RM, sure, but there seems to be many more registers all around the place than what are described in the EMI RM. Any ideas please ? Maybe this is not even the UniPHY anymore ?
What I've been told was that the UniPHY was not really properly documented, and that when anyone needed to modify the registers, they would have to go back to the RTL to figure out exactly what's going on.
So I've only been able to get the following information on the registers below:
[Read/Write manager - this is a small accelerator that can be programmed with custom microcode to "play" sequences of commands to the memory interface at memory speeds]
[This register will execute a specific RW MGR command for a single DQS group]
9 #define RW_MGR_RUN_SINGLE_GROUP_OFFSET 0x0
[This register will execute a specific RW MGR command for all DQS groups in the memory in parallel]
20 #define RW_MGR_RUN_ALL_GROUPS_OFFSET 0x0400
[Resets the read datapath to clear out any corrupted data]
21 #define RW_MGR_RESET_READ_DATAPATH_OFFSET 0x1000
[Configurable mask to specify which chip select should be asserted and what the value of ODT should be when CS is asserted]
22 #define RW_MGR_SET_CS_AND_ODT_MASK_OFFSET 0x1400
[Write pointer into the instruction microcode rom]
23 #define RW_MGR_INST_ROM_WRITE_OFFSET 0x1800
[Write pointer into the address ROM that is indexed via instruction microcode]
24 #define RW_MGR_AC_ROM_WRITE_OFFSET 0x1C00
[The Scan-Chain Control manager is a piece of hardware that interfaces to the serial scan chain configuration bus of the PHY. It is used to program and modify delay values during calibration and sometimes during operation for things like DQS tracking]
[which DQS group the SCC_MGR is talking to]
80 #define SCC_MGR_GROUP_COUNTER_OFFSET 0x0000
[Offset for DQS input delay]
81 #define SCC_MGR_DQS_IN_DELAY_OFFSET 0x0100
[Offset for DQS Enable Coarse input Phase register]
82 #define SCC_MGR_DQS_EN_PHASE_OFFSET 0x0200
[Offset for DQS Enable Phase fine-grained delay]
83 #define SCC_MGR_DQS_EN_DELAY_OFFSET 0x0300
[Offset for DQ/DQS coarse output phase register]
84 #define SCC_MGR_DQDQS_OUT_PHASE_OFFSET 0x0400
[Offset for termination control delay setting register]
85 #define SCC_MGR_OCT_OUT1_DELAY_OFFSET 0x0500
[Don't know]
86 #define SCC_MGR_IO_OUT1_DELAY_OFFSET 0x0700
[Input delay register]
87 #define SCC_MGR_IO_IN_DELAY_OFFSET 0x0900
[It seems these are added specifically for 28nm handshaking with HPS only. I'm strictly guessing here]
[DQS enable gating delay register]
90 #define SCC_MGR_DQS_EN_DELAY_GATE_OFFSET 0x0600
[Output enable timing register]
91 #define SCC_MGR_IO_OE_DELAY_OFFSET 0x0800
[Not sure]
92 #define SCC_MGR_HHP_GLOBALS_OFFSET 0x0A00
[Not sure]
93 #define SCC_MGR_HHP_RFILE_OFFSET 0x0B00
[Probably a register to query whether or not the AFI bus is still in calibration mode or if the HPS has control]
94 #define SCC_MGR_AFI_CAL_INIT_OFFSET 0x0D00
95
Dinh
v4 cover drivers/ddr/altera: Add the DDR controller driver for SoCFPGA
Quoted 27 lines · Dinh Nguyen
Quoted 17 lines · Marek Vasut
On Monday, July 20, 2015 at 09:31:39 PM, Dinh Nguyen wrote:
[...]Quoted 14 lines
Quoted 13 lines
Quoted 10 lines
Quoted 8 lines
Hi,
yeah, I have some insane amount of cleanup patches and fixes already. I will post them once I'm done. What I am sorely missing is the UniPHY register interface documentation, it looks like that is not public, so I don't exactly know if what
sequencer.cdoes is really correct. Sometimes I have serious doubts about that too . Can you give me the documentation please ?Have you seen this link[1]?
Yes, but that is by far not all of the registers used in the
sequencer.c, is it ?Quoted 8 lines
Quoted 2 lines
Looks like it's in the entire emi.pdf file[1]. Please look at volume 3, or page 531 of 895. The section for the UniPHY.
I extracted all the possible addresses used in the sequencer while cleaning it up, they're below. I cannot find these in any documentation. I checked the EMI RM, sure, but there seems to be many more registers all around the place than what are described in the EMI RM. Any ideas please ? Maybe this is not even the UniPHY anymore ?
Quoted 3 lines
What I've been told was that the UniPHY was not really properly documented, and that when anyone needed to modify the registers, they would have to go back to the RTL to figure out exactly what's going on.
I guess you cannot provide me with the RTL, right ?
Quoted 6 lines
So I've only been able to get the following information on the registers below:
[Read/Write manager - this is a small accelerator that can be programmed with custom microcode to "play" sequences of commands to the memory interface at memory speeds]
This makes sense from what I saw in the code, yeah. Is there any documentation?
Thanks!
Quoted 54 lines
[This register will execute a specific RW MGR command for a single DQS group]
9 #defineRW_MGR_RUN_SINGLE_GROUP_OFFSET0x0
[This register will execute a specific RW MGR command for all DQS groups in the memory in parallel]
20 #defineRW_MGR_RUN_ALL_GROUPS_OFFSET0x0400
[Resets the read datapath to clear out any corrupted data]
21 #defineRW_MGR_RESET_READ_DATAPATH_OFFSET0x1000
[Configurable mask to specify which chip select should be asserted and what the value of ODT should be when CS is asserted]
22 #defineRW_MGR_SET_CS_AND_ODT_MASK_OFFSET0x1400
[Write pointer into the instruction microcode rom]
23 #defineRW_MGR_INST_ROM_WRITE_OFFSET0x1800
[Write pointer into the address ROM that is indexed via instruction microcode]
24 #defineRW_MGR_AC_ROM_WRITE_OFFSET0x1C00[The Scan-Chain Control manager is a piece of hardware that interfaces to the serial scan chain configuration bus of the PHY. It is used to program and modify delay values during calibration and sometimes during operation for things like DQS tracking]
[which DQS group theSCC_MGRis talking to]
80 #defineSCC_MGR_GROUP_COUNTER_OFFSET0x0000
[Offset for DQS input delay]
81 #defineSCC_MGR_DQS_IN_DELAY_OFFSET0x0100
[Offset for DQS Enable Coarse input Phase register]
82 #defineSCC_MGR_DQS_EN_PHASE_OFFSET0x0200
[Offset for DQS Enable Phase fine-grained delay]
83 #defineSCC_MGR_DQS_EN_DELAY_OFFSET0x0300
[Offset for DQ/DQS coarse output phase register]
84 #defineSCC_MGR_DQDQS_OUT_PHASE_OFFSET0x0400
[Offset for termination control delay setting register]
85 #defineSCC_MGR_OCT_OUT1_DELAY_OFFSET0x0500
[Don't know]
86 #defineSCC_MGR_IO_OUT1_DELAY_OFFSET0x0700
[Input delay register]
87 #defineSCC_MGR_IO_IN_DELAY_OFFSET0x0900[It seems these are added specifically for 28nm handshaking with HPS only. I'm strictly guessing here]
[DQS enable gating delay register]
90 #defineSCC_MGR_DQS_EN_DELAY_GATE_OFFSET0x0600
[Output enable timing register]
91 #defineSCC_MGR_IO_OE_DELAY_OFFSET0x0800
[Not sure]
92 #defineSCC_MGR_HHP_GLOBALS_OFFSET0x0A00
[Not sure]
93 #defineSCC_MGR_HHP_RFILE_OFFSET0x0B00
[Probably a register to query whether or not the AFI bus is still in calibration mode or if the HPS has control]
94 #defineSCC_MGR_AFI_CAL_INIT_OFFSET0x0D00
95
Quoted 1 line
Dinh
Best regards,
Marek Vasut
v4 cover drivers/ddr/altera: Add the DDR controller driver for SoCFPGA
Quoted 16 lines · Marek Vasut
Quoted 15 lines · Dinh Nguyen
Quoted 14 lines · Marek Vasut
On Monday, July 20, 2015 at 09:31:39 PM, Dinh Nguyen wrote:
[...]Quoted 11 lines
Quoted 11 lines
Quoted 10 lines
Quoted 8 lines
Hi,
yeah, I have some insane amount of cleanup patches and fixes already. I will post them once I'm done. What I am sorely missing is the UniPHY register interface documentation, it looks like that is not public, so I don't exactly know if what
sequencer.cdoes is really correct. Sometimes I have serious doubts about that too . Can you give me the documentation please ?Have you seen this link[1]?
Quoted 8 lines
Quoted 8 lines
Quoted 8 lines
Quoted 5 lines
Quoted 2 lines
Yes, but that is by far not all of the registers used in the
sequencer.c, is it ?Looks like it's in the entire emi.pdf file[1]. Please look at volume 3, or page 531 of 895. The section for the UniPHY.
I extracted all the possible addresses used in the sequencer while cleaning it up, they're below.
I cannot find these in any documentation.
Quoted 10 lines
Quoted 7 lines
Quoted 3 lines
I checked the EMI RM, sure, but there seems to be many more registers all around the place than what are described in the EMI RM. Any ideas please ? Maybe this is not even the UniPHY anymore ?
What I've been told was that the UniPHY was not really properly documented, and that when anyone needed to modify the registers, they would have to go back to the RTL to figure out exactly what's going on.
I guess you cannot provide me with the RTL, right ?
I don't think so, but will ask.
Dinh
v4 cover drivers/ddr/altera: Add the DDR controller driver for SoCFPGA
Quoted 20 lines · Dinh Nguyen
Quoted 19 lines · Marek Vasut
Quoted 18 lines · Dinh Nguyen
Quoted 17 lines · Marek Vasut
On Monday, July 20, 2015 at 09:31:39 PM, Dinh Nguyen wrote:
[...]Quoted 14 lines
Quoted 13 lines
Quoted 10 lines
Quoted 8 lines
Hi,
yeah, I have some insane amount of cleanup patches and fixes already. I will post them once I'm done. What I am sorely missing is the UniPHY register interface documentation, it looks like that is not public, so I don't exactly know if what
sequencer.cdoes is really correct. Sometimes I have serious doubts about that too . Can you give me the documentation please ?Have you seen this link[1]?
Yes, but that is by far not all of the registers used in the
sequencer.c, is it ?
Quoted 7 lines
Quoted 5 lines
Quoted 5 lines
Quoted 5 lines
Quoted 2 lines
Looks like it's in the entire emi.pdf file[1]. Please look at volume 3, or page 531 of 895. The section for the UniPHY.
I extracted all the possible addresses used in the sequencer while cleaning it up, they're below.
I cannot find these in any documentation.
Cool %^)
Quoted 11 lines
Quoted 9 lines
Quoted 7 lines
Quoted 3 lines
I checked the EMI RM, sure, but there seems to be many more registers all around the place than what are described in the EMI RM. Any ideas please ? Maybe this is not even the UniPHY anymore ?
What I've been told was that the UniPHY was not really properly documented, and that when anyone needed to modify the registers, they would have to go back to the RTL to figure out exactly what's going on.
I guess you cannot provide me with the RTL, right ?
I don't think so, but will ask.
Thanks!
Best regards,
Marek Vasut
v4 cover drivers/ddr/altera: Add the DDR controller driver for SoCFPGA
Quoted 24 lines · Marek Vasut
Quoted 23 lines · Dinh Nguyen
Quoted 22 lines · Marek Vasut
Quoted 21 lines · Dinh Nguyen
Quoted 20 lines · Marek Vasut
On Monday, July 20, 2015 at 09:31:39 PM, Dinh Nguyen wrote:
[...]Quoted 16 lines
Quoted 9 lines
Quoted 9 lines
Quoted 8 lines
Hi,
yeah, I have some insane amount of cleanup patches and fixes already. I will post them once I'm done. What I am sorely missing is the UniPHY register interface documentation, it looks like that is not public, so I don't exactly know if what
sequencer.cdoes is really correct. Sometimes I have serious doubts about that too . Can you give me the documentation please ?Quoted 4 lines
Quoted 1 line
Have you seen this link[1]?
Yes, but that is by far not all of the registers used in the
sequencer.c, is it ?Looks like it's in the entire emi.pdf file[1]. Please look at volume 3, or page 531 of 895. The section for the UniPHY.
Quoted 19 lines
Quoted 4 lines
Quoted 2 lines
Quoted 2 lines
Quoted 2 lines
I extracted all the possible addresses used in the sequencer while cleaning it up, they're below.
I cannot find these in any documentation.
Cool %^)
Quoted 11 lines
Quoted 9 lines
Quoted 7 lines
Quoted 3 lines
I checked the EMI RM, sure, but there seems to be many more registers all around the place than what are described in the EMI RM. Any ideas please ? Maybe this is not even the UniPHY anymore ?
What I've been told was that the UniPHY was not really properly documented, and that when anyone needed to modify the registers, they would have to go back to the RTL to figure out exactly what's going on.
I guess you cannot provide me with the RTL, right ?
I don't think so, but will ask.
I was told that some of the RTL is actually deployed if you create a Verilog DDR3 UniPHY example design for AV/CV system through IP generation -- that should give you some more specific information. You may have to create a soft-phy, soft-controller version for it to deploy the unencrypted RTL.
I'll start this to see if I can find something helpful.
Dinh